Rev 6935 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 6935 | Rev 6937 | ||
---|---|---|---|
Line 48... | Line 48... | ||
48 | struct intel_encoder base; |
48 | struct intel_encoder base; |
49 | /* DPMS state is stored in the connector, which we need in the |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ |
50 | * encoder's enable/disable callbacks */ |
51 | struct intel_connector *connector; |
51 | struct intel_connector *connector; |
52 | bool force_hotplug_required; |
52 | bool force_hotplug_required; |
53 | u32 adpa_reg; |
53 | i915_reg_t adpa_reg; |
54 | }; |
54 | }; |
Line 55... | Line 55... | ||
55 | 55 | ||
56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
57 | { |
57 | { |
Line 69... | Line 69... | ||
69 | struct drm_device *dev = encoder->base.dev; |
69 | struct drm_device *dev = encoder->base.dev; |
70 | struct drm_i915_private *dev_priv = dev->dev_private; |
70 | struct drm_i915_private *dev_priv = dev->dev_private; |
71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
72 | enum intel_display_power_domain power_domain; |
72 | enum intel_display_power_domain power_domain; |
73 | u32 tmp; |
73 | u32 tmp; |
- | 74 | bool ret; |
|
Line 74... | Line 75... | ||
74 | 75 | ||
75 | power_domain = intel_display_port_power_domain(encoder); |
76 | power_domain = intel_display_port_power_domain(encoder); |
76 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
77 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Line -... | Line 78... | ||
- | 78 | return false; |
|
- | 79 | ||
77 | return false; |
80 | ret = false; |
Line 78... | Line 81... | ||
78 | 81 | ||
79 | tmp = I915_READ(crt->adpa_reg); |
82 | tmp = I915_READ(crt->adpa_reg); |
Line 80... | Line 83... | ||
80 | 83 | ||
81 | if (!(tmp & ADPA_DAC_ENABLE)) |
84 | if (!(tmp & ADPA_DAC_ENABLE)) |
82 | return false; |
85 | goto out; |
83 | 86 | ||
Line 84... | Line 87... | ||
84 | if (HAS_PCH_CPT(dev)) |
87 | if (HAS_PCH_CPT(dev)) |
- | 88 | *pipe = PORT_TO_PIPE_CPT(tmp); |
|
- | 89 | else |
|
- | 90 | *pipe = PORT_TO_PIPE(tmp); |
|
- | 91 | ||
85 | *pipe = PORT_TO_PIPE_CPT(tmp); |
92 | ret = true; |
Line 86... | Line 93... | ||
86 | else |
93 | out: |
87 | *pipe = PORT_TO_PIPE(tmp); |
94 | intel_display_power_put(dev_priv, power_domain); |
88 | 95 | ||
Line 443... | Line 450... | ||
443 | { |
450 | { |
444 | struct intel_crt *crt = intel_attached_crt(connector); |
451 | struct intel_crt *crt = intel_attached_crt(connector); |
445 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
452 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
446 | struct edid *edid; |
453 | struct edid *edid; |
447 | struct i2c_adapter *i2c; |
454 | struct i2c_adapter *i2c; |
448 | bool ret = false; |
- | |
Line 449... | Line 455... | ||
449 | 455 | ||
Line 450... | Line 456... | ||
450 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
456 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
451 | 457 | ||
Line 460... | Line 466... | ||
460 | * link between analog and digital outputs, so we |
466 | * link between analog and digital outputs, so we |
461 | * have to check the EDID input spec of the attached device. |
467 | * have to check the EDID input spec of the attached device. |
462 | */ |
468 | */ |
463 | if (!is_digital) { |
469 | if (!is_digital) { |
464 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
470 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
465 | ret = true; |
471 | return true; |
466 | } else { |
- | |
467 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
- | |
468 | } |
472 | } |
- | 473 | ||
- | 474 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
|
469 | } else { |
475 | } else { |
470 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
476 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
471 | } |
477 | } |
Line 472... | Line 478... | ||
472 | 478 | ||
Line 473... | Line 479... | ||
473 | kfree(edid); |
479 | kfree(edid); |
474 | 480 | ||
Line 475... | Line 481... | ||
475 | return ret; |
481 | return false; |
476 | } |
482 | } |
477 | 483 | ||
Line 485... | Line 491... | ||
485 | uint32_t save_vtotal; |
491 | uint32_t save_vtotal; |
486 | uint32_t vtotal, vactive; |
492 | uint32_t vtotal, vactive; |
487 | uint32_t vsample; |
493 | uint32_t vsample; |
488 | uint32_t vblank, vblank_start, vblank_end; |
494 | uint32_t vblank, vblank_start, vblank_end; |
489 | uint32_t dsl; |
495 | uint32_t dsl; |
490 | uint32_t bclrpat_reg; |
496 | i915_reg_t bclrpat_reg, vtotal_reg, |
491 | uint32_t vtotal_reg; |
- | |
492 | uint32_t vblank_reg; |
- | |
493 | uint32_t vsync_reg; |
- | |
494 | uint32_t pipeconf_reg; |
- | |
495 | uint32_t pipe_dsl_reg; |
497 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; |
496 | uint8_t st00; |
498 | uint8_t st00; |
497 | enum drm_connector_status status; |
499 | enum drm_connector_status status; |
Line 498... | Line 500... | ||
498 | 500 | ||
Line 523... | Line 525... | ||
523 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
525 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
524 | POSTING_READ(pipeconf_reg); |
526 | POSTING_READ(pipeconf_reg); |
525 | /* Wait for next Vblank to substitue |
527 | /* Wait for next Vblank to substitue |
526 | * border color for Color info */ |
528 | * border color for Color info */ |
527 | intel_wait_for_vblank(dev, pipe); |
529 | intel_wait_for_vblank(dev, pipe); |
528 | st00 = I915_READ8(VGA_MSR_WRITE); |
530 | st00 = I915_READ8(_VGA_MSR_WRITE); |
529 | status = ((st00 & (1 << 4)) != 0) ? |
531 | status = ((st00 & (1 << 4)) != 0) ? |
530 | connector_status_connected : |
532 | connector_status_connected : |
531 | connector_status_disconnected; |
533 | connector_status_disconnected; |
Line 532... | Line 534... | ||
532 | 534 | ||
Line 568... | Line 570... | ||
568 | detect = 0; |
570 | detect = 0; |
569 | count = 0; |
571 | count = 0; |
570 | do { |
572 | do { |
571 | count++; |
573 | count++; |
572 | /* Read the ST00 VGA status register */ |
574 | /* Read the ST00 VGA status register */ |
573 | st00 = I915_READ8(VGA_MSR_WRITE); |
575 | st00 = I915_READ8(_VGA_MSR_WRITE); |
574 | if (st00 & (1 << 4)) |
576 | if (st00 & (1 << 4)) |
575 | detect++; |
577 | detect++; |
576 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
578 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
Line 577... | Line 579... | ||
577 | 579 | ||
Line 786... | Line 788... | ||
786 | { |
788 | { |
787 | struct drm_connector *connector; |
789 | struct drm_connector *connector; |
788 | struct intel_crt *crt; |
790 | struct intel_crt *crt; |
789 | struct intel_connector *intel_connector; |
791 | struct intel_connector *intel_connector; |
790 | struct drm_i915_private *dev_priv = dev->dev_private; |
792 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 793 | i915_reg_t adpa_reg; |
|
- | 794 | u32 adpa; |
|
Line 791... | Line 795... | ||
791 | 795 | ||
792 | /* Skip machines without VGA that falsely report hotplug events */ |
796 | /* Skip machines without VGA that falsely report hotplug events */ |
793 | if (dmi_check_system(intel_no_crt)) |
797 | if (dmi_check_system(intel_no_crt)) |
Line -... | Line 798... | ||
- | 798 | return; |
|
- | 799 | ||
- | 800 | if (HAS_PCH_SPLIT(dev)) |
|
- | 801 | adpa_reg = PCH_ADPA; |
|
- | 802 | else if (IS_VALLEYVIEW(dev)) |
|
- | 803 | adpa_reg = VLV_ADPA; |
|
- | 804 | else |
|
- | 805 | adpa_reg = ADPA; |
|
- | 806 | ||
- | 807 | adpa = I915_READ(adpa_reg); |
|
- | 808 | if ((adpa & ADPA_DAC_ENABLE) == 0) { |
|
- | 809 | /* |
|
- | 810 | * On some machines (some IVB at least) CRT can be |
|
- | 811 | * fused off, but there's no known fuse bit to |
|
- | 812 | * indicate that. On these machine the ADPA register |
|
- | 813 | * works normally, except the DAC enable bit won't |
|
- | 814 | * take. So the only way to tell is attempt to enable |
|
- | 815 | * it and see what happens. |
|
- | 816 | */ |
|
- | 817 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | |
|
- | 818 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
|
- | 819 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) |
|
- | 820 | return; |
|
- | 821 | I915_WRITE(adpa_reg, adpa); |
|
794 | return; |
822 | } |
795 | 823 | ||
796 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
824 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
Line 797... | Line 825... | ||
797 | if (!crt) |
825 | if (!crt) |
Line 807... | Line 835... | ||
807 | crt->connector = intel_connector; |
835 | crt->connector = intel_connector; |
808 | drm_connector_init(dev, &intel_connector->base, |
836 | drm_connector_init(dev, &intel_connector->base, |
809 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
837 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
Line 810... | Line 838... | ||
810 | 838 | ||
811 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
839 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
Line 812... | Line 840... | ||
812 | DRM_MODE_ENCODER_DAC); |
840 | DRM_MODE_ENCODER_DAC, NULL); |
Line 813... | Line 841... | ||
813 | 841 | ||
814 | intel_connector_attach_encoder(intel_connector, &crt->base); |
842 | intel_connector_attach_encoder(intel_connector, &crt->base); |
Line 824... | Line 852... | ||
824 | connector->interlace_allowed = 0; |
852 | connector->interlace_allowed = 0; |
825 | else |
853 | else |
826 | connector->interlace_allowed = 1; |
854 | connector->interlace_allowed = 1; |
827 | connector->doublescan_allowed = 0; |
855 | connector->doublescan_allowed = 0; |
Line 828... | Line -... | ||
828 | - | ||
829 | if (HAS_PCH_SPLIT(dev)) |
- | |
830 | crt->adpa_reg = PCH_ADPA; |
- | |
831 | else if (IS_VALLEYVIEW(dev)) |
856 | |
832 | crt->adpa_reg = VLV_ADPA; |
- | |
833 | else |
- | |
Line 834... | Line 857... | ||
834 | crt->adpa_reg = ADPA; |
857 | crt->adpa_reg = adpa_reg; |
835 | 858 | ||
836 | crt->base.compute_config = intel_crt_compute_config; |
859 | crt->base.compute_config = intel_crt_compute_config; |
837 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) { |
860 | if (HAS_PCH_SPLIT(dev)) { |
838 | crt->base.disable = pch_disable_crt; |
861 | crt->base.disable = pch_disable_crt; |
839 | crt->base.post_disable = pch_post_disable_crt; |
862 | crt->base.post_disable = pch_post_disable_crt; |
840 | } else { |
863 | } else { |