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1 | /* |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | */ |
25 | */ |
- | 26 | ||
26 | 27 | #include |
|
27 | #include |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include "intel_drv.h" |
34 | #include "intel_drv.h" |
34 | #include |
35 | #include |
35 | #include "i915_drv.h" |
36 | #include "i915_drv.h" |
36 | 37 | ||
37 | /* Here's the desired hotplug mode */ |
38 | /* Here's the desired hotplug mode */ |
38 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
39 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
40 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
41 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
42 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
43 | ADPA_CRT_HOTPLUG_ENABLE) |
44 | ADPA_CRT_HOTPLUG_ENABLE) |
44 | 45 | ||
45 | struct intel_crt { |
46 | struct intel_crt { |
46 | struct intel_encoder base; |
47 | struct intel_encoder base; |
47 | /* DPMS state is stored in the connector, which we need in the |
48 | /* DPMS state is stored in the connector, which we need in the |
48 | * encoder's enable/disable callbacks */ |
49 | * encoder's enable/disable callbacks */ |
49 | struct intel_connector *connector; |
50 | struct intel_connector *connector; |
50 | bool force_hotplug_required; |
51 | bool force_hotplug_required; |
51 | u32 adpa_reg; |
52 | u32 adpa_reg; |
52 | }; |
53 | }; |
53 | 54 | ||
54 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
55 | { |
56 | { |
56 | return container_of(encoder, struct intel_crt, base); |
57 | return container_of(encoder, struct intel_crt, base); |
57 | } |
58 | } |
58 | 59 | ||
59 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
60 | { |
61 | { |
61 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
62 | } |
63 | } |
63 | 64 | ||
64 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
65 | enum pipe *pipe) |
66 | enum pipe *pipe) |
66 | { |
67 | { |
67 | struct drm_device *dev = encoder->base.dev; |
68 | struct drm_device *dev = encoder->base.dev; |
68 | struct drm_i915_private *dev_priv = dev->dev_private; |
69 | struct drm_i915_private *dev_priv = dev->dev_private; |
69 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
70 | enum intel_display_power_domain power_domain; |
71 | enum intel_display_power_domain power_domain; |
71 | u32 tmp; |
72 | u32 tmp; |
72 | 73 | ||
73 | power_domain = intel_display_port_power_domain(encoder); |
74 | power_domain = intel_display_port_power_domain(encoder); |
74 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
75 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
75 | return false; |
76 | return false; |
76 | 77 | ||
77 | tmp = I915_READ(crt->adpa_reg); |
78 | tmp = I915_READ(crt->adpa_reg); |
78 | 79 | ||
79 | if (!(tmp & ADPA_DAC_ENABLE)) |
80 | if (!(tmp & ADPA_DAC_ENABLE)) |
80 | return false; |
81 | return false; |
81 | 82 | ||
82 | if (HAS_PCH_CPT(dev)) |
83 | if (HAS_PCH_CPT(dev)) |
83 | *pipe = PORT_TO_PIPE_CPT(tmp); |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); |
84 | else |
85 | else |
85 | *pipe = PORT_TO_PIPE(tmp); |
86 | *pipe = PORT_TO_PIPE(tmp); |
86 | 87 | ||
87 | return true; |
88 | return true; |
88 | } |
89 | } |
89 | 90 | ||
90 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
91 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
91 | { |
92 | { |
92 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
93 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
93 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
94 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
94 | u32 tmp, flags = 0; |
95 | u32 tmp, flags = 0; |
95 | 96 | ||
96 | tmp = I915_READ(crt->adpa_reg); |
97 | tmp = I915_READ(crt->adpa_reg); |
97 | 98 | ||
98 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
99 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
99 | flags |= DRM_MODE_FLAG_PHSYNC; |
100 | flags |= DRM_MODE_FLAG_PHSYNC; |
100 | else |
101 | else |
101 | flags |= DRM_MODE_FLAG_NHSYNC; |
102 | flags |= DRM_MODE_FLAG_NHSYNC; |
102 | 103 | ||
103 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
104 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
104 | flags |= DRM_MODE_FLAG_PVSYNC; |
105 | flags |= DRM_MODE_FLAG_PVSYNC; |
105 | else |
106 | else |
106 | flags |= DRM_MODE_FLAG_NVSYNC; |
107 | flags |= DRM_MODE_FLAG_NVSYNC; |
107 | 108 | ||
108 | return flags; |
109 | return flags; |
109 | } |
110 | } |
110 | 111 | ||
111 | static void intel_crt_get_config(struct intel_encoder *encoder, |
112 | static void intel_crt_get_config(struct intel_encoder *encoder, |
112 | struct intel_crtc_config *pipe_config) |
113 | struct intel_crtc_config *pipe_config) |
113 | { |
114 | { |
114 | struct drm_device *dev = encoder->base.dev; |
115 | struct drm_device *dev = encoder->base.dev; |
115 | int dotclock; |
116 | int dotclock; |
116 | 117 | ||
117 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
118 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
118 | 119 | ||
119 | dotclock = pipe_config->port_clock; |
120 | dotclock = pipe_config->port_clock; |
120 | 121 | ||
121 | if (HAS_PCH_SPLIT(dev)) |
122 | if (HAS_PCH_SPLIT(dev)) |
122 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
123 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
123 | 124 | ||
124 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
125 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
125 | } |
126 | } |
126 | 127 | ||
127 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
128 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
128 | struct intel_crtc_config *pipe_config) |
129 | struct intel_crtc_config *pipe_config) |
129 | { |
130 | { |
130 | intel_ddi_get_config(encoder, pipe_config); |
131 | intel_ddi_get_config(encoder, pipe_config); |
131 | 132 | ||
132 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
133 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
133 | DRM_MODE_FLAG_NHSYNC | |
134 | DRM_MODE_FLAG_NHSYNC | |
134 | DRM_MODE_FLAG_PVSYNC | |
135 | DRM_MODE_FLAG_PVSYNC | |
135 | DRM_MODE_FLAG_NVSYNC); |
136 | DRM_MODE_FLAG_NVSYNC); |
136 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
137 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
137 | } |
138 | } |
138 | 139 | ||
139 | static void hsw_crt_pre_enable(struct intel_encoder *encoder) |
140 | static void hsw_crt_pre_enable(struct intel_encoder *encoder) |
140 | { |
141 | { |
141 | struct drm_device *dev = encoder->base.dev; |
142 | struct drm_device *dev = encoder->base.dev; |
142 | struct drm_i915_private *dev_priv = dev->dev_private; |
143 | struct drm_i915_private *dev_priv = dev->dev_private; |
143 | 144 | ||
144 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); |
145 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); |
145 | I915_WRITE(SPLL_CTL, |
146 | I915_WRITE(SPLL_CTL, |
146 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); |
147 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); |
147 | POSTING_READ(SPLL_CTL); |
148 | POSTING_READ(SPLL_CTL); |
148 | udelay(20); |
149 | udelay(20); |
149 | } |
150 | } |
150 | 151 | ||
151 | /* Note: The caller is required to filter out dpms modes not supported by the |
152 | /* Note: The caller is required to filter out dpms modes not supported by the |
152 | * platform. */ |
153 | * platform. */ |
153 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
154 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
154 | { |
155 | { |
155 | struct drm_device *dev = encoder->base.dev; |
156 | struct drm_device *dev = encoder->base.dev; |
156 | struct drm_i915_private *dev_priv = dev->dev_private; |
157 | struct drm_i915_private *dev_priv = dev->dev_private; |
157 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
158 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
158 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
159 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
159 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
160 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
160 | u32 adpa; |
161 | u32 adpa; |
161 | 162 | ||
162 | if (INTEL_INFO(dev)->gen >= 5) |
163 | if (INTEL_INFO(dev)->gen >= 5) |
163 | adpa = ADPA_HOTPLUG_BITS; |
164 | adpa = ADPA_HOTPLUG_BITS; |
164 | else |
165 | else |
165 | adpa = 0; |
166 | adpa = 0; |
166 | 167 | ||
167 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
168 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
168 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
169 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
170 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
170 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
171 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
171 | 172 | ||
172 | /* For CPT allow 3 pipe config, for others just use A or B */ |
173 | /* For CPT allow 3 pipe config, for others just use A or B */ |
173 | if (HAS_PCH_LPT(dev)) |
174 | if (HAS_PCH_LPT(dev)) |
174 | ; /* Those bits don't exist here */ |
175 | ; /* Those bits don't exist here */ |
175 | else if (HAS_PCH_CPT(dev)) |
176 | else if (HAS_PCH_CPT(dev)) |
176 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
177 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
177 | else if (crtc->pipe == 0) |
178 | else if (crtc->pipe == 0) |
178 | adpa |= ADPA_PIPE_A_SELECT; |
179 | adpa |= ADPA_PIPE_A_SELECT; |
179 | else |
180 | else |
180 | adpa |= ADPA_PIPE_B_SELECT; |
181 | adpa |= ADPA_PIPE_B_SELECT; |
181 | 182 | ||
182 | if (!HAS_PCH_SPLIT(dev)) |
183 | if (!HAS_PCH_SPLIT(dev)) |
183 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
184 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
184 | 185 | ||
185 | switch (mode) { |
186 | switch (mode) { |
186 | case DRM_MODE_DPMS_ON: |
187 | case DRM_MODE_DPMS_ON: |
187 | adpa |= ADPA_DAC_ENABLE; |
188 | adpa |= ADPA_DAC_ENABLE; |
188 | break; |
189 | break; |
189 | case DRM_MODE_DPMS_STANDBY: |
190 | case DRM_MODE_DPMS_STANDBY: |
190 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
191 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
191 | break; |
192 | break; |
192 | case DRM_MODE_DPMS_SUSPEND: |
193 | case DRM_MODE_DPMS_SUSPEND: |
193 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
194 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
194 | break; |
195 | break; |
195 | case DRM_MODE_DPMS_OFF: |
196 | case DRM_MODE_DPMS_OFF: |
196 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
197 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
197 | break; |
198 | break; |
198 | } |
199 | } |
199 | 200 | ||
200 | I915_WRITE(crt->adpa_reg, adpa); |
201 | I915_WRITE(crt->adpa_reg, adpa); |
201 | } |
202 | } |
202 | 203 | ||
203 | static void intel_disable_crt(struct intel_encoder *encoder) |
204 | static void intel_disable_crt(struct intel_encoder *encoder) |
204 | { |
205 | { |
205 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
206 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
206 | } |
207 | } |
207 | 208 | ||
208 | 209 | ||
209 | static void hsw_crt_post_disable(struct intel_encoder *encoder) |
210 | static void hsw_crt_post_disable(struct intel_encoder *encoder) |
210 | { |
211 | { |
211 | struct drm_device *dev = encoder->base.dev; |
212 | struct drm_device *dev = encoder->base.dev; |
212 | struct drm_i915_private *dev_priv = dev->dev_private; |
213 | struct drm_i915_private *dev_priv = dev->dev_private; |
213 | uint32_t val; |
214 | uint32_t val; |
214 | 215 | ||
215 | DRM_DEBUG_KMS("Disabling SPLL\n"); |
216 | DRM_DEBUG_KMS("Disabling SPLL\n"); |
216 | val = I915_READ(SPLL_CTL); |
217 | val = I915_READ(SPLL_CTL); |
217 | WARN_ON(!(val & SPLL_PLL_ENABLE)); |
218 | WARN_ON(!(val & SPLL_PLL_ENABLE)); |
218 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
219 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
219 | POSTING_READ(SPLL_CTL); |
220 | POSTING_READ(SPLL_CTL); |
220 | } |
221 | } |
221 | 222 | ||
222 | static void intel_enable_crt(struct intel_encoder *encoder) |
223 | static void intel_enable_crt(struct intel_encoder *encoder) |
223 | { |
224 | { |
224 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225 | 226 | ||
226 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
227 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
227 | } |
228 | } |
228 | 229 | ||
229 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
230 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
230 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
231 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
231 | { |
232 | { |
232 | struct drm_device *dev = connector->dev; |
233 | struct drm_device *dev = connector->dev; |
233 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
234 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
234 | struct drm_crtc *crtc; |
235 | struct drm_crtc *crtc; |
235 | int old_dpms; |
236 | int old_dpms; |
236 | 237 | ||
237 | /* PCH platforms and VLV only support on/off. */ |
238 | /* PCH platforms and VLV only support on/off. */ |
238 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
239 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
239 | mode = DRM_MODE_DPMS_OFF; |
240 | mode = DRM_MODE_DPMS_OFF; |
240 | 241 | ||
241 | if (mode == connector->dpms) |
242 | if (mode == connector->dpms) |
242 | return; |
243 | return; |
243 | 244 | ||
244 | old_dpms = connector->dpms; |
245 | old_dpms = connector->dpms; |
245 | connector->dpms = mode; |
246 | connector->dpms = mode; |
246 | 247 | ||
247 | /* Only need to change hw state when actually enabled */ |
248 | /* Only need to change hw state when actually enabled */ |
248 | crtc = encoder->base.crtc; |
249 | crtc = encoder->base.crtc; |
249 | if (!crtc) { |
250 | if (!crtc) { |
250 | encoder->connectors_active = false; |
251 | encoder->connectors_active = false; |
251 | return; |
252 | return; |
252 | } |
253 | } |
253 | 254 | ||
254 | /* We need the pipe to run for anything but OFF. */ |
255 | /* We need the pipe to run for anything but OFF. */ |
255 | if (mode == DRM_MODE_DPMS_OFF) |
256 | if (mode == DRM_MODE_DPMS_OFF) |
256 | encoder->connectors_active = false; |
257 | encoder->connectors_active = false; |
257 | else |
258 | else |
258 | encoder->connectors_active = true; |
259 | encoder->connectors_active = true; |
259 | 260 | ||
260 | /* We call connector dpms manually below in case pipe dpms doesn't |
261 | /* We call connector dpms manually below in case pipe dpms doesn't |
261 | * change due to cloning. */ |
262 | * change due to cloning. */ |
262 | if (mode < old_dpms) { |
263 | if (mode < old_dpms) { |
263 | /* From off to on, enable the pipe first. */ |
264 | /* From off to on, enable the pipe first. */ |
264 | intel_crtc_update_dpms(crtc); |
265 | intel_crtc_update_dpms(crtc); |
265 | 266 | ||
266 | intel_crt_set_dpms(encoder, mode); |
267 | intel_crt_set_dpms(encoder, mode); |
267 | } else { |
268 | } else { |
268 | intel_crt_set_dpms(encoder, mode); |
269 | intel_crt_set_dpms(encoder, mode); |
269 | 270 | ||
270 | intel_crtc_update_dpms(crtc); |
271 | intel_crtc_update_dpms(crtc); |
271 | } |
272 | } |
272 | 273 | ||
273 | intel_modeset_check_state(connector->dev); |
274 | intel_modeset_check_state(connector->dev); |
274 | } |
275 | } |
275 | 276 | ||
276 | static enum drm_mode_status |
277 | static enum drm_mode_status |
277 | intel_crt_mode_valid(struct drm_connector *connector, |
278 | intel_crt_mode_valid(struct drm_connector *connector, |
278 | struct drm_display_mode *mode) |
279 | struct drm_display_mode *mode) |
279 | { |
280 | { |
280 | struct drm_device *dev = connector->dev; |
281 | struct drm_device *dev = connector->dev; |
281 | 282 | ||
282 | int max_clock = 0; |
283 | int max_clock = 0; |
283 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
284 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
284 | return MODE_NO_DBLESCAN; |
285 | return MODE_NO_DBLESCAN; |
285 | 286 | ||
286 | if (mode->clock < 25000) |
287 | if (mode->clock < 25000) |
287 | return MODE_CLOCK_LOW; |
288 | return MODE_CLOCK_LOW; |
288 | 289 | ||
289 | if (IS_GEN2(dev)) |
290 | if (IS_GEN2(dev)) |
290 | max_clock = 350000; |
291 | max_clock = 350000; |
291 | else |
292 | else |
292 | max_clock = 400000; |
293 | max_clock = 400000; |
293 | if (mode->clock > max_clock) |
294 | if (mode->clock > max_clock) |
294 | return MODE_CLOCK_HIGH; |
295 | return MODE_CLOCK_HIGH; |
295 | 296 | ||
296 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
297 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
297 | if (HAS_PCH_LPT(dev) && |
298 | if (HAS_PCH_LPT(dev) && |
298 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
299 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
299 | return MODE_CLOCK_HIGH; |
300 | return MODE_CLOCK_HIGH; |
300 | 301 | ||
301 | return MODE_OK; |
302 | return MODE_OK; |
302 | } |
303 | } |
303 | 304 | ||
304 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
305 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
305 | struct intel_crtc_config *pipe_config) |
306 | struct intel_crtc_config *pipe_config) |
306 | { |
307 | { |
307 | struct drm_device *dev = encoder->base.dev; |
308 | struct drm_device *dev = encoder->base.dev; |
308 | 309 | ||
309 | if (HAS_PCH_SPLIT(dev)) |
310 | if (HAS_PCH_SPLIT(dev)) |
310 | pipe_config->has_pch_encoder = true; |
311 | pipe_config->has_pch_encoder = true; |
311 | 312 | ||
312 | /* LPT FDI RX only supports 8bpc. */ |
313 | /* LPT FDI RX only supports 8bpc. */ |
313 | if (HAS_PCH_LPT(dev)) |
314 | if (HAS_PCH_LPT(dev)) |
314 | pipe_config->pipe_bpp = 24; |
315 | pipe_config->pipe_bpp = 24; |
315 | 316 | ||
316 | /* FDI must always be 2.7 GHz */ |
317 | /* FDI must always be 2.7 GHz */ |
317 | if (HAS_DDI(dev)) { |
318 | if (HAS_DDI(dev)) { |
318 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
319 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
319 | pipe_config->port_clock = 135000 * 2; |
320 | pipe_config->port_clock = 135000 * 2; |
320 | } |
321 | } |
321 | 322 | ||
322 | return true; |
323 | return true; |
323 | } |
324 | } |
324 | 325 | ||
325 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
326 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
326 | { |
327 | { |
327 | struct drm_device *dev = connector->dev; |
328 | struct drm_device *dev = connector->dev; |
328 | struct intel_crt *crt = intel_attached_crt(connector); |
329 | struct intel_crt *crt = intel_attached_crt(connector); |
329 | struct drm_i915_private *dev_priv = dev->dev_private; |
330 | struct drm_i915_private *dev_priv = dev->dev_private; |
330 | u32 adpa; |
331 | u32 adpa; |
331 | bool ret; |
332 | bool ret; |
332 | 333 | ||
333 | /* The first time through, trigger an explicit detection cycle */ |
334 | /* The first time through, trigger an explicit detection cycle */ |
334 | if (crt->force_hotplug_required) { |
335 | if (crt->force_hotplug_required) { |
335 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
336 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
336 | u32 save_adpa; |
337 | u32 save_adpa; |
337 | 338 | ||
338 | crt->force_hotplug_required = 0; |
339 | crt->force_hotplug_required = 0; |
339 | 340 | ||
340 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
341 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
341 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
342 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
342 | 343 | ||
343 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
344 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
344 | if (turn_off_dac) |
345 | if (turn_off_dac) |
345 | adpa &= ~ADPA_DAC_ENABLE; |
346 | adpa &= ~ADPA_DAC_ENABLE; |
346 | 347 | ||
347 | I915_WRITE(crt->adpa_reg, adpa); |
348 | I915_WRITE(crt->adpa_reg, adpa); |
348 | 349 | ||
349 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
350 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
350 | 1000)) |
351 | 1000)) |
351 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
352 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
352 | 353 | ||
353 | if (turn_off_dac) { |
354 | if (turn_off_dac) { |
354 | I915_WRITE(crt->adpa_reg, save_adpa); |
355 | I915_WRITE(crt->adpa_reg, save_adpa); |
355 | POSTING_READ(crt->adpa_reg); |
356 | POSTING_READ(crt->adpa_reg); |
356 | } |
357 | } |
357 | } |
358 | } |
358 | 359 | ||
359 | /* Check the status to see if both blue and green are on now */ |
360 | /* Check the status to see if both blue and green are on now */ |
360 | adpa = I915_READ(crt->adpa_reg); |
361 | adpa = I915_READ(crt->adpa_reg); |
361 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
362 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
362 | ret = true; |
363 | ret = true; |
363 | else |
364 | else |
364 | ret = false; |
365 | ret = false; |
365 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
366 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
366 | 367 | ||
367 | return ret; |
368 | return ret; |
368 | } |
369 | } |
369 | 370 | ||
370 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
371 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
371 | { |
372 | { |
372 | struct drm_device *dev = connector->dev; |
373 | struct drm_device *dev = connector->dev; |
373 | struct intel_crt *crt = intel_attached_crt(connector); |
374 | struct intel_crt *crt = intel_attached_crt(connector); |
374 | struct drm_i915_private *dev_priv = dev->dev_private; |
375 | struct drm_i915_private *dev_priv = dev->dev_private; |
375 | u32 adpa; |
376 | u32 adpa; |
376 | bool ret; |
377 | bool ret; |
377 | u32 save_adpa; |
378 | u32 save_adpa; |
378 | 379 | ||
379 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
380 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
380 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
381 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
381 | 382 | ||
382 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
383 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
383 | 384 | ||
384 | I915_WRITE(crt->adpa_reg, adpa); |
385 | I915_WRITE(crt->adpa_reg, adpa); |
385 | 386 | ||
386 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
387 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
387 | 1000)) { |
388 | 1000)) { |
388 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
389 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
389 | I915_WRITE(crt->adpa_reg, save_adpa); |
390 | I915_WRITE(crt->adpa_reg, save_adpa); |
390 | } |
391 | } |
391 | 392 | ||
392 | /* Check the status to see if both blue and green are on now */ |
393 | /* Check the status to see if both blue and green are on now */ |
393 | adpa = I915_READ(crt->adpa_reg); |
394 | adpa = I915_READ(crt->adpa_reg); |
394 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
395 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
395 | ret = true; |
396 | ret = true; |
396 | else |
397 | else |
397 | ret = false; |
398 | ret = false; |
398 | 399 | ||
399 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
400 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
400 | 401 | ||
401 | return ret; |
402 | return ret; |
402 | } |
403 | } |
403 | 404 | ||
404 | /** |
405 | /** |
405 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
406 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
406 | * |
407 | * |
407 | * Not for i915G/i915GM |
408 | * Not for i915G/i915GM |
408 | * |
409 | * |
409 | * \return true if CRT is connected. |
410 | * \return true if CRT is connected. |
410 | * \return false if CRT is disconnected. |
411 | * \return false if CRT is disconnected. |
411 | */ |
412 | */ |
412 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
413 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
413 | { |
414 | { |
414 | struct drm_device *dev = connector->dev; |
415 | struct drm_device *dev = connector->dev; |
415 | struct drm_i915_private *dev_priv = dev->dev_private; |
416 | struct drm_i915_private *dev_priv = dev->dev_private; |
416 | u32 hotplug_en, orig, stat; |
417 | u32 hotplug_en, orig, stat; |
417 | bool ret = false; |
418 | bool ret = false; |
418 | int i, tries = 0; |
419 | int i, tries = 0; |
419 | 420 | ||
420 | if (HAS_PCH_SPLIT(dev)) |
421 | if (HAS_PCH_SPLIT(dev)) |
421 | return intel_ironlake_crt_detect_hotplug(connector); |
422 | return intel_ironlake_crt_detect_hotplug(connector); |
422 | 423 | ||
423 | if (IS_VALLEYVIEW(dev)) |
424 | if (IS_VALLEYVIEW(dev)) |
424 | return valleyview_crt_detect_hotplug(connector); |
425 | return valleyview_crt_detect_hotplug(connector); |
425 | 426 | ||
426 | /* |
427 | /* |
427 | * On 4 series desktop, CRT detect sequence need to be done twice |
428 | * On 4 series desktop, CRT detect sequence need to be done twice |
428 | * to get a reliable result. |
429 | * to get a reliable result. |
429 | */ |
430 | */ |
430 | 431 | ||
431 | if (IS_G4X(dev) && !IS_GM45(dev)) |
432 | if (IS_G4X(dev) && !IS_GM45(dev)) |
432 | tries = 2; |
433 | tries = 2; |
433 | else |
434 | else |
434 | tries = 1; |
435 | tries = 1; |
435 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
436 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
436 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
437 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
437 | 438 | ||
438 | for (i = 0; i < tries ; i++) { |
439 | for (i = 0; i < tries ; i++) { |
439 | /* turn on the FORCE_DETECT */ |
440 | /* turn on the FORCE_DETECT */ |
440 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
441 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
441 | /* wait for FORCE_DETECT to go off */ |
442 | /* wait for FORCE_DETECT to go off */ |
442 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
443 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
443 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
444 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
444 | 1000)) |
445 | 1000)) |
445 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
446 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
446 | } |
447 | } |
447 | 448 | ||
448 | stat = I915_READ(PORT_HOTPLUG_STAT); |
449 | stat = I915_READ(PORT_HOTPLUG_STAT); |
449 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
450 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
450 | ret = true; |
451 | ret = true; |
451 | 452 | ||
452 | /* clear the interrupt we just generated, if any */ |
453 | /* clear the interrupt we just generated, if any */ |
453 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
454 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
454 | 455 | ||
455 | /* and put the bits back */ |
456 | /* and put the bits back */ |
456 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
457 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
457 | 458 | ||
458 | return ret; |
459 | return ret; |
459 | } |
460 | } |
460 | 461 | ||
461 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
462 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
462 | struct i2c_adapter *i2c) |
463 | struct i2c_adapter *i2c) |
463 | { |
464 | { |
464 | struct edid *edid; |
465 | struct edid *edid; |
465 | 466 | ||
466 | edid = drm_get_edid(connector, i2c); |
467 | edid = drm_get_edid(connector, i2c); |
467 | 468 | ||
468 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
469 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
469 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
470 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
470 | intel_gmbus_force_bit(i2c, true); |
471 | intel_gmbus_force_bit(i2c, true); |
471 | edid = drm_get_edid(connector, i2c); |
472 | edid = drm_get_edid(connector, i2c); |
472 | intel_gmbus_force_bit(i2c, false); |
473 | intel_gmbus_force_bit(i2c, false); |
473 | } |
474 | } |
474 | 475 | ||
475 | return edid; |
476 | return edid; |
476 | } |
477 | } |
477 | 478 | ||
478 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
479 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
479 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
480 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
480 | struct i2c_adapter *adapter) |
481 | struct i2c_adapter *adapter) |
481 | { |
482 | { |
482 | struct edid *edid; |
483 | struct edid *edid; |
483 | int ret; |
484 | int ret; |
484 | 485 | ||
485 | edid = intel_crt_get_edid(connector, adapter); |
486 | edid = intel_crt_get_edid(connector, adapter); |
486 | if (!edid) |
487 | if (!edid) |
487 | return 0; |
488 | return 0; |
488 | 489 | ||
489 | ret = intel_connector_update_modes(connector, edid); |
490 | ret = intel_connector_update_modes(connector, edid); |
490 | kfree(edid); |
491 | kfree(edid); |
491 | 492 | ||
492 | return ret; |
493 | return ret; |
493 | } |
494 | } |
494 | 495 | ||
495 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
496 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
496 | { |
497 | { |
497 | struct intel_crt *crt = intel_attached_crt(connector); |
498 | struct intel_crt *crt = intel_attached_crt(connector); |
498 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
499 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
499 | struct edid *edid; |
500 | struct edid *edid; |
500 | struct i2c_adapter *i2c; |
501 | struct i2c_adapter *i2c; |
501 | 502 | ||
502 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
503 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
503 | 504 | ||
504 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
505 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
505 | edid = intel_crt_get_edid(connector, i2c); |
506 | edid = intel_crt_get_edid(connector, i2c); |
506 | 507 | ||
507 | if (edid) { |
508 | if (edid) { |
508 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
509 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
509 | 510 | ||
510 | /* |
511 | /* |
511 | * This may be a DVI-I connector with a shared DDC |
512 | * This may be a DVI-I connector with a shared DDC |
512 | * link between analog and digital outputs, so we |
513 | * link between analog and digital outputs, so we |
513 | * have to check the EDID input spec of the attached device. |
514 | * have to check the EDID input spec of the attached device. |
514 | */ |
515 | */ |
515 | if (!is_digital) { |
516 | if (!is_digital) { |
516 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
517 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
517 | return true; |
518 | return true; |
518 | } |
519 | } |
519 | 520 | ||
520 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
521 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
521 | } else { |
522 | } else { |
522 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
523 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
523 | } |
524 | } |
524 | 525 | ||
525 | kfree(edid); |
526 | kfree(edid); |
526 | 527 | ||
527 | return false; |
528 | return false; |
528 | } |
529 | } |
529 | 530 | ||
530 | static enum drm_connector_status |
531 | static enum drm_connector_status |
531 | intel_crt_load_detect(struct intel_crt *crt) |
532 | intel_crt_load_detect(struct intel_crt *crt) |
532 | { |
533 | { |
533 | struct drm_device *dev = crt->base.base.dev; |
534 | struct drm_device *dev = crt->base.base.dev; |
534 | struct drm_i915_private *dev_priv = dev->dev_private; |
535 | struct drm_i915_private *dev_priv = dev->dev_private; |
535 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
536 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
536 | uint32_t save_bclrpat; |
537 | uint32_t save_bclrpat; |
537 | uint32_t save_vtotal; |
538 | uint32_t save_vtotal; |
538 | uint32_t vtotal, vactive; |
539 | uint32_t vtotal, vactive; |
539 | uint32_t vsample; |
540 | uint32_t vsample; |
540 | uint32_t vblank, vblank_start, vblank_end; |
541 | uint32_t vblank, vblank_start, vblank_end; |
541 | uint32_t dsl; |
542 | uint32_t dsl; |
542 | uint32_t bclrpat_reg; |
543 | uint32_t bclrpat_reg; |
543 | uint32_t vtotal_reg; |
544 | uint32_t vtotal_reg; |
544 | uint32_t vblank_reg; |
545 | uint32_t vblank_reg; |
545 | uint32_t vsync_reg; |
546 | uint32_t vsync_reg; |
546 | uint32_t pipeconf_reg; |
547 | uint32_t pipeconf_reg; |
547 | uint32_t pipe_dsl_reg; |
548 | uint32_t pipe_dsl_reg; |
548 | uint8_t st00; |
549 | uint8_t st00; |
549 | enum drm_connector_status status; |
550 | enum drm_connector_status status; |
550 | 551 | ||
551 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
552 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
552 | 553 | ||
553 | bclrpat_reg = BCLRPAT(pipe); |
554 | bclrpat_reg = BCLRPAT(pipe); |
554 | vtotal_reg = VTOTAL(pipe); |
555 | vtotal_reg = VTOTAL(pipe); |
555 | vblank_reg = VBLANK(pipe); |
556 | vblank_reg = VBLANK(pipe); |
556 | vsync_reg = VSYNC(pipe); |
557 | vsync_reg = VSYNC(pipe); |
557 | pipeconf_reg = PIPECONF(pipe); |
558 | pipeconf_reg = PIPECONF(pipe); |
558 | pipe_dsl_reg = PIPEDSL(pipe); |
559 | pipe_dsl_reg = PIPEDSL(pipe); |
559 | 560 | ||
560 | save_bclrpat = I915_READ(bclrpat_reg); |
561 | save_bclrpat = I915_READ(bclrpat_reg); |
561 | save_vtotal = I915_READ(vtotal_reg); |
562 | save_vtotal = I915_READ(vtotal_reg); |
562 | vblank = I915_READ(vblank_reg); |
563 | vblank = I915_READ(vblank_reg); |
563 | 564 | ||
564 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
565 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
565 | vactive = (save_vtotal & 0x7ff) + 1; |
566 | vactive = (save_vtotal & 0x7ff) + 1; |
566 | 567 | ||
567 | vblank_start = (vblank & 0xfff) + 1; |
568 | vblank_start = (vblank & 0xfff) + 1; |
568 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
569 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
569 | 570 | ||
570 | /* Set the border color to purple. */ |
571 | /* Set the border color to purple. */ |
571 | I915_WRITE(bclrpat_reg, 0x500050); |
572 | I915_WRITE(bclrpat_reg, 0x500050); |
572 | 573 | ||
573 | if (!IS_GEN2(dev)) { |
574 | if (!IS_GEN2(dev)) { |
574 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
575 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
575 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
576 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
576 | POSTING_READ(pipeconf_reg); |
577 | POSTING_READ(pipeconf_reg); |
577 | /* Wait for next Vblank to substitue |
578 | /* Wait for next Vblank to substitue |
578 | * border color for Color info */ |
579 | * border color for Color info */ |
579 | intel_wait_for_vblank(dev, pipe); |
580 | intel_wait_for_vblank(dev, pipe); |
580 | st00 = I915_READ8(VGA_MSR_WRITE); |
581 | st00 = I915_READ8(VGA_MSR_WRITE); |
581 | status = ((st00 & (1 << 4)) != 0) ? |
582 | status = ((st00 & (1 << 4)) != 0) ? |
582 | connector_status_connected : |
583 | connector_status_connected : |
583 | connector_status_disconnected; |
584 | connector_status_disconnected; |
584 | 585 | ||
585 | I915_WRITE(pipeconf_reg, pipeconf); |
586 | I915_WRITE(pipeconf_reg, pipeconf); |
586 | } else { |
587 | } else { |
587 | bool restore_vblank = false; |
588 | bool restore_vblank = false; |
588 | int count, detect; |
589 | int count, detect; |
589 | 590 | ||
590 | /* |
591 | /* |
591 | * If there isn't any border, add some. |
592 | * If there isn't any border, add some. |
592 | * Yes, this will flicker |
593 | * Yes, this will flicker |
593 | */ |
594 | */ |
594 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
595 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
595 | uint32_t vsync = I915_READ(vsync_reg); |
596 | uint32_t vsync = I915_READ(vsync_reg); |
596 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
597 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
597 | 598 | ||
598 | vblank_start = vsync_start; |
599 | vblank_start = vsync_start; |
599 | I915_WRITE(vblank_reg, |
600 | I915_WRITE(vblank_reg, |
600 | (vblank_start - 1) | |
601 | (vblank_start - 1) | |
601 | ((vblank_end - 1) << 16)); |
602 | ((vblank_end - 1) << 16)); |
602 | restore_vblank = true; |
603 | restore_vblank = true; |
603 | } |
604 | } |
604 | /* sample in the vertical border, selecting the larger one */ |
605 | /* sample in the vertical border, selecting the larger one */ |
605 | if (vblank_start - vactive >= vtotal - vblank_end) |
606 | if (vblank_start - vactive >= vtotal - vblank_end) |
606 | vsample = (vblank_start + vactive) >> 1; |
607 | vsample = (vblank_start + vactive) >> 1; |
607 | else |
608 | else |
608 | vsample = (vtotal + vblank_end) >> 1; |
609 | vsample = (vtotal + vblank_end) >> 1; |
609 | 610 | ||
610 | /* |
611 | /* |
611 | * Wait for the border to be displayed |
612 | * Wait for the border to be displayed |
612 | */ |
613 | */ |
613 | while (I915_READ(pipe_dsl_reg) >= vactive) |
614 | while (I915_READ(pipe_dsl_reg) >= vactive) |
614 | ; |
615 | ; |
615 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
616 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
616 | ; |
617 | ; |
617 | /* |
618 | /* |
618 | * Watch ST00 for an entire scanline |
619 | * Watch ST00 for an entire scanline |
619 | */ |
620 | */ |
620 | detect = 0; |
621 | detect = 0; |
621 | count = 0; |
622 | count = 0; |
622 | do { |
623 | do { |
623 | count++; |
624 | count++; |
624 | /* Read the ST00 VGA status register */ |
625 | /* Read the ST00 VGA status register */ |
625 | st00 = I915_READ8(VGA_MSR_WRITE); |
626 | st00 = I915_READ8(VGA_MSR_WRITE); |
626 | if (st00 & (1 << 4)) |
627 | if (st00 & (1 << 4)) |
627 | detect++; |
628 | detect++; |
628 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
629 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
629 | 630 | ||
630 | /* restore vblank if necessary */ |
631 | /* restore vblank if necessary */ |
631 | if (restore_vblank) |
632 | if (restore_vblank) |
632 | I915_WRITE(vblank_reg, vblank); |
633 | I915_WRITE(vblank_reg, vblank); |
633 | /* |
634 | /* |
634 | * If more than 3/4 of the scanline detected a monitor, |
635 | * If more than 3/4 of the scanline detected a monitor, |
635 | * then it is assumed to be present. This works even on i830, |
636 | * then it is assumed to be present. This works even on i830, |
636 | * where there isn't any way to force the border color across |
637 | * where there isn't any way to force the border color across |
637 | * the screen |
638 | * the screen |
638 | */ |
639 | */ |
639 | status = detect * 4 > count * 3 ? |
640 | status = detect * 4 > count * 3 ? |
640 | connector_status_connected : |
641 | connector_status_connected : |
641 | connector_status_disconnected; |
642 | connector_status_disconnected; |
642 | } |
643 | } |
643 | 644 | ||
644 | /* Restore previous settings */ |
645 | /* Restore previous settings */ |
645 | I915_WRITE(bclrpat_reg, save_bclrpat); |
646 | I915_WRITE(bclrpat_reg, save_bclrpat); |
646 | 647 | ||
647 | return status; |
648 | return status; |
648 | } |
649 | } |
649 | 650 | ||
650 | static enum drm_connector_status |
651 | static enum drm_connector_status |
651 | intel_crt_detect(struct drm_connector *connector, bool force) |
652 | intel_crt_detect(struct drm_connector *connector, bool force) |
652 | { |
653 | { |
653 | struct drm_device *dev = connector->dev; |
654 | struct drm_device *dev = connector->dev; |
654 | struct drm_i915_private *dev_priv = dev->dev_private; |
655 | struct drm_i915_private *dev_priv = dev->dev_private; |
655 | struct intel_crt *crt = intel_attached_crt(connector); |
656 | struct intel_crt *crt = intel_attached_crt(connector); |
656 | struct intel_encoder *intel_encoder = &crt->base; |
657 | struct intel_encoder *intel_encoder = &crt->base; |
657 | enum intel_display_power_domain power_domain; |
658 | enum intel_display_power_domain power_domain; |
658 | enum drm_connector_status status; |
659 | enum drm_connector_status status; |
659 | struct intel_load_detect_pipe tmp; |
660 | struct intel_load_detect_pipe tmp; |
660 | struct drm_modeset_acquire_ctx ctx; |
661 | struct drm_modeset_acquire_ctx ctx; |
661 | 662 | ||
662 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
663 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
663 | connector->base.id, connector->name, |
664 | connector->base.id, connector->name, |
664 | force); |
665 | force); |
665 | 666 | ||
666 | power_domain = intel_display_port_power_domain(intel_encoder); |
667 | power_domain = intel_display_port_power_domain(intel_encoder); |
667 | intel_display_power_get(dev_priv, power_domain); |
668 | intel_display_power_get(dev_priv, power_domain); |
668 | 669 | ||
669 | if (I915_HAS_HOTPLUG(dev)) { |
670 | if (I915_HAS_HOTPLUG(dev)) { |
670 | /* We can not rely on the HPD pin always being correctly wired |
671 | /* We can not rely on the HPD pin always being correctly wired |
671 | * up, for example many KVM do not pass it through, and so |
672 | * up, for example many KVM do not pass it through, and so |
672 | * only trust an assertion that the monitor is connected. |
673 | * only trust an assertion that the monitor is connected. |
673 | */ |
674 | */ |
674 | if (intel_crt_detect_hotplug(connector)) { |
675 | if (intel_crt_detect_hotplug(connector)) { |
675 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
676 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
676 | status = connector_status_connected; |
677 | status = connector_status_connected; |
677 | goto out; |
678 | goto out; |
678 | } else |
679 | } else |
679 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
680 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
680 | } |
681 | } |
681 | 682 | ||
682 | if (intel_crt_detect_ddc(connector)) { |
683 | if (intel_crt_detect_ddc(connector)) { |
683 | status = connector_status_connected; |
684 | status = connector_status_connected; |
684 | goto out; |
685 | goto out; |
685 | } |
686 | } |
686 | 687 | ||
687 | /* Load detection is broken on HPD capable machines. Whoever wants a |
688 | /* Load detection is broken on HPD capable machines. Whoever wants a |
688 | * broken monitor (without edid) to work behind a broken kvm (that fails |
689 | * broken monitor (without edid) to work behind a broken kvm (that fails |
689 | * to have the right resistors for HP detection) needs to fix this up. |
690 | * to have the right resistors for HP detection) needs to fix this up. |
690 | * For now just bail out. */ |
691 | * For now just bail out. */ |
691 | if (I915_HAS_HOTPLUG(dev)) { |
692 | if (I915_HAS_HOTPLUG(dev)) { |
692 | status = connector_status_disconnected; |
693 | status = connector_status_disconnected; |
693 | goto out; |
694 | goto out; |
694 | } |
695 | } |
695 | 696 | ||
696 | if (!force) { |
697 | if (!force) { |
697 | status = connector->status; |
698 | status = connector->status; |
698 | goto out; |
699 | goto out; |
699 | } |
700 | } |
700 | 701 | ||
701 | drm_modeset_acquire_init(&ctx, 0); |
702 | drm_modeset_acquire_init(&ctx, 0); |
702 | 703 | ||
703 | /* for pre-945g platforms use load detect */ |
704 | /* for pre-945g platforms use load detect */ |
704 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
705 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
705 | if (intel_crt_detect_ddc(connector)) |
706 | if (intel_crt_detect_ddc(connector)) |
706 | status = connector_status_connected; |
707 | status = connector_status_connected; |
707 | else |
708 | else |
708 | status = intel_crt_load_detect(crt); |
709 | status = intel_crt_load_detect(crt); |
709 | intel_release_load_detect_pipe(connector, &tmp); |
710 | intel_release_load_detect_pipe(connector, &tmp); |
710 | } else |
711 | } else |
711 | status = connector_status_unknown; |
712 | status = connector_status_unknown; |
712 | 713 | ||
713 | drm_modeset_drop_locks(&ctx); |
714 | drm_modeset_drop_locks(&ctx); |
714 | drm_modeset_acquire_fini(&ctx); |
715 | drm_modeset_acquire_fini(&ctx); |
715 | 716 | ||
716 | out: |
717 | out: |
717 | intel_display_power_put(dev_priv, power_domain); |
718 | intel_display_power_put(dev_priv, power_domain); |
718 | return status; |
719 | return status; |
719 | } |
720 | } |
720 | 721 | ||
721 | static void intel_crt_destroy(struct drm_connector *connector) |
722 | static void intel_crt_destroy(struct drm_connector *connector) |
722 | { |
723 | { |
723 | drm_connector_cleanup(connector); |
724 | drm_connector_cleanup(connector); |
724 | kfree(connector); |
725 | kfree(connector); |
725 | } |
726 | } |
726 | 727 | ||
727 | static int intel_crt_get_modes(struct drm_connector *connector) |
728 | static int intel_crt_get_modes(struct drm_connector *connector) |
728 | { |
729 | { |
729 | struct drm_device *dev = connector->dev; |
730 | struct drm_device *dev = connector->dev; |
730 | struct drm_i915_private *dev_priv = dev->dev_private; |
731 | struct drm_i915_private *dev_priv = dev->dev_private; |
731 | struct intel_crt *crt = intel_attached_crt(connector); |
732 | struct intel_crt *crt = intel_attached_crt(connector); |
732 | struct intel_encoder *intel_encoder = &crt->base; |
733 | struct intel_encoder *intel_encoder = &crt->base; |
733 | enum intel_display_power_domain power_domain; |
734 | enum intel_display_power_domain power_domain; |
734 | int ret; |
735 | int ret; |
735 | struct i2c_adapter *i2c; |
736 | struct i2c_adapter *i2c; |
736 | 737 | ||
737 | power_domain = intel_display_port_power_domain(intel_encoder); |
738 | power_domain = intel_display_port_power_domain(intel_encoder); |
738 | intel_display_power_get(dev_priv, power_domain); |
739 | intel_display_power_get(dev_priv, power_domain); |
739 | 740 | ||
740 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
741 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
741 | ret = intel_crt_ddc_get_modes(connector, i2c); |
742 | ret = intel_crt_ddc_get_modes(connector, i2c); |
742 | if (ret || !IS_G4X(dev)) |
743 | if (ret || !IS_G4X(dev)) |
743 | goto out; |
744 | goto out; |
744 | 745 | ||
745 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
746 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
746 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
747 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
747 | ret = intel_crt_ddc_get_modes(connector, i2c); |
748 | ret = intel_crt_ddc_get_modes(connector, i2c); |
748 | 749 | ||
749 | out: |
750 | out: |
750 | intel_display_power_put(dev_priv, power_domain); |
751 | intel_display_power_put(dev_priv, power_domain); |
751 | 752 | ||
752 | return ret; |
753 | return ret; |
753 | } |
754 | } |
754 | 755 | ||
755 | static int intel_crt_set_property(struct drm_connector *connector, |
756 | static int intel_crt_set_property(struct drm_connector *connector, |
756 | struct drm_property *property, |
757 | struct drm_property *property, |
757 | uint64_t value) |
758 | uint64_t value) |
758 | { |
759 | { |
759 | return 0; |
760 | return 0; |
760 | } |
761 | } |
761 | 762 | ||
762 | static void intel_crt_reset(struct drm_connector *connector) |
763 | static void intel_crt_reset(struct drm_connector *connector) |
763 | { |
764 | { |
764 | struct drm_device *dev = connector->dev; |
765 | struct drm_device *dev = connector->dev; |
765 | struct drm_i915_private *dev_priv = dev->dev_private; |
766 | struct drm_i915_private *dev_priv = dev->dev_private; |
766 | struct intel_crt *crt = intel_attached_crt(connector); |
767 | struct intel_crt *crt = intel_attached_crt(connector); |
767 | 768 | ||
768 | if (INTEL_INFO(dev)->gen >= 5) { |
769 | if (INTEL_INFO(dev)->gen >= 5) { |
769 | u32 adpa; |
770 | u32 adpa; |
770 | 771 | ||
771 | adpa = I915_READ(crt->adpa_reg); |
772 | adpa = I915_READ(crt->adpa_reg); |
772 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
773 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
773 | adpa |= ADPA_HOTPLUG_BITS; |
774 | adpa |= ADPA_HOTPLUG_BITS; |
774 | I915_WRITE(crt->adpa_reg, adpa); |
775 | I915_WRITE(crt->adpa_reg, adpa); |
775 | POSTING_READ(crt->adpa_reg); |
776 | POSTING_READ(crt->adpa_reg); |
776 | 777 | ||
777 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
778 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
778 | crt->force_hotplug_required = 1; |
779 | crt->force_hotplug_required = 1; |
779 | } |
780 | } |
780 | 781 | ||
781 | } |
782 | } |
782 | 783 | ||
783 | /* |
784 | /* |
784 | * Routines for controlling stuff on the analog port |
785 | * Routines for controlling stuff on the analog port |
785 | */ |
786 | */ |
786 | 787 | ||
787 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
788 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
788 | .reset = intel_crt_reset, |
789 | .reset = intel_crt_reset, |
789 | .dpms = intel_crt_dpms, |
790 | .dpms = intel_crt_dpms, |
790 | .detect = intel_crt_detect, |
791 | .detect = intel_crt_detect, |
791 | .fill_modes = drm_helper_probe_single_connector_modes, |
792 | .fill_modes = drm_helper_probe_single_connector_modes, |
792 | .destroy = intel_crt_destroy, |
793 | .destroy = intel_crt_destroy, |
793 | .set_property = intel_crt_set_property, |
794 | .set_property = intel_crt_set_property, |
794 | }; |
795 | }; |
795 | 796 | ||
796 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
797 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
797 | .mode_valid = intel_crt_mode_valid, |
798 | .mode_valid = intel_crt_mode_valid, |
798 | .get_modes = intel_crt_get_modes, |
799 | .get_modes = intel_crt_get_modes, |
799 | .best_encoder = intel_best_encoder, |
800 | .best_encoder = intel_best_encoder, |
800 | }; |
801 | }; |
801 | 802 | ||
802 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
803 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
803 | .destroy = intel_encoder_destroy, |
804 | .destroy = intel_encoder_destroy, |
804 | }; |
805 | }; |
- | 806 | ||
- | 807 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
|
- | 808 | { |
|
- | 809 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
|
- | 810 | return 1; |
|
- | 811 | } |
|
- | 812 | ||
- | 813 | static const struct dmi_system_id intel_no_crt[] = { |
|
- | 814 | { |
|
- | 815 | .callback = intel_no_crt_dmi_callback, |
|
- | 816 | .ident = "ACER ZGB", |
|
- | 817 | .matches = { |
|
- | 818 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
|
- | 819 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
|
- | 820 | }, |
|
- | 821 | }, |
|
- | 822 | { |
|
- | 823 | .callback = intel_no_crt_dmi_callback, |
|
- | 824 | .ident = "DELL XPS 8700", |
|
- | 825 | .matches = { |
|
- | 826 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
|
- | 827 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), |
|
- | 828 | }, |
|
- | 829 | }, |
|
- | 830 | { } |
|
- | 831 | }; |
|
805 | 832 | ||
806 | void intel_crt_init(struct drm_device *dev) |
833 | void intel_crt_init(struct drm_device *dev) |
807 | { |
834 | { |
808 | struct drm_connector *connector; |
835 | struct drm_connector *connector; |
809 | struct intel_crt *crt; |
836 | struct intel_crt *crt; |
810 | struct intel_connector *intel_connector; |
837 | struct intel_connector *intel_connector; |
811 | struct drm_i915_private *dev_priv = dev->dev_private; |
838 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 839 | ||
- | 840 | /* Skip machines without VGA that falsely report hotplug events */ |
|
- | 841 | if (dmi_check_system(intel_no_crt)) |
|
- | 842 | return; |
|
812 | 843 | ||
813 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
844 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
814 | if (!crt) |
845 | if (!crt) |
815 | return; |
846 | return; |
816 | 847 | ||
817 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
848 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
818 | if (!intel_connector) { |
849 | if (!intel_connector) { |
819 | kfree(crt); |
850 | kfree(crt); |
820 | return; |
851 | return; |
821 | } |
852 | } |
822 | 853 | ||
823 | connector = &intel_connector->base; |
854 | connector = &intel_connector->base; |
824 | crt->connector = intel_connector; |
855 | crt->connector = intel_connector; |
825 | drm_connector_init(dev, &intel_connector->base, |
856 | drm_connector_init(dev, &intel_connector->base, |
826 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
857 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
827 | 858 | ||
828 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
859 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
829 | DRM_MODE_ENCODER_DAC); |
860 | DRM_MODE_ENCODER_DAC); |
830 | 861 | ||
831 | intel_connector_attach_encoder(intel_connector, &crt->base); |
862 | intel_connector_attach_encoder(intel_connector, &crt->base); |
832 | 863 | ||
833 | crt->base.type = INTEL_OUTPUT_ANALOG; |
864 | crt->base.type = INTEL_OUTPUT_ANALOG; |
834 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
865 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
835 | if (IS_I830(dev)) |
866 | if (IS_I830(dev)) |
836 | crt->base.crtc_mask = (1 << 0); |
867 | crt->base.crtc_mask = (1 << 0); |
837 | else |
868 | else |
838 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
869 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
839 | 870 | ||
840 | if (IS_GEN2(dev)) |
871 | if (IS_GEN2(dev)) |
841 | connector->interlace_allowed = 0; |
872 | connector->interlace_allowed = 0; |
842 | else |
873 | else |
843 | connector->interlace_allowed = 1; |
874 | connector->interlace_allowed = 1; |
844 | connector->doublescan_allowed = 0; |
875 | connector->doublescan_allowed = 0; |
845 | 876 | ||
846 | if (HAS_PCH_SPLIT(dev)) |
877 | if (HAS_PCH_SPLIT(dev)) |
847 | crt->adpa_reg = PCH_ADPA; |
878 | crt->adpa_reg = PCH_ADPA; |
848 | else if (IS_VALLEYVIEW(dev)) |
879 | else if (IS_VALLEYVIEW(dev)) |
849 | crt->adpa_reg = VLV_ADPA; |
880 | crt->adpa_reg = VLV_ADPA; |
850 | else |
881 | else |
851 | crt->adpa_reg = ADPA; |
882 | crt->adpa_reg = ADPA; |
852 | 883 | ||
853 | crt->base.compute_config = intel_crt_compute_config; |
884 | crt->base.compute_config = intel_crt_compute_config; |
854 | crt->base.disable = intel_disable_crt; |
885 | crt->base.disable = intel_disable_crt; |
855 | crt->base.enable = intel_enable_crt; |
886 | crt->base.enable = intel_enable_crt; |
856 | if (I915_HAS_HOTPLUG(dev)) |
887 | if (I915_HAS_HOTPLUG(dev)) |
857 | crt->base.hpd_pin = HPD_CRT; |
888 | crt->base.hpd_pin = HPD_CRT; |
858 | if (HAS_DDI(dev)) { |
889 | if (HAS_DDI(dev)) { |
859 | crt->base.get_config = hsw_crt_get_config; |
890 | crt->base.get_config = hsw_crt_get_config; |
860 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
891 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
861 | crt->base.pre_enable = hsw_crt_pre_enable; |
892 | crt->base.pre_enable = hsw_crt_pre_enable; |
862 | crt->base.post_disable = hsw_crt_post_disable; |
893 | crt->base.post_disable = hsw_crt_post_disable; |
863 | } else { |
894 | } else { |
864 | crt->base.get_config = intel_crt_get_config; |
895 | crt->base.get_config = intel_crt_get_config; |
865 | crt->base.get_hw_state = intel_crt_get_hw_state; |
896 | crt->base.get_hw_state = intel_crt_get_hw_state; |
866 | } |
897 | } |
867 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
898 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
868 | intel_connector->unregister = intel_connector_unregister; |
899 | intel_connector->unregister = intel_connector_unregister; |
869 | 900 | ||
870 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
901 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
871 | 902 | ||
872 | drm_connector_register(connector); |
903 | drm_connector_register(connector); |
873 | 904 | ||
874 | if (!I915_HAS_HOTPLUG(dev)) |
905 | if (!I915_HAS_HOTPLUG(dev)) |
875 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
906 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
876 | 907 | ||
877 | /* |
908 | /* |
878 | * Configure the automatic hotplug detection stuff |
909 | * Configure the automatic hotplug detection stuff |
879 | */ |
910 | */ |
880 | crt->force_hotplug_required = 0; |
911 | crt->force_hotplug_required = 0; |
881 | 912 | ||
882 | /* |
913 | /* |
883 | * TODO: find a proper way to discover whether we need to set the the |
914 | * TODO: find a proper way to discover whether we need to set the the |
884 | * polarity and link reversal bits or not, instead of relying on the |
915 | * polarity and link reversal bits or not, instead of relying on the |
885 | * BIOS. |
916 | * BIOS. |
886 | */ |
917 | */ |
887 | if (HAS_PCH_LPT(dev)) { |
918 | if (HAS_PCH_LPT(dev)) { |
888 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
919 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
889 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
920 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
890 | 921 | ||
891 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
922 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
892 | } |
923 | } |
893 | 924 | ||
894 | intel_crt_reset(connector); |
925 | intel_crt_reset(connector); |
895 | }><>><>><>><>><>><>><>=>><>=>><>>>> |
926 | }><>><>><>><>><>><>><>=>><>=>><>>>> |