WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_crt.c


/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt 
 */
 
#include 
#include 
#include 
#include 
#include 
#include 
#include "intel_drv.h"
#include 
#include "i915_drv.h"
 
/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
			   ADPA_CRT_HOTPLUG_ENABLE)
 
struct intel_crt {
	struct intel_encoder base;
	/* DPMS state is stored in the connector, which we need in the
	 * encoder's enable/disable callbacks */
	struct intel_connector *connector;
	bool force_hotplug_required;
	u32 adpa_reg;
};
 
static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_crt, base);
}
 
static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
{
	return intel_encoder_to_crt(intel_attached_encoder(connector));
}
 
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	enum intel_display_power_domain power_domain;
	u32 tmp;
 
	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_enabled(dev_priv, power_domain))
		return false;
 
	tmp = I915_READ(crt->adpa_reg);
 
	if (!(tmp & ADPA_DAC_ENABLE))
		return false;
 
	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);
 
	return true;
}
 
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	u32 tmp, flags = 0;
 
	tmp = I915_READ(crt->adpa_reg);
 
	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
 
	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;
 
	return flags;
}
 
static void intel_crt_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = encoder->base.dev;
	int dotclock;
 
	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
	dotclock = pipe_config->port_clock;
 
	if (HAS_PCH_SPLIT(dev))
		ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
	pipe_config->adjusted_mode.crtc_clock = dotclock;
}
 
static void hsw_crt_get_config(struct intel_encoder *encoder,
			       struct intel_crtc_config *pipe_config)
{
	intel_ddi_get_config(encoder, pipe_config);
 
	pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
					      DRM_MODE_FLAG_NHSYNC |
					      DRM_MODE_FLAG_PVSYNC |
					      DRM_MODE_FLAG_NVSYNC);
	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
}
 
static void hsw_crt_pre_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");
	I915_WRITE(SPLL_CTL,
		   SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC);
	POSTING_READ(SPLL_CTL);
	udelay(20);
}
 
/* Note: The caller is required to filter out dpms modes not supported by the
 * platform. */
static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
	u32 adpa;
 
	if (INTEL_INFO(dev)->gen >= 5)
		adpa = ADPA_HOTPLUG_BITS;
	else
		adpa = 0;
 
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 
	/* For CPT allow 3 pipe config, for others just use A or B */
	if (HAS_PCH_LPT(dev))
		; /* Those bits don't exist here */
	else if (HAS_PCH_CPT(dev))
		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
	else if (crtc->pipe == 0)
		adpa |= ADPA_PIPE_A_SELECT;
	else
		adpa |= ADPA_PIPE_B_SELECT;
 
	if (!HAS_PCH_SPLIT(dev))
		I915_WRITE(BCLRPAT(crtc->pipe), 0);
 
	switch (mode) {
	case DRM_MODE_DPMS_ON:
		adpa |= ADPA_DAC_ENABLE;
		break;
	case DRM_MODE_DPMS_STANDBY:
		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_OFF:
		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	}
 
	I915_WRITE(crt->adpa_reg, adpa);
}
 
static void intel_disable_crt(struct intel_encoder *encoder)
{
	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
}
 
 
static void hsw_crt_post_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t val;
 
	DRM_DEBUG_KMS("Disabling SPLL\n");
	val = I915_READ(SPLL_CTL);
	WARN_ON(!(val & SPLL_PLL_ENABLE));
	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
	POSTING_READ(SPLL_CTL);
}
 
static void intel_enable_crt(struct intel_encoder *encoder)
{
	struct intel_crt *crt = intel_encoder_to_crt(encoder);
 
	intel_crt_set_dpms(encoder, crt->connector->base.dpms);
}
 
/* Special dpms function to support cloning between dvo/sdvo/crt. */
static void intel_crt_dpms(struct drm_connector *connector, int mode)
{
	struct drm_device *dev = connector->dev;
	struct intel_encoder *encoder = intel_attached_encoder(connector);
	struct drm_crtc *crtc;
	int old_dpms;
 
	/* PCH platforms and VLV only support on/off. */
	if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;
 
	if (mode == connector->dpms)
		return;
 
	old_dpms = connector->dpms;
	connector->dpms = mode;
 
	/* Only need to change hw state when actually enabled */
	crtc = encoder->base.crtc;
	if (!crtc) {
		encoder->connectors_active = false;
		return;
	}
 
	/* We need the pipe to run for anything but OFF. */
	if (mode == DRM_MODE_DPMS_OFF)
		encoder->connectors_active = false;
	else
		encoder->connectors_active = true;
 
	/* We call connector dpms manually below in case pipe dpms doesn't
	 * change due to cloning. */
	if (mode < old_dpms) {
		/* From off to on, enable the pipe first. */
		intel_crtc_update_dpms(crtc);
 
		intel_crt_set_dpms(encoder, mode);
	} else {
		intel_crt_set_dpms(encoder, mode);
 
		intel_crtc_update_dpms(crtc);
	}
 
	intel_modeset_check_state(connector->dev);
}
 
static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;
 
	int max_clock = 0;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;
 
	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;
 
	if (IS_GEN2(dev))
		max_clock = 350000;
	else
		max_clock = 400000;
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;
 
	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
	if (HAS_PCH_LPT(dev) &&
	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
		return MODE_CLOCK_HIGH;
 
	return MODE_OK;
}
 
static bool intel_crt_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = encoder->base.dev;
 
	if (HAS_PCH_SPLIT(dev))
		pipe_config->has_pch_encoder = true;
 
	/* LPT FDI RX only supports 8bpc. */
	if (HAS_PCH_LPT(dev))
		pipe_config->pipe_bpp = 24;
 
	/* FDI must always be 2.7 GHz */
	if (HAS_DDI(dev)) {
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
		pipe_config->port_clock = 135000 * 2;
 
 
 
 
 
 
 
 
	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	return true;
}
 
static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;
 
	/* The first time through, trigger an explicit detection cycle */
	if (crt->force_hotplug_required) {
		bool turn_off_dac = HAS_PCH_SPLIT(dev);
		u32 save_adpa;
 
		crt->force_hotplug_required = 0;
 
		save_adpa = adpa = I915_READ(crt->adpa_reg);
		DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
		if (turn_off_dac)
			adpa &= ~ADPA_DAC_ENABLE;
 
		I915_WRITE(crt->adpa_reg, adpa);
 
		if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 
		if (turn_off_dac) {
			I915_WRITE(crt->adpa_reg, save_adpa);
			POSTING_READ(crt->adpa_reg);
		}
	}
 
	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(crt->adpa_reg);
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;
	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 
	return ret;
}
 
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;
	u32 save_adpa;
 
	save_adpa = adpa = I915_READ(crt->adpa_reg);
	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 
	I915_WRITE(crt->adpa_reg, adpa);
 
	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
		     1000)) {
		DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
		I915_WRITE(crt->adpa_reg, save_adpa);
	}
 
	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(crt->adpa_reg);
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;
 
	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 
	return ret;
}
 
/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_en, orig, stat;
	bool ret = false;
	int i, tries = 0;
 
	if (HAS_PCH_SPLIT(dev))
		return intel_ironlake_crt_detect_hotplug(connector);
 
	if (IS_VALLEYVIEW(dev))
		return valleyview_crt_detect_hotplug(connector);
 
	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */
 
	if (IS_G4X(dev) && !IS_GM45(dev))
		tries = 2;
	else
		tries = 1;
	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 
	for (i = 0; i < tries ; i++) {
		/* turn on the FORCE_DETECT */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
		/* wait for FORCE_DETECT to go off */
		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
			      CRT_HOTPLUG_FORCE_DETECT) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
	}
 
	stat = I915_READ(PORT_HOTPLUG_STAT);
	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
		ret = true;
 
	/* clear the interrupt we just generated, if any */
	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 
	/* and put the bits back */
	I915_WRITE(PORT_HOTPLUG_EN, orig);
 
	return ret;
}
 
static struct edid *intel_crt_get_edid(struct drm_connector *connector,
				struct i2c_adapter *i2c)
{
	struct edid *edid;
 
	edid = drm_get_edid(connector, i2c);
 
	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
		DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
		intel_gmbus_force_bit(i2c, true);
		edid = drm_get_edid(connector, i2c);
		intel_gmbus_force_bit(i2c, false);
	}
 
	return edid;
}
 
/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
static int intel_crt_ddc_get_modes(struct drm_connector *connector,
				struct i2c_adapter *adapter)
{
	struct edid *edid;
	int ret;
 
	edid = intel_crt_get_edid(connector, adapter);
	if (!edid)
		return 0;
 
	ret = intel_connector_update_modes(connector, edid);
	kfree(edid);
 
	return ret;
}
 
static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
	struct edid *edid;
	struct i2c_adapter *i2c;
 
	BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 
	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
	edid = intel_crt_get_edid(connector, i2c);
 
	if (edid) {
		bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 
		/*
		 * This may be a DVI-I connector with a shared DDC
		 * link between analog and digital outputs, so we
		 * have to check the EDID input spec of the attached device.
		 */
		if (!is_digital) {
			DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
			return true;
		}
 
		DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
	} else {
		DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
	}
 
	kfree(edid);
 
	return false;
}
 
static enum drm_connector_status
intel_crt_load_detect(struct intel_crt *crt)
{
	struct drm_device *dev = crt->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
	uint32_t bclrpat_reg;
	uint32_t vtotal_reg;
	uint32_t vblank_reg;
	uint32_t vsync_reg;
	uint32_t pipeconf_reg;
	uint32_t pipe_dsl_reg;
	uint8_t	st00;
	enum drm_connector_status status;
 
	DRM_DEBUG_KMS("starting load-detect on CRT\n");
 
	bclrpat_reg = BCLRPAT(pipe);
	vtotal_reg = VTOTAL(pipe);
	vblank_reg = VBLANK(pipe);
	vsync_reg = VSYNC(pipe);
	pipeconf_reg = PIPECONF(pipe);
	pipe_dsl_reg = PIPEDSL(pipe);
 
	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);
 
	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;
 
	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;
 
	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);
 
	if (!IS_GEN2(dev)) {
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
		POSTING_READ(pipeconf_reg);
		/* Wait for next Vblank to substitue
		 * border color for Color info */
		intel_wait_for_vblank(dev, pipe);
		st00 = I915_READ8(VGA_MSR_WRITE);
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;
 
		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;
 
		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;
 
			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;
 
		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
			st00 = I915_READ8(VGA_MSR_WRITE);
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));
 
		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}
 
	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);
 
	return status;
}
 
static enum drm_connector_status
intel_crt_detect(struct drm_connector *connector, bool force)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct intel_encoder *intel_encoder = &crt->base;
	enum intel_display_power_domain power_domain;
	enum drm_connector_status status;
	struct intel_load_detect_pipe tmp;
	struct drm_modeset_acquire_ctx ctx;
 
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
		      connector->base.id, connector->name,
		      force);
 
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
 
	if (I915_HAS_HOTPLUG(dev)) {
		/* We can not rely on the HPD pin always being correctly wired
		 * up, for example many KVM do not pass it through, and so
		 * only trust an assertion that the monitor is connected.
		 */
		if (intel_crt_detect_hotplug(connector)) {
			DRM_DEBUG_KMS("CRT detected via hotplug\n");
			status = connector_status_connected;
			goto out;
		} else
			DRM_DEBUG_KMS("CRT not detected via hotplug\n");
	}
 
	if (intel_crt_detect_ddc(connector)) {
		status = connector_status_connected;
		goto out;
	}
 
	/* Load detection is broken on HPD capable machines. Whoever wants a
	 * broken monitor (without edid) to work behind a broken kvm (that fails
	 * to have the right resistors for HP detection) needs to fix this up.
	 * For now just bail out. */
	if (I915_HAS_HOTPLUG(dev)) {
		status = connector_status_disconnected;
		goto out;
	}
 
	if (!force) {
		status = connector->status;
		goto out;
	}
 
 
	drm_modeset_acquire_init(&ctx, 0);
 
	/* for pre-945g platforms use load detect */
	if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
		if (intel_crt_detect_ddc(connector))
			status = connector_status_connected;
		else
			status = intel_crt_load_detect(crt);
		intel_release_load_detect_pipe(connector, &tmp);
	} else
		status = connector_status_unknown;
 
	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);
 
out:
	intel_display_power_put(dev_priv, power_domain);
	return status;
}
 
static void intel_crt_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}
 
static int intel_crt_get_modes(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct intel_encoder *intel_encoder = &crt->base;
	enum intel_display_power_domain power_domain;
	int ret;
	struct i2c_adapter *i2c;
 
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
 
	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
	ret = intel_crt_ddc_get_modes(connector, i2c);
	if (ret || !IS_G4X(dev))
		goto out;
 
	/* Try to probe digital port for output in DVI-I -> VGA mode. */
	i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
	ret = intel_crt_ddc_get_modes(connector, i2c);
 
out:
	intel_display_power_put(dev_priv, power_domain);
 
	return ret;
}
 
static int intel_crt_set_property(struct drm_connector *connector,
				  struct drm_property *property,
				  uint64_t value)
{
	return 0;
}
 
static void intel_crt_reset(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crt *crt = intel_attached_crt(connector);
 
	if (INTEL_INFO(dev)->gen >= 5) {
		u32 adpa;
 
		adpa = I915_READ(crt->adpa_reg);
		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
		adpa |= ADPA_HOTPLUG_BITS;
		I915_WRITE(crt->adpa_reg, adpa);
		POSTING_READ(crt->adpa_reg);
 
		DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
		crt->force_hotplug_required = 1;
	}
 
}
 
/*
 * Routines for controlling stuff on the analog port
 */
 
static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.reset = intel_crt_reset,
	.dpms = intel_crt_dpms,
	.detect = intel_crt_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_crt_destroy,
	.set_property = intel_crt_set_property,
};
 
static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
	.best_encoder = intel_best_encoder,
};
 
static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	.destroy = intel_encoder_destroy,
};
 
void intel_crt_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct intel_crt *crt;
	struct intel_connector *intel_connector;
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
	if (!crt)
		return;
 
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(crt);
		return;
	}
 
	connector = &intel_connector->base;
	crt->connector = intel_connector;
	drm_connector_init(dev, &intel_connector->base,
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 
	drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
			 DRM_MODE_ENCODER_DAC);
 
	intel_connector_attach_encoder(intel_connector, &crt->base);
 
	crt->base.type = INTEL_OUTPUT_ANALOG;
	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
	if (IS_I830(dev))
		crt->base.crtc_mask = (1 << 0);
	else
		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
	if (IS_GEN2(dev))
		connector->interlace_allowed = 0;
	else
	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;
 
	if (HAS_PCH_SPLIT(dev))
		crt->adpa_reg = PCH_ADPA;
	else if (IS_VALLEYVIEW(dev))
		crt->adpa_reg = VLV_ADPA;
	else
		crt->adpa_reg = ADPA;
 
	crt->base.compute_config = intel_crt_compute_config;
 
	crt->base.disable = intel_disable_crt;
	crt->base.enable = intel_enable_crt;
	if (I915_HAS_HOTPLUG(dev))
		crt->base.hpd_pin = HPD_CRT;
	if (HAS_DDI(dev)) {
		crt->base.get_config = hsw_crt_get_config;
		crt->base.get_hw_state = intel_ddi_get_hw_state;
		crt->base.pre_enable = hsw_crt_pre_enable;
		crt->base.post_disable = hsw_crt_post_disable;
	} else {
		crt->base.get_config = intel_crt_get_config;
	crt->base.get_hw_state = intel_crt_get_hw_state;
	}
	intel_connector->get_hw_state = intel_connector_get_hw_state;
	intel_connector->unregister = intel_connector_unregister;
 
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 
	drm_connector_register(connector);
 
	if (!I915_HAS_HOTPLUG(dev))
		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 
	/*
	 * Configure the automatic hotplug detection stuff
	 */
	crt->force_hotplug_required = 0;
 
	/*
	 * TODO: find a proper way to discover whether we need to set the the
	 * polarity and link reversal bits or not, instead of relying on the
	 * BIOS.
	 */
	if (HAS_PCH_LPT(dev)) {
		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
				 FDI_RX_LINK_REVERSAL_OVERRIDE;
 
		dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
	}
 
	intel_crt_reset(connector);
}

Rev 4560	Rev 5060
1	/*	1	/*
2	* Copyright © 2006-2007 Intel Corporation	2	* Copyright © 2006-2007 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.	21	* DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	*/	25	*/
26		26
27	#include	27	#include
28	#include	28	#include
29	#include	29	#include
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include "intel_drv.h"	33	#include "intel_drv.h"
34	#include	34	#include
35	#include "i915_drv.h"	35	#include "i915_drv.h"
36		36
37	/* Here's the desired hotplug mode */	37	/* Here's the desired hotplug mode */
38	#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 \| \	38	#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 \| \
39	ADPA_CRT_HOTPLUG_WARMUP_10MS \| \	39	ADPA_CRT_HOTPLUG_WARMUP_10MS \| \
40	ADPA_CRT_HOTPLUG_SAMPLE_4S \| \	40	ADPA_CRT_HOTPLUG_SAMPLE_4S \| \
41	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| \	41	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| \
42	ADPA_CRT_HOTPLUG_VOLREF_325MV \| \	42	ADPA_CRT_HOTPLUG_VOLREF_325MV \| \
43	ADPA_CRT_HOTPLUG_ENABLE)	43	ADPA_CRT_HOTPLUG_ENABLE)
44		44
45	struct intel_crt {	45	struct intel_crt {
46	struct intel_encoder base;	46	struct intel_encoder base;
47	/* DPMS state is stored in the connector, which we need in the	47	/* DPMS state is stored in the connector, which we need in the
48	* encoder's enable/disable callbacks */	48	* encoder's enable/disable callbacks */
49	struct intel_connector *connector;	49	struct intel_connector *connector;
50	bool force_hotplug_required;	50	bool force_hotplug_required;
51	u32 adpa_reg;	51	u32 adpa_reg;
52	};	52	};
53		53
54	static struct intel_crt intel_encoder_to_crt(struct intel_encoder encoder)	54	static struct intel_crt intel_encoder_to_crt(struct intel_encoder encoder)
55	{	55	{
56	return container_of(encoder, struct intel_crt, base);	56	return container_of(encoder, struct intel_crt, base);
57	}	57	}
58		58
59	static struct intel_crt intel_attached_crt(struct drm_connector connector)	59	static struct intel_crt intel_attached_crt(struct drm_connector connector)
60	{	60	{
61	return intel_encoder_to_crt(intel_attached_encoder(connector));	61	return intel_encoder_to_crt(intel_attached_encoder(connector));
62	}	62	}
63		63
64	static bool intel_crt_get_hw_state(struct intel_encoder *encoder,	64	static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
65	enum pipe *pipe)	65	enum pipe *pipe)
66	{	66	{
67	struct drm_device *dev = encoder->base.dev;	67	struct drm_device *dev = encoder->base.dev;
68	struct drm_i915_private *dev_priv = dev->dev_private;	68	struct drm_i915_private *dev_priv = dev->dev_private;
69	struct intel_crt *crt = intel_encoder_to_crt(encoder);	69	struct intel_crt *crt = intel_encoder_to_crt(encoder);
-		70	enum intel_display_power_domain power_domain;
70	u32 tmp;	71	u32 tmp;
-		72
-		73	power_domain = intel_display_port_power_domain(encoder);
-		74	if (!intel_display_power_enabled(dev_priv, power_domain))
-		75	return false;
71		76
72	tmp = I915_READ(crt->adpa_reg);	77	tmp = I915_READ(crt->adpa_reg);
73		78
74	if (!(tmp & ADPA_DAC_ENABLE))	79	if (!(tmp & ADPA_DAC_ENABLE))
75	return false;	80	return false;
76		81
77	if (HAS_PCH_CPT(dev))	82	if (HAS_PCH_CPT(dev))
78	*pipe = PORT_TO_PIPE_CPT(tmp);	83	*pipe = PORT_TO_PIPE_CPT(tmp);
79	else	84	else
80	*pipe = PORT_TO_PIPE(tmp);	85	*pipe = PORT_TO_PIPE(tmp);
81		86
82	return true;	87	return true;
83	}	88	}
84		89
85	static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)	90	static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
86	{	91	{
87	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;	92	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
88	struct intel_crt *crt = intel_encoder_to_crt(encoder);	93	struct intel_crt *crt = intel_encoder_to_crt(encoder);
89	u32 tmp, flags = 0;	94	u32 tmp, flags = 0;
90		95
91	tmp = I915_READ(crt->adpa_reg);	96	tmp = I915_READ(crt->adpa_reg);
92		97
93	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)	98	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
94	flags \|= DRM_MODE_FLAG_PHSYNC;	99	flags \|= DRM_MODE_FLAG_PHSYNC;
95	else	100	else
96	flags \|= DRM_MODE_FLAG_NHSYNC;	101	flags \|= DRM_MODE_FLAG_NHSYNC;
97		102
98	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)	103	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
99	flags \|= DRM_MODE_FLAG_PVSYNC;	104	flags \|= DRM_MODE_FLAG_PVSYNC;
100	else	105	else
101	flags \|= DRM_MODE_FLAG_NVSYNC;	106	flags \|= DRM_MODE_FLAG_NVSYNC;
102		107
103	return flags;	108	return flags;
104	}	109	}
105		110
106	static void intel_crt_get_config(struct intel_encoder *encoder,	111	static void intel_crt_get_config(struct intel_encoder *encoder,
107	struct intel_crtc_config *pipe_config)	112	struct intel_crtc_config *pipe_config)
108	{	113	{
109	struct drm_device *dev = encoder->base.dev;	114	struct drm_device *dev = encoder->base.dev;
110	int dotclock;	115	int dotclock;
111		116
112	pipe_config->adjusted_mode.flags \|= intel_crt_get_flags(encoder);	117	pipe_config->adjusted_mode.flags \|= intel_crt_get_flags(encoder);
113		118
114	dotclock = pipe_config->port_clock;	119	dotclock = pipe_config->port_clock;
115		120
116	if (HAS_PCH_SPLIT(dev))	121	if (HAS_PCH_SPLIT(dev))
117	ironlake_check_encoder_dotclock(pipe_config, dotclock);	122	ironlake_check_encoder_dotclock(pipe_config, dotclock);
118		123
119	pipe_config->adjusted_mode.crtc_clock = dotclock;	124	pipe_config->adjusted_mode.crtc_clock = dotclock;
120	}	125	}
121		126
122	static void hsw_crt_get_config(struct intel_encoder *encoder,	127	static void hsw_crt_get_config(struct intel_encoder *encoder,
123	struct intel_crtc_config *pipe_config)	128	struct intel_crtc_config *pipe_config)
124	{	129	{
125	intel_ddi_get_config(encoder, pipe_config);	130	intel_ddi_get_config(encoder, pipe_config);
126		131
127	pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC \|	132	pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC \|
128	DRM_MODE_FLAG_NHSYNC \|	133	DRM_MODE_FLAG_NHSYNC \|
129	DRM_MODE_FLAG_PVSYNC \|	134	DRM_MODE_FLAG_PVSYNC \|
130	DRM_MODE_FLAG_NVSYNC);	135	DRM_MODE_FLAG_NVSYNC);
131	pipe_config->adjusted_mode.flags \|= intel_crt_get_flags(encoder);	136	pipe_config->adjusted_mode.flags \|= intel_crt_get_flags(encoder);
132	}	137	}
-		138
-		139	static void hsw_crt_pre_enable(struct intel_encoder *encoder)
-		140	{
-		141	struct drm_device *dev = encoder->base.dev;
-		142	struct drm_i915_private *dev_priv = dev->dev_private;
-		143
-		144	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");
-		145	I915_WRITE(SPLL_CTL,
-		146	SPLL_PLL_ENABLE \| SPLL_PLL_FREQ_1350MHz \| SPLL_PLL_SSC);
-		147	POSTING_READ(SPLL_CTL);
-		148	udelay(20);
-		149	}
133		150
134	/* Note: The caller is required to filter out dpms modes not supported by the	151	/* Note: The caller is required to filter out dpms modes not supported by the
135	* platform. */	152	* platform. */
136	static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)	153	static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
137	{	154	{
138	struct drm_device *dev = encoder->base.dev;	155	struct drm_device *dev = encoder->base.dev;
139	struct drm_i915_private *dev_priv = dev->dev_private;	156	struct drm_i915_private *dev_priv = dev->dev_private;
140	struct intel_crt *crt = intel_encoder_to_crt(encoder);	157	struct intel_crt *crt = intel_encoder_to_crt(encoder);
-		158	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-		159	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
141	u32 temp;	160	u32 adpa;
-		161
142		162	if (INTEL_INFO(dev)->gen >= 5)
-		163	adpa = ADPA_HOTPLUG_BITS;
-		164	else
-		165	adpa = 0;
-		166
143	temp = I915_READ(crt->adpa_reg);	167	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
-		168	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;
-		169	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
-		170	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;
-		171
-		172	/* For CPT allow 3 pipe config, for others just use A or B */
-		173	if (HAS_PCH_LPT(dev))
-		174	; /* Those bits don't exist here */
-		175	else if (HAS_PCH_CPT(dev))
-		176	adpa \|= PORT_TRANS_SEL_CPT(crtc->pipe);
-		177	else if (crtc->pipe == 0)
-		178	adpa \|= ADPA_PIPE_A_SELECT;
144	temp &= ~(ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE);	179	else
-		180	adpa \|= ADPA_PIPE_B_SELECT;
-		181
-		182	if (!HAS_PCH_SPLIT(dev))
145	temp &= ~ADPA_DAC_ENABLE;	183	I915_WRITE(BCLRPAT(crtc->pipe), 0);
146		184
147	switch (mode) {	185	switch (mode) {
148	case DRM_MODE_DPMS_ON:	186	case DRM_MODE_DPMS_ON:
149	temp \|= ADPA_DAC_ENABLE;	187	adpa \|= ADPA_DAC_ENABLE;
150	break;	188	break;
151	case DRM_MODE_DPMS_STANDBY:	189	case DRM_MODE_DPMS_STANDBY:
152	temp \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;	190	adpa \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;
153	break;	191	break;
154	case DRM_MODE_DPMS_SUSPEND:	192	case DRM_MODE_DPMS_SUSPEND:
155	temp \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;	193	adpa \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;
156	break;	194	break;
157	case DRM_MODE_DPMS_OFF:	195	case DRM_MODE_DPMS_OFF:
158	temp \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;	196	adpa \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;
159	break;	197	break;
160	}	198	}
161		199
162	I915_WRITE(crt->adpa_reg, temp);	200	I915_WRITE(crt->adpa_reg, adpa);
163	}	201	}
164		202
165	static void intel_disable_crt(struct intel_encoder *encoder)	203	static void intel_disable_crt(struct intel_encoder *encoder)
166	{	204	{
167	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);	205	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
168	}	206	}
-		207
-		208
-		209	static void hsw_crt_post_disable(struct intel_encoder *encoder)
-		210	{
-		211	struct drm_device *dev = encoder->base.dev;
-		212	struct drm_i915_private *dev_priv = dev->dev_private;
-		213	uint32_t val;
-		214
-		215	DRM_DEBUG_KMS("Disabling SPLL\n");
-		216	val = I915_READ(SPLL_CTL);
-		217	WARN_ON(!(val & SPLL_PLL_ENABLE));
-		218	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
-		219	POSTING_READ(SPLL_CTL);
-		220	}
169		221
170	static void intel_enable_crt(struct intel_encoder *encoder)	222	static void intel_enable_crt(struct intel_encoder *encoder)
171	{	223	{
172	struct intel_crt *crt = intel_encoder_to_crt(encoder);	224	struct intel_crt *crt = intel_encoder_to_crt(encoder);
173		225
174	intel_crt_set_dpms(encoder, crt->connector->base.dpms);	226	intel_crt_set_dpms(encoder, crt->connector->base.dpms);
175	}	227	}
176		228
177	/* Special dpms function to support cloning between dvo/sdvo/crt. */	229	/* Special dpms function to support cloning between dvo/sdvo/crt. */
178	static void intel_crt_dpms(struct drm_connector *connector, int mode)	230	static void intel_crt_dpms(struct drm_connector *connector, int mode)
179	{	231	{
180	struct drm_device *dev = connector->dev;	232	struct drm_device *dev = connector->dev;
181	struct intel_encoder *encoder = intel_attached_encoder(connector);	233	struct intel_encoder *encoder = intel_attached_encoder(connector);
182	struct drm_crtc *crtc;	234	struct drm_crtc *crtc;
183	int old_dpms;	235	int old_dpms;
184		236
185	/* PCH platforms and VLV only support on/off. */	237	/* PCH platforms and VLV only support on/off. */
186	if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)	238	if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
187	mode = DRM_MODE_DPMS_OFF;	239	mode = DRM_MODE_DPMS_OFF;
188		240
189	if (mode == connector->dpms)	241	if (mode == connector->dpms)
190	return;	242	return;
191		243
192	old_dpms = connector->dpms;	244	old_dpms = connector->dpms;
193	connector->dpms = mode;	245	connector->dpms = mode;
194		246
195	/* Only need to change hw state when actually enabled */	247	/* Only need to change hw state when actually enabled */
196	crtc = encoder->base.crtc;	248	crtc = encoder->base.crtc;
197	if (!crtc) {	249	if (!crtc) {
198	encoder->connectors_active = false;	250	encoder->connectors_active = false;
199	return;	251	return;
200	}	252	}
201		253
202	/* We need the pipe to run for anything but OFF. */	254	/* We need the pipe to run for anything but OFF. */
203	if (mode == DRM_MODE_DPMS_OFF)	255	if (mode == DRM_MODE_DPMS_OFF)
204	encoder->connectors_active = false;	256	encoder->connectors_active = false;
205	else	257	else
206	encoder->connectors_active = true;	258	encoder->connectors_active = true;
207		259
208	/* We call connector dpms manually below in case pipe dpms doesn't	260	/* We call connector dpms manually below in case pipe dpms doesn't
209	* change due to cloning. */	261	* change due to cloning. */
210	if (mode < old_dpms) {	262	if (mode < old_dpms) {
211	/* From off to on, enable the pipe first. */	263	/* From off to on, enable the pipe first. */
212	intel_crtc_update_dpms(crtc);	264	intel_crtc_update_dpms(crtc);
213		265
214	intel_crt_set_dpms(encoder, mode);	266	intel_crt_set_dpms(encoder, mode);
215	} else {	267	} else {
216	intel_crt_set_dpms(encoder, mode);	268	intel_crt_set_dpms(encoder, mode);
217		269
218	intel_crtc_update_dpms(crtc);	270	intel_crtc_update_dpms(crtc);
219	}	271	}
220		272
221	intel_modeset_check_state(connector->dev);	273	intel_modeset_check_state(connector->dev);
222	}	274	}
223		275
224	static enum drm_mode_status	276	static enum drm_mode_status
225	intel_crt_mode_valid(struct drm_connector *connector,	277	intel_crt_mode_valid(struct drm_connector *connector,
226	struct drm_display_mode *mode)	278	struct drm_display_mode *mode)
227	{	279	{
228	struct drm_device *dev = connector->dev;	280	struct drm_device *dev = connector->dev;
229		281
230	int max_clock = 0;	282	int max_clock = 0;
231	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)	283	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
232	return MODE_NO_DBLESCAN;	284	return MODE_NO_DBLESCAN;
233		285
234	if (mode->clock < 25000)	286	if (mode->clock < 25000)
235	return MODE_CLOCK_LOW;	287	return MODE_CLOCK_LOW;
236		288
237	if (IS_GEN2(dev))	289	if (IS_GEN2(dev))
238	max_clock = 350000;	290	max_clock = 350000;
239	else	291	else
240	max_clock = 400000;	292	max_clock = 400000;
241	if (mode->clock > max_clock)	293	if (mode->clock > max_clock)
242	return MODE_CLOCK_HIGH;	294	return MODE_CLOCK_HIGH;
243		295
244	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */	296	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
245	if (HAS_PCH_LPT(dev) &&	297	if (HAS_PCH_LPT(dev) &&
246	(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))	298	(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
247	return MODE_CLOCK_HIGH;	299	return MODE_CLOCK_HIGH;
248		300
249	return MODE_OK;	301	return MODE_OK;
250	}	302	}
251		303
252	static bool intel_crt_compute_config(struct intel_encoder *encoder,	304	static bool intel_crt_compute_config(struct intel_encoder *encoder,
253	struct intel_crtc_config *pipe_config)	305	struct intel_crtc_config *pipe_config)
254	{	306	{
255	struct drm_device *dev = encoder->base.dev;	307	struct drm_device *dev = encoder->base.dev;
256		308
257	if (HAS_PCH_SPLIT(dev))	309	if (HAS_PCH_SPLIT(dev))
258	pipe_config->has_pch_encoder = true;	310	pipe_config->has_pch_encoder = true;
259		311
260	/* LPT FDI RX only supports 8bpc. */	312	/* LPT FDI RX only supports 8bpc. */
261	if (HAS_PCH_LPT(dev))	313	if (HAS_PCH_LPT(dev))
262	pipe_config->pipe_bpp = 24;	314	pipe_config->pipe_bpp = 24;
-		315
263		316	/* FDI must always be 2.7 GHz */
-		317	if (HAS_DDI(dev)) {
-		318	pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
264	return true;	319	pipe_config->port_clock = 135000 * 2;
265	}	-
266		-
267	static void intel_crt_mode_set(struct intel_encoder *encoder)	-
268	{	-
269		-
270	struct drm_device *dev = encoder->base.dev;	-
271	struct intel_crt *crt = intel_encoder_to_crt(encoder);	-
272	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);	-
273	struct drm_i915_private *dev_priv = dev->dev_private;	320	}
274	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;	-
275	u32 adpa;	-
276		-
277	if (INTEL_INFO(dev)->gen >= 5)	-
278	adpa = ADPA_HOTPLUG_BITS;	-
279	else	-
280	adpa = 0;	-
281		-
282	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)	-
283	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;	-
284	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)	-
285	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;	-
286		-
287	/* For CPT allow 3 pipe config, for others just use A or B */	-
288	if (HAS_PCH_LPT(dev))	-
289	; /* Those bits don't exist here */	-
290	else if (HAS_PCH_CPT(dev))	-
291	adpa \|= PORT_TRANS_SEL_CPT(crtc->pipe);	-
292	else if (crtc->pipe == 0)	-
293	adpa \|= ADPA_PIPE_A_SELECT;	-
294	else	-
295	adpa \|= ADPA_PIPE_B_SELECT;	-
296		-
297	if (!HAS_PCH_SPLIT(dev))	-
298	I915_WRITE(BCLRPAT(crtc->pipe), 0);	-
299		321
300	I915_WRITE(crt->adpa_reg, adpa);	322	return true;
301	}	323	}
302		324
303	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)	325	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
304	{	326	{
305	struct drm_device *dev = connector->dev;	327	struct drm_device *dev = connector->dev;
306	struct intel_crt *crt = intel_attached_crt(connector);	328	struct intel_crt *crt = intel_attached_crt(connector);
307	struct drm_i915_private *dev_priv = dev->dev_private;	329	struct drm_i915_private *dev_priv = dev->dev_private;
308	u32 adpa;	330	u32 adpa;
309	bool ret;	331	bool ret;
310		332
311	/* The first time through, trigger an explicit detection cycle */	333	/* The first time through, trigger an explicit detection cycle */
312	if (crt->force_hotplug_required) {	334	if (crt->force_hotplug_required) {
313	bool turn_off_dac = HAS_PCH_SPLIT(dev);	335	bool turn_off_dac = HAS_PCH_SPLIT(dev);
314	u32 save_adpa;	336	u32 save_adpa;
315		337
316	crt->force_hotplug_required = 0;	338	crt->force_hotplug_required = 0;
317		339
318	save_adpa = adpa = I915_READ(crt->adpa_reg);	340	save_adpa = adpa = I915_READ(crt->adpa_reg);
319	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);	341	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
320		342
321	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;	343	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
322	if (turn_off_dac)	344	if (turn_off_dac)
323	adpa &= ~ADPA_DAC_ENABLE;	345	adpa &= ~ADPA_DAC_ENABLE;
324		346
325	I915_WRITE(crt->adpa_reg, adpa);	347	I915_WRITE(crt->adpa_reg, adpa);
326		348
327	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,	349	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
328	1000))	350	1000))
329	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");	351	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
330		352
331	if (turn_off_dac) {	353	if (turn_off_dac) {
332	I915_WRITE(crt->adpa_reg, save_adpa);	354	I915_WRITE(crt->adpa_reg, save_adpa);
333	POSTING_READ(crt->adpa_reg);	355	POSTING_READ(crt->adpa_reg);
334	}	356	}
335	}	357	}
336		358
337	/* Check the status to see if both blue and green are on now */	359	/* Check the status to see if both blue and green are on now */
338	adpa = I915_READ(crt->adpa_reg);	360	adpa = I915_READ(crt->adpa_reg);
339	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)	361	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
340	ret = true;	362	ret = true;
341	else	363	else
342	ret = false;	364	ret = false;
343	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);	365	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
344		366
345	return ret;	367	return ret;
346	}	368	}
347		369
348	static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)	370	static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
349	{	371	{
350	struct drm_device *dev = connector->dev;	372	struct drm_device *dev = connector->dev;
351	struct intel_crt *crt = intel_attached_crt(connector);	373	struct intel_crt *crt = intel_attached_crt(connector);
352	struct drm_i915_private *dev_priv = dev->dev_private;	374	struct drm_i915_private *dev_priv = dev->dev_private;
353	u32 adpa;	375	u32 adpa;
354	bool ret;	376	bool ret;
355	u32 save_adpa;	377	u32 save_adpa;
356		378
357	save_adpa = adpa = I915_READ(crt->adpa_reg);	379	save_adpa = adpa = I915_READ(crt->adpa_reg);
358	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);	380	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
359		381
360	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;	382	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
361		383
362	I915_WRITE(crt->adpa_reg, adpa);	384	I915_WRITE(crt->adpa_reg, adpa);
363		385
364	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,	386	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
365	1000)) {	387	1000)) {
366	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");	388	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
367	I915_WRITE(crt->adpa_reg, save_adpa);	389	I915_WRITE(crt->adpa_reg, save_adpa);
368	}	390	}
369		391
370	/* Check the status to see if both blue and green are on now */	392	/* Check the status to see if both blue and green are on now */
371	adpa = I915_READ(crt->adpa_reg);	393	adpa = I915_READ(crt->adpa_reg);
372	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)	394	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
373	ret = true;	395	ret = true;
374	else	396	else
375	ret = false;	397	ret = false;
376		398
377	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);	399	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
378		400
379	return ret;	401	return ret;
380	}	402	}
381		403
382	/**	404	/**
383	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.	405	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
384	*	406	*
385	* Not for i915G/i915GM	407	* Not for i915G/i915GM
386	*	408	*
387	* \return true if CRT is connected.	409	* \return true if CRT is connected.
388	* \return false if CRT is disconnected.	410	* \return false if CRT is disconnected.
389	*/	411	*/
390	static bool intel_crt_detect_hotplug(struct drm_connector *connector)	412	static bool intel_crt_detect_hotplug(struct drm_connector *connector)
391	{	413	{
392	struct drm_device *dev = connector->dev;	414	struct drm_device *dev = connector->dev;
393	struct drm_i915_private *dev_priv = dev->dev_private;	415	struct drm_i915_private *dev_priv = dev->dev_private;
394	u32 hotplug_en, orig, stat;	416	u32 hotplug_en, orig, stat;
395	bool ret = false;	417	bool ret = false;
396	int i, tries = 0;	418	int i, tries = 0;
397		419
398	if (HAS_PCH_SPLIT(dev))	420	if (HAS_PCH_SPLIT(dev))
399	return intel_ironlake_crt_detect_hotplug(connector);	421	return intel_ironlake_crt_detect_hotplug(connector);
400		422
401	if (IS_VALLEYVIEW(dev))	423	if (IS_VALLEYVIEW(dev))
402	return valleyview_crt_detect_hotplug(connector);	424	return valleyview_crt_detect_hotplug(connector);
403		425
404	/*	426	/*
405	* On 4 series desktop, CRT detect sequence need to be done twice	427	* On 4 series desktop, CRT detect sequence need to be done twice
406	* to get a reliable result.	428	* to get a reliable result.
407	*/	429	*/
408		430
409	if (IS_G4X(dev) && !IS_GM45(dev))	431	if (IS_G4X(dev) && !IS_GM45(dev))
410	tries = 2;	432	tries = 2;
411	else	433	else
412	tries = 1;	434	tries = 1;
413	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);	435	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
414	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;	436	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;
415		437
416	for (i = 0; i < tries ; i++) {	438	for (i = 0; i < tries ; i++) {
417	/* turn on the FORCE_DETECT */	439	/* turn on the FORCE_DETECT */
418	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);	440	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
419	/* wait for FORCE_DETECT to go off */	441	/* wait for FORCE_DETECT to go off */
420	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &	442	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
421	CRT_HOTPLUG_FORCE_DETECT) == 0,	443	CRT_HOTPLUG_FORCE_DETECT) == 0,
422	1000))	444	1000))
423	DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");	445	DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
424	}	446	}
425		447
426	stat = I915_READ(PORT_HOTPLUG_STAT);	448	stat = I915_READ(PORT_HOTPLUG_STAT);
427	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)	449	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
428	ret = true;	450	ret = true;
429		451
430	/* clear the interrupt we just generated, if any */	452	/* clear the interrupt we just generated, if any */
431	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);	453	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
432		454
433	/* and put the bits back */	455	/* and put the bits back */
434	I915_WRITE(PORT_HOTPLUG_EN, orig);	456	I915_WRITE(PORT_HOTPLUG_EN, orig);
435		457
436	return ret;	458	return ret;
437	}	459	}
438		460
439	static struct edid intel_crt_get_edid(struct drm_connector connector,	461	static struct edid intel_crt_get_edid(struct drm_connector connector,
440	struct i2c_adapter *i2c)	462	struct i2c_adapter *i2c)
441	{	463	{
442	struct edid *edid;	464	struct edid *edid;
443		465
444	edid = drm_get_edid(connector, i2c);	466	edid = drm_get_edid(connector, i2c);
445		467

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(root)/drivers/video/drm/i915/intel_crt.c – Rev 4560 → 5060