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Rev 3120 | Rev 3243 | ||
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Line 195... | Line 195... | ||
195 | else |
195 | else |
196 | max_clock = 400000; |
196 | max_clock = 400000; |
197 | if (mode->clock > max_clock) |
197 | if (mode->clock > max_clock) |
198 | return MODE_CLOCK_HIGH; |
198 | return MODE_CLOCK_HIGH; |
Line -... | Line 199... | ||
- | 199 | ||
- | 200 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
|
- | 201 | if (HAS_PCH_LPT(dev) && |
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- | 202 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
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- | 203 | return MODE_CLOCK_HIGH; |
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199 | 204 | ||
200 | return MODE_OK; |
205 | return MODE_OK; |
Line 201... | Line 206... | ||
201 | } |
206 | } |
202 | 207 | ||
Line 218... | Line 223... | ||
218 | intel_encoder_to_crt(to_intel_encoder(encoder)); |
223 | intel_encoder_to_crt(to_intel_encoder(encoder)); |
219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
220 | struct drm_i915_private *dev_priv = dev->dev_private; |
225 | struct drm_i915_private *dev_priv = dev->dev_private; |
221 | u32 adpa; |
226 | u32 adpa; |
Line -... | Line 227... | ||
- | 227 | ||
222 | 228 | if (HAS_PCH_SPLIT(dev)) |
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- | 229 | adpa = ADPA_HOTPLUG_BITS; |
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- | 230 | else |
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- | 231 | adpa = 0; |
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223 | adpa = ADPA_HOTPLUG_BITS; |
232 | |
224 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
233 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
225 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
234 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
226 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
235 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
Line 227... | Line 236... | ||
227 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
236 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
228 | 237 | ||
- | 238 | /* For CPT allow 3 pipe config, for others just use A or B */ |
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- | 239 | if (HAS_PCH_LPT(dev)) |
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229 | /* For CPT allow 3 pipe config, for others just use A or B */ |
240 | ; /* Those bits don't exist here */ |
230 | if (HAS_PCH_CPT(dev)) |
241 | else if (HAS_PCH_CPT(dev)) |
231 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
242 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
232 | else if (intel_crtc->pipe == 0) |
243 | else if (intel_crtc->pipe == 0) |
233 | adpa |= ADPA_PIPE_A_SELECT; |
244 | adpa |= ADPA_PIPE_A_SELECT; |
Line 398... | Line 409... | ||
398 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
409 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
399 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
410 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
400 | struct i2c_adapter *adapter) |
411 | struct i2c_adapter *adapter) |
401 | { |
412 | { |
402 | struct edid *edid; |
413 | struct edid *edid; |
- | 414 | int ret; |
|
Line 403... | Line 415... | ||
403 | 415 | ||
404 | edid = intel_crt_get_edid(connector, adapter); |
416 | edid = intel_crt_get_edid(connector, adapter); |
405 | if (!edid) |
417 | if (!edid) |
Line 406... | Line 418... | ||
406 | return 0; |
418 | return 0; |
- | 419 | ||
- | 420 | ret = intel_connector_update_modes(connector, edid); |
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- | 421 | kfree(edid); |
|
407 | 422 | ||
Line 408... | Line 423... | ||
408 | return intel_connector_update_modes(connector, edid); |
423 | return ret; |
409 | } |
424 | } |
410 | 425 | ||
Line 641... | Line 656... | ||
641 | } |
656 | } |
Line 642... | Line 657... | ||
642 | 657 | ||
643 | static void intel_crt_reset(struct drm_connector *connector) |
658 | static void intel_crt_reset(struct drm_connector *connector) |
644 | { |
659 | { |
- | 660 | struct drm_device *dev = connector->dev; |
|
645 | struct drm_device *dev = connector->dev; |
661 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 646... | Line 662... | ||
646 | struct intel_crt *crt = intel_attached_crt(connector); |
662 | struct intel_crt *crt = intel_attached_crt(connector); |
- | 663 | ||
- | 664 | if (HAS_PCH_SPLIT(dev)) { |
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- | 665 | u32 adpa; |
|
- | 666 | ||
- | 667 | adpa = I915_READ(PCH_ADPA); |
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- | 668 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
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- | 669 | adpa |= ADPA_HOTPLUG_BITS; |
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- | 670 | I915_WRITE(PCH_ADPA, adpa); |
|
- | 671 | POSTING_READ(PCH_ADPA); |
|
647 | 672 | ||
648 | if (HAS_PCH_SPLIT(dev)) |
673 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
Line -... | Line 674... | ||
- | 674 | crt->force_hotplug_required = 1; |
|
- | 675 | } |
|
649 | crt->force_hotplug_required = 1; |
676 | |
650 | } |
677 | } |
651 | 678 | ||
Line 652... | Line 679... | ||
652 | /* |
679 | /* |
Line 704... | Line 731... | ||
704 | 731 | ||
Line 705... | Line 732... | ||
705 | intel_connector_attach_encoder(intel_connector, &crt->base); |
732 | intel_connector_attach_encoder(intel_connector, &crt->base); |
706 | 733 | ||
707 | crt->base.type = INTEL_OUTPUT_ANALOG; |
734 | crt->base.type = INTEL_OUTPUT_ANALOG; |
708 | crt->base.cloneable = true; |
735 | crt->base.cloneable = true; |
709 | if (IS_HASWELL(dev) || IS_I830(dev)) |
736 | if (IS_I830(dev)) |
710 | crt->base.crtc_mask = (1 << 0); |
737 | crt->base.crtc_mask = (1 << 0); |
Line 711... | Line 738... | ||
711 | else |
738 | else |
Line 724... | Line 751... | ||
724 | else |
751 | else |
725 | crt->adpa_reg = ADPA; |
752 | crt->adpa_reg = ADPA; |
Line 726... | Line 753... | ||
726 | 753 | ||
727 | crt->base.disable = intel_disable_crt; |
754 | crt->base.disable = intel_disable_crt; |
- | 755 | crt->base.enable = intel_enable_crt; |
|
- | 756 | if (IS_HASWELL(dev)) |
|
- | 757 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
|
728 | crt->base.enable = intel_enable_crt; |
758 | else |
729 | crt->base.get_hw_state = intel_crt_get_hw_state; |
759 | crt->base.get_hw_state = intel_crt_get_hw_state; |
Line 730... | Line 760... | ||
730 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
760 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
731 | 761 | ||
Line 741... | Line 771... | ||
741 | 771 | ||
742 | /* |
772 | /* |
743 | * Configure the automatic hotplug detection stuff |
773 | * Configure the automatic hotplug detection stuff |
744 | */ |
774 | */ |
745 | crt->force_hotplug_required = 0; |
- | |
746 | if (HAS_PCH_SPLIT(dev)) { |
- | |
747 | u32 adpa; |
- | |
748 | - | ||
749 | adpa = I915_READ(PCH_ADPA); |
- | |
750 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
- | |
751 | adpa |= ADPA_HOTPLUG_BITS; |
- | |
752 | I915_WRITE(PCH_ADPA, adpa); |
- | |
753 | POSTING_READ(PCH_ADPA); |
- | |
754 | - | ||
755 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
- | |
756 | crt->force_hotplug_required = 1; |
- | |
Line 757... | Line 775... | ||
757 | } |
775 | crt->force_hotplug_required = 0; |
- | 776 | ||
- | 777 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
|
- | 778 | ||
- | 779 | /* |
|
- | 780 | * TODO: find a proper way to discover whether we need to set the |
|
- | 781 | * polarity reversal bit or not, instead of relying on the BIOS. |
|
- | 782 | */ |
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- | 783 | if (HAS_PCH_LPT(dev)) |
|
758 | 784 | dev_priv->fdi_rx_polarity_reversed = |