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Rev 5354 | Rev 6084 | ||
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Line 20... | Line 20... | ||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
21 | * DEALINGS IN THE SOFTWARE. |
22 | */ |
22 | */ |
Line 23... | Line 23... | ||
23 | 23 | ||
- | 24 | #include |
|
- | 25 | #include |
|
- | 26 | #include |
|
Line 24... | Line 27... | ||
24 | #include |
27 | #include "intel_drv.h" |
25 | 28 | ||
26 | #include |
- | |
27 | #include |
29 | #include |
Line 28... | Line 30... | ||
28 | #include "intel_drv.h" |
30 | #include |
29 | #include "i915_drv.h" |
31 | #include "i915_drv.h" |
30 | 32 | ||
Line 37... | Line 39... | ||
37 | * handles the audio codec sequences, while the audio driver handles the audio |
39 | * handles the audio codec sequences, while the audio driver handles the audio |
38 | * controller sequences. |
40 | * controller sequences. |
39 | * |
41 | * |
40 | * The disable sequences must be performed before disabling the transcoder or |
42 | * The disable sequences must be performed before disabling the transcoder or |
41 | * port. The enable sequences may only be performed after enabling the |
43 | * port. The enable sequences may only be performed after enabling the |
42 | * transcoder and port, and after completed link training. |
44 | * transcoder and port, and after completed link training. Therefore the audio |
- | 45 | * enable/disable sequences are part of the modeset sequence. |
|
43 | * |
46 | * |
44 | * The codec and controller sequences could be done either parallel or serial, |
47 | * The codec and controller sequences could be done either parallel or serial, |
45 | * but generally the ELDV/PD change in the codec sequence indicates to the audio |
48 | * but generally the ELDV/PD change in the codec sequence indicates to the audio |
46 | * driver that the controller sequence should start. Indeed, most of the |
49 | * driver that the controller sequence should start. Indeed, most of the |
47 | * co-operation between the graphics and audio drivers is handled via audio |
50 | * co-operation between the graphics and audio drivers is handled via audio |
48 | * related registers. (The notable exception is the power management, not |
51 | * related registers. (The notable exception is the power management, not |
49 | * covered here.) |
52 | * covered here.) |
- | 53 | * |
|
- | 54 | * The struct i915_audio_component is used to interact between the graphics |
|
- | 55 | * and audio drivers. The struct i915_audio_component_ops *ops in it is |
|
- | 56 | * defined in graphics driver and called in audio driver. The |
|
- | 57 | * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver. |
|
50 | */ |
58 | */ |
Line 51... | Line 59... | ||
51 | 59 | ||
52 | static const struct { |
60 | static const struct { |
53 | int clock; |
61 | int clock; |
54 | u32 config; |
62 | u32 config; |
55 | } hdmi_audio_clock[] = { |
63 | } hdmi_audio_clock[] = { |
56 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
64 | { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
57 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
65 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
58 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
66 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
59 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
67 | { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
60 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
68 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
61 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
69 | { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
62 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
70 | { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
63 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
71 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
64 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
72 | { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
65 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
73 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
Line -... | Line 74... | ||
- | 74 | }; |
|
- | 75 | ||
- | 76 | /* HDMI N/CTS table */ |
|
- | 77 | #define TMDS_297M 297000 |
|
- | 78 | #define TMDS_296M 296703 |
|
- | 79 | static const struct { |
|
- | 80 | int sample_rate; |
|
- | 81 | int clock; |
|
- | 82 | int n; |
|
- | 83 | int cts; |
|
- | 84 | } aud_ncts[] = { |
|
- | 85 | { 44100, TMDS_296M, 4459, 234375 }, |
|
- | 86 | { 44100, TMDS_297M, 4704, 247500 }, |
|
- | 87 | { 48000, TMDS_296M, 5824, 281250 }, |
|
- | 88 | { 48000, TMDS_297M, 5120, 247500 }, |
|
- | 89 | { 32000, TMDS_296M, 5824, 421875 }, |
|
- | 90 | { 32000, TMDS_297M, 3072, 222750 }, |
|
- | 91 | { 88200, TMDS_296M, 8918, 234375 }, |
|
- | 92 | { 88200, TMDS_297M, 9408, 247500 }, |
|
- | 93 | { 96000, TMDS_296M, 11648, 281250 }, |
|
- | 94 | { 96000, TMDS_297M, 10240, 247500 }, |
|
- | 95 | { 176400, TMDS_296M, 17836, 234375 }, |
|
- | 96 | { 176400, TMDS_297M, 18816, 247500 }, |
|
- | 97 | { 192000, TMDS_296M, 23296, 281250 }, |
|
- | 98 | { 192000, TMDS_297M, 20480, 247500 }, |
|
66 | }; |
99 | }; |
67 | 100 | ||
68 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
101 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
69 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
102 | static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) |
Line 70... | Line 103... | ||
70 | { |
103 | { |
71 | int i; |
104 | int i; |
72 | 105 | ||
73 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
106 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
Line 74... | Line 107... | ||
74 | if (mode->clock == hdmi_audio_clock[i].clock) |
107 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
75 | break; |
108 | break; |
- | 109 | } |
|
76 | } |
110 | |
77 | 111 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
|
Line 78... | Line 112... | ||
78 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
112 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
79 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
113 | adjusted_mode->crtc_clock); |
80 | i = 1; |
114 | i = 1; |
Line 81... | Line 115... | ||
81 | } |
115 | } |
82 | 116 | ||
Line -... | Line 117... | ||
- | 117 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
|
- | 118 | hdmi_audio_clock[i].clock, |
|
- | 119 | hdmi_audio_clock[i].config); |
|
- | 120 | ||
- | 121 | return hdmi_audio_clock[i].config; |
|
- | 122 | } |
|
- | 123 | ||
- | 124 | static int audio_config_get_n(const struct drm_display_mode *mode, int rate) |
|
- | 125 | { |
|
- | 126 | int i; |
|
- | 127 | ||
- | 128 | for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { |
|
- | 129 | if ((rate == aud_ncts[i].sample_rate) && |
|
- | 130 | (mode->clock == aud_ncts[i].clock)) { |
|
- | 131 | return aud_ncts[i].n; |
|
- | 132 | } |
|
- | 133 | } |
|
- | 134 | return 0; |
|
- | 135 | } |
|
- | 136 | ||
- | 137 | static uint32_t audio_config_setup_n_reg(int n, uint32_t val) |
|
- | 138 | { |
|
- | 139 | int n_low, n_up; |
|
- | 140 | uint32_t tmp = val; |
|
- | 141 | ||
- | 142 | n_low = n & 0xfff; |
|
- | 143 | n_up = (n >> 12) & 0xff; |
|
- | 144 | tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); |
|
- | 145 | tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | |
|
- | 146 | (n_low << AUD_CONFIG_LOWER_N_SHIFT) | |
|
- | 147 | AUD_CONFIG_N_PROG_ENABLE); |
|
- | 148 | return tmp; |
|
- | 149 | } |
|
- | 150 | ||
- | 151 | /* check whether N/CTS/M need be set manually */ |
|
- | 152 | static bool audio_rate_need_prog(struct intel_crtc *crtc, |
|
- | 153 | const struct drm_display_mode *mode) |
|
- | 154 | { |
|
- | 155 | if (((mode->clock == TMDS_297M) || |
|
83 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
156 | (mode->clock == TMDS_296M)) && |
84 | hdmi_audio_clock[i].clock, |
157 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
85 | hdmi_audio_clock[i].config); |
158 | return true; |
86 | 159 | else |
|
87 | return hdmi_audio_clock[i].config; |
160 | return false; |
Line 133... | Line 206... | ||
133 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
206 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
134 | } |
207 | } |
Line 135... | Line 208... | ||
135 | 208 | ||
136 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
209 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
137 | struct intel_encoder *encoder, |
210 | struct intel_encoder *encoder, |
138 | struct drm_display_mode *mode) |
211 | const struct drm_display_mode *adjusted_mode) |
139 | { |
212 | { |
140 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
213 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
141 | uint8_t *eld = connector->eld; |
214 | uint8_t *eld = connector->eld; |
142 | uint32_t eldv; |
215 | uint32_t eldv; |
Line 179... | Line 252... | ||
179 | enum pipe pipe = intel_crtc->pipe; |
252 | enum pipe pipe = intel_crtc->pipe; |
180 | uint32_t tmp; |
253 | uint32_t tmp; |
Line 181... | Line 254... | ||
181 | 254 | ||
Line -... | Line 255... | ||
- | 255 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
|
- | 256 | ||
182 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
257 | mutex_lock(&dev_priv->av_mutex); |
183 | 258 | ||
184 | /* Disable timestamps */ |
259 | /* Disable timestamps */ |
185 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
260 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
186 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
261 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
Line 194... | Line 269... | ||
194 | /* Invalidate ELD */ |
269 | /* Invalidate ELD */ |
195 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
270 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
196 | tmp &= ~AUDIO_ELD_VALID(pipe); |
271 | tmp &= ~AUDIO_ELD_VALID(pipe); |
197 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
272 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
198 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
273 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
- | 274 | ||
- | 275 | mutex_unlock(&dev_priv->av_mutex); |
|
199 | } |
276 | } |
Line 200... | Line 277... | ||
200 | 277 | ||
201 | static void hsw_audio_codec_enable(struct drm_connector *connector, |
278 | static void hsw_audio_codec_enable(struct drm_connector *connector, |
202 | struct intel_encoder *encoder, |
279 | struct intel_encoder *encoder, |
203 | struct drm_display_mode *mode) |
280 | const struct drm_display_mode *adjusted_mode) |
204 | { |
281 | { |
205 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
282 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
206 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
283 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
- | 284 | enum pipe pipe = intel_crtc->pipe; |
|
207 | enum pipe pipe = intel_crtc->pipe; |
285 | struct i915_audio_component *acomp = dev_priv->audio_component; |
- | 286 | const uint8_t *eld = connector->eld; |
|
- | 287 | struct intel_digital_port *intel_dig_port = |
|
- | 288 | enc_to_dig_port(&encoder->base); |
|
208 | const uint8_t *eld = connector->eld; |
289 | enum port port = intel_dig_port->port; |
209 | uint32_t tmp; |
290 | uint32_t tmp; |
- | 291 | int len, i; |
|
Line 210... | Line 292... | ||
210 | int len, i; |
292 | int n, rate; |
211 | 293 | ||
Line -... | Line 294... | ||
- | 294 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
|
- | 295 | pipe_name(pipe), drm_eld_size(eld)); |
|
212 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
296 | |
213 | pipe_name(pipe), drm_eld_size(eld)); |
297 | mutex_lock(&dev_priv->av_mutex); |
214 | 298 | ||
215 | /* Enable audio presence detect, invalidate ELD */ |
299 | /* Enable audio presence detect, invalidate ELD */ |
216 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
300 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
Line 241... | Line 325... | ||
241 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
325 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
Line 242... | Line 326... | ||
242 | 326 | ||
243 | /* Enable timestamps */ |
327 | /* Enable timestamps */ |
244 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
328 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
245 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
- | |
246 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
329 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
247 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
330 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
248 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
331 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
249 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
332 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
250 | else |
333 | else |
- | 334 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
|
- | 335 | ||
- | 336 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
|
- | 337 | if (audio_rate_need_prog(intel_crtc, adjusted_mode)) { |
|
- | 338 | if (!acomp) |
|
- | 339 | rate = 0; |
|
- | 340 | else if (port >= PORT_A && port <= PORT_E) |
|
- | 341 | rate = acomp->aud_sample_rate[port]; |
|
- | 342 | else { |
|
- | 343 | DRM_ERROR("invalid port: %d\n", port); |
|
- | 344 | rate = 0; |
|
- | 345 | } |
|
- | 346 | n = audio_config_get_n(adjusted_mode, rate); |
|
- | 347 | if (n != 0) |
|
- | 348 | tmp = audio_config_setup_n_reg(n, tmp); |
|
- | 349 | else |
|
- | 350 | DRM_DEBUG_KMS("no suitable N value is found\n"); |
|
- | 351 | } |
|
251 | tmp |= audio_config_hdmi_pixel_clock(mode); |
352 | |
- | 353 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
|
- | 354 | ||
252 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
355 | mutex_unlock(&dev_priv->av_mutex); |
Line 253... | Line 356... | ||
253 | } |
356 | } |
254 | 357 | ||
255 | static void ilk_audio_codec_disable(struct intel_encoder *encoder) |
358 | static void ilk_audio_codec_disable(struct intel_encoder *encoder) |
Line 265... | Line 368... | ||
265 | int aud_cntrl_st2; |
368 | int aud_cntrl_st2; |
Line 266... | Line 369... | ||
266 | 369 | ||
267 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", |
370 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", |
Line -... | Line 371... | ||
- | 371 | port_name(port), pipe_name(pipe)); |
|
- | 372 | ||
- | 373 | if (WARN_ON(port == PORT_A)) |
|
268 | port_name(port), pipe_name(pipe)); |
374 | return; |
269 | 375 | ||
270 | if (HAS_PCH_IBX(dev_priv->dev)) { |
376 | if (HAS_PCH_IBX(dev_priv->dev)) { |
271 | aud_config = IBX_AUD_CFG(pipe); |
377 | aud_config = IBX_AUD_CFG(pipe); |
272 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
378 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
Line 286... | Line 392... | ||
286 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; |
392 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; |
287 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
393 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
288 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
394 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
289 | I915_WRITE(aud_config, tmp); |
395 | I915_WRITE(aud_config, tmp); |
Line 290... | Line -... | ||
290 | - | ||
291 | if (WARN_ON(!port)) { |
- | |
292 | eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | |
- | |
293 | IBX_ELD_VALID(PORT_D); |
- | |
294 | } else { |
396 | |
295 | eldv = IBX_ELD_VALID(port); |
- | |
Line 296... | Line 397... | ||
296 | } |
397 | eldv = IBX_ELD_VALID(port); |
297 | 398 | ||
298 | /* Invalidate ELD */ |
399 | /* Invalidate ELD */ |
299 | tmp = I915_READ(aud_cntrl_st2); |
400 | tmp = I915_READ(aud_cntrl_st2); |
300 | tmp &= ~eldv; |
401 | tmp &= ~eldv; |
Line 301... | Line 402... | ||
301 | I915_WRITE(aud_cntrl_st2, tmp); |
402 | I915_WRITE(aud_cntrl_st2, tmp); |
302 | } |
403 | } |
303 | 404 | ||
304 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
405 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
305 | struct intel_encoder *encoder, |
406 | struct intel_encoder *encoder, |
306 | struct drm_display_mode *mode) |
407 | const struct drm_display_mode *adjusted_mode) |
307 | { |
408 | { |
308 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
409 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Line 321... | Line 422... | ||
321 | int aud_cntrl_st2; |
422 | int aud_cntrl_st2; |
Line 322... | Line 423... | ||
322 | 423 | ||
323 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", |
424 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", |
Line -... | Line 425... | ||
- | 425 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
|
- | 426 | ||
- | 427 | if (WARN_ON(port == PORT_A)) |
|
324 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
428 | return; |
325 | 429 | ||
326 | /* |
430 | /* |
327 | * FIXME: We're supposed to wait for vblank here, but we have vblanks |
431 | * FIXME: We're supposed to wait for vblank here, but we have vblanks |
328 | * disabled during the mode set. The proper fix would be to push the |
432 | * disabled during the mode set. The proper fix would be to push the |
Line 345... | Line 449... | ||
345 | aud_config = CPT_AUD_CFG(pipe); |
449 | aud_config = CPT_AUD_CFG(pipe); |
346 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
450 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
347 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
451 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
348 | } |
452 | } |
Line 349... | Line -... | ||
349 | - | ||
350 | if (WARN_ON(!port)) { |
- | |
351 | eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | |
- | |
352 | IBX_ELD_VALID(PORT_D); |
- | |
353 | } else { |
453 | |
354 | eldv = IBX_ELD_VALID(port); |
- | |
Line 355... | Line 454... | ||
355 | } |
454 | eldv = IBX_ELD_VALID(port); |
356 | 455 | ||
357 | /* Invalidate ELD */ |
456 | /* Invalidate ELD */ |
358 | tmp = I915_READ(aud_cntrl_st2); |
457 | tmp = I915_READ(aud_cntrl_st2); |
Line 380... | Line 479... | ||
380 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
479 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
381 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
480 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
382 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
481 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
383 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
482 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
384 | else |
483 | else |
385 | tmp |= audio_config_hdmi_pixel_clock(mode); |
484 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
386 | I915_WRITE(aud_config, tmp); |
485 | I915_WRITE(aud_config, tmp); |
387 | } |
486 | } |
Line 388... | Line 487... | ||
388 | 487 | ||
389 | /** |
488 | /** |
Line 395... | Line 494... | ||
395 | */ |
494 | */ |
396 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) |
495 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) |
397 | { |
496 | { |
398 | struct drm_encoder *encoder = &intel_encoder->base; |
497 | struct drm_encoder *encoder = &intel_encoder->base; |
399 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
498 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
400 | struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
499 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
401 | struct drm_connector *connector; |
500 | struct drm_connector *connector; |
402 | struct drm_device *dev = encoder->dev; |
501 | struct drm_device *dev = encoder->dev; |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
502 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 503 | struct i915_audio_component *acomp = dev_priv->audio_component; |
|
- | 504 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
|
- | 505 | enum port port = intel_dig_port->port; |
|
Line 404... | Line 506... | ||
404 | 506 | ||
405 | connector = drm_select_eld(encoder, mode); |
507 | connector = drm_select_eld(encoder); |
406 | if (!connector) |
508 | if (!connector) |
Line 407... | Line 509... | ||
407 | return; |
509 | return; |
408 | 510 | ||
Line 415... | Line 517... | ||
415 | /* ELD Conn_Type */ |
517 | /* ELD Conn_Type */ |
416 | connector->eld[5] &= ~(3 << 2); |
518 | connector->eld[5] &= ~(3 << 2); |
417 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
519 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
418 | connector->eld[5] |= (1 << 2); |
520 | connector->eld[5] |= (1 << 2); |
Line 419... | Line 521... | ||
419 | 521 | ||
Line 420... | Line 522... | ||
420 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
522 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
421 | 523 | ||
- | 524 | if (dev_priv->display.audio_codec_enable) |
|
- | 525 | dev_priv->display.audio_codec_enable(connector, intel_encoder, |
|
- | 526 | adjusted_mode); |
|
- | 527 | ||
422 | if (dev_priv->display.audio_codec_enable) |
528 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
Line 423... | Line 529... | ||
423 | dev_priv->display.audio_codec_enable(connector, intel_encoder, mode); |
529 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); |
424 | } |
530 | } |
425 | 531 | ||
426 | /** |
532 | /** |
427 | * intel_audio_codec_disable - Disable the audio codec for HD audio |
533 | * intel_audio_codec_disable - Disable the audio codec for HD audio |
428 | * @encoder: encoder on which to disable audio |
534 | * @intel_encoder: encoder on which to disable audio |
429 | * |
535 | * |
430 | * The disable sequences must be performed before disabling the transcoder or |
536 | * The disable sequences must be performed before disabling the transcoder or |
431 | * port. |
537 | * port. |
- | 538 | */ |
|
432 | */ |
539 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
433 | void intel_audio_codec_disable(struct intel_encoder *encoder) |
540 | { |
- | 541 | struct drm_encoder *encoder = &intel_encoder->base; |
|
- | 542 | struct drm_device *dev = encoder->dev; |
|
- | 543 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
Line 434... | Line 544... | ||
434 | { |
544 | struct i915_audio_component *acomp = dev_priv->audio_component; |
435 | struct drm_device *dev = encoder->base.dev; |
545 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
- | 546 | enum port port = intel_dig_port->port; |
|
- | 547 | ||
- | 548 | if (dev_priv->display.audio_codec_disable) |
|
436 | struct drm_i915_private *dev_priv = dev->dev_private; |
549 | dev_priv->display.audio_codec_disable(intel_encoder); |
Line 437... | Line 550... | ||
437 | 550 | ||
438 | if (dev_priv->display.audio_codec_disable) |
551 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
439 | dev_priv->display.audio_codec_disable(encoder); |
552 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); |
Line 459... | Line 572... | ||
459 | } else if (HAS_PCH_SPLIT(dev)) { |
572 | } else if (HAS_PCH_SPLIT(dev)) { |
460 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
573 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
461 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
574 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
462 | } |
575 | } |
463 | }><>><>>>>>> |
576 | } |
- | 577 | ||
- | 578 | static void i915_audio_component_get_power(struct device *dev) |
|
- | 579 | { |
|
- | 580 | intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); |
|
- | 581 | } |
|
- | 582 | ||
- | 583 | static void i915_audio_component_put_power(struct device *dev) |
|
- | 584 | { |
|
- | 585 | intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); |
|
- | 586 | } |
|
- | 587 | ||
- | 588 | static void i915_audio_component_codec_wake_override(struct device *dev, |
|
- | 589 | bool enable) |
|
- | 590 | { |
|
- | 591 | struct drm_i915_private *dev_priv = dev_to_i915(dev); |
|
- | 592 | u32 tmp; |
|
- | 593 | ||
- | 594 | if (!IS_SKYLAKE(dev_priv)) |
|
- | 595 | return; |
|
- | 596 | ||
- | 597 | /* |
|
- | 598 | * Enable/disable generating the codec wake signal, overriding the |
|
- | 599 | * internal logic to generate the codec wake to controller. |
|
- | 600 | */ |
|
- | 601 | tmp = I915_READ(HSW_AUD_CHICKENBIT); |
|
- | 602 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; |
|
- | 603 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); |
|
- | 604 | usleep_range(1000, 1500); |
|
- | 605 | ||
- | 606 | if (enable) { |
|
- | 607 | tmp = I915_READ(HSW_AUD_CHICKENBIT); |
|
- | 608 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; |
|
- | 609 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); |
|
- | 610 | usleep_range(1000, 1500); |
|
- | 611 | } |
|
- | 612 | } |
|
- | 613 | ||
- | 614 | /* Get CDCLK in kHz */ |
|
- | 615 | static int i915_audio_component_get_cdclk_freq(struct device *dev) |
|
- | 616 | { |
|
- | 617 | struct drm_i915_private *dev_priv = dev_to_i915(dev); |
|
- | 618 | int ret; |
|
- | 619 | ||
- | 620 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) |
|
- | 621 | return -ENODEV; |
|
- | 622 | ||
- | 623 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
|
- | 624 | ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); |
|
- | 625 | ||
- | 626 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
|
- | 627 | ||
- | 628 | return ret; |
|
- | 629 | } |
|
- | 630 | ||
- | 631 | static int i915_audio_component_sync_audio_rate(struct device *dev, |
|
- | 632 | int port, int rate) |
|
- | 633 | { |
|
- | 634 | struct drm_i915_private *dev_priv = dev_to_i915(dev); |
|
- | 635 | struct drm_device *drm_dev = dev_priv->dev; |
|
- | 636 | struct intel_encoder *intel_encoder; |
|
- | 637 | struct intel_digital_port *intel_dig_port; |
|
- | 638 | struct intel_crtc *crtc; |
|
- | 639 | struct drm_display_mode *mode; |
|
- | 640 | struct i915_audio_component *acomp = dev_priv->audio_component; |
|
- | 641 | enum pipe pipe = -1; |
|
- | 642 | u32 tmp; |
|
- | 643 | int n; |
|
- | 644 | ||
- | 645 | /* HSW, BDW SKL need this fix */ |
|
- | 646 | if (!IS_SKYLAKE(dev_priv) && |
|
- | 647 | !IS_BROADWELL(dev_priv) && |
|
- | 648 | !IS_HASWELL(dev_priv)) |
|
- | 649 | return 0; |
|
- | 650 | ||
- | 651 | mutex_lock(&dev_priv->av_mutex); |
|
- | 652 | /* 1. get the pipe */ |
|
- | 653 | for_each_intel_encoder(drm_dev, intel_encoder) { |
|
- | 654 | if (intel_encoder->type != INTEL_OUTPUT_HDMI) |
|
- | 655 | continue; |
|
- | 656 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
|
- | 657 | if (port == intel_dig_port->port) { |
|
- | 658 | crtc = to_intel_crtc(intel_encoder->base.crtc); |
|
- | 659 | if (!crtc) { |
|
- | 660 | DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__); |
|
- | 661 | continue; |
|
- | 662 | } |
|
- | 663 | pipe = crtc->pipe; |
|
- | 664 | break; |
|
- | 665 | } |
|
- | 666 | } |
|
- | 667 | ||
- | 668 | if (pipe == INVALID_PIPE) { |
|
- | 669 | DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port)); |
|
- | 670 | mutex_unlock(&dev_priv->av_mutex); |
|
- | 671 | return -ENODEV; |
|
- | 672 | } |
|
- | 673 | DRM_DEBUG_KMS("pipe %c connects port %c\n", |
|
- | 674 | pipe_name(pipe), port_name(port)); |
|
- | 675 | mode = &crtc->config->base.adjusted_mode; |
|
- | 676 | ||
- | 677 | /* port must be valid now, otherwise the pipe will be invalid */ |
|
- | 678 | acomp->aud_sample_rate[port] = rate; |
|
- | 679 | ||
- | 680 | /* 2. check whether to set the N/CTS/M manually or not */ |
|
- | 681 | if (!audio_rate_need_prog(crtc, mode)) { |
|
- | 682 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
|
- | 683 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
|
- | 684 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
|
- | 685 | mutex_unlock(&dev_priv->av_mutex); |
|
- | 686 | return 0; |
|
- | 687 | } |
|
- | 688 | ||
- | 689 | n = audio_config_get_n(mode, rate); |
|
- | 690 | if (n == 0) { |
|
- | 691 | DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n", |
|
- | 692 | port_name(port)); |
|
- | 693 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
|
- | 694 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
|
- | 695 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
|
- | 696 | mutex_unlock(&dev_priv->av_mutex); |
|
- | 697 | return 0; |
|
- | 698 | } |
|
- | 699 | ||
- | 700 | /* 3. set the N/CTS/M */ |
|
- | 701 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
|
- | 702 | tmp = audio_config_setup_n_reg(n, tmp); |
|
- | 703 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
|
- | 704 | ||
- | 705 | mutex_unlock(&dev_priv->av_mutex); |
|
- | 706 | return 0; |
|
- | 707 | } |
|
- | 708 | ||
- | 709 | static const struct i915_audio_component_ops i915_audio_component_ops = { |
|
- | 710 | .owner = THIS_MODULE, |
|
- | 711 | .get_power = i915_audio_component_get_power, |
|
- | 712 | .put_power = i915_audio_component_put_power, |
|
- | 713 | .codec_wake_override = i915_audio_component_codec_wake_override, |
|
- | 714 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
|
- | 715 | .sync_audio_rate = i915_audio_component_sync_audio_rate, |
|
- | 716 | }; |
|
- | 717 | ||
- | 718 | static int i915_audio_component_bind(struct device *i915_dev, |
|
- | 719 | struct device *hda_dev, void *data) |
|
- | 720 | { |
|
- | 721 | struct i915_audio_component *acomp = data; |
|
- | 722 | struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); |
|
- | 723 | int i; |
|
- | 724 | ||
- | 725 | if (WARN_ON(acomp->ops || acomp->dev)) |
|
- | 726 | return -EEXIST; |
|
- | 727 | ||
- | 728 | drm_modeset_lock_all(dev_priv->dev); |
|
- | 729 | acomp->ops = &i915_audio_component_ops; |
|
- | 730 | acomp->dev = i915_dev; |
|
- | 731 | BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); |
|
- | 732 | for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) |
|
- | 733 | acomp->aud_sample_rate[i] = 0; |
|
- | 734 | dev_priv->audio_component = acomp; |
|
- | 735 | drm_modeset_unlock_all(dev_priv->dev); |
|
- | 736 | ||
- | 737 | return 0; |
|
- | 738 | } |
|
- | 739 | ||
- | 740 | static void i915_audio_component_unbind(struct device *i915_dev, |
|
- | 741 | struct device *hda_dev, void *data) |
|
- | 742 | { |
|
- | 743 | struct i915_audio_component *acomp = data; |
|
- | 744 | struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); |
|
- | 745 | ||
- | 746 | drm_modeset_lock_all(dev_priv->dev); |
|
- | 747 | acomp->ops = NULL; |
|
- | 748 | acomp->dev = NULL; |
|
- | 749 | dev_priv->audio_component = NULL; |
|
- | 750 | drm_modeset_unlock_all(dev_priv->dev); |
|
- | 751 | } |
|
- | 752 | ||
- | 753 | static const struct component_ops i915_audio_component_bind_ops = { |
|
- | 754 | .bind = i915_audio_component_bind, |
|
- | 755 | .unbind = i915_audio_component_unbind, |
|
- | 756 | }; |
|
- | 757 | ||
- | 758 | /** |
|
- | 759 | * i915_audio_component_init - initialize and register the audio component |
|
- | 760 | * @dev_priv: i915 device instance |
|
- | 761 | * |
|
- | 762 | * This will register with the component framework a child component which |
|
- | 763 | * will bind dynamically to the snd_hda_intel driver's corresponding master |
|
- | 764 | * component when the latter is registered. During binding the child |
|
- | 765 | * initializes an instance of struct i915_audio_component which it receives |
|
- | 766 | * from the master. The master can then start to use the interface defined by |
|
- | 767 | * this struct. Each side can break the binding at any point by deregistering |
|
- | 768 | * its own component after which each side's component unbind callback is |
|
- | 769 | * called. |
|
- | 770 | * |
|
- | 771 | * We ignore any error during registration and continue with reduced |
|
- | 772 | * functionality (i.e. without HDMI audio). |
|
- | 773 | */ |
|
- | 774 | void i915_audio_component_init(struct drm_i915_private *dev_priv) |
|
- | 775 | { |
|
- | 776 | } |
|
- | 777 | ||
- | 778 | /** |
|
- | 779 | * i915_audio_component_cleanup - deregister the audio component |
|
- | 780 | * @dev_priv: i915 device instance |
|
- | 781 | * |
|
- | 782 | * Deregisters the audio component, breaking any existing binding to the |
|
- | 783 | * corresponding snd_hda_intel driver's master component. |
|
- | 784 | */ |
|
- | 785 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) |
|
- | 786 | { |
|
- | 787 | }>><>><>>=>>>>><>><>>> |