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| Rev 6084 | Rev 6660 | ||
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| Line 2836... | Line 2836... | ||
| 2836 | #define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070) |
2836 | #define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070) |
| 2837 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
2837 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
| 2838 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
2838 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
| 2839 | #define BXT_RP_STATE_CAP 0x138170 |
2839 | #define BXT_RP_STATE_CAP 0x138170 |
| Line -... | Line 2840... | ||
| - | 2840 | ||
| - | 2841 | /* |
|
| - | 2842 | * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS |
|
| - | 2843 | * 8300) freezing up around GPU hangs. Looks as if even |
|
| - | 2844 | * scheduling/timer interrupts start misbehaving if the RPS |
|
| - | 2845 | * EI/thresholds are "bad", leading to a very sluggish or even |
|
| - | 2846 | * frozen machine. |
|
| 2840 | 2847 | */ |
|
| 2841 | #define INTERVAL_1_28_US(us) (((us) * 100) >> 7) |
2848 | #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) |
| 2842 | #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) |
2849 | #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) |
| 2843 | #define INTERVAL_0_833_US(us) (((us) * 6) / 5) |
2850 | #define INTERVAL_0_833_US(us) (((us) * 6) / 5) |
| 2844 | #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ |
2851 | #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ |
| 2845 | (IS_BROXTON(dev_priv) ? \ |
2852 | (IS_BROXTON(dev_priv) ? \ |
| Line 3231... | Line 3238... | ||
| 3231 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
3238 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
| 3232 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
3239 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
| Line 3233... | Line 3240... | ||
| 3233 | 3240 | ||
| 3234 | #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) |
3241 | #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) |
| 3235 | /* |
3242 | /* |
| 3236 | * HDMI/DP bits are gen4+ |
3243 | * HDMI/DP bits are g4x+ |
| 3237 | * |
3244 | * |
| 3238 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. |
3245 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. |
| 3239 | * Please check the detailed lore in the commit message for for experimental |
3246 | * Please check the detailed lore in the commit message for for experimental |
| 3240 | * evidence. |
3247 | * evidence. |
| - | 3248 | */ |
|
| - | 3249 | /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ |
|
| - | 3250 | #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) |
|
| - | 3251 | #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) |
|
| - | 3252 | #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) |
|
| 3241 | */ |
3253 | /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ |
| 3242 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
3254 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
| 3243 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
3255 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
| 3244 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
- | |
| 3245 | /* VLV DP/HDMI bits again match Bspec */ |
- | |
| 3246 | #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) |
- | |
| 3247 | #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) |
- | |
| 3248 | #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) |
3256 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
| 3249 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
3257 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
| 3250 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
3258 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
| 3251 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
3259 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
| 3252 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
3260 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
| Line 7348... | Line 7356... | ||
| 7348 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
7356 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
| 7349 | /* For each transcoder, we need to select the corresponding port clock */ |
7357 | /* For each transcoder, we need to select the corresponding port clock */ |
| 7350 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
7358 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
| 7351 | #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) |
7359 | #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) |
| Line -... | Line 7360... | ||
| - | 7360 | ||
| - | 7361 | #define CDCLK_FREQ 0x46200 |
|
| 7352 | 7362 | ||
| 7353 | #define TRANSA_MSA_MISC 0x60410 |
7363 | #define TRANSA_MSA_MISC 0x60410 |
| 7354 | #define TRANSB_MSA_MISC 0x61410 |
7364 | #define TRANSB_MSA_MISC 0x61410 |
| 7355 | #define TRANSC_MSA_MISC 0x62410 |
7365 | #define TRANSC_MSA_MISC 0x62410 |
| 7356 | #define TRANS_EDP_MSA_MISC 0x6f410 |
7366 | #define TRANS_EDP_MSA_MISC 0x6f410 |