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Rev 5354 | Rev 6084 | ||
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Line 29... | Line 29... | ||
29 | #define _PLANE(plane, a, b) _PIPE(plane, a, b) |
29 | #define _PLANE(plane, a, b) _PIPE(plane, a, b) |
30 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
30 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
32 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
32 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
33 | (pipe) == PIPE_B ? (b) : (c)) |
33 | (pipe) == PIPE_B ? (b) : (c)) |
- | 34 | #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ |
|
- | 35 | (port) == PORT_B ? (b) : (c)) |
|
Line 34... | Line 36... | ||
34 | 36 | ||
35 | #define _MASKED_FIELD(mask, value) ({ \ |
37 | #define _MASKED_FIELD(mask, value) ({ \ |
36 | if (__builtin_constant_p(mask)) \ |
38 | if (__builtin_constant_p(mask)) \ |
37 | BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ |
39 | BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ |
Line 46... | Line 48... | ||
46 | 48 | ||
Line 47... | Line 49... | ||
47 | 49 | ||
48 | 50 | ||
49 | /* PCI config space */ |
51 | /* PCI config space */ |
50 | 52 | ||
51 | #define HPLLCC 0xc0 /* 855 only */ |
53 | #define HPLLCC 0xc0 /* 85x only */ |
- | 54 | #define GC_CLOCK_CONTROL_MASK (0x7 << 0) |
|
- | 55 | #define GC_CLOCK_133_200 (0 << 0) |
|
- | 56 | #define GC_CLOCK_100_200 (1 << 0) |
|
- | 57 | #define GC_CLOCK_100_133 (2 << 0) |
|
52 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) |
58 | #define GC_CLOCK_133_266 (3 << 0) |
- | 59 | #define GC_CLOCK_133_200_2 (4 << 0) |
|
53 | #define GC_CLOCK_133_200 (0 << 0) |
60 | #define GC_CLOCK_133_266_2 (5 << 0) |
54 | #define GC_CLOCK_100_200 (1 << 0) |
61 | #define GC_CLOCK_166_266 (6 << 0) |
55 | #define GC_CLOCK_100_133 (2 << 0) |
62 | #define GC_CLOCK_166_250 (7 << 0) |
56 | #define GC_CLOCK_166_250 (3 << 0) |
63 | |
57 | #define GCFGC2 0xda |
64 | #define GCFGC2 0xda |
Line 96... | Line 103... | ||
96 | #define GRDOM_MEDIA (3<<2) |
103 | #define GRDOM_MEDIA (3<<2) |
97 | #define GRDOM_MASK (3<<2) |
104 | #define GRDOM_MASK (3<<2) |
98 | #define GRDOM_RESET_STATUS (1<<1) |
105 | #define GRDOM_RESET_STATUS (1<<1) |
99 | #define GRDOM_RESET_ENABLE (1<<0) |
106 | #define GRDOM_RESET_ENABLE (1<<0) |
Line 100... | Line 107... | ||
100 | 107 | ||
101 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
108 | #define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4) |
102 | #define ILK_GRDOM_FULL (0<<1) |
109 | #define ILK_GRDOM_FULL (0<<1) |
103 | #define ILK_GRDOM_RENDER (1<<1) |
110 | #define ILK_GRDOM_RENDER (1<<1) |
104 | #define ILK_GRDOM_MEDIA (3<<1) |
111 | #define ILK_GRDOM_MEDIA (3<<1) |
105 | #define ILK_GRDOM_MASK (3<<1) |
112 | #define ILK_GRDOM_MASK (3<<1) |
Line 135... | Line 142... | ||
135 | #define PP_DIR_DCLV_2G 0xffffffff |
142 | #define PP_DIR_DCLV_2G 0xffffffff |
Line 136... | Line 143... | ||
136 | 143 | ||
137 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) |
144 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) |
Line -... | Line 145... | ||
- | 145 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) |
|
- | 146 | ||
- | 147 | #define GEN8_R_PWR_CLK_STATE 0x20C8 |
|
- | 148 | #define GEN8_RPCS_ENABLE (1 << 31) |
|
- | 149 | #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) |
|
- | 150 | #define GEN8_RPCS_S_CNT_SHIFT 15 |
|
- | 151 | #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) |
|
- | 152 | #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) |
|
- | 153 | #define GEN8_RPCS_SS_CNT_SHIFT 8 |
|
- | 154 | #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) |
|
- | 155 | #define GEN8_RPCS_EU_MAX_SHIFT 4 |
|
- | 156 | #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) |
|
- | 157 | #define GEN8_RPCS_EU_MIN_SHIFT 0 |
|
138 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) |
158 | #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) |
- | 159 | ||
139 | 160 | #define GAM_ECOCHK 0x4090 |
|
- | 161 | #define BDW_DISABLE_HDC_INVALIDATION (1<<25) |
|
140 | #define GAM_ECOCHK 0x4090 |
162 | #define ECOCHK_SNB_BIT (1<<10) |
141 | #define ECOCHK_SNB_BIT (1<<10) |
163 | #define ECOCHK_DIS_TLB (1<<8) |
142 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
164 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
143 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
165 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
144 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
166 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
Line 154... | Line 176... | ||
154 | #define ECOBITS_PPGTT_CACHE4B (0<<8) |
176 | #define ECOBITS_PPGTT_CACHE4B (0<<8) |
Line 155... | Line 177... | ||
155 | 177 | ||
156 | #define GAB_CTL 0x24000 |
178 | #define GAB_CTL 0x24000 |
Line 157... | Line 179... | ||
157 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
179 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
- | 180 | ||
- | 181 | #define GEN6_STOLEN_RESERVED 0x1082C0 |
|
- | 182 | #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) |
|
- | 183 | #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) |
|
- | 184 | #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) |
|
- | 185 | #define GEN6_STOLEN_RESERVED_1M (0 << 4) |
|
- | 186 | #define GEN6_STOLEN_RESERVED_512K (1 << 4) |
|
- | 187 | #define GEN6_STOLEN_RESERVED_256K (2 << 4) |
|
158 | 188 | #define GEN6_STOLEN_RESERVED_128K (3 << 4) |
|
159 | #define GEN7_BIOS_RESERVED 0x1082C0 |
189 | #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) |
- | 190 | #define GEN7_STOLEN_RESERVED_1M (0 << 5) |
|
160 | #define GEN7_BIOS_RESERVED_1M (0 << 5) |
191 | #define GEN7_STOLEN_RESERVED_256K (1 << 5) |
161 | #define GEN7_BIOS_RESERVED_256K (1 << 5) |
192 | #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) |
162 | #define GEN8_BIOS_RESERVED_SHIFT 7 |
193 | #define GEN8_STOLEN_RESERVED_1M (0 << 7) |
163 | #define GEN7_BIOS_RESERVED_MASK 0x1 |
- | |
- | 194 | #define GEN8_STOLEN_RESERVED_2M (1 << 7) |
|
Line 164... | Line 195... | ||
164 | #define GEN8_BIOS_RESERVED_MASK 0x3 |
195 | #define GEN8_STOLEN_RESERVED_4M (2 << 7) |
Line 165... | Line 196... | ||
165 | 196 | #define GEN8_STOLEN_RESERVED_8M (3 << 7) |
|
166 | 197 | ||
Line 215... | Line 246... | ||
215 | #define INSTR_BC_CLIENT 0x2 |
246 | #define INSTR_BC_CLIENT 0x2 |
216 | #define INSTR_RC_CLIENT 0x3 |
247 | #define INSTR_RC_CLIENT 0x3 |
217 | #define INSTR_SUBCLIENT_SHIFT 27 |
248 | #define INSTR_SUBCLIENT_SHIFT 27 |
218 | #define INSTR_SUBCLIENT_MASK 0x18000000 |
249 | #define INSTR_SUBCLIENT_MASK 0x18000000 |
219 | #define INSTR_MEDIA_SUBCLIENT 0x2 |
250 | #define INSTR_MEDIA_SUBCLIENT 0x2 |
- | 251 | #define INSTR_26_TO_24_MASK 0x7000000 |
|
- | 252 | #define INSTR_26_TO_24_SHIFT 24 |
|
Line 220... | Line 253... | ||
220 | 253 | ||
221 | /* |
254 | /* |
222 | * Memory interface instructions used by the kernel |
255 | * Memory interface instructions used by the kernel |
223 | */ |
256 | */ |
Line 244... | Line 277... | ||
244 | #define MI_ARB_ENABLE (1<<0) |
277 | #define MI_ARB_ENABLE (1<<0) |
245 | #define MI_ARB_DISABLE (0<<0) |
278 | #define MI_ARB_DISABLE (0<<0) |
246 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
279 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
247 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
280 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
248 | #define MI_SUSPEND_FLUSH_EN (1<<0) |
281 | #define MI_SUSPEND_FLUSH_EN (1<<0) |
- | 282 | #define MI_SET_APPID MI_INSTR(0x0e, 0) |
|
249 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
283 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
250 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
284 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
251 | #define MI_OVERLAY_ON (0x1<<21) |
285 | #define MI_OVERLAY_ON (0x1<<21) |
252 | #define MI_OVERLAY_OFF (0x2<<21) |
286 | #define MI_OVERLAY_OFF (0x2<<21) |
253 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
287 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
Line 295... | Line 329... | ||
295 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
329 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
296 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
330 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
297 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
331 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
298 | #define MI_FORCE_RESTORE (1<<1) |
332 | #define MI_FORCE_RESTORE (1<<1) |
299 | #define MI_RESTORE_INHIBIT (1<<0) |
333 | #define MI_RESTORE_INHIBIT (1<<0) |
- | 334 | #define HSW_MI_RS_SAVE_STATE_EN (1<<3) |
|
- | 335 | #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) |
|
300 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
336 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
301 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) |
337 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) |
302 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
338 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
303 | #define MI_SEMAPHORE_POLL (1<<15) |
339 | #define MI_SEMAPHORE_POLL (1<<15) |
304 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) |
340 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) |
305 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
341 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
306 | #define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) |
342 | #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) |
307 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
343 | #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ |
- | 344 | #define MI_USE_GGTT (1 << 22) /* g4x+ */ |
|
308 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
345 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
309 | #define MI_STORE_DWORD_INDEX_SHIFT 2 |
346 | #define MI_STORE_DWORD_INDEX_SHIFT 2 |
310 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
347 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
311 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw |
348 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw |
312 | * simply ignores the register load under certain conditions. |
349 | * simply ignores the register load under certain conditions. |
313 | * - One can actually load arbitrary many arbitrary registers: Simply issue x |
350 | * - One can actually load arbitrary many arbitrary registers: Simply issue x |
314 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
351 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
315 | */ |
352 | */ |
316 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
353 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
317 | #define MI_LRI_FORCE_POSTED (1<<12) |
354 | #define MI_LRI_FORCE_POSTED (1<<12) |
318 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) |
355 | #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) |
319 | #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) |
356 | #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) |
320 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
357 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
321 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
358 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
322 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
359 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
323 | #define MI_INVALIDATE_TLB (1<<18) |
360 | #define MI_INVALIDATE_TLB (1<<18) |
324 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) |
361 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) |
325 | #define MI_FLUSH_DW_OP_MASK (3<<14) |
362 | #define MI_FLUSH_DW_OP_MASK (3<<14) |
326 | #define MI_FLUSH_DW_NOTIFY (1<<8) |
363 | #define MI_FLUSH_DW_NOTIFY (1<<8) |
327 | #define MI_INVALIDATE_BSD (1<<7) |
364 | #define MI_INVALIDATE_BSD (1<<7) |
328 | #define MI_FLUSH_DW_USE_GTT (1<<2) |
365 | #define MI_FLUSH_DW_USE_GTT (1<<2) |
329 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) |
366 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) |
- | 367 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) |
|
- | 368 | #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) |
|
330 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
369 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
331 | #define MI_BATCH_NON_SECURE (1) |
370 | #define MI_BATCH_NON_SECURE (1) |
332 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ |
371 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ |
333 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
372 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
334 | #define MI_BATCH_PPGTT_HSW (1<<8) |
373 | #define MI_BATCH_PPGTT_HSW (1<<8) |
335 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
374 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
336 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
375 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
337 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
376 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
338 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
377 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
- | 378 | #define MI_BATCH_RESOURCE_STREAMER (1<<10) |
|
Line 339... | Line 379... | ||
339 | 379 | ||
340 | #define MI_PREDICATE_SRC0 (0x2400) |
380 | #define MI_PREDICATE_SRC0 (0x2400) |
Line 341... | Line 381... | ||
341 | #define MI_PREDICATE_SRC1 (0x2408) |
381 | #define MI_PREDICATE_SRC1 (0x2408) |
Line 387... | Line 427... | ||
387 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
427 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
388 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
428 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
389 | #define ASYNC_FLIP (1<<22) |
429 | #define ASYNC_FLIP (1<<22) |
390 | #define DISPLAY_PLANE_A (0<<20) |
430 | #define DISPLAY_PLANE_A (0<<20) |
391 | #define DISPLAY_PLANE_B (1<<20) |
431 | #define DISPLAY_PLANE_B (1<<20) |
392 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
432 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) |
- | 433 | #define PIPE_CONTROL_FLUSH_L3 (1<<27) |
|
393 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
434 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
394 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) |
435 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) |
395 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
436 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
396 | #define PIPE_CONTROL_CS_STALL (1<<20) |
437 | #define PIPE_CONTROL_CS_STALL (1<<20) |
397 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
438 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
Line 404... | Line 445... | ||
404 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
445 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
405 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
446 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
406 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
447 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
407 | #define PIPE_CONTROL_NOTIFY (1<<8) |
448 | #define PIPE_CONTROL_NOTIFY (1<<8) |
408 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
449 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
- | 450 | #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) |
|
409 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
451 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
410 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
452 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
411 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
453 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
412 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
454 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
413 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
455 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
Line 427... | Line 469... | ||
427 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) |
469 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) |
428 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) |
470 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) |
429 | #define MI_CLFLUSH MI_INSTR(0x27, 0) |
471 | #define MI_CLFLUSH MI_INSTR(0x27, 0) |
430 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
472 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
431 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) |
473 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) |
432 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) |
- | |
433 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) |
474 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) |
434 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) |
475 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) |
435 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) |
476 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) |
436 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) |
477 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) |
437 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) |
478 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) |
Line 468... | Line 509... | ||
468 | /* |
509 | /* |
469 | * Registers used only by the command parser |
510 | * Registers used only by the command parser |
470 | */ |
511 | */ |
471 | #define BCS_SWCTRL 0x22200 |
512 | #define BCS_SWCTRL 0x22200 |
Line -... | Line 513... | ||
- | 513 | ||
472 | 514 | #define GPGPU_THREADS_DISPATCHED 0x2290 |
|
473 | #define HS_INVOCATION_COUNT 0x2300 |
515 | #define HS_INVOCATION_COUNT 0x2300 |
474 | #define DS_INVOCATION_COUNT 0x2308 |
516 | #define DS_INVOCATION_COUNT 0x2308 |
475 | #define IA_VERTICES_COUNT 0x2310 |
517 | #define IA_VERTICES_COUNT 0x2310 |
476 | #define IA_PRIMITIVES_COUNT 0x2318 |
518 | #define IA_PRIMITIVES_COUNT 0x2318 |
Line 492... | Line 534... | ||
492 | #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 |
534 | #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 |
493 | #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 |
535 | #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 |
494 | #define GEN7_3DPRIM_START_INSTANCE 0x243C |
536 | #define GEN7_3DPRIM_START_INSTANCE 0x243C |
495 | #define GEN7_3DPRIM_BASE_VERTEX 0x2440 |
537 | #define GEN7_3DPRIM_BASE_VERTEX 0x2440 |
Line -... | Line 538... | ||
- | 538 | ||
- | 539 | #define GEN7_GPGPU_DISPATCHDIMX 0x2500 |
|
- | 540 | #define GEN7_GPGPU_DISPATCHDIMY 0x2504 |
|
- | 541 | #define GEN7_GPGPU_DISPATCHDIMZ 0x2508 |
|
496 | 542 | ||
Line 497... | Line 543... | ||
497 | #define OACONTROL 0x2360 |
543 | #define OACONTROL 0x2360 |
498 | 544 | ||
499 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
545 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
Line 543... | Line 589... | ||
543 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) |
589 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) |
544 | #define DSPFREQSTAT_SHIFT 30 |
590 | #define DSPFREQSTAT_SHIFT 30 |
545 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
591 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
546 | #define DSPFREQGUAR_SHIFT 14 |
592 | #define DSPFREQGUAR_SHIFT 14 |
547 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
593 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
- | 594 | #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ |
|
- | 595 | #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ |
|
- | 596 | #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ |
|
548 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
597 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
549 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) |
598 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) |
550 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) |
599 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) |
551 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) |
600 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) |
552 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) |
601 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) |
Line 569... | Line 618... | ||
569 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, |
618 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, |
570 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, |
619 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, |
571 | PUNIT_POWER_WELL_DPIO_RX0 = 10, |
620 | PUNIT_POWER_WELL_DPIO_RX0 = 10, |
572 | PUNIT_POWER_WELL_DPIO_RX1 = 11, |
621 | PUNIT_POWER_WELL_DPIO_RX1 = 11, |
573 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
622 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
574 | /* FIXME: guesswork below */ |
- | |
575 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, |
- | |
576 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, |
- | |
577 | PUNIT_POWER_WELL_DPIO_RX2 = 15, |
- | |
Line 578... | Line 623... | ||
578 | 623 | ||
579 | PUNIT_POWER_WELL_NUM, |
624 | PUNIT_POWER_WELL_NUM, |
Line -... | Line 625... | ||
- | 625 | }; |
|
- | 626 | ||
- | 627 | enum skl_disp_power_wells { |
|
- | 628 | SKL_DISP_PW_MISC_IO, |
|
- | 629 | SKL_DISP_PW_DDI_A_E, |
|
- | 630 | SKL_DISP_PW_DDI_B, |
|
- | 631 | SKL_DISP_PW_DDI_C, |
|
- | 632 | SKL_DISP_PW_DDI_D, |
|
- | 633 | SKL_DISP_PW_1 = 14, |
|
- | 634 | SKL_DISP_PW_2, |
|
- | 635 | }; |
|
- | 636 | ||
- | 637 | #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) |
|
580 | }; |
638 | #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) |
581 | 639 | ||
582 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
640 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
583 | #define PUNIT_REG_PWRGT_STATUS 0x61 |
641 | #define PUNIT_REG_PWRGT_STATUS 0x61 |
584 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
642 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
Line 596... | Line 654... | ||
596 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
654 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
Line 597... | Line 655... | ||
597 | 655 | ||
598 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ |
656 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ |
Line -... | Line 657... | ||
- | 657 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ |
|
- | 658 | ||
- | 659 | #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 |
|
- | 660 | #define FB_GFX_FREQ_FUSE_MASK 0xff |
|
- | 661 | #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 |
|
- | 662 | #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 |
|
- | 663 | #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 |
|
- | 664 | ||
- | 665 | #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 |
|
- | 666 | #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 |
|
- | 667 | ||
- | 668 | #define PUNIT_REG_DDR_SETUP2 0x139 |
|
- | 669 | #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) |
|
- | 670 | #define FORCE_DDR_LOW_FREQ (1 << 1) |
|
599 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ |
671 | #define FORCE_DDR_HIGH_FREQ (1 << 0) |
600 | 672 | ||
601 | #define PUNIT_GPU_STATUS_REG 0xdb |
673 | #define PUNIT_GPU_STATUS_REG 0xdb |
602 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 |
674 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 |
603 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |
675 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |
Line 617... | Line 689... | ||
617 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
689 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
618 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
690 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
619 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
691 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
620 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
692 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
Line -... | Line 693... | ||
- | 693 | ||
- | 694 | #define VLV_TURBO_SOC_OVERRIDE 0x04 |
|
- | 695 | #define VLV_OVERRIDE_EN 1 |
|
- | 696 | #define VLV_SOC_TDP_EN (1 << 1) |
|
- | 697 | #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) |
|
- | 698 | #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) |
|
621 | 699 | ||
622 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
- | |
623 | #define VLV_RP_UP_EI_THRESHOLD 90 |
- | |
624 | #define VLV_RP_DOWN_EI_THRESHOLD 70 |
- | |
Line 625... | Line 700... | ||
625 | #define VLV_INT_COUNT_FOR_DOWN_EI 5 |
700 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
626 | 701 | ||
627 | /* vlv2 north clock has */ |
702 | /* vlv2 north clock has */ |
628 | #define CCK_FUSE_REG 0x8 |
703 | #define CCK_FUSE_REG 0x8 |
Line 655... | Line 730... | ||
655 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) |
730 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) |
656 | #define DSI_PLL_N1_DIV_SHIFT 16 |
731 | #define DSI_PLL_N1_DIV_SHIFT 16 |
657 | #define DSI_PLL_N1_DIV_MASK (3 << 16) |
732 | #define DSI_PLL_N1_DIV_MASK (3 << 16) |
658 | #define DSI_PLL_M1_DIV_SHIFT 0 |
733 | #define DSI_PLL_M1_DIV_SHIFT 0 |
659 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
734 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
- | 735 | #define CCK_CZ_CLOCK_CONTROL 0x62 |
|
660 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
736 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
661 | #define DISPLAY_TRUNK_FORCE_ON (1 << 17) |
737 | #define CCK_TRUNK_FORCE_ON (1 << 17) |
662 | #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) |
738 | #define CCK_TRUNK_FORCE_OFF (1 << 16) |
663 | #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) |
739 | #define CCK_FREQUENCY_STATUS (0x1f << 8) |
664 | #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 |
740 | #define CCK_FREQUENCY_STATUS_SHIFT 8 |
665 | #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) |
741 | #define CCK_FREQUENCY_VALUES (0x1f << 0) |
Line 666... | Line 742... | ||
666 | 742 | ||
667 | /** |
743 | /** |
668 | * DOC: DPIO |
744 | * DOC: DPIO |
669 | * |
745 | * |
670 | * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI |
746 | * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI |
671 | * ports. DPIO is the name given to such a display PHY. These PHYs |
747 | * ports. DPIO is the name given to such a display PHY. These PHYs |
672 | * don't follow the standard programming model using direct MMIO |
748 | * don't follow the standard programming model using direct MMIO |
673 | * registers, and instead their registers must be accessed trough IOSF |
749 | * registers, and instead their registers must be accessed trough IOSF |
674 | * sideband. VLV has one such PHY for driving ports B and C, and CHV |
750 | * sideband. VLV has one such PHY for driving ports B and C, and CHV |
Line 696... | Line 772... | ||
696 | * for each channel. This is used for DP AUX communication, but |
772 | * for each channel. This is used for DP AUX communication, but |
697 | * this fact isn't really relevant for the driver since AUX is |
773 | * this fact isn't really relevant for the driver since AUX is |
698 | * controlled from the display controller side. No DPIO registers |
774 | * controlled from the display controller side. No DPIO registers |
699 | * need to be accessed during AUX communication, |
775 | * need to be accessed during AUX communication, |
700 | * |
776 | * |
701 | * Generally the common lane corresponds to the pipe and |
777 | * Generally on VLV/CHV the common lane corresponds to the pipe and |
702 | * the spline (PCS/TX) corresponds to the port. |
778 | * the spline (PCS/TX) corresponds to the port. |
703 | * |
779 | * |
704 | * For dual channel PHY (VLV/CHV): |
780 | * For dual channel PHY (VLV/CHV): |
705 | * |
781 | * |
706 | * pipe A == CMN/PLL/REF CH0 |
782 | * pipe A == CMN/PLL/REF CH0 |
Line 718... | Line 794... | ||
718 | * |
794 | * |
719 | * pipe C == CMN/PLL/REF CH0 |
795 | * pipe C == CMN/PLL/REF CH0 |
720 | * |
796 | * |
721 | * port D == PCS/TX CH0 |
797 | * port D == PCS/TX CH0 |
722 | * |
798 | * |
- | 799 | * On BXT the entire PHY channel corresponds to the port. That means |
|
- | 800 | * the PLL is also now associated with the port rather than the pipe, |
|
- | 801 | * and so the clock needs to be routed to the appropriate transcoder. |
|
- | 802 | * Port A PLL is directly connected to transcoder EDP and port B/C |
|
- | 803 | * PLLs can be routed to any transcoder A/B/C. |
|
- | 804 | * |
|
723 | * Note: digital port B is DDI0, digital port C is DDI1, |
805 | * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is |
724 | * digital port D is DDI2 |
806 | * digital port D (CHV) or port A (BXT). |
725 | */ |
807 | */ |
726 | /* |
808 | /* |
727 | * Dual channel PHY (VLV/CHV) |
809 | * Dual channel PHY (VLV/CHV/BXT) |
728 | * --------------------------------- |
810 | * --------------------------------- |
729 | * | CH0 | CH1 | |
811 | * | CH0 | CH1 | |
730 | * | CMN/PLL/REF | CMN/PLL/REF | |
812 | * | CMN/PLL/REF | CMN/PLL/REF | |
731 | * |---------------|---------------| Display PHY |
813 | * |---------------|---------------| Display PHY |
732 | * | PCS01 | PCS23 | PCS01 | PCS23 | |
814 | * | PCS01 | PCS23 | PCS01 | PCS23 | |
Line 734... | Line 816... | ||
734 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| |
816 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| |
735 | * --------------------------------- |
817 | * --------------------------------- |
736 | * | DDI0 | DDI1 | DP/HDMI ports |
818 | * | DDI0 | DDI1 | DP/HDMI ports |
737 | * --------------------------------- |
819 | * --------------------------------- |
738 | * |
820 | * |
739 | * Single channel PHY (CHV) |
821 | * Single channel PHY (CHV/BXT) |
740 | * ----------------- |
822 | * ----------------- |
741 | * | CH0 | |
823 | * | CH0 | |
742 | * | CMN/PLL/REF | |
824 | * | CMN/PLL/REF | |
743 | * |---------------| Display PHY |
825 | * |---------------| Display PHY |
744 | * | PCS01 | PCS23 | |
826 | * | PCS01 | PCS23 | |
Line 899... | Line 981... | ||
899 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
981 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
900 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
982 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
Line 901... | Line 983... | ||
901 | 983 | ||
902 | #define _VLV_PCS_DW11_CH0 0x822c |
984 | #define _VLV_PCS_DW11_CH0 0x822c |
- | 985 | #define _VLV_PCS_DW11_CH1 0x842c |
|
903 | #define _VLV_PCS_DW11_CH1 0x842c |
986 | #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) |
904 | #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) |
987 | #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) |
905 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) |
988 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) |
906 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) |
989 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) |
Line 911... | Line 994... | ||
911 | #define _VLV_PCS01_DW11_CH1 0x262c |
994 | #define _VLV_PCS01_DW11_CH1 0x262c |
912 | #define _VLV_PCS23_DW11_CH1 0x282c |
995 | #define _VLV_PCS23_DW11_CH1 0x282c |
913 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
996 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
914 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) |
997 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) |
Line -... | Line 998... | ||
- | 998 | ||
- | 999 | #define _VLV_PCS01_DW12_CH0 0x0230 |
|
- | 1000 | #define _VLV_PCS23_DW12_CH0 0x0430 |
|
- | 1001 | #define _VLV_PCS01_DW12_CH1 0x2630 |
|
- | 1002 | #define _VLV_PCS23_DW12_CH1 0x2830 |
|
- | 1003 | #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) |
|
- | 1004 | #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) |
|
915 | 1005 | ||
916 | #define _VLV_PCS_DW12_CH0 0x8230 |
1006 | #define _VLV_PCS_DW12_CH0 0x8230 |
- | 1007 | #define _VLV_PCS_DW12_CH1 0x8430 |
|
- | 1008 | #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) |
|
- | 1009 | #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) |
|
- | 1010 | #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) |
|
- | 1011 | #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) |
|
917 | #define _VLV_PCS_DW12_CH1 0x8430 |
1012 | #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) |
Line 918... | Line 1013... | ||
918 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
1013 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
919 | 1014 | ||
920 | #define _VLV_PCS_DW14_CH0 0x8238 |
1015 | #define _VLV_PCS_DW14_CH0 0x8238 |
Line 984... | Line 1079... | ||
984 | #define _CHV_PLL_DW3_CH1 0x818c |
1079 | #define _CHV_PLL_DW3_CH1 0x818c |
985 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
1080 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
986 | #define DPIO_CHV_FIRST_MOD (0 << 8) |
1081 | #define DPIO_CHV_FIRST_MOD (0 << 8) |
987 | #define DPIO_CHV_SECOND_MOD (1 << 8) |
1082 | #define DPIO_CHV_SECOND_MOD (1 << 8) |
988 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
1083 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
- | 1084 | #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) |
|
989 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
1085 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
Line 990... | Line 1086... | ||
990 | 1086 | ||
991 | #define _CHV_PLL_DW6_CH0 0x8018 |
1087 | #define _CHV_PLL_DW6_CH0 0x8018 |
992 | #define _CHV_PLL_DW6_CH1 0x8198 |
1088 | #define _CHV_PLL_DW6_CH1 0x8198 |
993 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
1089 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
994 | #define DPIO_CHV_INT_COEFF_SHIFT 8 |
1090 | #define DPIO_CHV_INT_COEFF_SHIFT 8 |
995 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 |
1091 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 |
Line -... | Line 1092... | ||
- | 1092 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
|
- | 1093 | ||
- | 1094 | #define _CHV_PLL_DW8_CH0 0x8020 |
|
- | 1095 | #define _CHV_PLL_DW8_CH1 0x81A0 |
|
- | 1096 | #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 |
|
- | 1097 | #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) |
|
- | 1098 | #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) |
|
- | 1099 | ||
- | 1100 | #define _CHV_PLL_DW9_CH0 0x8024 |
|
- | 1101 | #define _CHV_PLL_DW9_CH1 0x81A4 |
|
- | 1102 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ |
|
- | 1103 | #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) |
|
- | 1104 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ |
|
- | 1105 | #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) |
|
- | 1106 | ||
- | 1107 | #define _CHV_CMN_DW0_CH0 0x8100 |
|
- | 1108 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 |
|
- | 1109 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 |
|
- | 1110 | #define DPIO_ALLDL_POWERDOWN (1 << 1) |
|
996 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
1111 | #define DPIO_ANYDL_POWERDOWN (1 << 0) |
997 | 1112 | ||
998 | #define _CHV_CMN_DW5_CH0 0x8114 |
1113 | #define _CHV_CMN_DW5_CH0 0x8114 |
999 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
1114 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
1000 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
1115 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
Line 1029... | Line 1144... | ||
1029 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
1144 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
1030 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
1145 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
Line 1031... | Line 1146... | ||
1031 | 1146 | ||
1032 | #define _CHV_CMN_DW19_CH0 0x814c |
1147 | #define _CHV_CMN_DW19_CH0 0x814c |
- | 1148 | #define _CHV_CMN_DW6_CH1 0x8098 |
|
- | 1149 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ |
|
- | 1150 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ |
|
1033 | #define _CHV_CMN_DW6_CH1 0x8098 |
1151 | #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ |
- | 1152 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
|
1034 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
1153 | |
Line -... | Line 1154... | ||
- | 1154 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
|
- | 1155 | ||
- | 1156 | #define CHV_CMN_DW28 0x8170 |
|
- | 1157 | #define DPIO_CL1POWERDOWNEN (1 << 23) |
|
- | 1158 | #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) |
|
- | 1159 | #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) |
|
- | 1160 | #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) |
|
- | 1161 | #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) |
|
1035 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
1162 | #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) |
- | 1163 | ||
1036 | 1164 | #define CHV_CMN_DW30 0x8178 |
|
Line 1037... | Line 1165... | ||
1037 | #define CHV_CMN_DW30 0x8178 |
1165 | #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) |
1038 | #define DPIO_LRC_BYPASS (1 << 3) |
1166 | #define DPIO_LRC_BYPASS (1 << 3) |
Line 1053... | Line 1181... | ||
1053 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
1181 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
1054 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
1182 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
1055 | #define DPIO_FRC_LATENCY_SHFIT 8 |
1183 | #define DPIO_FRC_LATENCY_SHFIT 8 |
1056 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
1184 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
1057 | #define DPIO_UPAR_SHIFT 30 |
1185 | #define DPIO_UPAR_SHIFT 30 |
- | 1186 | ||
- | 1187 | /* BXT PHY registers */ |
|
- | 1188 | #define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b)) |
|
- | 1189 | ||
- | 1190 | #define BXT_P_CR_GT_DISP_PWRON 0x138090 |
|
- | 1191 | #define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) |
|
- | 1192 | ||
- | 1193 | #define _PHY_CTL_FAMILY_EDP 0x64C80 |
|
- | 1194 | #define _PHY_CTL_FAMILY_DDI 0x64C90 |
|
- | 1195 | #define COMMON_RESET_DIS (1 << 31) |
|
- | 1196 | #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ |
|
- | 1197 | _PHY_CTL_FAMILY_EDP) |
|
- | 1198 | ||
- | 1199 | /* BXT PHY PLL registers */ |
|
- | 1200 | #define _PORT_PLL_A 0x46074 |
|
- | 1201 | #define _PORT_PLL_B 0x46078 |
|
- | 1202 | #define _PORT_PLL_C 0x4607c |
|
- | 1203 | #define PORT_PLL_ENABLE (1 << 31) |
|
- | 1204 | #define PORT_PLL_LOCK (1 << 30) |
|
- | 1205 | #define PORT_PLL_REF_SEL (1 << 27) |
|
- | 1206 | #define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B) |
|
- | 1207 | ||
- | 1208 | #define _PORT_PLL_EBB_0_A 0x162034 |
|
- | 1209 | #define _PORT_PLL_EBB_0_B 0x6C034 |
|
- | 1210 | #define _PORT_PLL_EBB_0_C 0x6C340 |
|
- | 1211 | #define PORT_PLL_P1_SHIFT 13 |
|
- | 1212 | #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) |
|
- | 1213 | #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) |
|
- | 1214 | #define PORT_PLL_P2_SHIFT 8 |
|
- | 1215 | #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) |
|
- | 1216 | #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) |
|
- | 1217 | #define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \ |
|
- | 1218 | _PORT_PLL_EBB_0_B, \ |
|
- | 1219 | _PORT_PLL_EBB_0_C) |
|
- | 1220 | ||
- | 1221 | #define _PORT_PLL_EBB_4_A 0x162038 |
|
- | 1222 | #define _PORT_PLL_EBB_4_B 0x6C038 |
|
- | 1223 | #define _PORT_PLL_EBB_4_C 0x6C344 |
|
- | 1224 | #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) |
|
- | 1225 | #define PORT_PLL_RECALIBRATE (1 << 14) |
|
- | 1226 | #define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \ |
|
- | 1227 | _PORT_PLL_EBB_4_B, \ |
|
- | 1228 | _PORT_PLL_EBB_4_C) |
|
- | 1229 | ||
- | 1230 | #define _PORT_PLL_0_A 0x162100 |
|
- | 1231 | #define _PORT_PLL_0_B 0x6C100 |
|
- | 1232 | #define _PORT_PLL_0_C 0x6C380 |
|
- | 1233 | /* PORT_PLL_0_A */ |
|
- | 1234 | #define PORT_PLL_M2_MASK 0xFF |
|
- | 1235 | /* PORT_PLL_1_A */ |
|
- | 1236 | #define PORT_PLL_N_SHIFT 8 |
|
- | 1237 | #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) |
|
- | 1238 | #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) |
|
- | 1239 | /* PORT_PLL_2_A */ |
|
- | 1240 | #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF |
|
- | 1241 | /* PORT_PLL_3_A */ |
|
- | 1242 | #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) |
|
- | 1243 | /* PORT_PLL_6_A */ |
|
- | 1244 | #define PORT_PLL_PROP_COEFF_MASK 0xF |
|
- | 1245 | #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) |
|
- | 1246 | #define PORT_PLL_INT_COEFF(x) ((x) << 8) |
|
- | 1247 | #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) |
|
- | 1248 | #define PORT_PLL_GAIN_CTL(x) ((x) << 16) |
|
- | 1249 | /* PORT_PLL_8_A */ |
|
- | 1250 | #define PORT_PLL_TARGET_CNT_MASK 0x3FF |
|
- | 1251 | /* PORT_PLL_9_A */ |
|
- | 1252 | #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 |
|
- | 1253 | #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) |
|
- | 1254 | /* PORT_PLL_10_A */ |
|
- | 1255 | #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) |
|
- | 1256 | #define PORT_PLL_DCO_AMP_DEFAULT 15 |
|
- | 1257 | #define PORT_PLL_DCO_AMP_MASK 0x3c00 |
|
- | 1258 | #define PORT_PLL_DCO_AMP(x) ((x)<<10) |
|
- | 1259 | #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ |
|
- | 1260 | _PORT_PLL_0_B, \ |
|
- | 1261 | _PORT_PLL_0_C) |
|
- | 1262 | #define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4) |
|
- | 1263 | ||
- | 1264 | /* BXT PHY common lane registers */ |
|
- | 1265 | #define _PORT_CL1CM_DW0_A 0x162000 |
|
- | 1266 | #define _PORT_CL1CM_DW0_BC 0x6C000 |
|
- | 1267 | #define PHY_POWER_GOOD (1 << 16) |
|
- | 1268 | #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ |
|
- | 1269 | _PORT_CL1CM_DW0_A) |
|
- | 1270 | ||
- | 1271 | #define _PORT_CL1CM_DW9_A 0x162024 |
|
- | 1272 | #define _PORT_CL1CM_DW9_BC 0x6C024 |
|
- | 1273 | #define IREF0RC_OFFSET_SHIFT 8 |
|
- | 1274 | #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) |
|
- | 1275 | #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \ |
|
- | 1276 | _PORT_CL1CM_DW9_A) |
|
- | 1277 | ||
- | 1278 | #define _PORT_CL1CM_DW10_A 0x162028 |
|
- | 1279 | #define _PORT_CL1CM_DW10_BC 0x6C028 |
|
- | 1280 | #define IREF1RC_OFFSET_SHIFT 8 |
|
- | 1281 | #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) |
|
- | 1282 | #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \ |
|
- | 1283 | _PORT_CL1CM_DW10_A) |
|
- | 1284 | ||
- | 1285 | #define _PORT_CL1CM_DW28_A 0x162070 |
|
- | 1286 | #define _PORT_CL1CM_DW28_BC 0x6C070 |
|
- | 1287 | #define OCL1_POWER_DOWN_EN (1 << 23) |
|
- | 1288 | #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) |
|
- | 1289 | #define SUS_CLK_CONFIG 0x3 |
|
- | 1290 | #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \ |
|
- | 1291 | _PORT_CL1CM_DW28_A) |
|
- | 1292 | ||
- | 1293 | #define _PORT_CL1CM_DW30_A 0x162078 |
|
- | 1294 | #define _PORT_CL1CM_DW30_BC 0x6C078 |
|
- | 1295 | #define OCL2_LDOFUSE_PWR_DIS (1 << 6) |
|
- | 1296 | #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \ |
|
- | 1297 | _PORT_CL1CM_DW30_A) |
|
- | 1298 | ||
- | 1299 | /* Defined for PHY0 only */ |
|
- | 1300 | #define BXT_PORT_CL2CM_DW6_BC 0x6C358 |
|
- | 1301 | #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) |
|
- | 1302 | ||
- | 1303 | /* BXT PHY Ref registers */ |
|
- | 1304 | #define _PORT_REF_DW3_A 0x16218C |
|
- | 1305 | #define _PORT_REF_DW3_BC 0x6C18C |
|
- | 1306 | #define GRC_DONE (1 << 22) |
|
- | 1307 | #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \ |
|
- | 1308 | _PORT_REF_DW3_A) |
|
- | 1309 | ||
- | 1310 | #define _PORT_REF_DW6_A 0x162198 |
|
- | 1311 | #define _PORT_REF_DW6_BC 0x6C198 |
|
- | 1312 | /* |
|
- | 1313 | * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them |
|
- | 1314 | * after testing. |
|
- | 1315 | */ |
|
- | 1316 | #define GRC_CODE_SHIFT 23 |
|
- | 1317 | #define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT) |
|
- | 1318 | #define GRC_CODE_FAST_SHIFT 16 |
|
- | 1319 | #define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT) |
|
- | 1320 | #define GRC_CODE_SLOW_SHIFT 8 |
|
- | 1321 | #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) |
|
- | 1322 | #define GRC_CODE_NOM_MASK 0xFF |
|
- | 1323 | #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \ |
|
- | 1324 | _PORT_REF_DW6_A) |
|
- | 1325 | ||
- | 1326 | #define _PORT_REF_DW8_A 0x1621A0 |
|
- | 1327 | #define _PORT_REF_DW8_BC 0x6C1A0 |
|
- | 1328 | #define GRC_DIS (1 << 15) |
|
- | 1329 | #define GRC_RDY_OVRD (1 << 1) |
|
- | 1330 | #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ |
|
- | 1331 | _PORT_REF_DW8_A) |
|
- | 1332 | ||
- | 1333 | /* BXT PHY PCS registers */ |
|
- | 1334 | #define _PORT_PCS_DW10_LN01_A 0x162428 |
|
- | 1335 | #define _PORT_PCS_DW10_LN01_B 0x6C428 |
|
- | 1336 | #define _PORT_PCS_DW10_LN01_C 0x6C828 |
|
- | 1337 | #define _PORT_PCS_DW10_GRP_A 0x162C28 |
|
- | 1338 | #define _PORT_PCS_DW10_GRP_B 0x6CC28 |
|
- | 1339 | #define _PORT_PCS_DW10_GRP_C 0x6CE28 |
|
- | 1340 | #define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \ |
|
- | 1341 | _PORT_PCS_DW10_LN01_B, \ |
|
- | 1342 | _PORT_PCS_DW10_LN01_C) |
|
- | 1343 | #define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \ |
|
- | 1344 | _PORT_PCS_DW10_GRP_B, \ |
|
- | 1345 | _PORT_PCS_DW10_GRP_C) |
|
- | 1346 | #define TX2_SWING_CALC_INIT (1 << 31) |
|
- | 1347 | #define TX1_SWING_CALC_INIT (1 << 30) |
|
- | 1348 | ||
- | 1349 | #define _PORT_PCS_DW12_LN01_A 0x162430 |
|
- | 1350 | #define _PORT_PCS_DW12_LN01_B 0x6C430 |
|
- | 1351 | #define _PORT_PCS_DW12_LN01_C 0x6C830 |
|
- | 1352 | #define _PORT_PCS_DW12_LN23_A 0x162630 |
|
- | 1353 | #define _PORT_PCS_DW12_LN23_B 0x6C630 |
|
- | 1354 | #define _PORT_PCS_DW12_LN23_C 0x6CA30 |
|
- | 1355 | #define _PORT_PCS_DW12_GRP_A 0x162c30 |
|
- | 1356 | #define _PORT_PCS_DW12_GRP_B 0x6CC30 |
|
- | 1357 | #define _PORT_PCS_DW12_GRP_C 0x6CE30 |
|
- | 1358 | #define LANESTAGGER_STRAP_OVRD (1 << 6) |
|
- | 1359 | #define LANE_STAGGER_MASK 0x1F |
|
- | 1360 | #define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \ |
|
- | 1361 | _PORT_PCS_DW12_LN01_B, \ |
|
- | 1362 | _PORT_PCS_DW12_LN01_C) |
|
- | 1363 | #define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \ |
|
- | 1364 | _PORT_PCS_DW12_LN23_B, \ |
|
- | 1365 | _PORT_PCS_DW12_LN23_C) |
|
- | 1366 | #define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \ |
|
- | 1367 | _PORT_PCS_DW12_GRP_B, \ |
|
- | 1368 | _PORT_PCS_DW12_GRP_C) |
|
- | 1369 | ||
- | 1370 | /* BXT PHY TX registers */ |
|
- | 1371 | #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ |
|
- | 1372 | ((lane) & 1) * 0x80) |
|
- | 1373 | ||
- | 1374 | #define _PORT_TX_DW2_LN0_A 0x162508 |
|
- | 1375 | #define _PORT_TX_DW2_LN0_B 0x6C508 |
|
- | 1376 | #define _PORT_TX_DW2_LN0_C 0x6C908 |
|
- | 1377 | #define _PORT_TX_DW2_GRP_A 0x162D08 |
|
- | 1378 | #define _PORT_TX_DW2_GRP_B 0x6CD08 |
|
- | 1379 | #define _PORT_TX_DW2_GRP_C 0x6CF08 |
|
- | 1380 | #define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \ |
|
- | 1381 | _PORT_TX_DW2_GRP_B, \ |
|
- | 1382 | _PORT_TX_DW2_GRP_C) |
|
- | 1383 | #define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \ |
|
- | 1384 | _PORT_TX_DW2_LN0_B, \ |
|
- | 1385 | _PORT_TX_DW2_LN0_C) |
|
- | 1386 | #define MARGIN_000_SHIFT 16 |
|
- | 1387 | #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) |
|
- | 1388 | #define UNIQ_TRANS_SCALE_SHIFT 8 |
|
- | 1389 | #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) |
|
- | 1390 | ||
- | 1391 | #define _PORT_TX_DW3_LN0_A 0x16250C |
|
- | 1392 | #define _PORT_TX_DW3_LN0_B 0x6C50C |
|
- | 1393 | #define _PORT_TX_DW3_LN0_C 0x6C90C |
|
- | 1394 | #define _PORT_TX_DW3_GRP_A 0x162D0C |
|
- | 1395 | #define _PORT_TX_DW3_GRP_B 0x6CD0C |
|
- | 1396 | #define _PORT_TX_DW3_GRP_C 0x6CF0C |
|
- | 1397 | #define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \ |
|
- | 1398 | _PORT_TX_DW3_GRP_B, \ |
|
- | 1399 | _PORT_TX_DW3_GRP_C) |
|
- | 1400 | #define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \ |
|
- | 1401 | _PORT_TX_DW3_LN0_B, \ |
|
- | 1402 | _PORT_TX_DW3_LN0_C) |
|
- | 1403 | #define SCALE_DCOMP_METHOD (1 << 26) |
|
- | 1404 | #define UNIQUE_TRANGE_EN_METHOD (1 << 27) |
|
- | 1405 | ||
- | 1406 | #define _PORT_TX_DW4_LN0_A 0x162510 |
|
- | 1407 | #define _PORT_TX_DW4_LN0_B 0x6C510 |
|
- | 1408 | #define _PORT_TX_DW4_LN0_C 0x6C910 |
|
- | 1409 | #define _PORT_TX_DW4_GRP_A 0x162D10 |
|
- | 1410 | #define _PORT_TX_DW4_GRP_B 0x6CD10 |
|
- | 1411 | #define _PORT_TX_DW4_GRP_C 0x6CF10 |
|
- | 1412 | #define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \ |
|
- | 1413 | _PORT_TX_DW4_LN0_B, \ |
|
- | 1414 | _PORT_TX_DW4_LN0_C) |
|
- | 1415 | #define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \ |
|
- | 1416 | _PORT_TX_DW4_GRP_B, \ |
|
- | 1417 | _PORT_TX_DW4_GRP_C) |
|
- | 1418 | #define DEEMPH_SHIFT 24 |
|
- | 1419 | #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) |
|
- | 1420 | ||
- | 1421 | #define _PORT_TX_DW14_LN0_A 0x162538 |
|
- | 1422 | #define _PORT_TX_DW14_LN0_B 0x6C538 |
|
- | 1423 | #define _PORT_TX_DW14_LN0_C 0x6C938 |
|
- | 1424 | #define LATENCY_OPTIM_SHIFT 30 |
|
- | 1425 | #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) |
|
- | 1426 | #define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \ |
|
- | 1427 | _PORT_TX_DW14_LN0_B, \ |
|
- | 1428 | _PORT_TX_DW14_LN0_C) + \ |
|
- | 1429 | _BXT_LANE_OFFSET(lane)) |
|
- | 1430 | ||
- | 1431 | /* UAIMI scratch pad register 1 */ |
|
- | 1432 | #define UAIMI_SPR1 0x4F074 |
|
- | 1433 | /* SKL VccIO mask */ |
|
- | 1434 | #define SKL_VCCIO_MASK 0x1 |
|
- | 1435 | /* SKL balance leg register */ |
|
- | 1436 | #define DISPIO_CR_TX_BMU_CR0 0x6C00C |
|
- | 1437 | /* I_boost values */ |
|
- | 1438 | #define BALANCE_LEG_SHIFT(port) (8+3*(port)) |
|
- | 1439 | #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) |
|
- | 1440 | /* Balance leg disable bits */ |
|
- | 1441 | #define BALANCE_LEG_DISABLE_SHIFT 23 |
|
- | 1442 | ||
1058 | /* |
1443 | /* |
1059 | * Fence registers |
1444 | * Fence registers |
- | 1445 | * [0-7] @ 0x2000 gen2,gen3 |
|
- | 1446 | * [8-15] @ 0x3000 945,g33,pnv |
|
- | 1447 | * |
|
- | 1448 | * [0-15] @ 0x3000 gen4,gen5 |
|
- | 1449 | * |
|
- | 1450 | * [0-15] @ 0x100000 gen6,vlv,chv |
|
- | 1451 | * [0-31] @ 0x100000 gen7+ |
|
1060 | */ |
1452 | */ |
1061 | #define FENCE_REG_830_0 0x2000 |
1453 | #define FENCE_REG(i) (0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) |
1062 | #define FENCE_REG_945_8 0x3000 |
- | |
1063 | #define I830_FENCE_START_MASK 0x07f80000 |
1454 | #define I830_FENCE_START_MASK 0x07f80000 |
1064 | #define I830_FENCE_TILING_Y_SHIFT 12 |
1455 | #define I830_FENCE_TILING_Y_SHIFT 12 |
1065 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
1456 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
1066 | #define I830_FENCE_PITCH_SHIFT 4 |
1457 | #define I830_FENCE_PITCH_SHIFT 4 |
1067 | #define I830_FENCE_REG_VALID (1<<0) |
1458 | #define I830_FENCE_REG_VALID (1<<0) |
Line 1070... | Line 1461... | ||
1070 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
1461 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
Line 1071... | Line 1462... | ||
1071 | 1462 | ||
1072 | #define I915_FENCE_START_MASK 0x0ff00000 |
1463 | #define I915_FENCE_START_MASK 0x0ff00000 |
Line 1073... | Line 1464... | ||
1073 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
1464 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
- | 1465 | ||
1074 | 1466 | #define FENCE_REG_965_LO(i) (0x03000 + (i) * 8) |
|
1075 | #define FENCE_REG_965_0 0x03000 |
1467 | #define FENCE_REG_965_HI(i) (0x03000 + (i) * 8 + 4) |
1076 | #define I965_FENCE_PITCH_SHIFT 2 |
1468 | #define I965_FENCE_PITCH_SHIFT 2 |
1077 | #define I965_FENCE_TILING_Y_SHIFT 1 |
1469 | #define I965_FENCE_TILING_Y_SHIFT 1 |
Line 1078... | Line 1470... | ||
1078 | #define I965_FENCE_REG_VALID (1<<0) |
1470 | #define I965_FENCE_REG_VALID (1<<0) |
- | 1471 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
|
1079 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
1472 | |
1080 | 1473 | #define FENCE_REG_GEN6_LO(i) (0x100000 + (i) * 8) |
|
Line 1081... | Line 1474... | ||
1081 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
1474 | #define FENCE_REG_GEN6_HI(i) (0x100000 + (i) * 8 + 4) |
1082 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
1475 | #define GEN6_FENCE_PITCH_SHIFT 32 |
1083 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
1476 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
- | 1477 | ||
1084 | 1478 | ||
1085 | 1479 | /* control register for cpu gtt access */ |
|
Line 1086... | Line 1480... | ||
1086 | /* control register for cpu gtt access */ |
1480 | #define TILECTL 0x101000 |
1087 | #define TILECTL 0x101000 |
1481 | #define TILECTL_SWZCTL (1 << 0) |
Line 1131... | Line 1525... | ||
1131 | #define GEN6_NOSYNC 0 |
1525 | #define GEN6_NOSYNC 0 |
1132 | #define RING_PSMI_CTL(base) ((base)+0x50) |
1526 | #define RING_PSMI_CTL(base) ((base)+0x50) |
1133 | #define RING_MAX_IDLE(base) ((base)+0x54) |
1527 | #define RING_MAX_IDLE(base) ((base)+0x54) |
1134 | #define RING_HWS_PGA(base) ((base)+0x80) |
1528 | #define RING_HWS_PGA(base) ((base)+0x80) |
1135 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
1529 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
- | 1530 | #define RING_RESET_CTL(base) ((base)+0xd0) |
|
- | 1531 | #define RESET_CTL_REQUEST_RESET (1 << 0) |
|
- | 1532 | #define RESET_CTL_READY_TO_RESET (1 << 1) |
|
Line -... | Line 1533... | ||
- | 1533 | ||
- | 1534 | #define HSW_GTT_CACHE_EN 0x4024 |
|
1136 | 1535 | #define GTT_CACHE_EN_ALL 0xF0007FFF |
|
1137 | #define GEN7_WR_WATERMARK 0x4028 |
1536 | #define GEN7_WR_WATERMARK 0x4028 |
1138 | #define GEN7_GFX_PRIO_CTRL 0x402C |
1537 | #define GEN7_GFX_PRIO_CTRL 0x402C |
1139 | #define ARB_MODE 0x4030 |
1538 | #define ARB_MODE 0x4030 |
1140 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
1539 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
1141 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
1540 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
1142 | #define GEN7_GFX_PEND_TLB0 0x4034 |
1541 | #define GEN7_GFX_PEND_TLB0 0x4034 |
1143 | #define GEN7_GFX_PEND_TLB1 0x4038 |
1542 | #define GEN7_GFX_PEND_TLB1 0x4038 |
1144 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
1543 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
1145 | #define GEN7_LRA_LIMITS_BASE 0x403C |
1544 | #define GEN7_LRA_LIMITS(i) (0x403C + (i) * 4) |
1146 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
1545 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
1147 | #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 |
1546 | #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 |
Line 1148... | Line 1547... | ||
1148 | #define GEN7_GFX_MAX_REQ_COUNT 0x4074 |
1547 | #define GEN7_GFX_MAX_REQ_COUNT 0x4074 |
1149 | 1548 | ||
1150 | #define GAMTARBMODE 0x04a08 |
1549 | #define GAMTARBMODE 0x04a08 |
1151 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
1550 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
1152 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
1551 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
1153 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
1552 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
1154 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
1553 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
1155 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
1554 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
1156 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) |
1555 | #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) |
1157 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) |
1556 | #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) |
1158 | #define RING_FAULT_VALID (1<<0) |
1557 | #define RING_FAULT_VALID (1<<0) |
- | 1558 | #define DONE_REG 0x40b0 |
|
1159 | #define DONE_REG 0x40b0 |
1559 | #define GEN8_PRIVATE_PAT_LO 0x40e0 |
1160 | #define GEN8_PRIVATE_PAT 0x40e0 |
1560 | #define GEN8_PRIVATE_PAT_HI (0x40e0 + 4) |
1161 | #define BSD_HWS_PGA_GEN7 (0x04180) |
1561 | #define BSD_HWS_PGA_GEN7 (0x04180) |
1162 | #define BLT_HWS_PGA_GEN7 (0x04280) |
1562 | #define BLT_HWS_PGA_GEN7 (0x04280) |
1163 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
1563 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
Line 1195... | Line 1595... | ||
1195 | #define PRB1_START 0x02048 /* 915+ only */ |
1595 | #define PRB1_START 0x02048 /* 915+ only */ |
1196 | #define PRB1_CTL 0x0204c /* 915+ only */ |
1596 | #define PRB1_CTL 0x0204c /* 915+ only */ |
1197 | #endif |
1597 | #endif |
1198 | #define IPEIR_I965 0x02064 |
1598 | #define IPEIR_I965 0x02064 |
1199 | #define IPEHR_I965 0x02068 |
1599 | #define IPEHR_I965 0x02068 |
1200 | #define INSTDONE_I965 0x0206c |
- | |
1201 | #define GEN7_INSTDONE_1 0x0206c |
- | |
1202 | #define GEN7_SC_INSTDONE 0x07100 |
1600 | #define GEN7_SC_INSTDONE 0x07100 |
1203 | #define GEN7_SAMPLER_INSTDONE 0x0e160 |
1601 | #define GEN7_SAMPLER_INSTDONE 0x0e160 |
1204 | #define GEN7_ROW_INSTDONE 0x0e164 |
1602 | #define GEN7_ROW_INSTDONE 0x0e164 |
1205 | #define I915_NUM_INSTDONE_REG 4 |
1603 | #define I915_NUM_INSTDONE_REG 4 |
1206 | #define RING_IPEIR(base) ((base)+0x64) |
1604 | #define RING_IPEIR(base) ((base)+0x64) |
1207 | #define RING_IPEHR(base) ((base)+0x68) |
1605 | #define RING_IPEHR(base) ((base)+0x68) |
- | 1606 | /* |
|
- | 1607 | * On GEN4, only the render ring INSTDONE exists and has a different |
|
- | 1608 | * layout than the GEN7+ version. |
|
- | 1609 | * The GEN2 counterpart of this register is GEN2_INSTDONE. |
|
- | 1610 | */ |
|
1208 | #define RING_INSTDONE(base) ((base)+0x6c) |
1611 | #define RING_INSTDONE(base) ((base)+0x6c) |
1209 | #define RING_INSTPS(base) ((base)+0x70) |
1612 | #define RING_INSTPS(base) ((base)+0x70) |
1210 | #define RING_DMA_FADD(base) ((base)+0x78) |
1613 | #define RING_DMA_FADD(base) ((base)+0x78) |
1211 | #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ |
1614 | #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ |
1212 | #define RING_INSTPM(base) ((base)+0xc0) |
1615 | #define RING_INSTPM(base) ((base)+0xc0) |
1213 | #define RING_MI_MODE(base) ((base)+0x9c) |
1616 | #define RING_MI_MODE(base) ((base)+0x9c) |
1214 | #define INSTPS 0x02070 /* 965+ only */ |
1617 | #define INSTPS 0x02070 /* 965+ only */ |
1215 | #define INSTDONE1 0x0207c /* 965+ only */ |
1618 | #define GEN4_INSTDONE1 0x0207c /* 965+ only, aka INSTDONE_2 on SNB */ |
1216 | #define ACTHD_I965 0x02074 |
1619 | #define ACTHD_I965 0x02074 |
1217 | #define HWS_PGA 0x02080 |
1620 | #define HWS_PGA 0x02080 |
1218 | #define HWS_ADDRESS_MASK 0xfffff000 |
1621 | #define HWS_ADDRESS_MASK 0xfffff000 |
1219 | #define HWS_START_ADDRESS_SHIFT 4 |
1622 | #define HWS_START_ADDRESS_SHIFT 4 |
1220 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
1623 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
1221 | #define PWRCTX_EN (1<<0) |
1624 | #define PWRCTX_EN (1<<0) |
1222 | #define IPEIR 0x02088 |
1625 | #define IPEIR 0x02088 |
1223 | #define IPEHR 0x0208c |
1626 | #define IPEHR 0x0208c |
1224 | #define INSTDONE 0x02090 |
1627 | #define GEN2_INSTDONE 0x02090 |
1225 | #define NOPID 0x02094 |
1628 | #define NOPID 0x02094 |
1226 | #define HWSTAM 0x02098 |
1629 | #define HWSTAM 0x02098 |
1227 | #define DMA_FADD_I8XX 0x020d0 |
1630 | #define DMA_FADD_I8XX 0x020d0 |
1228 | #define RING_BBSTATE(base) ((base)+0x110) |
1631 | #define RING_BBSTATE(base) ((base)+0x110) |
1229 | #define RING_BBADDR(base) ((base)+0x140) |
1632 | #define RING_BBADDR(base) ((base)+0x140) |
Line 1236... | Line 1639... | ||
1236 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
1639 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
1237 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
1640 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
1238 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
1641 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
1239 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
1642 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
1240 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
1643 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
1241 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) |
1644 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3)) |
1242 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
1645 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
1243 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
1646 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) |
- | 1647 | ||
- | 1648 | #define GEN8_FAULT_TLB_DATA0 0x04b10 |
|
- | 1649 | #define GEN8_FAULT_TLB_DATA1 0x04b14 |
|
Line 1244... | Line 1650... | ||
1244 | 1650 | ||
1245 | #define FPGA_DBG 0x42300 |
1651 | #define FPGA_DBG 0x42300 |
Line 1246... | Line 1652... | ||
1246 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
1652 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
Line 1296... | Line 1702... | ||
1296 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) |
1702 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) |
1297 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) |
1703 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) |
1298 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) |
1704 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) |
1299 | #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) |
1705 | #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) |
1300 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
1706 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
- | 1707 | #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) |
|
- | 1708 | #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) |
|
Line 1301... | Line 1709... | ||
1301 | 1709 | ||
1302 | #define GFX_MODE 0x02520 |
1710 | #define GFX_MODE 0x02520 |
1303 | #define GFX_MODE_GEN7 0x0229c |
1711 | #define GFX_MODE_GEN7 0x0229c |
1304 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
1712 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
- | 1713 | #define GFX_RUN_LIST_ENABLE (1<<15) |
|
1305 | #define GFX_RUN_LIST_ENABLE (1<<15) |
1714 | #define GFX_INTERRUPT_STEERING (1<<14) |
1306 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
1715 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
1307 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
1716 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
1308 | #define GFX_REPLAY_MODE (1<<11) |
1717 | #define GFX_REPLAY_MODE (1<<11) |
1309 | #define GFX_PSMI_GRANULARITY (1<<10) |
1718 | #define GFX_PSMI_GRANULARITY (1<<10) |
- | 1719 | #define GFX_PPGTT_ENABLE (1<<9) |
|
- | 1720 | #define GEN8_GFX_PPGTT_48B (1<<7) |
|
- | 1721 | ||
- | 1722 | #define GFX_FORWARD_VBLANK_MASK (3<<5) |
|
- | 1723 | #define GFX_FORWARD_VBLANK_NEVER (0<<5) |
|
- | 1724 | #define GFX_FORWARD_VBLANK_ALWAYS (1<<5) |
|
Line 1310... | Line 1725... | ||
1310 | #define GFX_PPGTT_ENABLE (1<<9) |
1725 | #define GFX_FORWARD_VBLANK_COND (2<<5) |
1311 | 1726 | ||
Line 1312... | Line 1727... | ||
1312 | #define VLV_DISPLAY_BASE 0x180000 |
1727 | #define VLV_DISPLAY_BASE 0x180000 |
Line 1452... | Line 1867... | ||
1452 | #define RC_OP_FLUSH_ENABLE (1<<0) |
1867 | #define RC_OP_FLUSH_ENABLE (1<<0) |
1453 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
1868 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
1454 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
1869 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
1455 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
1870 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
1456 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) |
1871 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) |
- | 1872 | #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) |
|
Line 1457... | Line 1873... | ||
1457 | 1873 | ||
1458 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
1874 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
1459 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
1875 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
Line 1460... | Line 1876... | ||
1460 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
1876 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
1461 | 1877 | ||
1462 | #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
1878 | #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
1463 | #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) |
1879 | #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) |
Line -... | Line 1880... | ||
- | 1880 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
|
- | 1881 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
|
- | 1882 | ||
- | 1883 | /* Fuse readout registers for GT */ |
|
- | 1884 | #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) |
|
- | 1885 | #define CHV_FGT_DISABLE_SS0 (1 << 10) |
|
- | 1886 | #define CHV_FGT_DISABLE_SS1 (1 << 11) |
|
- | 1887 | #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 |
|
- | 1888 | #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
|
- | 1889 | #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 |
|
- | 1890 | #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) |
|
- | 1891 | #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 |
|
- | 1892 | #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
|
- | 1893 | #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 |
|
- | 1894 | #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) |
|
- | 1895 | ||
- | 1896 | #define GEN8_FUSE2 0x9120 |
|
- | 1897 | #define GEN8_F2_SS_DIS_SHIFT 21 |
|
- | 1898 | #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) |
|
- | 1899 | #define GEN8_F2_S_ENA_SHIFT 25 |
|
- | 1900 | #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) |
|
- | 1901 | ||
- | 1902 | #define GEN9_F2_SS_DIS_SHIFT 20 |
|
- | 1903 | #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) |
|
- | 1904 | ||
- | 1905 | #define GEN8_EU_DISABLE0 0x9134 |
|
- | 1906 | #define GEN8_EU_DIS0_S0_MASK 0xffffff |
|
- | 1907 | #define GEN8_EU_DIS0_S1_SHIFT 24 |
|
- | 1908 | #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) |
|
- | 1909 | ||
- | 1910 | #define GEN8_EU_DISABLE1 0x9138 |
|
- | 1911 | #define GEN8_EU_DIS1_S1_MASK 0xffff |
|
- | 1912 | #define GEN8_EU_DIS1_S2_SHIFT 16 |
|
- | 1913 | #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) |
|
- | 1914 | ||
- | 1915 | #define GEN8_EU_DISABLE2 0x913c |
|
- | 1916 | #define GEN8_EU_DIS2_S2_MASK 0xff |
|
1464 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
1917 | |
1465 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
1918 | #define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4) |
1466 | 1919 | ||
1467 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
1920 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
1468 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
1921 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
Line 1507... | Line 1960... | ||
1507 | 1960 | ||
1508 | #define I915_PM_INTERRUPT (1<<31) |
1961 | #define I915_PM_INTERRUPT (1<<31) |
1509 | #define I915_ISP_INTERRUPT (1<<22) |
1962 | #define I915_ISP_INTERRUPT (1<<22) |
1510 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) |
1963 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) |
1511 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) |
1964 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) |
1512 | #define I915_MIPIB_INTERRUPT (1<<19) |
1965 | #define I915_MIPIC_INTERRUPT (1<<19) |
1513 | #define I915_MIPIA_INTERRUPT (1<<18) |
1966 | #define I915_MIPIA_INTERRUPT (1<<18) |
1514 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
1967 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
1515 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
1968 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
1516 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
1969 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
Line 1589... | Line 2042... | ||
1589 | #define FBC_CTL_IDLE_LINE (2<<2) |
2042 | #define FBC_CTL_IDLE_LINE (2<<2) |
1590 | #define FBC_CTL_IDLE_DEBUG (3<<2) |
2043 | #define FBC_CTL_IDLE_DEBUG (3<<2) |
1591 | #define FBC_CTL_CPU_FENCE (1<<1) |
2044 | #define FBC_CTL_CPU_FENCE (1<<1) |
1592 | #define FBC_CTL_PLANE(plane) ((plane)<<0) |
2045 | #define FBC_CTL_PLANE(plane) ((plane)<<0) |
1593 | #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ |
2046 | #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ |
- | 2047 | #define FBC_TAG(i) (0x03300 + (i) * 4) |
|
- | 2048 | ||
1594 | #define FBC_TAG 0x03300 |
2049 | #define FBC_STATUS2 0x43214 |
- | 2050 | #define FBC_COMPRESSION_MASK 0x7ff |
|
Line 1595... | Line 2051... | ||
1595 | 2051 | ||
Line 1596... | Line 2052... | ||
1596 | #define FBC_LL_SIZE (1536) |
2052 | #define FBC_LL_SIZE (1536) |
1597 | 2053 | ||
Line 1686... | Line 2142... | ||
1686 | # define GPIO_DATA_VAL_MASK (1 << 10) |
2142 | # define GPIO_DATA_VAL_MASK (1 << 10) |
1687 | # define GPIO_DATA_VAL_OUT (1 << 11) |
2143 | # define GPIO_DATA_VAL_OUT (1 << 11) |
1688 | # define GPIO_DATA_VAL_IN (1 << 12) |
2144 | # define GPIO_DATA_VAL_IN (1 << 12) |
1689 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
2145 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
Line 1690... | Line 2146... | ||
1690 | 2146 | ||
1691 | #define GMBUS0 0x5100 /* clock/port select */ |
2147 | #define GMBUS0 (dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ |
1692 | #define GMBUS_RATE_100KHZ (0<<8) |
2148 | #define GMBUS_RATE_100KHZ (0<<8) |
1693 | #define GMBUS_RATE_50KHZ (1<<8) |
2149 | #define GMBUS_RATE_50KHZ (1<<8) |
1694 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |
2150 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |
1695 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ |
2151 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ |
1696 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ |
2152 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ |
1697 | #define GMBUS_PORT_DISABLED 0 |
2153 | #define GMBUS_PIN_DISABLED 0 |
1698 | #define GMBUS_PORT_SSC 1 |
2154 | #define GMBUS_PIN_SSC 1 |
1699 | #define GMBUS_PORT_VGADDC 2 |
2155 | #define GMBUS_PIN_VGADDC 2 |
1700 | #define GMBUS_PORT_PANEL 3 |
2156 | #define GMBUS_PIN_PANEL 3 |
1701 | #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ |
2157 | #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ |
1702 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
2158 | #define GMBUS_PIN_DPC 4 /* HDMIC */ |
1703 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
2159 | #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ |
1704 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
2160 | #define GMBUS_PIN_DPD 6 /* HDMID */ |
- | 2161 | #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ |
|
- | 2162 | #define GMBUS_PIN_1_BXT 1 |
|
- | 2163 | #define GMBUS_PIN_2_BXT 2 |
|
1705 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
2164 | #define GMBUS_PIN_3_BXT 3 |
1706 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
2165 | #define GMBUS_NUM_PINS 7 /* including 0 */ |
1707 | #define GMBUS1 0x5104 /* command/status */ |
2166 | #define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* command/status */ |
1708 | #define GMBUS_SW_CLR_INT (1<<31) |
2167 | #define GMBUS_SW_CLR_INT (1<<31) |
1709 | #define GMBUS_SW_RDY (1<<30) |
2168 | #define GMBUS_SW_RDY (1<<30) |
1710 | #define GMBUS_ENT (1<<29) /* enable timeout */ |
2169 | #define GMBUS_ENT (1<<29) /* enable timeout */ |
1711 | #define GMBUS_CYCLE_NONE (0<<25) |
2170 | #define GMBUS_CYCLE_NONE (0<<25) |
1712 | #define GMBUS_CYCLE_WAIT (1<<25) |
2171 | #define GMBUS_CYCLE_WAIT (1<<25) |
1713 | #define GMBUS_CYCLE_INDEX (2<<25) |
2172 | #define GMBUS_CYCLE_INDEX (2<<25) |
1714 | #define GMBUS_CYCLE_STOP (4<<25) |
2173 | #define GMBUS_CYCLE_STOP (4<<25) |
- | 2174 | #define GMBUS_BYTE_COUNT_SHIFT 16 |
|
1715 | #define GMBUS_BYTE_COUNT_SHIFT 16 |
2175 | #define GMBUS_BYTE_COUNT_MAX 256U |
1716 | #define GMBUS_SLAVE_INDEX_SHIFT 8 |
2176 | #define GMBUS_SLAVE_INDEX_SHIFT 8 |
1717 | #define GMBUS_SLAVE_ADDR_SHIFT 1 |
2177 | #define GMBUS_SLAVE_ADDR_SHIFT 1 |
1718 | #define GMBUS_SLAVE_READ (1<<0) |
2178 | #define GMBUS_SLAVE_READ (1<<0) |
1719 | #define GMBUS_SLAVE_WRITE (0<<0) |
2179 | #define GMBUS_SLAVE_WRITE (0<<0) |
1720 | #define GMBUS2 0x5108 /* status */ |
2180 | #define GMBUS2 (dev_priv->gpio_mmio_base + 0x5108) /* status */ |
1721 | #define GMBUS_INUSE (1<<15) |
2181 | #define GMBUS_INUSE (1<<15) |
1722 | #define GMBUS_HW_WAIT_PHASE (1<<14) |
2182 | #define GMBUS_HW_WAIT_PHASE (1<<14) |
1723 | #define GMBUS_STALL_TIMEOUT (1<<13) |
2183 | #define GMBUS_STALL_TIMEOUT (1<<13) |
1724 | #define GMBUS_INT (1<<12) |
2184 | #define GMBUS_INT (1<<12) |
1725 | #define GMBUS_HW_RDY (1<<11) |
2185 | #define GMBUS_HW_RDY (1<<11) |
1726 | #define GMBUS_SATOER (1<<10) |
2186 | #define GMBUS_SATOER (1<<10) |
1727 | #define GMBUS_ACTIVE (1<<9) |
2187 | #define GMBUS_ACTIVE (1<<9) |
1728 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ |
2188 | #define GMBUS3 (dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ |
1729 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ |
2189 | #define GMBUS4 (dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ |
1730 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
2190 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
1731 | #define GMBUS_NAK_EN (1<<3) |
2191 | #define GMBUS_NAK_EN (1<<3) |
1732 | #define GMBUS_IDLE_EN (1<<2) |
2192 | #define GMBUS_IDLE_EN (1<<2) |
1733 | #define GMBUS_HW_WAIT_EN (1<<1) |
2193 | #define GMBUS_HW_WAIT_EN (1<<1) |
1734 | #define GMBUS_HW_RDY_EN (1<<0) |
2194 | #define GMBUS_HW_RDY_EN (1<<0) |
1735 | #define GMBUS5 0x5120 /* byte index */ |
2195 | #define GMBUS5 (dev_priv->gpio_mmio_base + 0x5120) /* byte index */ |
Line 1736... | Line 2196... | ||
1736 | #define GMBUS_2BYTE_INDEX_EN (1<<31) |
2196 | #define GMBUS_2BYTE_INDEX_EN (1<<31) |
1737 | 2197 | ||
1738 | /* |
2198 | /* |
Line 1757... | Line 2217... | ||
1757 | #define DPLL_VCO_ENABLE (1 << 31) |
2217 | #define DPLL_VCO_ENABLE (1 << 31) |
1758 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
2218 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
1759 | #define DPLL_DVO_2X_MODE (1 << 30) |
2219 | #define DPLL_DVO_2X_MODE (1 << 30) |
1760 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
2220 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
1761 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
2221 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
1762 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
2222 | #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) |
1763 | #define DPLL_VGA_MODE_DIS (1 << 28) |
2223 | #define DPLL_VGA_MODE_DIS (1 << 28) |
1764 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
2224 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
1765 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
2225 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
1766 | #define DPLL_MODE_MASK (3 << 26) |
2226 | #define DPLL_MODE_MASK (3 << 26) |
1767 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
2227 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
Line 1771... | Line 2231... | ||
1771 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
2231 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
1772 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
2232 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
1773 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
2233 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
1774 | #define DPLL_LOCK_VLV (1<<15) |
2234 | #define DPLL_LOCK_VLV (1<<15) |
1775 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
2235 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
1776 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
2236 | #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) |
1777 | #define DPLL_SSC_REF_CLOCK_CHV (1<<13) |
2237 | #define DPLL_SSC_REF_CLK_CHV (1<<13) |
1778 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
2238 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
1779 | #define DPLL_PORTB_READY_MASK (0xf) |
2239 | #define DPLL_PORTB_READY_MASK (0xf) |
Line 1780... | Line 2240... | ||
1780 | 2240 | ||
Line 1781... | Line 2241... | ||
1781 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
2241 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
1782 | 2242 | ||
1783 | /* Additional CHV pll/phy registers */ |
2243 | /* Additional CHV pll/phy registers */ |
1784 | #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) |
2244 | #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) |
- | 2245 | #define DPLL_PORTD_READY_MASK (0xf) |
|
- | 2246 | #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
|
- | 2247 | #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27)) |
|
- | 2248 | #define PHY_LDO_DELAY_0NS 0x0 |
|
- | 2249 | #define PHY_LDO_DELAY_200NS 0x1 |
|
- | 2250 | #define PHY_LDO_DELAY_600NS 0x2 |
|
- | 2251 | #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) |
|
- | 2252 | #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11)) |
|
- | 2253 | #define PHY_CH_SU_PSR 0x1 |
|
1785 | #define DPLL_PORTD_READY_MASK (0xf) |
2254 | #define PHY_CH_DEEP_PSR 0x7 |
1786 | #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
2255 | #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) |
1787 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
2256 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
- | 2257 | #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
|
- | 2258 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) |
|
Line 1788... | Line 2259... | ||
1788 | #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
2259 | #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch)))) |
1789 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) |
2260 | #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline)))) |
1790 | 2261 | ||
1791 | /* |
2262 | /* |
Line 2019... | Line 2490... | ||
2019 | 2490 | ||
2020 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) |
2491 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) |
2021 | #define CDCLK_FREQ_SHIFT 4 |
2492 | #define CDCLK_FREQ_SHIFT 4 |
2022 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
2493 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
- | 2494 | #define CZCLK_FREQ_MASK 0xf |
|
- | 2495 | ||
- | 2496 | #define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C) |
|
- | 2497 | #define PFI_CREDIT_63 (9 << 28) /* chv only */ |
|
- | 2498 | #define PFI_CREDIT_31 (8 << 28) /* chv only */ |
|
- | 2499 | #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ |
|
- | 2500 | #define PFI_CREDIT_RESEND (1 << 27) |
|
- | 2501 | #define VGA_FAST_MODE_DISABLE (1 << 14) |
|
2023 | #define CZCLK_FREQ_MASK 0xf |
2502 | |
Line 2024... | Line 2503... | ||
2024 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) |
2503 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) |
2025 | 2504 | ||
2026 | /* |
2505 | /* |
2027 | * Palette regs |
2506 | * Palette regs |
2028 | */ |
2507 | */ |
2029 | #define PALETTE_A_OFFSET 0xa000 |
2508 | #define PALETTE_A_OFFSET 0xa000 |
2030 | #define PALETTE_B_OFFSET 0xa800 |
2509 | #define PALETTE_B_OFFSET 0xa800 |
2031 | #define CHV_PALETTE_C_OFFSET 0xc000 |
2510 | #define CHV_PALETTE_C_OFFSET 0xc000 |
Line 2032... | Line 2511... | ||
2032 | #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ |
2511 | #define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \ |
Line 2033... | Line 2512... | ||
2033 | dev_priv->info.display_mmio_offset) |
2512 | dev_priv->info.display_mmio_offset + (i) * 4) |
2034 | 2513 | ||
Line 2046... | Line 2525... | ||
2046 | */ |
2525 | */ |
2047 | #define MCHBAR_MIRROR_BASE 0x10000 |
2526 | #define MCHBAR_MIRROR_BASE 0x10000 |
Line 2048... | Line 2527... | ||
2048 | 2527 | ||
Line -... | Line 2528... | ||
- | 2528 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
|
- | 2529 | ||
- | 2530 | #define CTG_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x34) |
|
- | 2531 | #define ELK_STOLEN_RESERVED (MCHBAR_MIRROR_BASE + 0x48) |
|
- | 2532 | #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) |
|
2049 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
2533 | #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) |
2050 | 2534 | ||
Line 2051... | Line 2535... | ||
2051 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
2535 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
2052 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
2536 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
Line 2114... | Line 2598... | ||
2114 | #define CLKCFG_MEM_533 (1 << 4) |
2598 | #define CLKCFG_MEM_533 (1 << 4) |
2115 | #define CLKCFG_MEM_667 (2 << 4) |
2599 | #define CLKCFG_MEM_667 (2 << 4) |
2116 | #define CLKCFG_MEM_800 (3 << 4) |
2600 | #define CLKCFG_MEM_800 (3 << 4) |
2117 | #define CLKCFG_MEM_MASK (7 << 4) |
2601 | #define CLKCFG_MEM_MASK (7 << 4) |
Line -... | Line 2602... | ||
- | 2602 | ||
- | 2603 | #define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38) |
|
- | 2604 | #define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f) |
|
2118 | 2605 | ||
2119 | #define TSC1 0x11001 |
2606 | #define TSC1 0x11001 |
2120 | #define TSE (1<<0) |
2607 | #define TSE (1<<0) |
2121 | #define TR1 0x11006 |
2608 | #define TR1 0x11006 |
2122 | #define TSFS 0x11020 |
2609 | #define TSFS 0x11020 |
2123 | #define TSFS_SLOPE_MASK 0x0000ff00 |
2610 | #define TSFS_SLOPE_MASK 0x0000ff00 |
2124 | #define TSFS_SLOPE_SHIFT 8 |
2611 | #define TSFS_SLOPE_SHIFT 8 |
Line 2125... | Line 2612... | ||
2125 | #define TSFS_INTR_MASK 0x000000ff |
2612 | #define TSFS_INTR_MASK 0x000000ff |
2126 | 2613 | ||
2127 | #define CRSTANDVID 0x11100 |
2614 | #define CRSTANDVID 0x11100 |
2128 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
2615 | #define PXVFREQ(i) (0x11110 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
2129 | #define PXVFREQ_PX_MASK 0x7f000000 |
2616 | #define PXVFREQ_PX_MASK 0x7f000000 |
2130 | #define PXVFREQ_PX_SHIFT 24 |
2617 | #define PXVFREQ_PX_SHIFT 24 |
2131 | #define VIDFREQ_BASE 0x11110 |
2618 | #define VIDFREQ_BASE 0x11110 |
Line 2307... | Line 2794... | ||
2307 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ |
2794 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ |
2308 | #define SDEW 0x1124c |
2795 | #define SDEW 0x1124c |
2309 | #define CSIEW0 0x11250 |
2796 | #define CSIEW0 0x11250 |
2310 | #define CSIEW1 0x11254 |
2797 | #define CSIEW1 0x11254 |
2311 | #define CSIEW2 0x11258 |
2798 | #define CSIEW2 0x11258 |
2312 | #define PEW 0x1125c |
2799 | #define PEW(i) (0x1125c + (i) * 4) /* 5 registers */ |
2313 | #define DEW 0x11270 |
2800 | #define DEW(i) (0x11270 + (i) * 4) /* 3 registers */ |
2314 | #define MCHAFE 0x112c0 |
2801 | #define MCHAFE 0x112c0 |
2315 | #define CSIEC 0x112e0 |
2802 | #define CSIEC 0x112e0 |
2316 | #define DMIEC 0x112e4 |
2803 | #define DMIEC 0x112e4 |
2317 | #define DDREC 0x112e8 |
2804 | #define DDREC 0x112e8 |
2318 | #define PEG0EC 0x112ec |
2805 | #define PEG0EC 0x112ec |
Line 2332... | Line 2819... | ||
2332 | #define EG3 0x1161c |
2819 | #define EG3 0x1161c |
2333 | #define EG4 0x11620 |
2820 | #define EG4 0x11620 |
2334 | #define EG5 0x11624 |
2821 | #define EG5 0x11624 |
2335 | #define EG6 0x11628 |
2822 | #define EG6 0x11628 |
2336 | #define EG7 0x1162c |
2823 | #define EG7 0x1162c |
2337 | #define PXW 0x11664 |
2824 | #define PXW(i) (0x11664 + (i) * 4) /* 4 registers */ |
2338 | #define PXWL 0x11680 |
2825 | #define PXWL(i) (0x11680 + (i) * 4) /* 8 registers */ |
2339 | #define LCFUSE02 0x116c0 |
2826 | #define LCFUSE02 0x116c0 |
2340 | #define LCFUSE_HIV_MASK 0x000000ff |
2827 | #define LCFUSE_HIV_MASK 0x000000ff |
2341 | #define CSIPLL0 0x12c10 |
2828 | #define CSIPLL0 0x12c10 |
2342 | #define DDRMPLL1 0X12c20 |
2829 | #define DDRMPLL1 0X12c20 |
2343 | #define PEG_BAND_GAP_DATA 0x14d68 |
2830 | #define PEG_BAND_GAP_DATA 0x14d68 |
Line 2344... | Line 2831... | ||
2344 | 2831 | ||
2345 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
2832 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
Line 2346... | Line 2833... | ||
2346 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
2833 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
- | 2834 | ||
2347 | 2835 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
|
2348 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
2836 | #define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070) |
- | 2837 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
|
- | 2838 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
|
- | 2839 | #define BXT_RP_STATE_CAP 0x138170 |
|
- | 2840 | ||
- | 2841 | #define INTERVAL_1_28_US(us) (((us) * 100) >> 7) |
|
- | 2842 | #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) |
|
- | 2843 | #define INTERVAL_0_833_US(us) (((us) * 6) / 5) |
|
- | 2844 | #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ |
|
- | 2845 | (IS_BROXTON(dev_priv) ? \ |
|
- | 2846 | INTERVAL_0_833_US(us) : \ |
|
Line 2349... | Line 2847... | ||
2349 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
2847 | INTERVAL_1_33_US(us)) : \ |
2350 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
2848 | INTERVAL_1_28_US(us)) |
2351 | 2849 | ||
2352 | /* |
2850 | /* |
Line 2366... | Line 2864... | ||
2366 | * - Pipelined/VF state is saved on SNB/IVB respectively |
2864 | * - Pipelined/VF state is saved on SNB/IVB respectively |
2367 | * - GT1 size just indicates how much of render context |
2865 | * - GT1 size just indicates how much of render context |
2368 | * doesn't need saving on GT1 |
2866 | * doesn't need saving on GT1 |
2369 | */ |
2867 | */ |
2370 | #define CXT_SIZE 0x21a0 |
2868 | #define CXT_SIZE 0x21a0 |
2371 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) |
2869 | #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) |
2372 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) |
2870 | #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) |
2373 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) |
2871 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) |
2374 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) |
2872 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) |
2375 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) |
2873 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) |
2376 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
2874 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
2377 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
2875 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
2378 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) |
2876 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) |
2379 | #define GEN7_CXT_SIZE 0x21a8 |
2877 | #define GEN7_CXT_SIZE 0x21a8 |
2380 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
2878 | #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) |
2381 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) |
2879 | #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) |
2382 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
2880 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) |
2383 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) |
2881 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) |
2384 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) |
2882 | #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) |
2385 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) |
2883 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) |
2386 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
2884 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
2387 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
2885 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
2388 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
2886 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
2389 | * valid. Now, docs explain in dwords what is in the context object. The full |
2887 | * valid. Now, docs explain in dwords what is in the context object. The full |
2390 | * size is 70720 bytes, however, the power context and execlist context will |
2888 | * size is 70720 bytes, however, the power context and execlist context will |
2391 | * never be saved (power context is stored elsewhere, and execlists don't work |
2889 | * never be saved (power context is stored elsewhere, and execlists don't work |
- | 2890 | * on HSW) - so the final size, including the extra state required for the |
|
2392 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. |
2891 | * Resource Streamer, is 66944 bytes, which rounds to 17 pages. |
2393 | */ |
2892 | */ |
2394 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) |
2893 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) |
2395 | /* Same as Haswell, but 72064 bytes now. */ |
2894 | /* Same as Haswell, but 72064 bytes now. */ |
2396 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) |
2895 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) |
Line 2537... | Line 3036... | ||
2537 | #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) |
3036 | #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) |
2538 | #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) |
3037 | #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) |
2539 | #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) |
3038 | #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) |
2540 | #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) |
3039 | #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) |
Line -... | Line 3040... | ||
- | 3040 | ||
- | 3041 | /* VLV eDP PSR registers */ |
|
- | 3042 | #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) |
|
- | 3043 | #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) |
|
- | 3044 | #define VLV_EDP_PSR_ENABLE (1<<0) |
|
- | 3045 | #define VLV_EDP_PSR_RESET (1<<1) |
|
- | 3046 | #define VLV_EDP_PSR_MODE_MASK (7<<2) |
|
- | 3047 | #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) |
|
- | 3048 | #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) |
|
- | 3049 | #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) |
|
- | 3050 | #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) |
|
- | 3051 | #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) |
|
- | 3052 | #define VLV_EDP_PSR_DBL_FRAME (1<<10) |
|
- | 3053 | #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) |
|
- | 3054 | #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 |
|
- | 3055 | #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB) |
|
- | 3056 | ||
- | 3057 | #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) |
|
- | 3058 | #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) |
|
- | 3059 | #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) |
|
- | 3060 | #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) |
|
- | 3061 | #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) |
|
- | 3062 | #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB) |
|
- | 3063 | ||
- | 3064 | #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) |
|
- | 3065 | #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) |
|
- | 3066 | #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) |
|
- | 3067 | #define VLV_EDP_PSR_CURR_STATE_MASK 7 |
|
- | 3068 | #define VLV_EDP_PSR_DISABLED (0<<0) |
|
- | 3069 | #define VLV_EDP_PSR_INACTIVE (1<<0) |
|
- | 3070 | #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) |
|
- | 3071 | #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) |
|
- | 3072 | #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) |
|
- | 3073 | #define VLV_EDP_PSR_EXIT (5<<0) |
|
- | 3074 | #define VLV_EDP_PSR_IN_TRANS (1<<7) |
|
- | 3075 | #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB) |
|
2541 | 3076 | ||
2542 | /* HSW+ eDP PSR registers */ |
3077 | /* HSW+ eDP PSR registers */ |
2543 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
3078 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
2544 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
3079 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
2545 | #define EDP_PSR_ENABLE (1<<31) |
3080 | #define EDP_PSR_ENABLE (1<<31) |
2546 | #define BDW_PSR_SINGLE_FRAME (1<<30) |
- | |
2547 | #define EDP_PSR_LINK_DISABLE (0<<27) |
3081 | #define BDW_PSR_SINGLE_FRAME (1<<30) |
2548 | #define EDP_PSR_LINK_STANDBY (1<<27) |
3082 | #define EDP_PSR_LINK_STANDBY (1<<27) |
2549 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) |
3083 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) |
2550 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) |
3084 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) |
2551 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) |
3085 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) |
Line 2602... | Line 3136... | ||
2602 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) |
3136 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) |
2603 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
3137 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
2604 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) |
3138 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) |
2605 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) |
3139 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) |
Line -... | Line 3140... | ||
- | 3140 | ||
- | 3141 | #define EDP_PSR2_CTL 0x6f900 |
|
- | 3142 | #define EDP_PSR2_ENABLE (1<<31) |
|
- | 3143 | #define EDP_SU_TRACK_ENABLE (1<<30) |
|
- | 3144 | #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) |
|
- | 3145 | #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) |
|
- | 3146 | #define EDP_PSR2_TP2_TIME_500 (0<<8) |
|
- | 3147 | #define EDP_PSR2_TP2_TIME_100 (1<<8) |
|
- | 3148 | #define EDP_PSR2_TP2_TIME_2500 (2<<8) |
|
- | 3149 | #define EDP_PSR2_TP2_TIME_50 (3<<8) |
|
- | 3150 | #define EDP_PSR2_TP2_TIME_MASK (3<<8) |
|
- | 3151 | #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 |
|
- | 3152 | #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) |
|
- | 3153 | #define EDP_PSR2_IDLE_MASK 0xf |
|
2606 | 3154 | ||
2607 | /* VGA port control */ |
3155 | /* VGA port control */ |
2608 | #define ADPA 0x61100 |
3156 | #define ADPA 0x61100 |
2609 | #define PCH_ADPA 0xe1100 |
3157 | #define PCH_ADPA 0xe1100 |
Line 2750... | Line 3298... | ||
2750 | * The same register may be used for SDVO or HDMI */ |
3298 | * The same register may be used for SDVO or HDMI */ |
2751 | #define GEN3_SDVOB 0x61140 |
3299 | #define GEN3_SDVOB 0x61140 |
2752 | #define GEN3_SDVOC 0x61160 |
3300 | #define GEN3_SDVOC 0x61160 |
2753 | #define GEN4_HDMIB GEN3_SDVOB |
3301 | #define GEN4_HDMIB GEN3_SDVOB |
2754 | #define GEN4_HDMIC GEN3_SDVOC |
3302 | #define GEN4_HDMIC GEN3_SDVOC |
- | 3303 | #define VLV_HDMIB (VLV_DISPLAY_BASE + GEN4_HDMIB) |
|
- | 3304 | #define VLV_HDMIC (VLV_DISPLAY_BASE + GEN4_HDMIC) |
|
2755 | #define CHV_HDMID 0x6116C |
3305 | #define CHV_HDMID (VLV_DISPLAY_BASE + 0x6116C) |
2756 | #define PCH_SDVOB 0xe1140 |
3306 | #define PCH_SDVOB 0xe1140 |
2757 | #define PCH_HDMIB PCH_SDVOB |
3307 | #define PCH_HDMIB PCH_SDVOB |
2758 | #define PCH_HDMIC 0xe1150 |
3308 | #define PCH_HDMIC 0xe1150 |
2759 | #define PCH_HDMID 0xe1160 |
3309 | #define PCH_HDMID 0xe1160 |
Line 2760... | Line 3310... | ||
2760 | 3310 | ||
2761 | #define PORT_DFT_I9XX 0x61150 |
3311 | #define PORT_DFT_I9XX 0x61150 |
2762 | #define DC_BALANCE_RESET (1 << 25) |
3312 | #define DC_BALANCE_RESET (1 << 25) |
2763 | #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) |
3313 | #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) |
2764 | #define DC_BALANCE_RESET_VLV (1 << 31) |
3314 | #define DC_BALANCE_RESET_VLV (1 << 31) |
- | 3315 | #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) |
|
2765 | #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) |
3316 | #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ |
2766 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
3317 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
Line 2767... | Line 3318... | ||
2767 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) |
3318 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) |
2768 | 3319 | ||
Line 2902... | Line 3453... | ||
2902 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
3453 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
2903 | #define LVDS_B0B3_POWER_UP (3 << 2) |
3454 | #define LVDS_B0B3_POWER_UP (3 << 2) |
Line 2904... | Line 3455... | ||
2904 | 3455 | ||
2905 | /* Video Data Island Packet control */ |
3456 | /* Video Data Island Packet control */ |
2906 | #define VIDEO_DIP_DATA 0x61178 |
3457 | #define VIDEO_DIP_DATA 0x61178 |
2907 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC |
3458 | /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC |
2908 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
3459 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
2909 | * of the infoframe structure specified by CEA-861. */ |
3460 | * of the infoframe structure specified by CEA-861. */ |
2910 | #define VIDEO_DIP_DATA_SIZE 32 |
3461 | #define VIDEO_DIP_DATA_SIZE 32 |
2911 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
3462 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
Line 3061... | Line 3612... | ||
3061 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
3612 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
3062 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
3613 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
3063 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
3614 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
Line 3064... | Line 3615... | ||
3064 | 3615 | ||
- | 3616 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
|
Line 3065... | Line 3617... | ||
3065 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
3617 | #define BLM_HISTOGRAM_ENABLE (1 << 31) |
3066 | 3618 | ||
3067 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
3619 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
3068 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
3620 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
Line 3080... | Line 3632... | ||
3080 | #define BLC_PWM_PCH_CTL2 0xc8254 |
3632 | #define BLC_PWM_PCH_CTL2 0xc8254 |
Line 3081... | Line 3633... | ||
3081 | 3633 | ||
3082 | #define UTIL_PIN_CTL 0x48400 |
3634 | #define UTIL_PIN_CTL 0x48400 |
Line -... | Line 3635... | ||
- | 3635 | #define UTIL_PIN_ENABLE (1 << 31) |
|
- | 3636 | ||
- | 3637 | #define UTIL_PIN_PIPE(x) ((x) << 29) |
|
- | 3638 | #define UTIL_PIN_PIPE_MASK (3 << 29) |
|
- | 3639 | #define UTIL_PIN_MODE_PWM (1 << 24) |
|
- | 3640 | #define UTIL_PIN_MODE_MASK (0xf << 24) |
|
- | 3641 | #define UTIL_PIN_POLARITY (1 << 22) |
|
- | 3642 | ||
- | 3643 | /* BXT backlight register definition. */ |
|
- | 3644 | #define _BXT_BLC_PWM_CTL1 0xC8250 |
|
- | 3645 | #define BXT_BLC_PWM_ENABLE (1 << 31) |
|
- | 3646 | #define BXT_BLC_PWM_POLARITY (1 << 29) |
|
- | 3647 | #define _BXT_BLC_PWM_FREQ1 0xC8254 |
|
- | 3648 | #define _BXT_BLC_PWM_DUTY1 0xC8258 |
|
- | 3649 | ||
- | 3650 | #define _BXT_BLC_PWM_CTL2 0xC8350 |
|
- | 3651 | #define _BXT_BLC_PWM_FREQ2 0xC8354 |
|
- | 3652 | #define _BXT_BLC_PWM_DUTY2 0xC8358 |
|
- | 3653 | ||
- | 3654 | #define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \ |
|
- | 3655 | _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) |
|
- | 3656 | #define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \ |
|
- | 3657 | _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) |
|
- | 3658 | #define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \ |
|
3083 | #define UTIL_PIN_ENABLE (1 << 31) |
3659 | _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) |
3084 | 3660 | ||
Line 3085... | Line 3661... | ||
3085 | #define PCH_GTC_CTL 0xe7000 |
3661 | #define PCH_GTC_CTL 0xe7000 |
3086 | #define PCH_GTC_ENABLE (1 << 31) |
3662 | #define PCH_GTC_ENABLE (1 << 31) |
Line 3554... | Line 4130... | ||
3554 | # define TV_CC_DATA_2_SHIFT 16 |
4130 | # define TV_CC_DATA_2_SHIFT 16 |
3555 | /* First word of CC data to be transmitted. */ |
4131 | /* First word of CC data to be transmitted. */ |
3556 | # define TV_CC_DATA_1_MASK 0x0000007f |
4132 | # define TV_CC_DATA_1_MASK 0x0000007f |
3557 | # define TV_CC_DATA_1_SHIFT 0 |
4133 | # define TV_CC_DATA_1_SHIFT 0 |
Line 3558... | Line 4134... | ||
3558 | 4134 | ||
3559 | #define TV_H_LUMA_0 0x68100 |
- | |
3560 | #define TV_H_LUMA_59 0x681ec |
4135 | #define TV_H_LUMA(i) (0x68100 + (i) * 4) /* 60 registers */ |
3561 | #define TV_H_CHROMA_0 0x68200 |
- | |
3562 | #define TV_H_CHROMA_59 0x682ec |
4136 | #define TV_H_CHROMA(i) (0x68200 + (i) * 4) /* 60 registers */ |
3563 | #define TV_V_LUMA_0 0x68300 |
- | |
3564 | #define TV_V_LUMA_42 0x683a8 |
4137 | #define TV_V_LUMA(i) (0x68300 + (i) * 4) /* 43 registers */ |
3565 | #define TV_V_CHROMA_0 0x68400 |
- | |
Line 3566... | Line 4138... | ||
3566 | #define TV_V_CHROMA_42 0x684a8 |
4138 | #define TV_V_CHROMA(i) (0x68400 + (i) * 4) /* 43 registers */ |
3567 | 4139 | ||
3568 | /* Display Port */ |
4140 | /* Display Port */ |
3569 | #define DP_A 0x64000 /* eDP */ |
4141 | #define DP_A 0x64000 /* eDP */ |
3570 | #define DP_B 0x64100 |
4142 | #define DP_B 0x64100 |
Line -... | Line 4143... | ||
- | 4143 | #define DP_C 0x64200 |
|
- | 4144 | #define DP_D 0x64300 |
|
- | 4145 | ||
- | 4146 | #define VLV_DP_B (VLV_DISPLAY_BASE + DP_B) |
|
3571 | #define DP_C 0x64200 |
4147 | #define VLV_DP_C (VLV_DISPLAY_BASE + DP_C) |
3572 | #define DP_D 0x64300 |
4148 | #define CHV_DP_D (VLV_DISPLAY_BASE + DP_D) |
3573 | 4149 | ||
3574 | #define DP_PORT_EN (1 << 31) |
4150 | #define DP_PORT_EN (1 << 31) |
3575 | #define DP_PIPEB_SELECT (1 << 30) |
4151 | #define DP_PIPEB_SELECT (1 << 30) |
Line 3614... | Line 4190... | ||
3614 | #define DP_PRE_EMPHASIS_SHIFT 22 |
4190 | #define DP_PRE_EMPHASIS_SHIFT 22 |
Line 3615... | Line 4191... | ||
3615 | 4191 | ||
3616 | /* How many wires to use. I guess 3 was too hard */ |
4192 | /* How many wires to use. I guess 3 was too hard */ |
3617 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
4193 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
- | 4194 | #define DP_PORT_WIDTH_MASK (7 << 19) |
|
Line 3618... | Line 4195... | ||
3618 | #define DP_PORT_WIDTH_MASK (7 << 19) |
4195 | #define DP_PORT_WIDTH_SHIFT 19 |
3619 | 4196 | ||
Line 3620... | Line 4197... | ||
3620 | /* Mystic DPCD version 1.1 special mode */ |
4197 | /* Mystic DPCD version 1.1 special mode */ |
Line 3702... | Line 4279... | ||
3702 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
4279 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
3703 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
4280 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
3704 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
4281 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
3705 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
4282 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
3706 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
4283 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
- | 4284 | #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) |
|
- | 4285 | #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) |
|
- | 4286 | #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) |
|
- | 4287 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) |
|
- | 4288 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) |
|
3707 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
4289 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
Line 3708... | Line 4290... | ||
3708 | 4290 | ||
3709 | /* |
4291 | /* |
3710 | * Computing GMCH M and N values for the Display Port link |
4292 | * Computing GMCH M and N values for the Display Port link |
Line 3794... | Line 4376... | ||
3794 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
4376 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
3795 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
4377 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
3796 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
4378 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
3797 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
4379 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
3798 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
4380 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
- | 4381 | #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) |
|
3799 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
4382 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
3800 | #define PIPECONF_BPC_MASK (0x7 << 5) |
4383 | #define PIPECONF_BPC_MASK (0x7 << 5) |
3801 | #define PIPECONF_8BPC (0<<5) |
4384 | #define PIPECONF_8BPC (0<<5) |
3802 | #define PIPECONF_10BPC (1<<5) |
4385 | #define PIPECONF_10BPC (1<<5) |
3803 | #define PIPECONF_6BPC (2<<5) |
4386 | #define PIPECONF_6BPC (2<<5) |
Line 3942... | Line 4525... | ||
3942 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) |
4525 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) |
3943 | #define PLANEA_INVALID_GTT_STATUS (1<<0) |
4526 | #define PLANEA_INVALID_GTT_STATUS (1<<0) |
3944 | #define DPINVGTT_STATUS_MASK 0xff |
4527 | #define DPINVGTT_STATUS_MASK 0xff |
3945 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
4528 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
Line 3946... | Line 4529... | ||
3946 | 4529 | ||
3947 | #define DSPARB 0x70030 |
4530 | #define DSPARB (dev_priv->info.display_mmio_offset + 0x70030) |
3948 | #define DSPARB_CSTART_MASK (0x7f << 7) |
4531 | #define DSPARB_CSTART_MASK (0x7f << 7) |
3949 | #define DSPARB_CSTART_SHIFT 7 |
4532 | #define DSPARB_CSTART_SHIFT 7 |
3950 | #define DSPARB_BSTART_MASK (0x7f) |
4533 | #define DSPARB_BSTART_MASK (0x7f) |
3951 | #define DSPARB_BSTART_SHIFT 0 |
4534 | #define DSPARB_BSTART_SHIFT 0 |
3952 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
4535 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
- | 4536 | #define DSPARB_AEND_SHIFT 0 |
|
- | 4537 | #define DSPARB_SPRITEA_SHIFT_VLV 0 |
|
- | 4538 | #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) |
|
- | 4539 | #define DSPARB_SPRITEB_SHIFT_VLV 8 |
|
- | 4540 | #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) |
|
- | 4541 | #define DSPARB_SPRITEC_SHIFT_VLV 16 |
|
- | 4542 | #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) |
|
- | 4543 | #define DSPARB_SPRITED_SHIFT_VLV 24 |
|
- | 4544 | #define DSPARB_SPRITED_MASK_VLV (0xff << 24) |
|
- | 4545 | #define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ |
|
- | 4546 | #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 |
|
- | 4547 | #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) |
|
- | 4548 | #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 |
|
- | 4549 | #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) |
|
- | 4550 | #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 |
|
- | 4551 | #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) |
|
- | 4552 | #define DSPARB_SPRITED_HI_SHIFT_VLV 12 |
|
- | 4553 | #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) |
|
- | 4554 | #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 |
|
- | 4555 | #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) |
|
- | 4556 | #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 |
|
- | 4557 | #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) |
|
- | 4558 | #define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */ |
|
- | 4559 | #define DSPARB_SPRITEE_SHIFT_VLV 0 |
|
- | 4560 | #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) |
|
- | 4561 | #define DSPARB_SPRITEF_SHIFT_VLV 8 |
|
Line 3953... | Line 4562... | ||
3953 | #define DSPARB_AEND_SHIFT 0 |
4562 | #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) |
3954 | 4563 | ||
3955 | /* pnv/gen4/g4x/vlv/chv */ |
4564 | /* pnv/gen4/g4x/vlv/chv */ |
3956 | #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
4565 | #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
Line 3973... | Line 4582... | ||
3973 | #define DSPFW_SPRITEB_SHIFT (16) |
4582 | #define DSPFW_SPRITEB_SHIFT (16) |
3974 | #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ |
4583 | #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ |
3975 | #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ |
4584 | #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ |
3976 | #define DSPFW_CURSORA_SHIFT 8 |
4585 | #define DSPFW_CURSORA_SHIFT 8 |
3977 | #define DSPFW_CURSORA_MASK (0x3f<<8) |
4586 | #define DSPFW_CURSORA_MASK (0x3f<<8) |
3978 | #define DSPFW_PLANEC_SHIFT_OLD 0 |
4587 | #define DSPFW_PLANEC_OLD_SHIFT 0 |
3979 | #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ |
4588 | #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ |
3980 | #define DSPFW_SPRITEA_SHIFT 0 |
4589 | #define DSPFW_SPRITEA_SHIFT 0 |
3981 | #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ |
4590 | #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ |
3982 | #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ |
4591 | #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ |
3983 | #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
4592 | #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
3984 | #define DSPFW_HPLL_SR_EN (1<<31) |
4593 | #define DSPFW_HPLL_SR_EN (1<<31) |
Line 4013... | Line 4622... | ||
4013 | #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) |
4622 | #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) |
4014 | #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
4623 | #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
4015 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
4624 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
4016 | #define DSPFW_SPRITED_WM1_MASK (0xff<<24) |
4625 | #define DSPFW_SPRITED_WM1_MASK (0xff<<24) |
4017 | #define DSPFW_SPRITED_SHIFT 16 |
4626 | #define DSPFW_SPRITED_SHIFT 16 |
4018 | #define DSPFW_SPRITED_MASK (0xff<<16) |
4627 | #define DSPFW_SPRITED_MASK_VLV (0xff<<16) |
4019 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
4628 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
4020 | #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) |
4629 | #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) |
4021 | #define DSPFW_SPRITEC_SHIFT 0 |
4630 | #define DSPFW_SPRITEC_SHIFT 0 |
4022 | #define DSPFW_SPRITEC_MASK (0xff<<0) |
4631 | #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) |
4023 | #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) |
4632 | #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) |
4024 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
4633 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
4025 | #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) |
4634 | #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) |
4026 | #define DSPFW_SPRITEF_SHIFT 16 |
4635 | #define DSPFW_SPRITEF_SHIFT 16 |
4027 | #define DSPFW_SPRITEF_MASK (0xff<<16) |
4636 | #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) |
4028 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
4637 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
4029 | #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) |
4638 | #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) |
4030 | #define DSPFW_SPRITEE_SHIFT 0 |
4639 | #define DSPFW_SPRITEE_SHIFT 0 |
4031 | #define DSPFW_SPRITEE_MASK (0xff<<0) |
4640 | #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) |
4032 | #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
4641 | #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
4033 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
4642 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
4034 | #define DSPFW_PLANEC_WM1_MASK (0xff<<24) |
4643 | #define DSPFW_PLANEC_WM1_MASK (0xff<<24) |
4035 | #define DSPFW_PLANEC_SHIFT 16 |
4644 | #define DSPFW_PLANEC_SHIFT 16 |
4036 | #define DSPFW_PLANEC_MASK (0xff<<16) |
4645 | #define DSPFW_PLANEC_MASK_VLV (0xff<<16) |
4037 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
4646 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
4038 | #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) |
4647 | #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) |
4039 | #define DSPFW_CURSORC_SHIFT 0 |
4648 | #define DSPFW_CURSORC_SHIFT 0 |
4040 | #define DSPFW_CURSORC_MASK (0x3f<<0) |
4649 | #define DSPFW_CURSORC_MASK (0x3f<<0) |
Line 4041... | Line 4650... | ||
4041 | 4650 | ||
4042 | /* vlv/chv high order bits */ |
4651 | /* vlv/chv high order bits */ |
4043 | #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) |
4652 | #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) |
4044 | #define DSPFW_SR_HI_SHIFT 24 |
4653 | #define DSPFW_SR_HI_SHIFT 24 |
4045 | #define DSPFW_SR_HI_MASK (1<<24) |
4654 | #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ |
4046 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
4655 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
4047 | #define DSPFW_SPRITEF_HI_MASK (1<<23) |
4656 | #define DSPFW_SPRITEF_HI_MASK (1<<23) |
4048 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
4657 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
4049 | #define DSPFW_SPRITEE_HI_MASK (1<<22) |
4658 | #define DSPFW_SPRITEE_HI_MASK (1<<22) |
Line 4061... | Line 4670... | ||
4061 | #define DSPFW_SPRITEA_HI_MASK (1<<4) |
4670 | #define DSPFW_SPRITEA_HI_MASK (1<<4) |
4062 | #define DSPFW_PLANEA_HI_SHIFT 0 |
4671 | #define DSPFW_PLANEA_HI_SHIFT 0 |
4063 | #define DSPFW_PLANEA_HI_MASK (1<<0) |
4672 | #define DSPFW_PLANEA_HI_MASK (1<<0) |
4064 | #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) |
4673 | #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) |
4065 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
4674 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
4066 | #define DSPFW_SR_WM1_HI_MASK (1<<24) |
4675 | #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ |
4067 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
4676 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
4068 | #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) |
4677 | #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) |
4069 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
4678 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
4070 | #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) |
4679 | #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) |
4071 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
4680 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
Line 4082... | Line 4691... | ||
4082 | #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) |
4691 | #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) |
4083 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
4692 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
4084 | #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) |
4693 | #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) |
Line 4085... | Line 4694... | ||
4085 | 4694 | ||
4086 | /* drain latency register values*/ |
- | |
4087 | #define DRAIN_LATENCY_PRECISION_16 16 |
- | |
4088 | #define DRAIN_LATENCY_PRECISION_32 32 |
- | |
4089 | #define DRAIN_LATENCY_PRECISION_64 64 |
4695 | /* drain latency register values*/ |
4090 | #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
- | |
4091 | #define DDL_CURSOR_PRECISION_HIGH (1<<31) |
- | |
4092 | #define DDL_CURSOR_PRECISION_LOW (0<<31) |
4696 | #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
4093 | #define DDL_CURSOR_SHIFT 24 |
- | |
4094 | #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite))) |
- | |
4095 | #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite))) |
4697 | #define DDL_CURSOR_SHIFT 24 |
4096 | #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) |
- | |
4097 | #define DDL_PLANE_PRECISION_HIGH (1<<7) |
- | |
4098 | #define DDL_PLANE_PRECISION_LOW (0<<7) |
4698 | #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) |
- | 4699 | #define DDL_PLANE_SHIFT 0 |
|
- | 4700 | #define DDL_PRECISION_HIGH (1<<7) |
|
4099 | #define DDL_PLANE_SHIFT 0 |
4701 | #define DDL_PRECISION_LOW (0<<7) |
Line -... | Line 4702... | ||
- | 4702 | #define DRAIN_LATENCY_MASK 0x7f |
|
- | 4703 | ||
- | 4704 | #define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400) |
|
- | 4705 | #define CBR_PND_DEADLINE_DISABLE (1<<31) |
|
4100 | #define DRAIN_LATENCY_MASK 0x7f |
4706 | #define CBR_PWM_CLOCK_MUX_SELECT (1<<30) |
4101 | 4707 | ||
4102 | /* FIFO watermark sizes etc */ |
4708 | /* FIFO watermark sizes etc */ |
4103 | #define G4X_FIFO_LINE_SIZE 64 |
4709 | #define G4X_FIFO_LINE_SIZE 64 |
Line 4238... | Line 4844... | ||
4238 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
4844 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
4239 | #define PIPE_FRAME_LOW_SHIFT 24 |
4845 | #define PIPE_FRAME_LOW_SHIFT 24 |
4240 | #define PIPE_PIXEL_MASK 0x00ffffff |
4846 | #define PIPE_PIXEL_MASK 0x00ffffff |
4241 | #define PIPE_PIXEL_SHIFT 0 |
4847 | #define PIPE_PIXEL_SHIFT 0 |
4242 | /* GM45+ just has to be different */ |
4848 | /* GM45+ just has to be different */ |
4243 | #define _PIPEA_FRMCOUNT_GM45 0x70040 |
4849 | #define _PIPEA_FRMCOUNT_G4X 0x70040 |
4244 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 |
4850 | #define _PIPEA_FLIPCOUNT_G4X 0x70044 |
4245 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) |
4851 | #define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) |
4246 | #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) |
4852 | #define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) |
Line 4247... | Line 4853... | ||
4247 | 4853 | ||
4248 | /* Cursor A & B regs */ |
4854 | /* Cursor A & B regs */ |
4249 | #define _CURACNTR 0x70080 |
4855 | #define _CURACNTR 0x70080 |
4250 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
4856 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
Line 4383... | Line 4989... | ||
4383 | /* Display/Sprite base address macros */ |
4989 | /* Display/Sprite base address macros */ |
4384 | #define DISP_BASEADDR_MASK (0xfffff000) |
4990 | #define DISP_BASEADDR_MASK (0xfffff000) |
4385 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
4991 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
4386 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
4992 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
Line -... | Line 4993... | ||
- | 4993 | ||
4387 | 4994 | /* |
|
- | 4995 | * VBIOS flags |
|
4388 | /* VBIOS flags */ |
4996 | * gen2: |
4389 | #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) |
- | |
4390 | #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) |
4997 | * [00:06] alm,mgm |
4391 | #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) |
4998 | * [10:16] all |
4392 | #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) |
4999 | * [30:32] alm,mgm |
4393 | #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) |
5000 | * gen3+: |
4394 | #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) |
5001 | * [00:0f] all |
4395 | #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) |
5002 | * [10:1f] all |
- | 5003 | * [30:32] all |
|
4396 | #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) |
5004 | */ |
4397 | #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) |
5005 | #define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) |
4398 | #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) |
5006 | #define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) |
4399 | #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) |
- | |
4400 | #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) |
- | |
Line 4401... | Line 5007... | ||
4401 | #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) |
5007 | #define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) |
4402 | 5008 | ||
4403 | /* Pipe B */ |
5009 | /* Pipe B */ |
4404 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
5010 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
4405 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) |
5011 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) |
4406 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) |
5012 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) |
4407 | #define _PIPEBFRAMEHIGH 0x71040 |
5013 | #define _PIPEBFRAMEHIGH 0x71040 |
4408 | #define _PIPEBFRAMEPIXEL 0x71044 |
5014 | #define _PIPEBFRAMEPIXEL 0x71044 |
Line 4409... | Line 5015... | ||
4409 | #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) |
5015 | #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) |
4410 | #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) |
5016 | #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) |
4411 | 5017 | ||
Line 4615... | Line 5221... | ||
4615 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) |
5221 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) |
4616 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) |
5222 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) |
4617 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) |
5223 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) |
4618 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) |
5224 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) |
Line 4619... | Line 5225... | ||
4619 | 5225 | ||
4620 | #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) |
5226 | #define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR) |
4621 | #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) |
5227 | #define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF) |
4622 | #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) |
5228 | #define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE) |
4623 | #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) |
5229 | #define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS) |
4624 | #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) |
5230 | #define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE) |
4625 | #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) |
5231 | #define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL) |
4626 | #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) |
5232 | #define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK) |
4627 | #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) |
5233 | #define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF) |
4628 | #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) |
5234 | #define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL) |
4629 | #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) |
5235 | #define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF) |
4630 | #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) |
5236 | #define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA) |
Line 4631... | Line 5237... | ||
4631 | #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) |
5237 | #define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC) |
4632 | 5238 | ||
4633 | /* |
5239 | /* |
4634 | * CHV pipe B sprite CSC |
5240 | * CHV pipe B sprite CSC |
Line 4702... | Line 5308... | ||
4702 | #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) |
5308 | #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) |
4703 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) |
5309 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) |
4704 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) |
5310 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) |
4705 | #define PLANE_CTL_ROTATE_MASK 0x3 |
5311 | #define PLANE_CTL_ROTATE_MASK 0x3 |
4706 | #define PLANE_CTL_ROTATE_0 0x0 |
5312 | #define PLANE_CTL_ROTATE_0 0x0 |
- | 5313 | #define PLANE_CTL_ROTATE_90 0x1 |
|
4707 | #define PLANE_CTL_ROTATE_180 0x2 |
5314 | #define PLANE_CTL_ROTATE_180 0x2 |
- | 5315 | #define PLANE_CTL_ROTATE_270 0x3 |
|
4708 | #define _PLANE_STRIDE_1_A 0x70188 |
5316 | #define _PLANE_STRIDE_1_A 0x70188 |
4709 | #define _PLANE_STRIDE_2_A 0x70288 |
5317 | #define _PLANE_STRIDE_2_A 0x70288 |
4710 | #define _PLANE_STRIDE_3_A 0x70388 |
5318 | #define _PLANE_STRIDE_3_A 0x70388 |
4711 | #define _PLANE_POS_1_A 0x7018c |
5319 | #define _PLANE_POS_1_A 0x7018c |
4712 | #define _PLANE_POS_2_A 0x7028c |
5320 | #define _PLANE_POS_2_A 0x7028c |
Line 4726... | Line 5334... | ||
4726 | #define _PLANE_KEYMSK_2_A 0x70298 |
5334 | #define _PLANE_KEYMSK_2_A 0x70298 |
4727 | #define _PLANE_KEYMAX_1_A 0x701a0 |
5335 | #define _PLANE_KEYMAX_1_A 0x701a0 |
4728 | #define _PLANE_KEYMAX_2_A 0x702a0 |
5336 | #define _PLANE_KEYMAX_2_A 0x702a0 |
4729 | #define _PLANE_BUF_CFG_1_A 0x7027c |
5337 | #define _PLANE_BUF_CFG_1_A 0x7027c |
4730 | #define _PLANE_BUF_CFG_2_A 0x7037c |
5338 | #define _PLANE_BUF_CFG_2_A 0x7037c |
- | 5339 | #define _PLANE_NV12_BUF_CFG_1_A 0x70278 |
|
- | 5340 | #define _PLANE_NV12_BUF_CFG_2_A 0x70378 |
|
Line 4731... | Line 5341... | ||
4731 | 5341 | ||
4732 | #define _PLANE_CTL_1_B 0x71180 |
5342 | #define _PLANE_CTL_1_B 0x71180 |
4733 | #define _PLANE_CTL_2_B 0x71280 |
5343 | #define _PLANE_CTL_2_B 0x71280 |
4734 | #define _PLANE_CTL_3_B 0x71380 |
5344 | #define _PLANE_CTL_3_B 0x71380 |
Line 4812... | Line 5422... | ||
4812 | #define _PLANE_BUF_CFG_2(pipe) \ |
5422 | #define _PLANE_BUF_CFG_2(pipe) \ |
4813 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) |
5423 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) |
4814 | #define PLANE_BUF_CFG(pipe, plane) \ |
5424 | #define PLANE_BUF_CFG(pipe, plane) \ |
4815 | _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) |
5425 | _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) |
Line -... | Line 5426... | ||
- | 5426 | ||
- | 5427 | #define _PLANE_NV12_BUF_CFG_1_B 0x71278 |
|
- | 5428 | #define _PLANE_NV12_BUF_CFG_2_B 0x71378 |
|
- | 5429 | #define _PLANE_NV12_BUF_CFG_1(pipe) \ |
|
- | 5430 | _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) |
|
- | 5431 | #define _PLANE_NV12_BUF_CFG_2(pipe) \ |
|
- | 5432 | _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) |
|
- | 5433 | #define PLANE_NV12_BUF_CFG(pipe, plane) \ |
|
- | 5434 | _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) |
|
4816 | 5435 | ||
4817 | /* SKL new cursor registers */ |
5436 | /* SKL new cursor registers */ |
4818 | #define _CUR_BUF_CFG_A 0x7017c |
5437 | #define _CUR_BUF_CFG_A 0x7017c |
4819 | #define _CUR_BUF_CFG_B 0x7117c |
5438 | #define _CUR_BUF_CFG_B 0x7117c |
Line 4831... | Line 5450... | ||
4831 | 5450 | ||
Line 4832... | Line 5451... | ||
4832 | #define CPU_VGACNTRL 0x41000 |
5451 | #define CPU_VGACNTRL 0x41000 |
4833 | 5452 | ||
4834 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
5453 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
4835 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
5454 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
4836 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) |
5455 | #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ |
- | 5456 | #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ |
|
- | 5457 | #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ |
|
4837 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) |
5458 | #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ |
4838 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) |
5459 | #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ |
4839 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) |
5460 | #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) |
4840 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) |
5461 | #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) |
Line 4841... | Line 5462... | ||
4841 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) |
5462 | #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) |
4842 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) |
5463 | #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) |
4843 | 5464 | ||
4844 | /* refresh rate hardware control */ |
5465 | /* refresh rate hardware control */ |
Line 4944... | Line 5565... | ||
4944 | 5565 | ||
4945 | #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) |
5566 | #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) |
4946 | #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) |
5567 | #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) |
Line -... | Line 5568... | ||
- | 5568 | #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) |
|
- | 5569 | ||
- | 5570 | /* |
|
- | 5571 | * Skylake scalers |
|
- | 5572 | */ |
|
- | 5573 | #define _PS_1A_CTRL 0x68180 |
|
- | 5574 | #define _PS_2A_CTRL 0x68280 |
|
- | 5575 | #define _PS_1B_CTRL 0x68980 |
|
- | 5576 | #define _PS_2B_CTRL 0x68A80 |
|
- | 5577 | #define _PS_1C_CTRL 0x69180 |
|
- | 5578 | #define PS_SCALER_EN (1 << 31) |
|
- | 5579 | #define PS_SCALER_MODE_MASK (3 << 28) |
|
- | 5580 | #define PS_SCALER_MODE_DYN (0 << 28) |
|
- | 5581 | #define PS_SCALER_MODE_HQ (1 << 28) |
|
- | 5582 | #define PS_PLANE_SEL_MASK (7 << 25) |
|
- | 5583 | #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) |
|
- | 5584 | #define PS_FILTER_MASK (3 << 23) |
|
- | 5585 | #define PS_FILTER_MEDIUM (0 << 23) |
|
- | 5586 | #define PS_FILTER_EDGE_ENHANCE (2 << 23) |
|
- | 5587 | #define PS_FILTER_BILINEAR (3 << 23) |
|
- | 5588 | #define PS_VERT3TAP (1 << 21) |
|
- | 5589 | #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) |
|
- | 5590 | #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) |
|
- | 5591 | #define PS_PWRUP_PROGRESS (1 << 17) |
|
- | 5592 | #define PS_V_FILTER_BYPASS (1 << 8) |
|
- | 5593 | #define PS_VADAPT_EN (1 << 7) |
|
- | 5594 | #define PS_VADAPT_MODE_MASK (3 << 5) |
|
- | 5595 | #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) |
|
- | 5596 | #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) |
|
- | 5597 | #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) |
|
- | 5598 | ||
- | 5599 | #define _PS_PWR_GATE_1A 0x68160 |
|
- | 5600 | #define _PS_PWR_GATE_2A 0x68260 |
|
- | 5601 | #define _PS_PWR_GATE_1B 0x68960 |
|
- | 5602 | #define _PS_PWR_GATE_2B 0x68A60 |
|
- | 5603 | #define _PS_PWR_GATE_1C 0x69160 |
|
- | 5604 | #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) |
|
- | 5605 | #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) |
|
- | 5606 | #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) |
|
- | 5607 | #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) |
|
- | 5608 | #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) |
|
- | 5609 | #define PS_PWR_GATE_SLPEN_8 0 |
|
- | 5610 | #define PS_PWR_GATE_SLPEN_16 1 |
|
- | 5611 | #define PS_PWR_GATE_SLPEN_24 2 |
|
- | 5612 | #define PS_PWR_GATE_SLPEN_32 3 |
|
- | 5613 | ||
- | 5614 | #define _PS_WIN_POS_1A 0x68170 |
|
- | 5615 | #define _PS_WIN_POS_2A 0x68270 |
|
- | 5616 | #define _PS_WIN_POS_1B 0x68970 |
|
- | 5617 | #define _PS_WIN_POS_2B 0x68A70 |
|
- | 5618 | #define _PS_WIN_POS_1C 0x69170 |
|
- | 5619 | ||
- | 5620 | #define _PS_WIN_SZ_1A 0x68174 |
|
- | 5621 | #define _PS_WIN_SZ_2A 0x68274 |
|
- | 5622 | #define _PS_WIN_SZ_1B 0x68974 |
|
- | 5623 | #define _PS_WIN_SZ_2B 0x68A74 |
|
- | 5624 | #define _PS_WIN_SZ_1C 0x69174 |
|
- | 5625 | ||
- | 5626 | #define _PS_VSCALE_1A 0x68184 |
|
- | 5627 | #define _PS_VSCALE_2A 0x68284 |
|
- | 5628 | #define _PS_VSCALE_1B 0x68984 |
|
- | 5629 | #define _PS_VSCALE_2B 0x68A84 |
|
- | 5630 | #define _PS_VSCALE_1C 0x69184 |
|
- | 5631 | ||
- | 5632 | #define _PS_HSCALE_1A 0x68190 |
|
- | 5633 | #define _PS_HSCALE_2A 0x68290 |
|
- | 5634 | #define _PS_HSCALE_1B 0x68990 |
|
- | 5635 | #define _PS_HSCALE_2B 0x68A90 |
|
- | 5636 | #define _PS_HSCALE_1C 0x69190 |
|
- | 5637 | ||
- | 5638 | #define _PS_VPHASE_1A 0x68188 |
|
- | 5639 | #define _PS_VPHASE_2A 0x68288 |
|
- | 5640 | #define _PS_VPHASE_1B 0x68988 |
|
- | 5641 | #define _PS_VPHASE_2B 0x68A88 |
|
- | 5642 | #define _PS_VPHASE_1C 0x69188 |
|
- | 5643 | ||
- | 5644 | #define _PS_HPHASE_1A 0x68194 |
|
- | 5645 | #define _PS_HPHASE_2A 0x68294 |
|
- | 5646 | #define _PS_HPHASE_1B 0x68994 |
|
- | 5647 | #define _PS_HPHASE_2B 0x68A94 |
|
- | 5648 | #define _PS_HPHASE_1C 0x69194 |
|
- | 5649 | ||
- | 5650 | #define _PS_ECC_STAT_1A 0x681D0 |
|
- | 5651 | #define _PS_ECC_STAT_2A 0x682D0 |
|
- | 5652 | #define _PS_ECC_STAT_1B 0x689D0 |
|
- | 5653 | #define _PS_ECC_STAT_2B 0x68AD0 |
|
- | 5654 | #define _PS_ECC_STAT_1C 0x691D0 |
|
- | 5655 | ||
- | 5656 | #define _ID(id, a, b) ((a) + (id)*((b)-(a))) |
|
- | 5657 | #define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \ |
|
- | 5658 | _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ |
|
- | 5659 | _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) |
|
- | 5660 | #define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \ |
|
- | 5661 | _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ |
|
- | 5662 | _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) |
|
- | 5663 | #define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \ |
|
- | 5664 | _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ |
|
- | 5665 | _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) |
|
- | 5666 | #define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \ |
|
- | 5667 | _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ |
|
- | 5668 | _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) |
|
- | 5669 | #define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \ |
|
- | 5670 | _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ |
|
- | 5671 | _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) |
|
- | 5672 | #define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \ |
|
- | 5673 | _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ |
|
- | 5674 | _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) |
|
- | 5675 | #define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \ |
|
- | 5676 | _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ |
|
- | 5677 | _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) |
|
- | 5678 | #define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \ |
|
- | 5679 | _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ |
|
- | 5680 | _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) |
|
- | 5681 | #define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \ |
|
- | 5682 | _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ |
|
4947 | #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) |
5683 | _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B) |
4948 | 5684 | ||
4949 | /* legacy palette */ |
5685 | /* legacy palette */ |
4950 | #define _LGC_PALETTE_A 0x4a000 |
5686 | #define _LGC_PALETTE_A 0x4a000 |
Line 4951... | Line 5687... | ||
4951 | #define _LGC_PALETTE_B 0x4a800 |
5687 | #define _LGC_PALETTE_B 0x4a800 |
4952 | #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) |
5688 | #define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) |
4953 | 5689 | ||
4954 | #define _GAMMA_MODE_A 0x4a480 |
5690 | #define _GAMMA_MODE_A 0x4a480 |
Line 5007... | Line 5743... | ||
5007 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
5743 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
5008 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
5744 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
5009 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
5745 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
5010 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
5746 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
5011 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
5747 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
5012 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) |
5748 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) |
Line 5013... | Line 5749... | ||
5013 | 5749 | ||
5014 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
5750 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
Line 5015... | Line 5751... | ||
5015 | #define MASTER_INTERRUPT_ENABLE (1<<31) |
5751 | #define MASTER_INTERRUPT_ENABLE (1<<31) |
Line 5031... | Line 5767... | ||
5031 | #define GEN8_DE_MISC_IRQ (1<<22) |
5767 | #define GEN8_DE_MISC_IRQ (1<<22) |
5032 | #define GEN8_DE_PORT_IRQ (1<<20) |
5768 | #define GEN8_DE_PORT_IRQ (1<<20) |
5033 | #define GEN8_DE_PIPE_C_IRQ (1<<18) |
5769 | #define GEN8_DE_PIPE_C_IRQ (1<<18) |
5034 | #define GEN8_DE_PIPE_B_IRQ (1<<17) |
5770 | #define GEN8_DE_PIPE_B_IRQ (1<<17) |
5035 | #define GEN8_DE_PIPE_A_IRQ (1<<16) |
5771 | #define GEN8_DE_PIPE_A_IRQ (1<<16) |
5036 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) |
5772 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe))) |
5037 | #define GEN8_GT_VECS_IRQ (1<<6) |
5773 | #define GEN8_GT_VECS_IRQ (1<<6) |
5038 | #define GEN8_GT_PM_IRQ (1<<4) |
5774 | #define GEN8_GT_PM_IRQ (1<<4) |
5039 | #define GEN8_GT_VCS2_IRQ (1<<3) |
5775 | #define GEN8_GT_VCS2_IRQ (1<<3) |
5040 | #define GEN8_GT_VCS1_IRQ (1<<2) |
5776 | #define GEN8_GT_VCS1_IRQ (1<<2) |
5041 | #define GEN8_GT_BCS_IRQ (1<<1) |
5777 | #define GEN8_GT_BCS_IRQ (1<<1) |
Line 5044... | Line 5780... | ||
5044 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) |
5780 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) |
5045 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) |
5781 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) |
5046 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) |
5782 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) |
5047 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) |
5783 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) |
Line 5048... | Line -... | ||
5048 | - | ||
5049 | #define GEN8_BCS_IRQ_SHIFT 16 |
5784 | |
5050 | #define GEN8_RCS_IRQ_SHIFT 0 |
5785 | #define GEN8_RCS_IRQ_SHIFT 0 |
5051 | #define GEN8_VCS2_IRQ_SHIFT 16 |
5786 | #define GEN8_BCS_IRQ_SHIFT 16 |
- | 5787 | #define GEN8_VCS1_IRQ_SHIFT 0 |
|
5052 | #define GEN8_VCS1_IRQ_SHIFT 0 |
5788 | #define GEN8_VCS2_IRQ_SHIFT 16 |
- | 5789 | #define GEN8_VECS_IRQ_SHIFT 0 |
|
Line 5053... | Line 5790... | ||
5053 | #define GEN8_VECS_IRQ_SHIFT 0 |
5790 | #define GEN8_WD_IRQ_SHIFT 16 |
5054 | 5791 | ||
5055 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) |
5792 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) |
5056 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) |
5793 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) |
Line 5066... | Line 5803... | ||
5066 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
5803 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
5067 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
5804 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
5068 | #define GEN8_PIPE_VSYNC (1 << 1) |
5805 | #define GEN8_PIPE_VSYNC (1 << 1) |
5069 | #define GEN8_PIPE_VBLANK (1 << 0) |
5806 | #define GEN8_PIPE_VBLANK (1 << 0) |
5070 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
5807 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
- | 5808 | #define GEN9_PIPE_PLANE4_FAULT (1 << 10) |
|
5071 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
5809 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
5072 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) |
5810 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) |
5073 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) |
5811 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) |
- | 5812 | #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) |
|
5074 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
5813 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
5075 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) |
5814 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) |
5076 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) |
5815 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) |
5077 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) |
5816 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) |
5078 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
5817 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
5079 | (GEN8_PIPE_CURSOR_FAULT | \ |
5818 | (GEN8_PIPE_CURSOR_FAULT | \ |
5080 | GEN8_PIPE_SPRITE_FAULT | \ |
5819 | GEN8_PIPE_SPRITE_FAULT | \ |
5081 | GEN8_PIPE_PRIMARY_FAULT) |
5820 | GEN8_PIPE_PRIMARY_FAULT) |
5082 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
5821 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
5083 | (GEN9_PIPE_CURSOR_FAULT | \ |
5822 | (GEN9_PIPE_CURSOR_FAULT | \ |
- | 5823 | GEN9_PIPE_PLANE4_FAULT | \ |
|
5084 | GEN9_PIPE_PLANE3_FAULT | \ |
5824 | GEN9_PIPE_PLANE3_FAULT | \ |
5085 | GEN9_PIPE_PLANE2_FAULT | \ |
5825 | GEN9_PIPE_PLANE2_FAULT | \ |
5086 | GEN9_PIPE_PLANE1_FAULT) |
5826 | GEN9_PIPE_PLANE1_FAULT) |
Line 5087... | Line 5827... | ||
5087 | 5827 | ||
5088 | #define GEN8_DE_PORT_ISR 0x44440 |
5828 | #define GEN8_DE_PORT_ISR 0x44440 |
5089 | #define GEN8_DE_PORT_IMR 0x44444 |
5829 | #define GEN8_DE_PORT_IMR 0x44444 |
5090 | #define GEN8_DE_PORT_IIR 0x44448 |
5830 | #define GEN8_DE_PORT_IIR 0x44448 |
5091 | #define GEN8_DE_PORT_IER 0x4444c |
- | |
5092 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
5831 | #define GEN8_DE_PORT_IER 0x4444c |
5093 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
5832 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
5094 | #define GEN9_AUX_CHANNEL_C (1 << 26) |
5833 | #define GEN9_AUX_CHANNEL_C (1 << 26) |
- | 5834 | #define GEN9_AUX_CHANNEL_B (1 << 25) |
|
- | 5835 | #define BXT_DE_PORT_HP_DDIC (1 << 5) |
|
- | 5836 | #define BXT_DE_PORT_HP_DDIB (1 << 4) |
|
- | 5837 | #define BXT_DE_PORT_HP_DDIA (1 << 3) |
|
- | 5838 | #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ |
|
- | 5839 | BXT_DE_PORT_HP_DDIB | \ |
|
- | 5840 | BXT_DE_PORT_HP_DDIC) |
|
- | 5841 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
|
5095 | #define GEN9_AUX_CHANNEL_B (1 << 25) |
5842 | #define BXT_DE_PORT_GMBUS (1 << 1) |
Line 5096... | Line 5843... | ||
5096 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
5843 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
5097 | 5844 | ||
5098 | #define GEN8_DE_MISC_ISR 0x44460 |
5845 | #define GEN8_DE_MISC_ISR 0x44460 |
Line 5144... | Line 5891... | ||
5144 | #define DISP_ARB_CTL 0x45000 |
5891 | #define DISP_ARB_CTL 0x45000 |
5145 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
5892 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
5146 | #define DISP_FBC_WM_DIS (1<<15) |
5893 | #define DISP_FBC_WM_DIS (1<<15) |
5147 | #define DISP_ARB_CTL2 0x45004 |
5894 | #define DISP_ARB_CTL2 0x45004 |
5148 | #define DISP_DATA_PARTITION_5_6 (1<<6) |
5895 | #define DISP_DATA_PARTITION_5_6 (1<<6) |
- | 5896 | #define DBUF_CTL 0x45008 |
|
- | 5897 | #define DBUF_POWER_REQUEST (1<<31) |
|
- | 5898 | #define DBUF_POWER_STATE (1<<30) |
|
5149 | #define GEN7_MSG_CTL 0x45010 |
5899 | #define GEN7_MSG_CTL 0x45010 |
5150 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
5900 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
5151 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) |
5901 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) |
5152 | #define HSW_NDE_RSTWRN_OPT 0x46408 |
5902 | #define HSW_NDE_RSTWRN_OPT 0x46408 |
5153 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
5903 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
Line -... | Line 5904... | ||
- | 5904 | ||
- | 5905 | #define SKL_DFSM 0x51000 |
|
- | 5906 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
|
- | 5907 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) |
|
- | 5908 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) |
|
- | 5909 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) |
|
- | 5910 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) |
|
- | 5911 | ||
- | 5912 | #define FF_SLICE_CS_CHICKEN2 0x20e4 |
|
- | 5913 | #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) |
|
5154 | 5914 | ||
5155 | /* GEN7 chicken */ |
5915 | /* GEN7 chicken */ |
5156 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
5916 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
- | 5917 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
|
5157 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
5918 | # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) |
5158 | #define COMMON_SLICE_CHICKEN2 0x7014 |
5919 | #define COMMON_SLICE_CHICKEN2 0x7014 |
Line -... | Line 5920... | ||
- | 5920 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
|
- | 5921 | ||
- | 5922 | #define HIZ_CHICKEN 0x7018 |
|
- | 5923 | # define CHV_HZ_8X8_MODE_IN_1X (1<<15) |
|
- | 5924 | # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) |
|
- | 5925 | ||
- | 5926 | #define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308 |
|
5159 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
5927 | #define DISABLE_PIXEL_MASK_CAMMING (1<<14) |
5160 | 5928 | ||
Line -... | Line 5929... | ||
- | 5929 | #define GEN7_L3SQCREG1 0xB010 |
|
- | 5930 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
|
- | 5931 | ||
5161 | #define GEN7_L3SQCREG1 0xB010 |
5932 | #define GEN8_L3SQCREG1 0xB100 |
5162 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
5933 | #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 |
5163 | 5934 | ||
5164 | #define GEN7_L3CNTLREG1 0xB01C |
5935 | #define GEN7_L3CNTLREG1 0xB01C |
5165 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
5936 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
Line 5171... | Line 5942... | ||
5171 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
5942 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
Line 5172... | Line 5943... | ||
5172 | 5943 | ||
5173 | #define GEN7_L3SQCREG4 0xb034 |
5944 | #define GEN7_L3SQCREG4 0xb034 |
Line -... | Line 5945... | ||
- | 5945 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
|
- | 5946 | ||
- | 5947 | #define GEN8_L3SQCREG4 0xb118 |
|
- | 5948 | #define GEN8_LQSC_RO_PERF_DIS (1<<27) |
|
5174 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
5949 | #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) |
5175 | 5950 | ||
5176 | /* GEN8 chicken */ |
5951 | /* GEN8 chicken */ |
5177 | #define HDC_CHICKEN0 0x7300 |
- | |
5178 | #define HDC_FORCE_NON_COHERENT (1<<4) |
5952 | #define HDC_CHICKEN0 0x7300 |
- | 5953 | #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) |
|
- | 5954 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
|
- | 5955 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
|
- | 5956 | #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) |
|
- | 5957 | #define HDC_FORCE_NON_COHERENT (1<<4) |
|
- | 5958 | #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) |
|
- | 5959 | ||
- | 5960 | /* GEN9 chicken */ |
|
Line 5179... | Line 5961... | ||
5179 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
5961 | #define SLICE_ECO_CHICKEN0 0x7308 |
5180 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
5962 | #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) |
5181 | 5963 | ||
Line 5182... | Line 5964... | ||
5182 | /* WaCatErrorRejectionIssue */ |
5964 | /* WaCatErrorRejectionIssue */ |
5183 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
5965 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
Line -... | Line 5966... | ||
- | 5966 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
|
- | 5967 | ||
- | 5968 | #define HSW_SCRATCH1 0xb038 |
|
5184 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
5969 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) |
Line 5185... | Line 5970... | ||
5185 | 5970 | ||
5186 | #define HSW_SCRATCH1 0xb038 |
5971 | #define BDW_SCRATCH1 0xb11c |
5187 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) |
5972 | #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) |
Line 5237... | Line 6022... | ||
5237 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
6022 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
5238 | #define SDE_AUXD_CPT (1 << 27) |
6023 | #define SDE_AUXD_CPT (1 << 27) |
5239 | #define SDE_AUXC_CPT (1 << 26) |
6024 | #define SDE_AUXC_CPT (1 << 26) |
5240 | #define SDE_AUXB_CPT (1 << 25) |
6025 | #define SDE_AUXB_CPT (1 << 25) |
5241 | #define SDE_AUX_MASK_CPT (7 << 25) |
6026 | #define SDE_AUX_MASK_CPT (7 << 25) |
- | 6027 | #define SDE_PORTE_HOTPLUG_SPT (1 << 25) |
|
- | 6028 | #define SDE_PORTA_HOTPLUG_SPT (1 << 24) |
|
5242 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
6029 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
5243 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
6030 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
5244 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
6031 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
5245 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
6032 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
5246 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
6033 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
5247 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
6034 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
5248 | SDE_SDVOB_HOTPLUG_CPT | \ |
6035 | SDE_SDVOB_HOTPLUG_CPT | \ |
5249 | SDE_PORTD_HOTPLUG_CPT | \ |
6036 | SDE_PORTD_HOTPLUG_CPT | \ |
5250 | SDE_PORTC_HOTPLUG_CPT | \ |
6037 | SDE_PORTC_HOTPLUG_CPT | \ |
5251 | SDE_PORTB_HOTPLUG_CPT) |
6038 | SDE_PORTB_HOTPLUG_CPT) |
- | 6039 | #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ |
|
- | 6040 | SDE_PORTD_HOTPLUG_CPT | \ |
|
- | 6041 | SDE_PORTC_HOTPLUG_CPT | \ |
|
- | 6042 | SDE_PORTB_HOTPLUG_CPT | \ |
|
- | 6043 | SDE_PORTA_HOTPLUG_SPT) |
|
5252 | #define SDE_GMBUS_CPT (1 << 17) |
6044 | #define SDE_GMBUS_CPT (1 << 17) |
5253 | #define SDE_ERROR_CPT (1 << 16) |
6045 | #define SDE_ERROR_CPT (1 << 16) |
5254 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
6046 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
5255 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
6047 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
5256 | #define SDE_FDI_RXC_CPT (1 << 8) |
6048 | #define SDE_FDI_RXC_CPT (1 << 8) |
Line 5278... | Line 6070... | ||
5278 | #define SERR_INT 0xc4040 |
6070 | #define SERR_INT 0xc4040 |
5279 | #define SERR_INT_POISON (1<<31) |
6071 | #define SERR_INT_POISON (1<<31) |
5280 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
6072 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
5281 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) |
6073 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) |
5282 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) |
6074 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) |
5283 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
6075 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) |
Line 5284... | Line 6076... | ||
5284 | 6076 | ||
5285 | /* digital port hotplug */ |
6077 | /* digital port hotplug */ |
- | 6078 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
|
- | 6079 | #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ |
|
- | 6080 | #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ |
|
- | 6081 | #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ |
|
- | 6082 | #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ |
|
5286 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
6083 | #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ |
5287 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
6084 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
5288 | #define PORTD_PULSE_DURATION_2ms (0) |
6085 | #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ |
5289 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) |
6086 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ |
5290 | #define PORTD_PULSE_DURATION_6ms (2 << 18) |
6087 | #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ |
5291 | #define PORTD_PULSE_DURATION_100ms (3 << 18) |
6088 | #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ |
5292 | #define PORTD_PULSE_DURATION_MASK (3 << 18) |
6089 | #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ |
5293 | #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) |
6090 | #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) |
5294 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
6091 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
5295 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
6092 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
5296 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) |
6093 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) |
5297 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
6094 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
5298 | #define PORTC_PULSE_DURATION_2ms (0) |
6095 | #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ |
5299 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) |
6096 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ |
5300 | #define PORTC_PULSE_DURATION_6ms (2 << 10) |
6097 | #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ |
5301 | #define PORTC_PULSE_DURATION_100ms (3 << 10) |
6098 | #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ |
5302 | #define PORTC_PULSE_DURATION_MASK (3 << 10) |
6099 | #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ |
5303 | #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) |
6100 | #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) |
5304 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
6101 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
5305 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
6102 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
5306 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) |
6103 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) |
5307 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
6104 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
5308 | #define PORTB_PULSE_DURATION_2ms (0) |
6105 | #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ |
5309 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) |
6106 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ |
5310 | #define PORTB_PULSE_DURATION_6ms (2 << 2) |
6107 | #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ |
5311 | #define PORTB_PULSE_DURATION_100ms (3 << 2) |
6108 | #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ |
5312 | #define PORTB_PULSE_DURATION_MASK (3 << 2) |
6109 | #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ |
5313 | #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) |
6110 | #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) |
5314 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
6111 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
5315 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
6112 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
Line -... | Line 6113... | ||
- | 6113 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) |
|
- | 6114 | ||
- | 6115 | #define PCH_PORT_HOTPLUG2 0xc403C /* SHOTPLUG_CTL2 SPT+ */ |
|
- | 6116 | #define PORTE_HOTPLUG_ENABLE (1 << 4) |
|
- | 6117 | #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) |
|
- | 6118 | #define PORTE_HOTPLUG_NO_DETECT (0 << 0) |
|
- | 6119 | #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) |
|
5316 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) |
6120 | #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) |
5317 | 6121 | ||
5318 | #define PCH_GPIOA 0xc5010 |
6122 | #define PCH_GPIOA 0xc5010 |
5319 | #define PCH_GPIOB 0xc5014 |
6123 | #define PCH_GPIOB 0xc5014 |
5320 | #define PCH_GPIOC 0xc5018 |
6124 | #define PCH_GPIOC 0xc5018 |
Line 5377... | Line 6181... | ||
5377 | 6181 | ||
5378 | #define PCH_SSC4_PARMS 0xc6210 |
6182 | #define PCH_SSC4_PARMS 0xc6210 |
Line 5379... | Line 6183... | ||
5379 | #define PCH_SSC4_AUX_PARMS 0xc6214 |
6183 | #define PCH_SSC4_AUX_PARMS 0xc6214 |
5380 | 6184 | ||
5381 | #define PCH_DPLL_SEL 0xc7000 |
6185 | #define PCH_DPLL_SEL 0xc7000 |
5382 | #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) |
6186 | #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) |
Line 5383... | Line 6187... | ||
5383 | #define TRANS_DPLLA_SEL(pipe) 0 |
6187 | #define TRANS_DPLLA_SEL(pipe) 0 |
Line 5384... | Line 6188... | ||
5384 | #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) |
6188 | #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) |
5385 | 6189 | ||
Line 5416... | Line 6220... | ||
5416 | 6220 | ||
5417 | /* Per-transcoder DIP controls (PCH) */ |
6221 | /* Per-transcoder DIP controls (PCH) */ |
5418 | #define _VIDEO_DIP_CTL_A 0xe0200 |
6222 | #define _VIDEO_DIP_CTL_A 0xe0200 |
5419 | #define _VIDEO_DIP_DATA_A 0xe0208 |
6223 | #define _VIDEO_DIP_DATA_A 0xe0208 |
- | 6224 | #define _VIDEO_DIP_GCP_A 0xe0210 |
|
- | 6225 | #define GCP_COLOR_INDICATION (1 << 2) |
|
- | 6226 | #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) |
|
Line 5420... | Line 6227... | ||
5420 | #define _VIDEO_DIP_GCP_A 0xe0210 |
6227 | #define GCP_AV_MUTE (1 << 0) |
5421 | 6228 | ||
5422 | #define _VIDEO_DIP_CTL_B 0xe1200 |
6229 | #define _VIDEO_DIP_CTL_B 0xe1200 |
Line 5477... | Line 6284... | ||
5477 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
6284 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
5478 | #define HSW_VIDEO_DIP_GCP_B 0x61210 |
6285 | #define HSW_VIDEO_DIP_GCP_B 0x61210 |
Line 5479... | Line 6286... | ||
5479 | 6286 | ||
5480 | #define HSW_TVIDEO_DIP_CTL(trans) \ |
6287 | #define HSW_TVIDEO_DIP_CTL(trans) \ |
5481 | _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) |
6288 | _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) |
5482 | #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ |
6289 | #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \ |
5483 | _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) |
6290 | (_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4) |
5484 | #define HSW_TVIDEO_DIP_VS_DATA(trans) \ |
6291 | #define HSW_TVIDEO_DIP_VS_DATA(trans, i) \ |
5485 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) |
6292 | (_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4) |
5486 | #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ |
6293 | #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \ |
5487 | _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) |
6294 | (_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4) |
5488 | #define HSW_TVIDEO_DIP_GCP(trans) \ |
6295 | #define HSW_TVIDEO_DIP_GCP(trans) \ |
5489 | _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) |
6296 | _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) |
5490 | #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ |
6297 | #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \ |
Line 5491... | Line 6298... | ||
5491 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) |
6298 | (_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4) |
5492 | 6299 | ||
5493 | #define HSW_STEREO_3D_CTL_A 0x70020 |
6300 | #define HSW_STEREO_3D_CTL_A 0x70020 |
Line 5555... | Line 6362... | ||
5555 | #define TRANS_12BPC (3<<5) |
6362 | #define TRANS_12BPC (3<<5) |
Line 5556... | Line 6363... | ||
5556 | 6363 | ||
5557 | #define _TRANSA_CHICKEN1 0xf0060 |
6364 | #define _TRANSA_CHICKEN1 0xf0060 |
5558 | #define _TRANSB_CHICKEN1 0xf1060 |
6365 | #define _TRANSB_CHICKEN1 0xf1060 |
- | 6366 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
|
5559 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
6367 | #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10) |
5560 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
6368 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
5561 | #define _TRANSA_CHICKEN2 0xf0064 |
6369 | #define _TRANSA_CHICKEN2 0xf0064 |
5562 | #define _TRANSB_CHICKEN2 0xf1064 |
6370 | #define _TRANSB_CHICKEN2 0xf1064 |
5563 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
6371 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
Line 5571... | Line 6379... | ||
5571 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
6379 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
5572 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 |
6380 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 |
5573 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
6381 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
5574 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
6382 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
5575 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
6383 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
- | 6384 | #define SPT_PWM_GRANULARITY (1<<0) |
|
5576 | #define SOUTH_CHICKEN2 0xc2004 |
6385 | #define SOUTH_CHICKEN2 0xc2004 |
5577 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
6386 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
5578 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) |
6387 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) |
- | 6388 | #define LPT_PWM_GRANULARITY (1<<5) |
|
5579 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) |
6389 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) |
Line 5580... | Line 6390... | ||
5580 | 6390 | ||
5581 | #define _FDI_RXA_CHICKEN 0xc200c |
6391 | #define _FDI_RXA_CHICKEN 0xc200c |
5582 | #define _FDI_RXB_CHICKEN 0xc2010 |
6392 | #define _FDI_RXB_CHICKEN 0xc2010 |
Line 5739... | Line 6549... | ||
5739 | 6549 | ||
5740 | #define PCH_PP_STATUS 0xc7200 |
6550 | #define PCH_PP_STATUS 0xc7200 |
5741 | #define PCH_PP_CONTROL 0xc7204 |
6551 | #define PCH_PP_CONTROL 0xc7204 |
5742 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
6552 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
- | 6553 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
|
- | 6554 | #define BXT_POWER_CYCLE_DELAY_MASK (0x1f0) |
|
5743 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
6555 | #define BXT_POWER_CYCLE_DELAY_SHIFT 4 |
5744 | #define EDP_FORCE_VDD (1 << 3) |
6556 | #define EDP_FORCE_VDD (1 << 3) |
5745 | #define EDP_BLC_ENABLE (1 << 2) |
6557 | #define EDP_BLC_ENABLE (1 << 2) |
5746 | #define PANEL_POWER_RESET (1 << 1) |
6558 | #define PANEL_POWER_RESET (1 << 1) |
5747 | #define PANEL_POWER_OFF (0 << 0) |
6559 | #define PANEL_POWER_OFF (0 << 0) |
Line 5767... | Line 6579... | ||
5767 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
6579 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
5768 | #define PP_REFERENCE_DIVIDER_SHIFT 8 |
6580 | #define PP_REFERENCE_DIVIDER_SHIFT 8 |
5769 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) |
6581 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) |
5770 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 |
6582 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 |
Line -... | Line 6583... | ||
- | 6583 | ||
- | 6584 | /* BXT PPS changes - 2nd set of PPS registers */ |
|
- | 6585 | #define _BXT_PP_STATUS2 0xc7300 |
|
- | 6586 | #define _BXT_PP_CONTROL2 0xc7304 |
|
- | 6587 | #define _BXT_PP_ON_DELAYS2 0xc7308 |
|
- | 6588 | #define _BXT_PP_OFF_DELAYS2 0xc730c |
|
- | 6589 | ||
- | 6590 | #define BXT_PP_STATUS(n) _PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2) |
|
- | 6591 | #define BXT_PP_CONTROL(n) _PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2) |
|
- | 6592 | #define BXT_PP_ON_DELAYS(n) _PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2) |
|
- | 6593 | #define BXT_PP_OFF_DELAYS(n) _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2) |
|
5771 | 6594 | ||
5772 | #define PCH_DP_B 0xe4100 |
6595 | #define PCH_DP_B 0xe4100 |
5773 | #define PCH_DPB_AUX_CH_CTL 0xe4110 |
6596 | #define PCH_DPB_AUX_CH_CTL 0xe4110 |
5774 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 |
6597 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 |
5775 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 |
6598 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 |
Line 5812... | Line 6635... | ||
5812 | #define TRANS_DP_PORT_SEL_B (0<<29) |
6635 | #define TRANS_DP_PORT_SEL_B (0<<29) |
5813 | #define TRANS_DP_PORT_SEL_C (1<<29) |
6636 | #define TRANS_DP_PORT_SEL_C (1<<29) |
5814 | #define TRANS_DP_PORT_SEL_D (2<<29) |
6637 | #define TRANS_DP_PORT_SEL_D (2<<29) |
5815 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
6638 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
5816 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
6639 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
- | 6640 | #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) |
|
5817 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
6641 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
5818 | #define TRANS_DP_ENH_FRAMING (1<<18) |
6642 | #define TRANS_DP_ENH_FRAMING (1<<18) |
5819 | #define TRANS_DP_8BPC (0<<9) |
6643 | #define TRANS_DP_8BPC (0<<9) |
5820 | #define TRANS_DP_10BPC (1<<9) |
6644 | #define TRANS_DP_10BPC (1<<9) |
5821 | #define TRANS_DP_6BPC (2<<9) |
6645 | #define TRANS_DP_6BPC (2<<9) |
Line 5902... | Line 6726... | ||
5902 | #define GT_FIFO_IARDERR (1<<0) |
6726 | #define GT_FIFO_IARDERR (1<<0) |
Line 5903... | Line 6727... | ||
5903 | 6727 | ||
5904 | #define GTFIFOCTL 0x120008 |
6728 | #define GTFIFOCTL 0x120008 |
5905 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
6729 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
- | 6730 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
|
- | 6731 | #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) |
|
Line 5906... | Line 6732... | ||
5906 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
6732 | #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) |
5907 | 6733 | ||
5908 | #define HSW_IDICR 0x9008 |
6734 | #define HSW_IDICR 0x9008 |
- | 6735 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
|
Line 5909... | Line 6736... | ||
5909 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
6736 | #define HSW_EDRAM_PRESENT 0x120010 |
5910 | #define HSW_EDRAM_PRESENT 0x120010 |
6737 | #define EDRAM_ENABLED 0x1 |
5911 | 6738 | ||
5912 | #define GEN6_UCGCTL1 0x9400 |
6739 | #define GEN6_UCGCTL1 0x9400 |
Line 5913... | Line 6740... | ||
5913 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
6740 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
- | 6741 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
|
5914 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
6742 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
5915 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
6743 | |
5916 | 6744 | #define GEN6_UCGCTL2 0x9404 |
|
5917 | #define GEN6_UCGCTL2 0x9404 |
6745 | # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) |
5918 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
6746 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
Line 5929... | Line 6757... | ||
5929 | #define GEN6_RCGCTL1 0x9410 |
6757 | #define GEN6_RCGCTL1 0x9410 |
5930 | #define GEN6_RCGCTL2 0x9414 |
6758 | #define GEN6_RCGCTL2 0x9414 |
5931 | #define GEN6_RSTCTL 0x9420 |
6759 | #define GEN6_RSTCTL 0x9420 |
Line 5932... | Line 6760... | ||
5932 | 6760 | ||
- | 6761 | #define GEN8_UCGCTL6 0x9430 |
|
5933 | #define GEN8_UCGCTL6 0x9430 |
6762 | #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) |
- | 6763 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) |
|
Line 5934... | Line 6764... | ||
5934 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) |
6764 | #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) |
5935 | 6765 | ||
5936 | #define GEN6_GFXPAUSE 0xA000 |
6766 | #define GEN6_GFXPAUSE 0xA000 |
5937 | #define GEN6_RPNSWREQ 0xA008 |
6767 | #define GEN6_RPNSWREQ 0xA008 |
5938 | #define GEN6_TURBO_DISABLE (1<<31) |
6768 | #define GEN6_TURBO_DISABLE (1<<31) |
- | 6769 | #define GEN6_FREQUENCY(x) ((x)<<25) |
|
5939 | #define GEN6_FREQUENCY(x) ((x)<<25) |
6770 | #define HSW_FREQUENCY(x) ((x)<<24) |
5940 | #define HSW_FREQUENCY(x) ((x)<<24) |
6771 | #define GEN9_FREQUENCY(x) ((x)<<23) |
5941 | #define GEN6_OFFSET(x) ((x)<<19) |
6772 | #define GEN6_OFFSET(x) ((x)<<19) |
5942 | #define GEN6_AGGRESSIVE_TURBO (0<<15) |
6773 | #define GEN6_AGGRESSIVE_TURBO (0<<15) |
5943 | #define GEN6_RC_VIDEO_FREQ 0xA00C |
6774 | #define GEN6_RC_VIDEO_FREQ 0xA00C |
Line 5954... | Line 6785... | ||
5954 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 |
6785 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 |
5955 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
6786 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
5956 | #define GEN6_RPSTAT1 0xA01C |
6787 | #define GEN6_RPSTAT1 0xA01C |
5957 | #define GEN6_CAGF_SHIFT 8 |
6788 | #define GEN6_CAGF_SHIFT 8 |
5958 | #define HSW_CAGF_SHIFT 7 |
6789 | #define HSW_CAGF_SHIFT 7 |
- | 6790 | #define GEN9_CAGF_SHIFT 23 |
|
5959 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
6791 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
5960 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
6792 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
- | 6793 | #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) |
|
5961 | #define GEN6_RP_CONTROL 0xA024 |
6794 | #define GEN6_RP_CONTROL 0xA024 |
5962 | #define GEN6_RP_MEDIA_TURBO (1<<11) |
6795 | #define GEN6_RP_MEDIA_TURBO (1<<11) |
5963 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
6796 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
5964 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) |
6797 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) |
5965 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) |
6798 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) |
Line 6003... | Line 6836... | ||
6003 | #define VLV_RCEDATA 0xA0BC |
6836 | #define VLV_RCEDATA 0xA0BC |
6004 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 |
6837 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 |
6005 | #define GEN6_PMINTRMSK 0xA168 |
6838 | #define GEN6_PMINTRMSK 0xA168 |
6006 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
6839 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
6007 | #define VLV_PWRDWNUPCTL 0xA294 |
6840 | #define VLV_PWRDWNUPCTL 0xA294 |
- | 6841 | #define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4 |
|
- | 6842 | #define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8 |
|
- | 6843 | #define GEN9_PG_ENABLE 0xA210 |
|
- | 6844 | #define GEN9_RENDER_PG_ENABLE (1<<0) |
|
- | 6845 | #define GEN9_MEDIA_PG_ENABLE (1<<1) |
|
- | 6846 | ||
- | 6847 | #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C) |
|
- | 6848 | #define PIXEL_OVERLAP_CNT_MASK (3 << 30) |
|
- | 6849 | #define PIXEL_OVERLAP_CNT_SHIFT 30 |
|
Line 6008... | Line 6850... | ||
6008 | 6850 | ||
6009 | #define GEN6_PMISR 0x44020 |
6851 | #define GEN6_PMISR 0x44020 |
6010 | #define GEN6_PMIMR 0x44024 /* rps_lock */ |
6852 | #define GEN6_PMIMR 0x44024 /* rps_lock */ |
6011 | #define GEN6_PMIIR 0x44028 |
6853 | #define GEN6_PMIIR 0x44028 |
Line 6019... | Line 6861... | ||
6019 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
6861 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
6020 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
6862 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
6021 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
6863 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
6022 | GEN6_PM_RP_DOWN_TIMEOUT) |
6864 | GEN6_PM_RP_DOWN_TIMEOUT) |
Line 6023... | Line 6865... | ||
6023 | 6865 | ||
6024 | #define GEN7_GT_SCRATCH_BASE 0x4F100 |
6866 | #define GEN7_GT_SCRATCH(i) (0x4F100 + (i) * 4) |
Line 6025... | Line 6867... | ||
6025 | #define GEN7_GT_SCRATCH_REG_NUM 8 |
6867 | #define GEN7_GT_SCRATCH_REG_NUM 8 |
6026 | 6868 | ||
6027 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
6869 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
Line 6039... | Line 6881... | ||
6039 | #define VLV_GT_RENDER_RC6 0x138108 |
6881 | #define VLV_GT_RENDER_RC6 0x138108 |
6040 | #define VLV_GT_MEDIA_RC6 0x13810C |
6882 | #define VLV_GT_MEDIA_RC6 0x13810C |
Line 6041... | Line 6883... | ||
6041 | 6883 | ||
6042 | #define GEN6_GT_GFX_RC6p 0x13810C |
6884 | #define GEN6_GT_GFX_RC6p 0x13810C |
6043 | #define GEN6_GT_GFX_RC6pp 0x138110 |
6885 | #define GEN6_GT_GFX_RC6pp 0x138110 |
6044 | #define VLV_RENDER_C0_COUNT_REG 0x138118 |
6886 | #define VLV_RENDER_C0_COUNT 0x138118 |
Line 6045... | Line 6887... | ||
6045 | #define VLV_MEDIA_C0_COUNT_REG 0x13811C |
6887 | #define VLV_MEDIA_C0_COUNT 0x13811C |
6046 | 6888 | ||
6047 | #define GEN6_PCODE_MAILBOX 0x138124 |
- | |
6048 | #define GEN6_PCODE_READY (1<<31) |
- | |
6049 | #define GEN6_READ_OC_PARAMS 0xc |
- | |
6050 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
6889 | #define GEN6_PCODE_MAILBOX 0x138124 |
6051 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
6890 | #define GEN6_PCODE_READY (1<<31) |
6052 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
- | |
6053 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
- | |
6054 | #define GEN6_PCODE_READ_D_COMP 0x10 |
6891 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
6055 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
6892 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
- | 6893 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
|
- | 6894 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
|
- | 6895 | #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 |
|
- | 6896 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
|
- | 6897 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF |
|
- | 6898 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 |
|
- | 6899 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 |
|
- | 6900 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 |
|
- | 6901 | #define SKL_PCODE_CDCLK_CONTROL 0x7 |
|
- | 6902 | #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 |
|
- | 6903 | #define SKL_CDCLK_READY_FOR_CHANGE 0x1 |
|
- | 6904 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
|
- | 6905 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
|
- | 6906 | #define GEN6_READ_OC_PARAMS 0xc |
|
- | 6907 | #define GEN6_PCODE_READ_D_COMP 0x10 |
|
6056 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
6908 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
6057 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
6909 | #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 |
6058 | #define DISPLAY_IPS_CONTROL 0x19 |
6910 | #define DISPLAY_IPS_CONTROL 0x19 |
6059 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
6911 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
6060 | #define GEN6_PCODE_DATA 0x138128 |
6912 | #define GEN6_PCODE_DATA 0x138128 |
6061 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
6913 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
Line 6062... | Line -... | ||
6062 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
- | |
6063 | #define GEN6_PCODE_DATA1 0x13812C |
- | |
6064 | - | ||
6065 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
- | |
6066 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF |
- | |
6067 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 |
- | |
6068 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 |
6914 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
6069 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 |
6915 | #define GEN6_PCODE_DATA1 0x13812C |
6070 | 6916 | ||
6071 | #define GEN6_GT_CORE_STATUS 0x138060 |
6917 | #define GEN6_GT_CORE_STATUS 0x138060 |
6072 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) |
6918 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) |
6073 | #define GEN6_RCn_MASK 7 |
6919 | #define GEN6_RCn_MASK 7 |
6074 | #define GEN6_RC0 0 |
6920 | #define GEN6_RC0 0 |
Line -... | Line 6921... | ||
- | 6921 | #define GEN6_RC3 2 |
|
- | 6922 | #define GEN6_RC6 3 |
|
- | 6923 | #define GEN6_RC7 4 |
|
- | 6924 | ||
- | 6925 | #define GEN8_GT_SLICE_INFO 0x138064 |
|
- | 6926 | #define GEN8_LSLICESTAT_MASK 0x7 |
|
- | 6927 | ||
- | 6928 | #define CHV_POWER_SS0_SIG1 0xa720 |
|
- | 6929 | #define CHV_POWER_SS1_SIG1 0xa728 |
|
- | 6930 | #define CHV_SS_PG_ENABLE (1<<1) |
|
- | 6931 | #define CHV_EU08_PG_ENABLE (1<<9) |
|
- | 6932 | #define CHV_EU19_PG_ENABLE (1<<17) |
|
- | 6933 | #define CHV_EU210_PG_ENABLE (1<<25) |
|
- | 6934 | ||
- | 6935 | #define CHV_POWER_SS0_SIG2 0xa724 |
|
- | 6936 | #define CHV_POWER_SS1_SIG2 0xa72c |
|
- | 6937 | #define CHV_EU311_PG_ENABLE (1<<1) |
|
- | 6938 | ||
- | 6939 | #define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4) |
|
- | 6940 | #define GEN9_PGCTL_SLICE_ACK (1 << 0) |
|
- | 6941 | #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) |
|
- | 6942 | ||
- | 6943 | #define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8) |
|
- | 6944 | #define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8) |
|
- | 6945 | #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) |
|
- | 6946 | #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) |
|
- | 6947 | #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) |
|
- | 6948 | #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) |
|
- | 6949 | #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) |
|
6075 | #define GEN6_RC3 2 |
6950 | #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) |
6076 | #define GEN6_RC6 3 |
6951 | #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) |
- | 6952 | #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) |
|
- | 6953 | ||
- | 6954 | #define GEN7_MISCCPCTL (0x9424) |
|
- | 6955 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
|
- | 6956 | #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2) |
|
- | 6957 | #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) |
|
Line 6077... | Line 6958... | ||
6077 | #define GEN6_RC7 4 |
6958 | #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) |
6078 | 6959 | ||
6079 | #define GEN7_MISCCPCTL (0x9424) |
6960 | #define GEN8_GARBCNTL 0xB004 |
6080 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
6961 | #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) |
Line 6100... | Line 6981... | ||
6100 | 6981 | ||
6101 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
6982 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
6102 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
6983 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
6103 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
6984 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
- | 6985 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
|
6104 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
6986 | #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) |
Line 6105... | Line 6987... | ||
6105 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
6987 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
6106 | 6988 | ||
- | 6989 | #define GEN9_HALF_SLICE_CHICKEN5 0xe188 |
|
Line 6107... | Line 6990... | ||
6107 | #define GEN9_HALF_SLICE_CHICKEN5 0xe188 |
6990 | #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) |
6108 | #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) |
6991 | #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) |
6109 | 6992 | ||
Line 6116... | Line 6999... | ||
6116 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
6999 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
Line 6117... | Line 7000... | ||
6117 | 7000 | ||
6118 | #define HSW_ROW_CHICKEN3 0xe49c |
7001 | #define HSW_ROW_CHICKEN3 0xe49c |
Line -... | Line 7002... | ||
- | 7002 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
|
- | 7003 | ||
- | 7004 | #define HALF_SLICE_CHICKEN2 0xe180 |
|
6119 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
7005 | #define GEN8_ST_PO_DISABLE (1<<13) |
- | 7006 | ||
6120 | 7007 | #define HALF_SLICE_CHICKEN3 0xe184 |
|
- | 7008 | #define HSW_SAMPLE_C_PERFORMANCE (1<<9) |
|
6121 | #define HALF_SLICE_CHICKEN3 0xe184 |
7009 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
Line -... | Line 7010... | ||
- | 7010 | #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) |
|
- | 7011 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
|
- | 7012 | ||
6122 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
7013 | #define GEN9_HALF_SLICE_CHICKEN7 0xe194 |
6123 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
7014 | #define GEN9_ENABLE_YV12_BUGFIX (1<<4) |
6124 | 7015 | ||
6125 | /* Audio */ |
7016 | /* Audio */ |
6126 | #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
7017 | #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
Line 6256... | Line 7147... | ||
6256 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
7147 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
6257 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) |
7148 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) |
6258 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) |
7149 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) |
6259 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) |
7150 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) |
Line -... | Line 7151... | ||
- | 7151 | ||
- | 7152 | #define HSW_AUD_CHICKENBIT 0x65f10 |
|
- | 7153 | #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) |
|
6260 | 7154 | ||
6261 | /* HSW Power Wells */ |
7155 | /* HSW Power Wells */ |
6262 | #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ |
7156 | #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ |
6263 | #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ |
7157 | #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ |
6264 | #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ |
7158 | #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ |
Line 6269... | Line 7163... | ||
6269 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
7163 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
6270 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
7164 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
6271 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
7165 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
6272 | #define HSW_PWR_WELL_CTL6 0x45414 |
7166 | #define HSW_PWR_WELL_CTL6 0x45414 |
Line -... | Line 7167... | ||
- | 7167 | ||
- | 7168 | /* SKL Fuse Status */ |
|
- | 7169 | #define SKL_FUSE_STATUS 0x42000 |
|
- | 7170 | #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) |
|
- | 7171 | #define SKL_FUSE_PG0_DIST_STATUS (1<<27) |
|
- | 7172 | #define SKL_FUSE_PG1_DIST_STATUS (1<<26) |
|
- | 7173 | #define SKL_FUSE_PG2_DIST_STATUS (1<<25) |
|
6273 | 7174 | ||
6274 | /* Per-pipe DDI Function Control */ |
7175 | /* Per-pipe DDI Function Control */ |
6275 | #define TRANS_DDI_FUNC_CTL_A 0x60400 |
7176 | #define TRANS_DDI_FUNC_CTL_A 0x60400 |
6276 | #define TRANS_DDI_FUNC_CTL_B 0x61400 |
7177 | #define TRANS_DDI_FUNC_CTL_B 0x61400 |
6277 | #define TRANS_DDI_FUNC_CTL_C 0x62400 |
7178 | #define TRANS_DDI_FUNC_CTL_C 0x62400 |
Line 6344... | Line 7245... | ||
6344 | #define DDI_BUF_EMP_MASK (0xf<<24) |
7245 | #define DDI_BUF_EMP_MASK (0xf<<24) |
6345 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
7246 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
6346 | #define DDI_BUF_IS_IDLE (1<<7) |
7247 | #define DDI_BUF_IS_IDLE (1<<7) |
6347 | #define DDI_A_4_LANES (1<<4) |
7248 | #define DDI_A_4_LANES (1<<4) |
6348 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
7249 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
- | 7250 | #define DDI_PORT_WIDTH_MASK (7 << 1) |
|
- | 7251 | #define DDI_PORT_WIDTH_SHIFT 1 |
|
6349 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
7252 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
Line 6350... | Line 7253... | ||
6350 | 7253 | ||
6351 | /* DDI Buffer Translations */ |
7254 | /* DDI Buffer Translations */ |
6352 | #define DDI_BUF_TRANS_A 0x64E00 |
7255 | #define DDI_BUF_TRANS_A 0x64E00 |
6353 | #define DDI_BUF_TRANS_B 0x64E60 |
7256 | #define DDI_BUF_TRANS_B 0x64E60 |
- | 7257 | #define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8) |
|
Line 6354... | Line 7258... | ||
6354 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
7258 | #define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) + (i) * 8 + 4) |
6355 | 7259 | ||
6356 | /* Sideband Interface (SBI) is programmed indirectly, via |
7260 | /* Sideband Interface (SBI) is programmed indirectly, via |
6357 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
7261 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
Line 6442... | Line 7346... | ||
6442 | #define TRANS_CLK_SEL_A 0x46140 |
7346 | #define TRANS_CLK_SEL_A 0x46140 |
6443 | #define TRANS_CLK_SEL_B 0x46144 |
7347 | #define TRANS_CLK_SEL_B 0x46144 |
6444 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
7348 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
6445 | /* For each transcoder, we need to select the corresponding port clock */ |
7349 | /* For each transcoder, we need to select the corresponding port clock */ |
6446 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
7350 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
6447 | #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) |
7351 | #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) |
Line 6448... | Line 7352... | ||
6448 | 7352 | ||
6449 | #define TRANSA_MSA_MISC 0x60410 |
7353 | #define TRANSA_MSA_MISC 0x60410 |
6450 | #define TRANSB_MSA_MISC 0x61410 |
7354 | #define TRANSB_MSA_MISC 0x61410 |
6451 | #define TRANSC_MSA_MISC 0x62410 |
7355 | #define TRANSC_MSA_MISC 0x62410 |
Line 6467... | Line 7371... | ||
6467 | #define LCPLL_CLK_FREQ_450 (0<<26) |
7371 | #define LCPLL_CLK_FREQ_450 (0<<26) |
6468 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
7372 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
6469 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) |
7373 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) |
6470 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) |
7374 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) |
6471 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
7375 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
- | 7376 | #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24) |
|
6472 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
7377 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
6473 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
7378 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
6474 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
7379 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
6475 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
7380 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
Line 6485... | Line 7390... | ||
6485 | #define CDCLK_FREQ_540 (1<<26) |
7390 | #define CDCLK_FREQ_540 (1<<26) |
6486 | #define CDCLK_FREQ_337_308 (2<<26) |
7391 | #define CDCLK_FREQ_337_308 (2<<26) |
6487 | #define CDCLK_FREQ_675_617 (3<<26) |
7392 | #define CDCLK_FREQ_675_617 (3<<26) |
6488 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
7393 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
Line -... | Line 7394... | ||
- | 7394 | ||
- | 7395 | #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) |
|
- | 7396 | #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) |
|
- | 7397 | #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) |
|
- | 7398 | #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) |
|
- | 7399 | #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) |
|
- | 7400 | #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) |
|
6489 | 7401 | ||
6490 | /* LCPLL_CTL */ |
7402 | /* LCPLL_CTL */ |
6491 | #define LCPLL1_CTL 0x46010 |
7403 | #define LCPLL1_CTL 0x46010 |
6492 | #define LCPLL2_CTL 0x46014 |
7404 | #define LCPLL2_CTL 0x46014 |
Line 6493... | Line 7405... | ||
6493 | #define LCPLL_PLL_ENABLE (1<<31) |
7405 | #define LCPLL_PLL_ENABLE (1<<31) |
6494 | 7406 | ||
6495 | /* DPLL control1 */ |
7407 | /* DPLL control1 */ |
6496 | #define DPLL_CTRL1 0x6C058 |
7408 | #define DPLL_CTRL1 0x6C058 |
6497 | #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) |
7409 | #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) |
6498 | #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) |
7410 | #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) |
6499 | #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) |
7411 | #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) |
6500 | #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) |
7412 | #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) |
6501 | #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) |
7413 | #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) |
6502 | #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) |
7414 | #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) |
6503 | #define DPLL_CRTL1_LINK_RATE_2700 0 |
7415 | #define DPLL_CTRL1_LINK_RATE_2700 0 |
6504 | #define DPLL_CRTL1_LINK_RATE_1350 1 |
7416 | #define DPLL_CTRL1_LINK_RATE_1350 1 |
6505 | #define DPLL_CRTL1_LINK_RATE_810 2 |
7417 | #define DPLL_CTRL1_LINK_RATE_810 2 |
6506 | #define DPLL_CRTL1_LINK_RATE_1620 3 |
7418 | #define DPLL_CTRL1_LINK_RATE_1620 3 |
Line 6507... | Line 7419... | ||
6507 | #define DPLL_CRTL1_LINK_RATE_1080 4 |
7419 | #define DPLL_CTRL1_LINK_RATE_1080 4 |
6508 | #define DPLL_CRTL1_LINK_RATE_2160 5 |
7420 | #define DPLL_CTRL1_LINK_RATE_2160 5 |
6509 | 7421 | ||
6510 | /* DPLL control2 */ |
7422 | /* DPLL control2 */ |
6511 | #define DPLL_CTRL2 0x6C05C |
7423 | #define DPLL_CTRL2 0x6C05C |
6512 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) |
7424 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15)) |
6513 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) |
7425 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) |
Line 6514... | Line 7426... | ||
6514 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) |
7426 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) |
6515 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) |
7427 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1)) |
6516 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) |
7428 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) |
Line 6523... | Line 7435... | ||
6523 | #define DPLL1_CFGCR1 0x6C040 |
7435 | #define DPLL1_CFGCR1 0x6C040 |
6524 | #define DPLL2_CFGCR1 0x6C048 |
7436 | #define DPLL2_CFGCR1 0x6C048 |
6525 | #define DPLL3_CFGCR1 0x6C050 |
7437 | #define DPLL3_CFGCR1 0x6C050 |
6526 | #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) |
7438 | #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) |
6527 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) |
7439 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) |
6528 | #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) |
7440 | #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9) |
6529 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
7441 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
Line 6530... | Line 7442... | ||
6530 | 7442 | ||
6531 | #define DPLL1_CFGCR2 0x6C044 |
7443 | #define DPLL1_CFGCR2 0x6C044 |
6532 | #define DPLL2_CFGCR2 0x6C04C |
7444 | #define DPLL2_CFGCR2 0x6C04C |
6533 | #define DPLL3_CFGCR2 0x6C054 |
7445 | #define DPLL3_CFGCR2 0x6C054 |
6534 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) |
7446 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) |
6535 | #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) |
7447 | #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8) |
6536 | #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) |
7448 | #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7) |
6537 | #define DPLL_CFGCR2_KDIV_MASK (3<<5) |
7449 | #define DPLL_CFGCR2_KDIV_MASK (3<<5) |
6538 | #define DPLL_CFGCR2_KDIV(x) (x<<5) |
7450 | #define DPLL_CFGCR2_KDIV(x) ((x)<<5) |
6539 | #define DPLL_CFGCR2_KDIV_5 (0<<5) |
7451 | #define DPLL_CFGCR2_KDIV_5 (0<<5) |
6540 | #define DPLL_CFGCR2_KDIV_2 (1<<5) |
7452 | #define DPLL_CFGCR2_KDIV_2 (1<<5) |
6541 | #define DPLL_CFGCR2_KDIV_3 (2<<5) |
7453 | #define DPLL_CFGCR2_KDIV_3 (2<<5) |
6542 | #define DPLL_CFGCR2_KDIV_1 (3<<5) |
7454 | #define DPLL_CFGCR2_KDIV_1 (3<<5) |
6543 | #define DPLL_CFGCR2_PDIV_MASK (7<<2) |
7455 | #define DPLL_CFGCR2_PDIV_MASK (7<<2) |
6544 | #define DPLL_CFGCR2_PDIV(x) (x<<2) |
7456 | #define DPLL_CFGCR2_PDIV(x) ((x)<<2) |
6545 | #define DPLL_CFGCR2_PDIV_1 (0<<2) |
7457 | #define DPLL_CFGCR2_PDIV_1 (0<<2) |
6546 | #define DPLL_CFGCR2_PDIV_2 (1<<2) |
7458 | #define DPLL_CFGCR2_PDIV_2 (1<<2) |
6547 | #define DPLL_CFGCR2_PDIV_3 (2<<2) |
7459 | #define DPLL_CFGCR2_PDIV_3 (2<<2) |
6548 | #define DPLL_CFGCR2_PDIV_7 (4<<2) |
7460 | #define DPLL_CFGCR2_PDIV_7 (4<<2) |
Line 6549... | Line 7461... | ||
6549 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
7461 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
6550 | 7462 | ||
- | 7463 | #define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8) |
|
- | 7464 | #define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8) |
|
- | 7465 | ||
- | 7466 | /* BXT display engine PLL */ |
|
- | 7467 | #define BXT_DE_PLL_CTL 0x6d000 |
|
- | 7468 | #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ |
|
- | 7469 | #define BXT_DE_PLL_RATIO_MASK 0xff |
|
- | 7470 | ||
- | 7471 | #define BXT_DE_PLL_ENABLE 0x46070 |
|
- | 7472 | #define BXT_DE_PLL_PLL_ENABLE (1 << 31) |
|
- | 7473 | #define BXT_DE_PLL_LOCK (1 << 30) |
|
- | 7474 | ||
- | 7475 | /* GEN9 DC */ |
|
- | 7476 | #define DC_STATE_EN 0x45504 |
|
- | 7477 | #define DC_STATE_EN_UPTO_DC5 (1<<0) |
|
- | 7478 | #define DC_STATE_EN_DC9 (1<<3) |
|
- | 7479 | #define DC_STATE_EN_UPTO_DC6 (2<<0) |
|
- | 7480 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
|
- | 7481 | ||
Line 6551... | Line 7482... | ||
6551 | #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) |
7482 | #define DC_STATE_DEBUG 0x45520 |
6552 | #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) |
7483 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) |
6553 | 7484 | ||
6554 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
7485 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
Line 6629... | Line 7560... | ||
6629 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) |
7560 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) |
6630 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) |
7561 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) |
6631 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) |
7562 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) |
6632 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) |
7563 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) |
Line 6633... | Line 7564... | ||
6633 | 7564 | ||
- | 7565 | /* MIPI DSI registers */ |
|
- | 7566 | ||
- | 7567 | #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ |
|
- | 7568 | ||
- | 7569 | /* BXT MIPI clock controls */ |
|
- | 7570 | #define BXT_MAX_VAR_OUTPUT_KHZ 39500 |
|
- | 7571 | ||
- | 7572 | #define BXT_MIPI_CLOCK_CTL 0x46090 |
|
- | 7573 | #define BXT_MIPI1_DIV_SHIFT 26 |
|
- | 7574 | #define BXT_MIPI2_DIV_SHIFT 10 |
|
- | 7575 | #define BXT_MIPI_DIV_SHIFT(port) \ |
|
- | 7576 | _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ |
|
- | 7577 | BXT_MIPI2_DIV_SHIFT) |
|
- | 7578 | /* Var clock divider to generate TX source. Result must be < 39.5 M */ |
|
- | 7579 | #define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26) |
|
- | 7580 | #define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10) |
|
- | 7581 | #define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \ |
|
- | 7582 | _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \ |
|
- | 7583 | BXT_MIPI2_ESCLK_VAR_DIV_MASK) |
|
- | 7584 | ||
- | 7585 | #define BXT_MIPI_ESCLK_VAR_DIV(port, val) \ |
|
- | 7586 | (val << BXT_MIPI_DIV_SHIFT(port)) |
|
- | 7587 | /* TX control divider to select actual TX clock output from (8x/var) */ |
|
- | 7588 | #define BXT_MIPI1_TX_ESCLK_SHIFT 21 |
|
- | 7589 | #define BXT_MIPI2_TX_ESCLK_SHIFT 5 |
|
- | 7590 | #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ |
|
- | 7591 | _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ |
|
- | 7592 | BXT_MIPI2_TX_ESCLK_SHIFT) |
|
- | 7593 | #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21) |
|
- | 7594 | #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5) |
|
- | 7595 | #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ |
|
- | 7596 | _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ |
|
- | 7597 | BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) |
|
- | 7598 | #define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \ |
|
- | 7599 | (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port)) |
|
- | 7600 | #define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \ |
|
- | 7601 | (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port)) |
|
- | 7602 | #define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \ |
|
- | 7603 | (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port)) |
|
- | 7604 | /* RX control divider to select actual RX clock output from 8x*/ |
|
- | 7605 | #define BXT_MIPI1_RX_ESCLK_SHIFT 19 |
|
- | 7606 | #define BXT_MIPI2_RX_ESCLK_SHIFT 3 |
|
- | 7607 | #define BXT_MIPI_RX_ESCLK_SHIFT(port) \ |
|
- | 7608 | _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \ |
|
- | 7609 | BXT_MIPI2_RX_ESCLK_SHIFT) |
|
- | 7610 | #define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19) |
|
- | 7611 | #define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3) |
|
- | 7612 | #define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \ |
|
- | 7613 | (3 << BXT_MIPI_RX_ESCLK_SHIFT(port)) |
|
- | 7614 | #define BXT_MIPI_RX_ESCLK_8X_BY2(port) \ |
|
- | 7615 | (1 << BXT_MIPI_RX_ESCLK_SHIFT(port)) |
|
- | 7616 | #define BXT_MIPI_RX_ESCLK_8X_BY3(port) \ |
|
- | 7617 | (2 << BXT_MIPI_RX_ESCLK_SHIFT(port)) |
|
- | 7618 | #define BXT_MIPI_RX_ESCLK_8X_BY4(port) \ |
|
- | 7619 | (3 << BXT_MIPI_RX_ESCLK_SHIFT(port)) |
|
- | 7620 | /* BXT-A WA: Always prog DPHY dividers to 00 */ |
|
- | 7621 | #define BXT_MIPI1_DPHY_DIV_SHIFT 16 |
|
- | 7622 | #define BXT_MIPI2_DPHY_DIV_SHIFT 0 |
|
- | 7623 | #define BXT_MIPI_DPHY_DIV_SHIFT(port) \ |
|
- | 7624 | _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \ |
|
- | 7625 | BXT_MIPI2_DPHY_DIV_SHIFT) |
|
- | 7626 | #define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16) |
|
- | 7627 | #define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0) |
|
- | 7628 | #define BXT_MIPI_DPHY_DIVIDER_MASK(port) \ |
|
- | 7629 | (3 << BXT_MIPI_DPHY_DIV_SHIFT(port)) |
|
- | 7630 | ||
- | 7631 | /* BXT MIPI mode configure */ |
|
- | 7632 | #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 |
|
- | 7633 | #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 |
|
- | 7634 | #define BXT_MIPI_TRANS_HACTIVE(tc) _MIPI_PORT(tc, \ |
|
- | 7635 | _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) |
|
- | 7636 | ||
- | 7637 | #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC |
|
- | 7638 | #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC |
|
- | 7639 | #define BXT_MIPI_TRANS_VACTIVE(tc) _MIPI_PORT(tc, \ |
|
- | 7640 | _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) |
|
- | 7641 | ||
- | 7642 | #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 |
|
- | 7643 | #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 |
|
- | 7644 | #define BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \ |
|
- | 7645 | _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) |
|
- | 7646 | ||
- | 7647 | #define BXT_DSI_PLL_CTL 0x161000 |
|
- | 7648 | #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 |
|
- | 7649 | #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) |
|
- | 7650 | #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) |
|
- | 7651 | #define BXT_DSIC_16X_BY2 (1 << 10) |
|
- | 7652 | #define BXT_DSIC_16X_BY3 (2 << 10) |
|
- | 7653 | #define BXT_DSIC_16X_BY4 (3 << 10) |
|
- | 7654 | #define BXT_DSIA_16X_BY2 (1 << 8) |
|
- | 7655 | #define BXT_DSIA_16X_BY3 (2 << 8) |
|
- | 7656 | #define BXT_DSIA_16X_BY4 (3 << 8) |
|
- | 7657 | #define BXT_DSI_FREQ_SEL_SHIFT 8 |
|
- | 7658 | #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) |
|
- | 7659 | ||
- | 7660 | #define BXT_DSI_PLL_RATIO_MAX 0x7D |
|
- | 7661 | #define BXT_DSI_PLL_RATIO_MIN 0x22 |
|
- | 7662 | #define BXT_DSI_PLL_RATIO_MASK 0xFF |
|
- | 7663 | #define BXT_REF_CLOCK_KHZ 19500 |
|
- | 7664 | ||
- | 7665 | #define BXT_DSI_PLL_ENABLE 0x46080 |
|
- | 7666 | #define BXT_DSI_PLL_DO_ENABLE (1 << 31) |
|
Line 6634... | Line 7667... | ||
6634 | /* VLV MIPI registers */ |
7667 | #define BXT_DSI_PLL_LOCKED (1 << 30) |
6635 | 7668 | ||
- | 7669 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
|
- | 7670 | #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
|
- | 7671 | #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) |
|
- | 7672 | ||
- | 7673 | /* BXT port control */ |
|
6636 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
7674 | #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 |
6637 | #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
7675 | #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 |
- | 7676 | #define BXT_MIPI_PORT_CTRL(tc) _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \ |
|
6638 | #define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ |
7677 | _BXT_MIPIC_PORT_CTRL) |
6639 | _MIPIB_PORT_CTRL) |
7678 | |
6640 | #define DPI_ENABLE (1 << 31) /* A + B */ |
7679 | #define DPI_ENABLE (1 << 31) /* A + C */ |
- | 7680 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
|
6641 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
7681 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
6642 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
7682 | #define DUAL_LINK_MODE_SHIFT 26 |
6643 | #define DUAL_LINK_MODE_MASK (1 << 26) |
7683 | #define DUAL_LINK_MODE_MASK (1 << 26) |
6644 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) |
7684 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) |
6645 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) |
7685 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) |
6646 | #define DITHERING_ENABLE (1 << 25) /* A + B */ |
7686 | #define DITHERING_ENABLE (1 << 25) /* A + C */ |
6647 | #define FLOPPED_HSTX (1 << 23) |
7687 | #define FLOPPED_HSTX (1 << 23) |
6648 | #define DE_INVERT (1 << 19) /* XXX */ |
7688 | #define DE_INVERT (1 << 19) /* XXX */ |
6649 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 |
7689 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 |
6650 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) |
7690 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) |
6651 | #define AFE_LATCHOUT (1 << 17) |
7691 | #define AFE_LATCHOUT (1 << 17) |
6652 | #define LP_OUTPUT_HOLD (1 << 16) |
7692 | #define LP_OUTPUT_HOLD (1 << 16) |
6653 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
7693 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
6654 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) |
7694 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) |
6655 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 |
7695 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 |
6656 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) |
7696 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) |
6657 | #define CSB_SHIFT 9 |
7697 | #define CSB_SHIFT 9 |
6658 | #define CSB_MASK (3 << 9) |
7698 | #define CSB_MASK (3 << 9) |
6659 | #define CSB_20MHZ (0 << 9) |
7699 | #define CSB_20MHZ (0 << 9) |
6660 | #define CSB_10MHZ (1 << 9) |
7700 | #define CSB_10MHZ (1 << 9) |
6661 | #define CSB_40MHZ (2 << 9) |
7701 | #define CSB_40MHZ (2 << 9) |
6662 | #define BANDGAP_MASK (1 << 8) |
7702 | #define BANDGAP_MASK (1 << 8) |
6663 | #define BANDGAP_PNW_CIRCUIT (0 << 8) |
7703 | #define BANDGAP_PNW_CIRCUIT (0 << 8) |
6664 | #define BANDGAP_LNC_CIRCUIT (1 << 8) |
7704 | #define BANDGAP_LNC_CIRCUIT (1 << 8) |
6665 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
7705 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
6666 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) |
7706 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) |
6667 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ |
7707 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ |
6668 | #define TEARING_EFFECT_SHIFT 2 /* A + B */ |
7708 | #define TEARING_EFFECT_SHIFT 2 /* A + C */ |
6669 | #define TEARING_EFFECT_MASK (3 << 2) |
7709 | #define TEARING_EFFECT_MASK (3 << 2) |
6670 | #define TEARING_EFFECT_OFF (0 << 2) |
7710 | #define TEARING_EFFECT_OFF (0 << 2) |
6671 | #define TEARING_EFFECT_DSI (1 << 2) |
7711 | #define TEARING_EFFECT_DSI (1 << 2) |
Line 6675... | Line 7715... | ||
6675 | #define LANE_CONFIGURATION_4LANE (0 << 0) |
7715 | #define LANE_CONFIGURATION_4LANE (0 << 0) |
6676 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) |
7716 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) |
6677 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) |
7717 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) |
Line 6678... | Line 7718... | ||
6678 | 7718 | ||
6679 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
7719 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
6680 | #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
7720 | #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
6681 | #define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ |
7721 | #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ |
6682 | _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) |
7722 | _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) |
6683 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
7723 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
Line 6684... | Line 7724... | ||
6684 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
7724 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
6685 | 7725 | ||
Line 6686... | Line 7726... | ||
6686 | /* XXX: all bits reserved */ |
7726 | /* XXX: all bits reserved */ |
Line 6687... | Line 7727... | ||
6687 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
7727 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
6688 | 7728 | ||
6689 | /* MIPI DSI Controller and D-PHY registers */ |
7729 | /* MIPI DSI Controller and D-PHY registers */ |
6690 | 7730 | ||
6691 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
7731 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
6692 | #define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
7732 | #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
6693 | #define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ |
7733 | #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ |
6694 | _MIPIB_DEVICE_READY) |
7734 | _MIPIC_DEVICE_READY) |
6695 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
7735 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
6696 | #define ULPS_STATE_MASK (3 << 1) |
7736 | #define ULPS_STATE_MASK (3 << 1) |
Line 6697... | Line 7737... | ||
6697 | #define ULPS_STATE_ENTER (2 << 1) |
7737 | #define ULPS_STATE_ENTER (2 << 1) |
6698 | #define ULPS_STATE_EXIT (1 << 1) |
7738 | #define ULPS_STATE_EXIT (1 << 1) |
6699 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
7739 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
6700 | #define DEVICE_READY (1 << 0) |
7740 | #define DEVICE_READY (1 << 0) |
6701 | 7741 | ||
6702 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
7742 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
6703 | #define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
7743 | #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
6704 | #define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ |
7744 | #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ |
6705 | _MIPIB_INTR_STAT) |
7745 | _MIPIC_INTR_STAT) |
6706 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
7746 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
6707 | #define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
7747 | #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
6708 | #define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ |
7748 | #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ |
6709 | _MIPIB_INTR_EN) |
7749 | _MIPIC_INTR_EN) |
Line 6739... | Line 7779... | ||
6739 | #define RXEOT_SYNC_ERROR (1 << 2) |
7779 | #define RXEOT_SYNC_ERROR (1 << 2) |
6740 | #define RXSOT_SYNC_ERROR (1 << 1) |
7780 | #define RXSOT_SYNC_ERROR (1 << 1) |
6741 | #define RXSOT_ERROR (1 << 0) |
7781 | #define RXSOT_ERROR (1 << 0) |
Line 6742... | Line 7782... | ||
6742 | 7782 | ||
6743 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
7783 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
6744 | #define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
7784 | #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
6745 | #define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ |
7785 | #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ |
6746 | _MIPIB_DSI_FUNC_PRG) |
7786 | _MIPIC_DSI_FUNC_PRG) |
6747 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
7787 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
6748 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) |
7788 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) |
6749 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
7789 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
6750 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) |
7790 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) |
Line 6763... | Line 7803... | ||
6763 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) |
7803 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) |
6764 | #define DATA_LANES_PRG_REG_SHIFT 0 |
7804 | #define DATA_LANES_PRG_REG_SHIFT 0 |
6765 | #define DATA_LANES_PRG_REG_MASK (7 << 0) |
7805 | #define DATA_LANES_PRG_REG_MASK (7 << 0) |
Line 6766... | Line 7806... | ||
6766 | 7806 | ||
6767 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
7807 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
6768 | #define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
7808 | #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
6769 | #define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ |
7809 | #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ |
6770 | _MIPIB_HS_TX_TIMEOUT) |
7810 | _MIPIC_HS_TX_TIMEOUT) |
Line 6771... | Line 7811... | ||
6771 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
7811 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
6772 | 7812 | ||
6773 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
7813 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
6774 | #define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
7814 | #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
6775 | #define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ |
7815 | #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ |
Line 6776... | Line 7816... | ||
6776 | _MIPIB_LP_RX_TIMEOUT) |
7816 | _MIPIC_LP_RX_TIMEOUT) |
6777 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
7817 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
6778 | 7818 | ||
6779 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
7819 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
6780 | #define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
7820 | #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
Line 6781... | Line 7821... | ||
6781 | #define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ |
7821 | #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ |
6782 | _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) |
7822 | _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) |
6783 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
7823 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
6784 | 7824 | ||
6785 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
7825 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
Line 6786... | Line 7826... | ||
6786 | #define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
7826 | #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
6787 | #define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ |
7827 | #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ |
6788 | _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) |
7828 | _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) |
6789 | #define DEVICE_RESET_TIMER_MASK 0xffff |
7829 | #define DEVICE_RESET_TIMER_MASK 0xffff |
6790 | 7830 | ||
6791 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
7831 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
6792 | #define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
7832 | #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
6793 | #define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ |
7833 | #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ |
Line 6794... | Line 7834... | ||
6794 | _MIPIB_DPI_RESOLUTION) |
7834 | _MIPIC_DPI_RESOLUTION) |
6795 | #define VERTICAL_ADDRESS_SHIFT 16 |
7835 | #define VERTICAL_ADDRESS_SHIFT 16 |
6796 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) |
7836 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) |
6797 | #define HORIZONTAL_ADDRESS_SHIFT 0 |
7837 | #define HORIZONTAL_ADDRESS_SHIFT 0 |
6798 | #define HORIZONTAL_ADDRESS_MASK 0xffff |
7838 | #define HORIZONTAL_ADDRESS_MASK 0xffff |
6799 | 7839 | ||
6800 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
7840 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
Line 6801... | Line 7841... | ||
6801 | #define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
7841 | #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
6802 | #define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ |
7842 | #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ |
6803 | _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) |
7843 | _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) |
6804 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
7844 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
6805 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
7845 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
Line 6806... | Line 7846... | ||
6806 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
7846 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
6807 | 7847 | ||
6808 | /* regs below are bits 15:0 */ |
7848 | /* regs below are bits 15:0 */ |
6809 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
7849 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
Line 6810... | Line 7850... | ||
6810 | #define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
7850 | #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
6811 | #define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
7851 | #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ |
6812 | _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) |
7852 | _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) |
6813 | 7853 | ||
Line 6814... | Line 7854... | ||
6814 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
7854 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
6815 | #define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
7855 | #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
6816 | #define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ |
7856 | #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ |
6817 | _MIPIB_HBP_COUNT) |
7857 | _MIPIC_HBP_COUNT) |
Line 6818... | Line 7858... | ||
6818 | 7858 | ||
6819 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
7859 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
6820 | #define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
7860 | #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
6821 | #define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ |
7861 | #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ |
Line 6822... | Line 7862... | ||
6822 | _MIPIB_HFP_COUNT) |
7862 | _MIPIC_HFP_COUNT) |
6823 | 7863 | ||
6824 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
7864 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
6825 | #define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
7865 | #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
Line 6826... | Line 7866... | ||
6826 | #define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ |
7866 | #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ |
6827 | _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) |
7867 | _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) |
6828 | 7868 | ||
6829 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
7869 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
Line 6830... | Line 7870... | ||
6830 | #define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
7870 | #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
6831 | #define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
7871 | #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ |
6832 | _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) |
7872 | _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) |
6833 | 7873 | ||
Line 6834... | Line 7874... | ||
6834 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
7874 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
Line 6835... | Line 7875... | ||
6835 | #define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
7875 | #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
6836 | #define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ |
7876 | #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ |
6837 | _MIPIB_VBP_COUNT) |
7877 | _MIPIC_VBP_COUNT) |
6838 | 7878 | ||
6839 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
7879 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
6840 | #define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
7880 | #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
6841 | #define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ |
7881 | #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ |
6842 | _MIPIB_VFP_COUNT) |
7882 | _MIPIC_VFP_COUNT) |
6843 | 7883 | ||
6844 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
7884 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
6845 | #define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
7885 | #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
Line 6846... | Line 7886... | ||
6846 | #define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ |
7886 | #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ |
6847 | _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) |
7887 | _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) |
6848 | 7888 | ||
6849 | /* regs above are bits 15:0 */ |
7889 | /* regs above are bits 15:0 */ |
6850 | 7890 | ||
6851 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
7891 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
Line 6852... | Line 7892... | ||
6852 | #define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
7892 | #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
6853 | #define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ |
7893 | #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ |
6854 | _MIPIB_DPI_CONTROL) |
7894 | _MIPIC_DPI_CONTROL) |
6855 | #define DPI_LP_MODE (1 << 6) |
7895 | #define DPI_LP_MODE (1 << 6) |
6856 | #define BACKLIGHT_OFF (1 << 5) |
7896 | #define BACKLIGHT_OFF (1 << 5) |
6857 | #define BACKLIGHT_ON (1 << 4) |
7897 | #define BACKLIGHT_ON (1 << 4) |
Line 6858... | Line 7898... | ||
6858 | #define COLOR_MODE_OFF (1 << 3) |
7898 | #define COLOR_MODE_OFF (1 << 3) |
6859 | #define COLOR_MODE_ON (1 << 2) |
7899 | #define COLOR_MODE_ON (1 << 2) |
6860 | #define TURN_ON (1 << 1) |
7900 | #define TURN_ON (1 << 1) |
6861 | #define SHUTDOWN (1 << 0) |
7901 | #define SHUTDOWN (1 << 0) |
6862 | 7902 | ||
6863 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
7903 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
Line 6864... | Line 7904... | ||
6864 | #define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
7904 | #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
6865 | #define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ |
7905 | #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ |
6866 | _MIPIB_DPI_DATA) |
7906 | _MIPIC_DPI_DATA) |
6867 | #define COMMAND_BYTE_SHIFT 0 |
7907 | #define COMMAND_BYTE_SHIFT 0 |
6868 | #define COMMAND_BYTE_MASK (0x3f << 0) |
7908 | #define COMMAND_BYTE_MASK (0x3f << 0) |
6869 | 7909 | ||
6870 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
7910 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
6871 | #define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
7911 | #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
6872 | #define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ |
7912 | #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ |
6873 | _MIPIB_INIT_COUNT) |
7913 | _MIPIC_INIT_COUNT) |
Line 6874... | Line 7914... | ||
6874 | #define MASTER_INIT_TIMER_SHIFT 0 |
7914 | #define MASTER_INIT_TIMER_SHIFT 0 |
6875 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) |
7915 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) |
6876 | 7916 | ||
6877 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
7917 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
6878 | #define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
7918 | #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
6879 | #define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ |
7919 | #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ |
6880 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) |
7920 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) |
6881 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
7921 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
6882 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
7922 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
6883 | 7923 | ||
6884 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
7924 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
6885 | #define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
7925 | #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
Line 6886... | Line 7926... | ||
6886 | #define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ |
7926 | #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ |
6887 | _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) |
7927 | _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) |
6888 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
7928 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
6889 | #define DISABLE_VIDEO_BTA (1 << 3) |
7929 | #define DISABLE_VIDEO_BTA (1 << 3) |
6890 | #define IP_TG_CONFIG (1 << 2) |
7930 | #define IP_TG_CONFIG (1 << 2) |
6891 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) |
7931 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) |
Line 6892... | Line 7932... | ||
6892 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
7932 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
6893 | #define VIDEO_MODE_BURST (3 << 0) |
7933 | #define VIDEO_MODE_BURST (3 << 0) |
6894 | 7934 | ||
6895 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
7935 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
6896 | #define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
7936 | #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
Line 6897... | Line 7937... | ||
6897 | #define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ |
7937 | #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ |
6898 | _MIPIB_EOT_DISABLE) |
7938 | _MIPIC_EOT_DISABLE) |
6899 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
7939 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
6900 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
7940 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
6901 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
7941 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
Line 6902... | Line 7942... | ||
6902 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) |
7942 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) |
6903 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) |
7943 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) |
6904 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) |
7944 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) |
6905 | #define CLOCKSTOP (1 << 1) |
7945 | #define CLOCKSTOP (1 << 1) |
6906 | #define EOT_DISABLE (1 << 0) |
7946 | #define EOT_DISABLE (1 << 0) |
6907 | 7947 | ||
6908 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
7948 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
6909 | #define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
7949 | #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
6910 | #define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ |
7950 | #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ |
6911 | _MIPIB_LP_BYTECLK) |
7951 | _MIPIC_LP_BYTECLK) |
6912 | #define LP_BYTECLK_SHIFT 0 |
7952 | #define LP_BYTECLK_SHIFT 0 |
6913 | #define LP_BYTECLK_MASK (0xffff << 0) |
7953 | #define LP_BYTECLK_MASK (0xffff << 0) |
6914 | 7954 | ||
6915 | /* bits 31:0 */ |
7955 | /* bits 31:0 */ |
6916 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
7956 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
6917 | #define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
7957 | #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
6918 | #define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ |
7958 | #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ |
Line 6919... | Line 7959... | ||
6919 | _MIPIB_LP_GEN_DATA) |
7959 | _MIPIC_LP_GEN_DATA) |
6920 | 7960 | ||
6921 | /* bits 31:0 */ |
7961 | /* bits 31:0 */ |
6922 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
7962 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
6923 | #define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
7963 | #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
6924 | #define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ |
7964 | #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ |
6925 | _MIPIB_HS_GEN_DATA) |
7965 | _MIPIC_HS_GEN_DATA) |
6926 | 7966 | ||
6927 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
7967 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
Line 6960... | Line 8000... | ||
6960 | #define HS_DATA_FIFO_EMPTY (1 << 2) |
8000 | #define HS_DATA_FIFO_EMPTY (1 << 2) |
6961 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
8001 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
6962 | #define HS_DATA_FIFO_FULL (1 << 0) |
8002 | #define HS_DATA_FIFO_FULL (1 << 0) |
Line 6963... | Line 8003... | ||
6963 | 8003 | ||
6964 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
8004 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
6965 | #define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
8005 | #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
6966 | #define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ |
8006 | #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ |
6967 | _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) |
8007 | _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) |
6968 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
8008 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
6969 | #define DBI_LP_MODE (1 << 0) |
8009 | #define DBI_LP_MODE (1 << 0) |
Line 6970... | Line 8010... | ||
6970 | #define DBI_HS_MODE (0 << 0) |
8010 | #define DBI_HS_MODE (0 << 0) |
6971 | 8011 | ||
6972 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
8012 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
6973 | #define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
8013 | #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
6974 | #define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ |
8014 | #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ |
6975 | _MIPIB_DPHY_PARAM) |
8015 | _MIPIC_DPHY_PARAM) |
6976 | #define EXIT_ZERO_COUNT_SHIFT 24 |
8016 | #define EXIT_ZERO_COUNT_SHIFT 24 |
6977 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
8017 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
6978 | #define TRAIL_COUNT_SHIFT 16 |
8018 | #define TRAIL_COUNT_SHIFT 16 |
Line 6982... | Line 8022... | ||
6982 | #define PREPARE_COUNT_SHIFT 0 |
8022 | #define PREPARE_COUNT_SHIFT 0 |
6983 | #define PREPARE_COUNT_MASK (0x3f << 0) |
8023 | #define PREPARE_COUNT_MASK (0x3f << 0) |
Line 6984... | Line 8024... | ||
6984 | 8024 | ||
6985 | /* bits 31:0 */ |
8025 | /* bits 31:0 */ |
6986 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
8026 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
6987 | #define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
8027 | #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
6988 | #define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ |
8028 | #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ |
Line 6989... | Line 8029... | ||
6989 | _MIPIB_DBI_BW_CTRL) |
8029 | _MIPIC_DBI_BW_CTRL) |
6990 | 8030 | ||
6991 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
8031 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
6992 | + 0xb088) |
8032 | + 0xb088) |
6993 | #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
8033 | #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
6994 | + 0xb888) |
8034 | + 0xb888) |
6995 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ |
8035 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ |
6996 | _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) |
8036 | _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) |
6997 | #define LP_HS_SSW_CNT_SHIFT 16 |
8037 | #define LP_HS_SSW_CNT_SHIFT 16 |
6998 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) |
8038 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) |
Line 6999... | Line 8039... | ||
6999 | #define HS_LP_PWR_SW_CNT_SHIFT 0 |
8039 | #define HS_LP_PWR_SW_CNT_SHIFT 0 |
7000 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
8040 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
7001 | 8041 | ||
7002 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
8042 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
7003 | #define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
8043 | #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
7004 | #define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ |
8044 | #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ |
Line 7005... | Line 8045... | ||
7005 | _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) |
8045 | _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) |
7006 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
8046 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
7007 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
8047 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
7008 | 8048 | ||
7009 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
8049 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
7010 | #define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
8050 | #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
7011 | #define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ |
8051 | #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ |
7012 | _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) |
8052 | _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) |
7013 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
8053 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
Line 7014... | Line 8054... | ||
7014 | #define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
8054 | #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
7015 | #define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ |
8055 | #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ |
7016 | _MIPIB_INTR_EN_REG_1) |
8056 | _MIPIC_INTR_EN_REG_1) |
Line 7030... | Line 8070... | ||
7030 | 8070 | ||
Line 7031... | Line 8071... | ||
7031 | 8071 | ||
7032 | /* MIPI adapter registers */ |
8072 | /* MIPI adapter registers */ |
7033 | 8073 | ||
7034 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
8074 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
7035 | #define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
8075 | #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
7036 | #define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ |
8076 | #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ |
7037 | _MIPIB_CTRL) |
8077 | _MIPIC_CTRL) |
7038 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
8078 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
7039 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
8079 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
Line 7044... | Line 8084... | ||
7044 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) |
8084 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) |
7045 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) |
8085 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) |
7046 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
8086 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
7047 | #define RGB_FLIP_TO_BGR (1 << 2) |
8087 | #define RGB_FLIP_TO_BGR (1 << 2) |
Line -... | Line 8088... | ||
- | 8088 | ||
- | 8089 | #define BXT_PIPE_SELECT_MASK (7 << 7) |
|
- | 8090 | #define BXT_PIPE_SELECT_C (2 << 7) |
|
- | 8091 | #define BXT_PIPE_SELECT_B (1 << 7) |
|
- | 8092 | #define BXT_PIPE_SELECT_A (0 << 7) |
|
7048 | 8093 | ||
7049 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
8094 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
7050 | #define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
8095 | #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
7051 | #define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ |
8096 | #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ |
7052 | _MIPIB_DATA_ADDRESS) |
8097 | _MIPIC_DATA_ADDRESS) |
7053 | #define DATA_MEM_ADDRESS_SHIFT 5 |
8098 | #define DATA_MEM_ADDRESS_SHIFT 5 |
7054 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
8099 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
Line 7055... | Line 8100... | ||
7055 | #define DATA_VALID (1 << 0) |
8100 | #define DATA_VALID (1 << 0) |
7056 | 8101 | ||
7057 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
8102 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
7058 | #define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
8103 | #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
7059 | #define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ |
8104 | #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ |
7060 | _MIPIB_DATA_LENGTH) |
8105 | _MIPIC_DATA_LENGTH) |
Line 7061... | Line 8106... | ||
7061 | #define DATA_LENGTH_SHIFT 0 |
8106 | #define DATA_LENGTH_SHIFT 0 |
7062 | #define DATA_LENGTH_MASK (0xfffff << 0) |
8107 | #define DATA_LENGTH_MASK (0xfffff << 0) |
7063 | 8108 | ||
7064 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
8109 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
7065 | #define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
8110 | #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
7066 | #define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ |
8111 | #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ |
7067 | _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) |
8112 | _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) |
7068 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
8113 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
7069 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
8114 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
Line 7070... | Line 8115... | ||
7070 | #define AUTO_PWG_ENABLE (1 << 2) |
8115 | #define AUTO_PWG_ENABLE (1 << 2) |
7071 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
8116 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
7072 | #define COMMAND_VALID (1 << 0) |
8117 | #define COMMAND_VALID (1 << 0) |
7073 | 8118 | ||
7074 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
8119 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
7075 | #define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
8120 | #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
Line 7076... | Line 8121... | ||
7076 | #define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ |
8121 | #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ |
7077 | _MIPIB_COMMAND_LENGTH) |
8122 | _MIPIC_COMMAND_LENGTH) |
7078 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
8123 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
7079 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
8124 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
7080 | 8125 | ||
Line 7081... | Line 8126... | ||
7081 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
8126 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
7082 | #define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
8127 | #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
7083 | #define MIPI_READ_DATA_RETURN(tc, n) \ |
8128 | #define MIPI_READ_DATA_RETURN(port, n) \ |
7084 | (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ |
8129 | (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ |
7085 | + 4 * (n)) /* n: 0...7 */ |
8130 | + 4 * (n)) /* n: 0...7 */ |
Line 7086... | Line 8131... | ||
7086 | 8131 | ||
7087 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
8132 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
7088 | #define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
8133 | #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
Line -... | Line 8134... | ||
- | 8134 | #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ |
|
- | 8135 | _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) |
|
- | 8136 | #define READ_DATA_VALID(n) (1 << (n)) |
|
- | 8137 | ||
- | 8138 | /* For UMS only (deprecated): */ |
|
- | 8139 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
|
- | 8140 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) |
|
- | 8141 | ||
- | 8142 | /* MOCS (Memory Object Control State) registers */ |
|
7089 | #define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ |
8143 | #define GEN9_LNCFCMOCS0 0xb020 /* L3 Cache Control base */ |