Rev 5128 | Rev 6084 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5128 | Rev 5354 | ||
---|---|---|---|
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * All Rights Reserved. |
2 | * All Rights Reserved. |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the |
5 | * copy of this software and associated documentation files (the |
6 | * "Software"), to deal in the Software without restriction, including |
6 | * "Software"), to deal in the Software without restriction, including |
7 | * without limitation the rights to use, copy, modify, merge, publish, |
7 | * without limitation the rights to use, copy, modify, merge, publish, |
8 | * distribute, sub license, and/or sell copies of the Software, and to |
8 | * distribute, sub license, and/or sell copies of the Software, and to |
9 | * permit persons to whom the Software is furnished to do so, subject to |
9 | * permit persons to whom the Software is furnished to do so, subject to |
10 | * the following conditions: |
10 | * the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice (including the |
12 | * The above copyright notice and this permission notice (including the |
13 | * next paragraph) shall be included in all copies or substantial portions |
13 | * next paragraph) shall be included in all copies or substantial portions |
14 | * of the Software. |
14 | * of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
23 | */ |
23 | */ |
24 | 24 | ||
25 | #ifndef _I915_REG_H_ |
25 | #ifndef _I915_REG_H_ |
26 | #define _I915_REG_H_ |
26 | #define _I915_REG_H_ |
27 | 27 | ||
28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
- | 29 | #define _PLANE(plane, a, b) _PIPE(plane, a, b) |
|
29 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
30 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
30 | - | ||
31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
32 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
32 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
33 | (pipe) == PIPE_B ? (b) : (c)) |
33 | (pipe) == PIPE_B ? (b) : (c)) |
- | 34 | ||
- | 35 | #define _MASKED_FIELD(mask, value) ({ \ |
|
- | 36 | if (__builtin_constant_p(mask)) \ |
|
- | 37 | BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ |
|
- | 38 | if (__builtin_constant_p(value)) \ |
|
- | 39 | BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ |
|
- | 40 | if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ |
|
- | 41 | BUILD_BUG_ON_MSG((value) & ~(mask), \ |
|
- | 42 | "Incorrect value for mask"); \ |
|
34 | 43 | (mask) << 16 | (value); }) |
|
35 | #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
44 | #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) |
- | 45 | #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) |
|
- | 46 | ||
36 | #define _MASKED_BIT_DISABLE(a) ((a) << 16) |
47 | |
37 | 48 | ||
38 | /* PCI config space */ |
49 | /* PCI config space */ |
39 | 50 | ||
40 | #define HPLLCC 0xc0 /* 855 only */ |
51 | #define HPLLCC 0xc0 /* 855 only */ |
41 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) |
52 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) |
42 | #define GC_CLOCK_133_200 (0 << 0) |
53 | #define GC_CLOCK_133_200 (0 << 0) |
43 | #define GC_CLOCK_100_200 (1 << 0) |
54 | #define GC_CLOCK_100_200 (1 << 0) |
44 | #define GC_CLOCK_100_133 (2 << 0) |
55 | #define GC_CLOCK_100_133 (2 << 0) |
45 | #define GC_CLOCK_166_250 (3 << 0) |
56 | #define GC_CLOCK_166_250 (3 << 0) |
46 | #define GCFGC2 0xda |
57 | #define GCFGC2 0xda |
47 | #define GCFGC 0xf0 /* 915+ only */ |
58 | #define GCFGC 0xf0 /* 915+ only */ |
48 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
59 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
49 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
60 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
50 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) |
61 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) |
51 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) |
62 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) |
52 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) |
63 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) |
53 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) |
64 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) |
54 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) |
65 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) |
55 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) |
66 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) |
56 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) |
67 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) |
57 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
68 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
58 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
69 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
59 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
70 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
60 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) |
71 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) |
61 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) |
72 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) |
62 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) |
73 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) |
63 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) |
74 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) |
64 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) |
75 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) |
65 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) |
76 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) |
66 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) |
77 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) |
67 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) |
78 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) |
68 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) |
79 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) |
69 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
80 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
70 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
81 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
71 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) |
82 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) |
72 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) |
83 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) |
73 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) |
84 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) |
74 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
85 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
75 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
86 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
76 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
87 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
- | 88 | #define GCDGMBUS 0xcc |
|
77 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
89 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
78 | 90 | ||
79 | 91 | ||
80 | /* Graphics reset regs */ |
92 | /* Graphics reset regs */ |
81 | #define I965_GDRST 0xc0 /* PCI config register */ |
93 | #define I915_GDRST 0xc0 /* PCI config register */ |
82 | #define GRDOM_FULL (0<<2) |
94 | #define GRDOM_FULL (0<<2) |
83 | #define GRDOM_RENDER (1<<2) |
95 | #define GRDOM_RENDER (1<<2) |
84 | #define GRDOM_MEDIA (3<<2) |
96 | #define GRDOM_MEDIA (3<<2) |
85 | #define GRDOM_MASK (3<<2) |
97 | #define GRDOM_MASK (3<<2) |
- | 98 | #define GRDOM_RESET_STATUS (1<<1) |
|
86 | #define GRDOM_RESET_ENABLE (1<<0) |
99 | #define GRDOM_RESET_ENABLE (1<<0) |
87 | 100 | ||
88 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
101 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
89 | #define ILK_GRDOM_FULL (0<<1) |
102 | #define ILK_GRDOM_FULL (0<<1) |
90 | #define ILK_GRDOM_RENDER (1<<1) |
103 | #define ILK_GRDOM_RENDER (1<<1) |
91 | #define ILK_GRDOM_MEDIA (3<<1) |
104 | #define ILK_GRDOM_MEDIA (3<<1) |
92 | #define ILK_GRDOM_MASK (3<<1) |
105 | #define ILK_GRDOM_MASK (3<<1) |
93 | #define ILK_GRDOM_RESET_ENABLE (1<<0) |
106 | #define ILK_GRDOM_RESET_ENABLE (1<<0) |
94 | 107 | ||
95 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
108 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
96 | #define GEN6_MBC_SNPCR_SHIFT 21 |
109 | #define GEN6_MBC_SNPCR_SHIFT 21 |
97 | #define GEN6_MBC_SNPCR_MASK (3<<21) |
110 | #define GEN6_MBC_SNPCR_MASK (3<<21) |
98 | #define GEN6_MBC_SNPCR_MAX (0<<21) |
111 | #define GEN6_MBC_SNPCR_MAX (0<<21) |
99 | #define GEN6_MBC_SNPCR_MED (1<<21) |
112 | #define GEN6_MBC_SNPCR_MED (1<<21) |
100 | #define GEN6_MBC_SNPCR_LOW (2<<21) |
113 | #define GEN6_MBC_SNPCR_LOW (2<<21) |
101 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
114 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
102 | 115 | ||
103 | #define VLV_G3DCTL 0x9024 |
116 | #define VLV_G3DCTL 0x9024 |
104 | #define VLV_GSCKGCTL 0x9028 |
117 | #define VLV_GSCKGCTL 0x9028 |
105 | 118 | ||
106 | #define GEN6_MBCTL 0x0907c |
119 | #define GEN6_MBCTL 0x0907c |
107 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
120 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
108 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
121 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
109 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) |
122 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) |
110 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) |
123 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) |
111 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) |
124 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) |
112 | 125 | ||
113 | #define GEN6_GDRST 0x941c |
126 | #define GEN6_GDRST 0x941c |
114 | #define GEN6_GRDOM_FULL (1 << 0) |
127 | #define GEN6_GRDOM_FULL (1 << 0) |
115 | #define GEN6_GRDOM_RENDER (1 << 1) |
128 | #define GEN6_GRDOM_RENDER (1 << 1) |
116 | #define GEN6_GRDOM_MEDIA (1 << 2) |
129 | #define GEN6_GRDOM_MEDIA (1 << 2) |
117 | #define GEN6_GRDOM_BLT (1 << 3) |
130 | #define GEN6_GRDOM_BLT (1 << 3) |
118 | 131 | ||
119 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
132 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
120 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) |
133 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) |
121 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) |
134 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) |
122 | #define PP_DIR_DCLV_2G 0xffffffff |
135 | #define PP_DIR_DCLV_2G 0xffffffff |
123 | 136 | ||
124 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) |
137 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) |
125 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) |
138 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) |
126 | 139 | ||
127 | #define GAM_ECOCHK 0x4090 |
140 | #define GAM_ECOCHK 0x4090 |
128 | #define ECOCHK_SNB_BIT (1<<10) |
141 | #define ECOCHK_SNB_BIT (1<<10) |
129 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
142 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
130 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
143 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
131 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
144 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
132 | #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) |
145 | #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) |
133 | #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) |
146 | #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) |
134 | #define ECOCHK_PPGTT_UC_HSW (0x1<<3) |
147 | #define ECOCHK_PPGTT_UC_HSW (0x1<<3) |
135 | #define ECOCHK_PPGTT_WT_HSW (0x2<<3) |
148 | #define ECOCHK_PPGTT_WT_HSW (0x2<<3) |
136 | #define ECOCHK_PPGTT_WB_HSW (0x3<<3) |
149 | #define ECOCHK_PPGTT_WB_HSW (0x3<<3) |
137 | 150 | ||
138 | #define GAC_ECO_BITS 0x14090 |
151 | #define GAC_ECO_BITS 0x14090 |
139 | #define ECOBITS_SNB_BIT (1<<13) |
152 | #define ECOBITS_SNB_BIT (1<<13) |
140 | #define ECOBITS_PPGTT_CACHE64B (3<<8) |
153 | #define ECOBITS_PPGTT_CACHE64B (3<<8) |
141 | #define ECOBITS_PPGTT_CACHE4B (0<<8) |
154 | #define ECOBITS_PPGTT_CACHE4B (0<<8) |
142 | 155 | ||
143 | #define GAB_CTL 0x24000 |
156 | #define GAB_CTL 0x24000 |
144 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
157 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
- | 158 | ||
- | 159 | #define GEN7_BIOS_RESERVED 0x1082C0 |
|
- | 160 | #define GEN7_BIOS_RESERVED_1M (0 << 5) |
|
- | 161 | #define GEN7_BIOS_RESERVED_256K (1 << 5) |
|
- | 162 | #define GEN8_BIOS_RESERVED_SHIFT 7 |
|
- | 163 | #define GEN7_BIOS_RESERVED_MASK 0x1 |
|
- | 164 | #define GEN8_BIOS_RESERVED_MASK 0x3 |
|
- | 165 | ||
145 | 166 | ||
146 | /* VGA stuff */ |
167 | /* VGA stuff */ |
147 | 168 | ||
148 | #define VGA_ST01_MDA 0x3ba |
169 | #define VGA_ST01_MDA 0x3ba |
149 | #define VGA_ST01_CGA 0x3da |
170 | #define VGA_ST01_CGA 0x3da |
150 | 171 | ||
151 | #define VGA_MSR_WRITE 0x3c2 |
172 | #define VGA_MSR_WRITE 0x3c2 |
152 | #define VGA_MSR_READ 0x3cc |
173 | #define VGA_MSR_READ 0x3cc |
153 | #define VGA_MSR_MEM_EN (1<<1) |
174 | #define VGA_MSR_MEM_EN (1<<1) |
154 | #define VGA_MSR_CGA_MODE (1<<0) |
175 | #define VGA_MSR_CGA_MODE (1<<0) |
155 | 176 | ||
156 | #define VGA_SR_INDEX 0x3c4 |
177 | #define VGA_SR_INDEX 0x3c4 |
157 | #define SR01 1 |
178 | #define SR01 1 |
158 | #define VGA_SR_DATA 0x3c5 |
179 | #define VGA_SR_DATA 0x3c5 |
159 | 180 | ||
160 | #define VGA_AR_INDEX 0x3c0 |
181 | #define VGA_AR_INDEX 0x3c0 |
161 | #define VGA_AR_VID_EN (1<<5) |
182 | #define VGA_AR_VID_EN (1<<5) |
162 | #define VGA_AR_DATA_WRITE 0x3c0 |
183 | #define VGA_AR_DATA_WRITE 0x3c0 |
163 | #define VGA_AR_DATA_READ 0x3c1 |
184 | #define VGA_AR_DATA_READ 0x3c1 |
164 | 185 | ||
165 | #define VGA_GR_INDEX 0x3ce |
186 | #define VGA_GR_INDEX 0x3ce |
166 | #define VGA_GR_DATA 0x3cf |
187 | #define VGA_GR_DATA 0x3cf |
167 | /* GR05 */ |
188 | /* GR05 */ |
168 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 |
189 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 |
169 | #define VGA_GR_MEM_READ_MODE_PLANE 1 |
190 | #define VGA_GR_MEM_READ_MODE_PLANE 1 |
170 | /* GR06 */ |
191 | /* GR06 */ |
171 | #define VGA_GR_MEM_MODE_MASK 0xc |
192 | #define VGA_GR_MEM_MODE_MASK 0xc |
172 | #define VGA_GR_MEM_MODE_SHIFT 2 |
193 | #define VGA_GR_MEM_MODE_SHIFT 2 |
173 | #define VGA_GR_MEM_A0000_AFFFF 0 |
194 | #define VGA_GR_MEM_A0000_AFFFF 0 |
174 | #define VGA_GR_MEM_A0000_BFFFF 1 |
195 | #define VGA_GR_MEM_A0000_BFFFF 1 |
175 | #define VGA_GR_MEM_B0000_B7FFF 2 |
196 | #define VGA_GR_MEM_B0000_B7FFF 2 |
176 | #define VGA_GR_MEM_B0000_BFFFF 3 |
197 | #define VGA_GR_MEM_B0000_BFFFF 3 |
177 | 198 | ||
178 | #define VGA_DACMASK 0x3c6 |
199 | #define VGA_DACMASK 0x3c6 |
179 | #define VGA_DACRX 0x3c7 |
200 | #define VGA_DACRX 0x3c7 |
180 | #define VGA_DACWX 0x3c8 |
201 | #define VGA_DACWX 0x3c8 |
181 | #define VGA_DACDATA 0x3c9 |
202 | #define VGA_DACDATA 0x3c9 |
182 | 203 | ||
183 | #define VGA_CR_INDEX_MDA 0x3b4 |
204 | #define VGA_CR_INDEX_MDA 0x3b4 |
184 | #define VGA_CR_DATA_MDA 0x3b5 |
205 | #define VGA_CR_DATA_MDA 0x3b5 |
185 | #define VGA_CR_INDEX_CGA 0x3d4 |
206 | #define VGA_CR_INDEX_CGA 0x3d4 |
186 | #define VGA_CR_DATA_CGA 0x3d5 |
207 | #define VGA_CR_DATA_CGA 0x3d5 |
187 | 208 | ||
188 | /* |
209 | /* |
189 | * Instruction field definitions used by the command parser |
210 | * Instruction field definitions used by the command parser |
190 | */ |
211 | */ |
191 | #define INSTR_CLIENT_SHIFT 29 |
212 | #define INSTR_CLIENT_SHIFT 29 |
192 | #define INSTR_CLIENT_MASK 0xE0000000 |
213 | #define INSTR_CLIENT_MASK 0xE0000000 |
193 | #define INSTR_MI_CLIENT 0x0 |
214 | #define INSTR_MI_CLIENT 0x0 |
194 | #define INSTR_BC_CLIENT 0x2 |
215 | #define INSTR_BC_CLIENT 0x2 |
195 | #define INSTR_RC_CLIENT 0x3 |
216 | #define INSTR_RC_CLIENT 0x3 |
196 | #define INSTR_SUBCLIENT_SHIFT 27 |
217 | #define INSTR_SUBCLIENT_SHIFT 27 |
197 | #define INSTR_SUBCLIENT_MASK 0x18000000 |
218 | #define INSTR_SUBCLIENT_MASK 0x18000000 |
198 | #define INSTR_MEDIA_SUBCLIENT 0x2 |
219 | #define INSTR_MEDIA_SUBCLIENT 0x2 |
199 | 220 | ||
200 | /* |
221 | /* |
201 | * Memory interface instructions used by the kernel |
222 | * Memory interface instructions used by the kernel |
202 | */ |
223 | */ |
203 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) |
224 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) |
204 | /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ |
225 | /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ |
205 | #define MI_GLOBAL_GTT (1<<22) |
226 | #define MI_GLOBAL_GTT (1<<22) |
206 | 227 | ||
207 | #define MI_NOOP MI_INSTR(0, 0) |
228 | #define MI_NOOP MI_INSTR(0, 0) |
208 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
229 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
209 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) |
230 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) |
210 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
231 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
211 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
232 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
212 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
233 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
213 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
234 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
214 | #define MI_FLUSH MI_INSTR(0x04, 0) |
235 | #define MI_FLUSH MI_INSTR(0x04, 0) |
215 | #define MI_READ_FLUSH (1 << 0) |
236 | #define MI_READ_FLUSH (1 << 0) |
216 | #define MI_EXE_FLUSH (1 << 1) |
237 | #define MI_EXE_FLUSH (1 << 1) |
217 | #define MI_NO_WRITE_FLUSH (1 << 2) |
238 | #define MI_NO_WRITE_FLUSH (1 << 2) |
218 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
239 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
219 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
240 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
220 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
241 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
221 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
242 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
222 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
243 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
223 | #define MI_ARB_ENABLE (1<<0) |
244 | #define MI_ARB_ENABLE (1<<0) |
224 | #define MI_ARB_DISABLE (0<<0) |
245 | #define MI_ARB_DISABLE (0<<0) |
225 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
246 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
226 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
247 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
227 | #define MI_SUSPEND_FLUSH_EN (1<<0) |
248 | #define MI_SUSPEND_FLUSH_EN (1<<0) |
228 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
249 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
229 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
250 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
230 | #define MI_OVERLAY_ON (0x1<<21) |
251 | #define MI_OVERLAY_ON (0x1<<21) |
231 | #define MI_OVERLAY_OFF (0x2<<21) |
252 | #define MI_OVERLAY_OFF (0x2<<21) |
232 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
253 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
233 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
254 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
234 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
255 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
235 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
256 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
236 | /* IVB has funny definitions for which plane to flip. */ |
257 | /* IVB has funny definitions for which plane to flip. */ |
237 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) |
258 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) |
238 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
259 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
239 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
260 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
240 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
261 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
241 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
262 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
242 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
263 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
- | 264 | /* SKL ones */ |
|
- | 265 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) |
|
- | 266 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) |
|
- | 267 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) |
|
- | 268 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) |
|
- | 269 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) |
|
- | 270 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) |
|
- | 271 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) |
|
- | 272 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) |
|
- | 273 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) |
|
243 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ |
274 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ |
244 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
275 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
245 | #define MI_SEMAPHORE_UPDATE (1<<21) |
276 | #define MI_SEMAPHORE_UPDATE (1<<21) |
246 | #define MI_SEMAPHORE_COMPARE (1<<20) |
277 | #define MI_SEMAPHORE_COMPARE (1<<20) |
247 | #define MI_SEMAPHORE_REGISTER (1<<18) |
278 | #define MI_SEMAPHORE_REGISTER (1<<18) |
248 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ |
279 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ |
249 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ |
280 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ |
250 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ |
281 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ |
251 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ |
282 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ |
252 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ |
283 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ |
253 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ |
284 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ |
254 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ |
285 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ |
255 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ |
286 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ |
256 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ |
287 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ |
257 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ |
288 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ |
258 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ |
289 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ |
259 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ |
290 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ |
260 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
291 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
261 | #define MI_SEMAPHORE_SYNC_MASK (3<<16) |
292 | #define MI_SEMAPHORE_SYNC_MASK (3<<16) |
262 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
293 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
263 | #define MI_MM_SPACE_GTT (1<<8) |
294 | #define MI_MM_SPACE_GTT (1<<8) |
264 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
295 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
265 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
296 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
266 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
297 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
267 | #define MI_FORCE_RESTORE (1<<1) |
298 | #define MI_FORCE_RESTORE (1<<1) |
268 | #define MI_RESTORE_INHIBIT (1<<0) |
299 | #define MI_RESTORE_INHIBIT (1<<0) |
269 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
300 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
270 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) |
301 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) |
271 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
302 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
272 | #define MI_SEMAPHORE_POLL (1<<15) |
303 | #define MI_SEMAPHORE_POLL (1<<15) |
273 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) |
304 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) |
274 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
305 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
- | 306 | #define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) |
|
275 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
307 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
276 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
308 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
277 | #define MI_STORE_DWORD_INDEX_SHIFT 2 |
309 | #define MI_STORE_DWORD_INDEX_SHIFT 2 |
278 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
310 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
279 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw |
311 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw |
280 | * simply ignores the register load under certain conditions. |
312 | * simply ignores the register load under certain conditions. |
281 | * - One can actually load arbitrary many arbitrary registers: Simply issue x |
313 | * - One can actually load arbitrary many arbitrary registers: Simply issue x |
282 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
314 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
283 | */ |
315 | */ |
284 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
316 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
- | 317 | #define MI_LRI_FORCE_POSTED (1<<12) |
|
285 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) |
318 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) |
286 | #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) |
319 | #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) |
287 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
320 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
288 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
321 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
289 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
322 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
290 | #define MI_INVALIDATE_TLB (1<<18) |
323 | #define MI_INVALIDATE_TLB (1<<18) |
291 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) |
324 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) |
292 | #define MI_FLUSH_DW_OP_MASK (3<<14) |
325 | #define MI_FLUSH_DW_OP_MASK (3<<14) |
293 | #define MI_FLUSH_DW_NOTIFY (1<<8) |
326 | #define MI_FLUSH_DW_NOTIFY (1<<8) |
294 | #define MI_INVALIDATE_BSD (1<<7) |
327 | #define MI_INVALIDATE_BSD (1<<7) |
295 | #define MI_FLUSH_DW_USE_GTT (1<<2) |
328 | #define MI_FLUSH_DW_USE_GTT (1<<2) |
296 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) |
329 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) |
297 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
330 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
298 | #define MI_BATCH_NON_SECURE (1) |
331 | #define MI_BATCH_NON_SECURE (1) |
299 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ |
332 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ |
300 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
333 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
301 | #define MI_BATCH_PPGTT_HSW (1<<8) |
334 | #define MI_BATCH_PPGTT_HSW (1<<8) |
302 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
335 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
303 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
336 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
304 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
337 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
305 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
338 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
- | 339 | ||
- | 340 | #define MI_PREDICATE_SRC0 (0x2400) |
|
306 | 341 | #define MI_PREDICATE_SRC1 (0x2408) |
|
307 | 342 | ||
308 | #define MI_PREDICATE_RESULT_2 (0x2214) |
343 | #define MI_PREDICATE_RESULT_2 (0x2214) |
309 | #define LOWER_SLICE_ENABLED (1<<0) |
344 | #define LOWER_SLICE_ENABLED (1<<0) |
310 | #define LOWER_SLICE_DISABLED (0<<0) |
345 | #define LOWER_SLICE_DISABLED (0<<0) |
311 | 346 | ||
312 | /* |
347 | /* |
313 | * 3D instructions used by the kernel |
348 | * 3D instructions used by the kernel |
314 | */ |
349 | */ |
315 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) |
350 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) |
316 | 351 | ||
317 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) |
352 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) |
318 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
353 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
319 | #define SC_UPDATE_SCISSOR (0x1<<1) |
354 | #define SC_UPDATE_SCISSOR (0x1<<1) |
320 | #define SC_ENABLE_MASK (0x1<<0) |
355 | #define SC_ENABLE_MASK (0x1<<0) |
321 | #define SC_ENABLE (0x1<<0) |
356 | #define SC_ENABLE (0x1<<0) |
322 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
357 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
323 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
358 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
324 | #define SCI_YMIN_MASK (0xffff<<16) |
359 | #define SCI_YMIN_MASK (0xffff<<16) |
325 | #define SCI_XMIN_MASK (0xffff<<0) |
360 | #define SCI_XMIN_MASK (0xffff<<0) |
326 | #define SCI_YMAX_MASK (0xffff<<16) |
361 | #define SCI_YMAX_MASK (0xffff<<16) |
327 | #define SCI_XMAX_MASK (0xffff<<0) |
362 | #define SCI_XMAX_MASK (0xffff<<0) |
328 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
363 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
329 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
364 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
330 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
365 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
331 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
366 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
332 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
367 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
333 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
368 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
334 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
369 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
335 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
370 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
336 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
371 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
337 | 372 | ||
338 | #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) |
373 | #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) |
339 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
374 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
340 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
375 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
341 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) |
376 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) |
342 | #define BLT_WRITE_A (2<<20) |
377 | #define BLT_WRITE_A (2<<20) |
343 | #define BLT_WRITE_RGB (1<<20) |
378 | #define BLT_WRITE_RGB (1<<20) |
344 | #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) |
379 | #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) |
345 | #define BLT_DEPTH_8 (0<<24) |
380 | #define BLT_DEPTH_8 (0<<24) |
346 | #define BLT_DEPTH_16_565 (1<<24) |
381 | #define BLT_DEPTH_16_565 (1<<24) |
347 | #define BLT_DEPTH_16_1555 (2<<24) |
382 | #define BLT_DEPTH_16_1555 (2<<24) |
348 | #define BLT_DEPTH_32 (3<<24) |
383 | #define BLT_DEPTH_32 (3<<24) |
349 | #define BLT_ROP_SRC_COPY (0xcc<<16) |
384 | #define BLT_ROP_SRC_COPY (0xcc<<16) |
350 | #define BLT_ROP_COLOR_COPY (0xf0<<16) |
385 | #define BLT_ROP_COLOR_COPY (0xf0<<16) |
351 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
386 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
352 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
387 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
353 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
388 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
354 | #define ASYNC_FLIP (1<<22) |
389 | #define ASYNC_FLIP (1<<22) |
355 | #define DISPLAY_PLANE_A (0<<20) |
390 | #define DISPLAY_PLANE_A (0<<20) |
356 | #define DISPLAY_PLANE_B (1<<20) |
391 | #define DISPLAY_PLANE_B (1<<20) |
357 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
392 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
358 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
393 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
359 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) |
394 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) |
360 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
395 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
361 | #define PIPE_CONTROL_CS_STALL (1<<20) |
396 | #define PIPE_CONTROL_CS_STALL (1<<20) |
362 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
397 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
- | 398 | #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) |
|
363 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
399 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
364 | #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) |
400 | #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) |
365 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
401 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
366 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) |
402 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) |
367 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
403 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
368 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
404 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
369 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
405 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
370 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
406 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
371 | #define PIPE_CONTROL_NOTIFY (1<<8) |
407 | #define PIPE_CONTROL_NOTIFY (1<<8) |
372 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
408 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
373 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
409 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
374 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
410 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
375 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
411 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
376 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
412 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
377 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
413 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
378 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
414 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
379 | 415 | ||
380 | /* |
416 | /* |
381 | * Commands used only by the command parser |
417 | * Commands used only by the command parser |
382 | */ |
418 | */ |
383 | #define MI_SET_PREDICATE MI_INSTR(0x01, 0) |
419 | #define MI_SET_PREDICATE MI_INSTR(0x01, 0) |
384 | #define MI_ARB_CHECK MI_INSTR(0x05, 0) |
420 | #define MI_ARB_CHECK MI_INSTR(0x05, 0) |
385 | #define MI_RS_CONTROL MI_INSTR(0x06, 0) |
421 | #define MI_RS_CONTROL MI_INSTR(0x06, 0) |
386 | #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) |
422 | #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) |
387 | #define MI_PREDICATE MI_INSTR(0x0C, 0) |
423 | #define MI_PREDICATE MI_INSTR(0x0C, 0) |
388 | #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) |
424 | #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) |
389 | #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) |
425 | #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) |
390 | #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) |
426 | #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) |
391 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) |
427 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) |
392 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) |
428 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) |
393 | #define MI_CLFLUSH MI_INSTR(0x27, 0) |
429 | #define MI_CLFLUSH MI_INSTR(0x27, 0) |
394 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
430 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
395 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) |
431 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) |
396 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) |
432 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) |
397 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) |
433 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) |
398 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) |
434 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) |
399 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) |
435 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) |
400 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) |
436 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) |
401 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) |
437 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) |
402 | 438 | ||
403 | #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
439 | #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
404 | #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
440 | #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
405 | #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
441 | #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
406 | #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) |
442 | #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) |
407 | #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
443 | #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
408 | #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
444 | #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
409 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ |
445 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ |
410 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
446 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
411 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ |
447 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ |
412 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
448 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
413 | #define GFX_OP_3DSTATE_SO_DECL_LIST \ |
449 | #define GFX_OP_3DSTATE_SO_DECL_LIST \ |
414 | ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
450 | ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
415 | 451 | ||
416 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ |
452 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ |
417 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
453 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
418 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ |
454 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ |
419 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
455 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
420 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ |
456 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ |
421 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
457 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
422 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ |
458 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ |
423 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
459 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
424 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ |
460 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ |
425 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
461 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
426 | 462 | ||
427 | #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) |
463 | #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) |
428 | 464 | ||
429 | #define COLOR_BLT ((0x2<<29)|(0x40<<22)) |
465 | #define COLOR_BLT ((0x2<<29)|(0x40<<22)) |
430 | #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) |
466 | #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) |
431 | 467 | ||
432 | /* |
468 | /* |
433 | * Registers used only by the command parser |
469 | * Registers used only by the command parser |
434 | */ |
470 | */ |
435 | #define BCS_SWCTRL 0x22200 |
471 | #define BCS_SWCTRL 0x22200 |
436 | 472 | ||
437 | #define HS_INVOCATION_COUNT 0x2300 |
473 | #define HS_INVOCATION_COUNT 0x2300 |
438 | #define DS_INVOCATION_COUNT 0x2308 |
474 | #define DS_INVOCATION_COUNT 0x2308 |
439 | #define IA_VERTICES_COUNT 0x2310 |
475 | #define IA_VERTICES_COUNT 0x2310 |
440 | #define IA_PRIMITIVES_COUNT 0x2318 |
476 | #define IA_PRIMITIVES_COUNT 0x2318 |
441 | #define VS_INVOCATION_COUNT 0x2320 |
477 | #define VS_INVOCATION_COUNT 0x2320 |
442 | #define GS_INVOCATION_COUNT 0x2328 |
478 | #define GS_INVOCATION_COUNT 0x2328 |
443 | #define GS_PRIMITIVES_COUNT 0x2330 |
479 | #define GS_PRIMITIVES_COUNT 0x2330 |
444 | #define CL_INVOCATION_COUNT 0x2338 |
480 | #define CL_INVOCATION_COUNT 0x2338 |
445 | #define CL_PRIMITIVES_COUNT 0x2340 |
481 | #define CL_PRIMITIVES_COUNT 0x2340 |
446 | #define PS_INVOCATION_COUNT 0x2348 |
482 | #define PS_INVOCATION_COUNT 0x2348 |
447 | #define PS_DEPTH_COUNT 0x2350 |
483 | #define PS_DEPTH_COUNT 0x2350 |
448 | 484 | ||
449 | /* There are the 4 64-bit counter registers, one for each stream output */ |
485 | /* There are the 4 64-bit counter registers, one for each stream output */ |
450 | #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) |
486 | #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) |
451 | 487 | ||
452 | #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) |
488 | #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) |
453 | 489 | ||
454 | #define GEN7_3DPRIM_END_OFFSET 0x2420 |
490 | #define GEN7_3DPRIM_END_OFFSET 0x2420 |
455 | #define GEN7_3DPRIM_START_VERTEX 0x2430 |
491 | #define GEN7_3DPRIM_START_VERTEX 0x2430 |
456 | #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 |
492 | #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 |
457 | #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 |
493 | #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 |
458 | #define GEN7_3DPRIM_START_INSTANCE 0x243C |
494 | #define GEN7_3DPRIM_START_INSTANCE 0x243C |
459 | #define GEN7_3DPRIM_BASE_VERTEX 0x2440 |
495 | #define GEN7_3DPRIM_BASE_VERTEX 0x2440 |
460 | 496 | ||
461 | #define OACONTROL 0x2360 |
497 | #define OACONTROL 0x2360 |
462 | 498 | ||
463 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
499 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
464 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |
500 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |
465 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ |
501 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ |
466 | _GEN7_PIPEA_DE_LOAD_SL, \ |
502 | _GEN7_PIPEA_DE_LOAD_SL, \ |
467 | _GEN7_PIPEB_DE_LOAD_SL) |
503 | _GEN7_PIPEB_DE_LOAD_SL) |
468 | 504 | ||
469 | /* |
505 | /* |
470 | * Reset registers |
506 | * Reset registers |
471 | */ |
507 | */ |
472 | #define DEBUG_RESET_I830 0x6070 |
508 | #define DEBUG_RESET_I830 0x6070 |
473 | #define DEBUG_RESET_FULL (1<<7) |
509 | #define DEBUG_RESET_FULL (1<<7) |
474 | #define DEBUG_RESET_RENDER (1<<8) |
510 | #define DEBUG_RESET_RENDER (1<<8) |
475 | #define DEBUG_RESET_DISPLAY (1<<9) |
511 | #define DEBUG_RESET_DISPLAY (1<<9) |
476 | 512 | ||
477 | /* |
513 | /* |
478 | * IOSF sideband |
514 | * IOSF sideband |
479 | */ |
515 | */ |
480 | #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) |
516 | #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) |
481 | #define IOSF_DEVFN_SHIFT 24 |
517 | #define IOSF_DEVFN_SHIFT 24 |
482 | #define IOSF_OPCODE_SHIFT 16 |
518 | #define IOSF_OPCODE_SHIFT 16 |
483 | #define IOSF_PORT_SHIFT 8 |
519 | #define IOSF_PORT_SHIFT 8 |
484 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
520 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
485 | #define IOSF_BAR_SHIFT 1 |
521 | #define IOSF_BAR_SHIFT 1 |
486 | #define IOSF_SB_BUSY (1<<0) |
522 | #define IOSF_SB_BUSY (1<<0) |
487 | #define IOSF_PORT_BUNIT 0x3 |
523 | #define IOSF_PORT_BUNIT 0x3 |
488 | #define IOSF_PORT_PUNIT 0x4 |
524 | #define IOSF_PORT_PUNIT 0x4 |
489 | #define IOSF_PORT_NC 0x11 |
525 | #define IOSF_PORT_NC 0x11 |
490 | #define IOSF_PORT_DPIO 0x12 |
526 | #define IOSF_PORT_DPIO 0x12 |
491 | #define IOSF_PORT_DPIO_2 0x1a |
527 | #define IOSF_PORT_DPIO_2 0x1a |
492 | #define IOSF_PORT_GPIO_NC 0x13 |
528 | #define IOSF_PORT_GPIO_NC 0x13 |
493 | #define IOSF_PORT_CCK 0x14 |
529 | #define IOSF_PORT_CCK 0x14 |
494 | #define IOSF_PORT_CCU 0xA9 |
530 | #define IOSF_PORT_CCU 0xA9 |
495 | #define IOSF_PORT_GPS_CORE 0x48 |
531 | #define IOSF_PORT_GPS_CORE 0x48 |
496 | #define IOSF_PORT_FLISDSI 0x1B |
532 | #define IOSF_PORT_FLISDSI 0x1B |
497 | #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) |
533 | #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) |
498 | #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) |
534 | #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) |
499 | 535 | ||
500 | /* See configdb bunit SB addr map */ |
536 | /* See configdb bunit SB addr map */ |
501 | #define BUNIT_REG_BISOC 0x11 |
537 | #define BUNIT_REG_BISOC 0x11 |
502 | 538 | ||
503 | #define PUNIT_REG_DSPFREQ 0x36 |
539 | #define PUNIT_REG_DSPFREQ 0x36 |
- | 540 | #define DSPFREQSTAT_SHIFT_CHV 24 |
|
- | 541 | #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) |
|
- | 542 | #define DSPFREQGUAR_SHIFT_CHV 8 |
|
- | 543 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) |
|
504 | #define DSPFREQSTAT_SHIFT 30 |
544 | #define DSPFREQSTAT_SHIFT 30 |
505 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
545 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
506 | #define DSPFREQGUAR_SHIFT 14 |
546 | #define DSPFREQGUAR_SHIFT 14 |
507 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
547 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
- | 548 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
|
- | 549 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) |
|
- | 550 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) |
|
- | 551 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) |
|
- | 552 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) |
|
- | 553 | #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) |
|
- | 554 | #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) |
|
- | 555 | #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) |
|
- | 556 | #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) |
|
- | 557 | #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) |
|
- | 558 | #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) |
|
- | 559 | #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) |
|
508 | 560 | ||
509 | /* See the PUNIT HAS v0.8 for the below bits */ |
561 | /* See the PUNIT HAS v0.8 for the below bits */ |
510 | enum punit_power_well { |
562 | enum punit_power_well { |
511 | PUNIT_POWER_WELL_RENDER = 0, |
563 | PUNIT_POWER_WELL_RENDER = 0, |
512 | PUNIT_POWER_WELL_MEDIA = 1, |
564 | PUNIT_POWER_WELL_MEDIA = 1, |
513 | PUNIT_POWER_WELL_DISP2D = 3, |
565 | PUNIT_POWER_WELL_DISP2D = 3, |
514 | PUNIT_POWER_WELL_DPIO_CMN_BC = 5, |
566 | PUNIT_POWER_WELL_DPIO_CMN_BC = 5, |
515 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, |
567 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, |
516 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, |
568 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, |
517 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, |
569 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, |
518 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, |
570 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, |
519 | PUNIT_POWER_WELL_DPIO_RX0 = 10, |
571 | PUNIT_POWER_WELL_DPIO_RX0 = 10, |
520 | PUNIT_POWER_WELL_DPIO_RX1 = 11, |
572 | PUNIT_POWER_WELL_DPIO_RX1 = 11, |
- | 573 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
|
- | 574 | /* FIXME: guesswork below */ |
|
- | 575 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, |
|
- | 576 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, |
|
- | 577 | PUNIT_POWER_WELL_DPIO_RX2 = 15, |
|
521 | 578 | ||
522 | PUNIT_POWER_WELL_NUM, |
579 | PUNIT_POWER_WELL_NUM, |
523 | }; |
580 | }; |
524 | 581 | ||
525 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
582 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
526 | #define PUNIT_REG_PWRGT_STATUS 0x61 |
583 | #define PUNIT_REG_PWRGT_STATUS 0x61 |
527 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
584 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
528 | #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) |
585 | #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) |
529 | #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) |
586 | #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) |
530 | #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) |
587 | #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) |
531 | #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) |
588 | #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) |
532 | 589 | ||
533 | #define PUNIT_REG_GPU_LFM 0xd3 |
590 | #define PUNIT_REG_GPU_LFM 0xd3 |
534 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
591 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
535 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 |
592 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 |
- | 593 | #define GPLLENABLE (1<<4) |
|
536 | #define GENFREQSTATUS (1<<0) |
594 | #define GENFREQSTATUS (1<<0) |
537 | #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
595 | #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
538 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
596 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
539 | 597 | ||
540 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ |
598 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ |
541 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ |
599 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ |
542 | 600 | ||
543 | #define PUNIT_GPU_STATUS_REG 0xdb |
601 | #define PUNIT_GPU_STATUS_REG 0xdb |
544 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 |
602 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 |
545 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |
603 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |
546 | #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 |
604 | #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 |
547 | #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff |
605 | #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff |
548 | 606 | ||
549 | #define PUNIT_GPU_DUTYCYCLE_REG 0xdf |
607 | #define PUNIT_GPU_DUTYCYCLE_REG 0xdf |
550 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 |
608 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 |
551 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff |
609 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff |
552 | 610 | ||
553 | #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
611 | #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
554 | #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 |
612 | #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 |
555 | #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 |
613 | #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 |
556 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 |
614 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 |
557 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 |
615 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 |
558 | #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 |
616 | #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 |
559 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
617 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
560 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
618 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
561 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
619 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
562 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
620 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
563 | 621 | ||
564 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
622 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
565 | #define VLV_RP_UP_EI_THRESHOLD 90 |
623 | #define VLV_RP_UP_EI_THRESHOLD 90 |
566 | #define VLV_RP_DOWN_EI_THRESHOLD 70 |
624 | #define VLV_RP_DOWN_EI_THRESHOLD 70 |
567 | #define VLV_INT_COUNT_FOR_DOWN_EI 5 |
625 | #define VLV_INT_COUNT_FOR_DOWN_EI 5 |
568 | 626 | ||
569 | /* vlv2 north clock has */ |
627 | /* vlv2 north clock has */ |
570 | #define CCK_FUSE_REG 0x8 |
628 | #define CCK_FUSE_REG 0x8 |
571 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 |
629 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 |
572 | #define CCK_REG_DSI_PLL_FUSE 0x44 |
630 | #define CCK_REG_DSI_PLL_FUSE 0x44 |
573 | #define CCK_REG_DSI_PLL_CONTROL 0x48 |
631 | #define CCK_REG_DSI_PLL_CONTROL 0x48 |
574 | #define DSI_PLL_VCO_EN (1 << 31) |
632 | #define DSI_PLL_VCO_EN (1 << 31) |
575 | #define DSI_PLL_LDO_GATE (1 << 30) |
633 | #define DSI_PLL_LDO_GATE (1 << 30) |
576 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 |
634 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 |
577 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) |
635 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) |
578 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) |
636 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) |
579 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) |
637 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) |
580 | #define DSI_PLL_MUX_MASK (3 << 9) |
638 | #define DSI_PLL_MUX_MASK (3 << 9) |
581 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) |
639 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) |
582 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) |
640 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) |
583 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) |
641 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) |
584 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) |
642 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) |
585 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) |
643 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) |
586 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) |
644 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) |
587 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) |
645 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) |
588 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) |
646 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) |
589 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) |
647 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) |
590 | #define DSI_PLL_LOCK (1 << 0) |
648 | #define DSI_PLL_LOCK (1 << 0) |
591 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c |
649 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c |
592 | #define DSI_PLL_LFSR (1 << 31) |
650 | #define DSI_PLL_LFSR (1 << 31) |
593 | #define DSI_PLL_FRACTION_EN (1 << 30) |
651 | #define DSI_PLL_FRACTION_EN (1 << 30) |
594 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 |
652 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 |
595 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) |
653 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) |
596 | #define DSI_PLL_USYNC_CNT_SHIFT 18 |
654 | #define DSI_PLL_USYNC_CNT_SHIFT 18 |
597 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) |
655 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) |
598 | #define DSI_PLL_N1_DIV_SHIFT 16 |
656 | #define DSI_PLL_N1_DIV_SHIFT 16 |
599 | #define DSI_PLL_N1_DIV_MASK (3 << 16) |
657 | #define DSI_PLL_N1_DIV_MASK (3 << 16) |
600 | #define DSI_PLL_M1_DIV_SHIFT 0 |
658 | #define DSI_PLL_M1_DIV_SHIFT 0 |
601 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
659 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
602 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
660 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
603 | #define DISPLAY_TRUNK_FORCE_ON (1 << 17) |
661 | #define DISPLAY_TRUNK_FORCE_ON (1 << 17) |
604 | #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) |
662 | #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) |
605 | #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) |
663 | #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) |
606 | #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 |
664 | #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 |
607 | #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) |
665 | #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) |
608 | 666 | ||
609 | /** |
667 | /** |
610 | * DOC: DPIO |
668 | * DOC: DPIO |
611 | * |
669 | * |
612 | * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI |
670 | * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI |
613 | * ports. DPIO is the name given to such a display PHY. These PHYs |
671 | * ports. DPIO is the name given to such a display PHY. These PHYs |
614 | * don't follow the standard programming model using direct MMIO |
672 | * don't follow the standard programming model using direct MMIO |
615 | * registers, and instead their registers must be accessed trough IOSF |
673 | * registers, and instead their registers must be accessed trough IOSF |
616 | * sideband. VLV has one such PHY for driving ports B and C, and CHV |
674 | * sideband. VLV has one such PHY for driving ports B and C, and CHV |
617 | * adds another PHY for driving port D. Each PHY responds to specific |
675 | * adds another PHY for driving port D. Each PHY responds to specific |
618 | * IOSF-SB port. |
676 | * IOSF-SB port. |
619 | * |
677 | * |
620 | * Each display PHY is made up of one or two channels. Each channel |
678 | * Each display PHY is made up of one or two channels. Each channel |
621 | * houses a common lane part which contains the PLL and other common |
679 | * houses a common lane part which contains the PLL and other common |
622 | * logic. CH0 common lane also contains the IOSF-SB logic for the |
680 | * logic. CH0 common lane also contains the IOSF-SB logic for the |
623 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock |
681 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock |
624 | * must be running when any DPIO registers are accessed. |
682 | * must be running when any DPIO registers are accessed. |
625 | * |
683 | * |
626 | * In addition to having their own registers, the PHYs are also |
684 | * In addition to having their own registers, the PHYs are also |
627 | * controlled through some dedicated signals from the display |
685 | * controlled through some dedicated signals from the display |
628 | * controller. These include PLL reference clock enable, PLL enable, |
686 | * controller. These include PLL reference clock enable, PLL enable, |
629 | * and CRI clock selection, for example. |
687 | * and CRI clock selection, for example. |
630 | * |
688 | * |
631 | * Eeach channel also has two splines (also called data lanes), and |
689 | * Eeach channel also has two splines (also called data lanes), and |
632 | * each spline is made up of one Physical Access Coding Sub-Layer |
690 | * each spline is made up of one Physical Access Coding Sub-Layer |
633 | * (PCS) block and two TX lanes. So each channel has two PCS blocks |
691 | * (PCS) block and two TX lanes. So each channel has two PCS blocks |
634 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS |
692 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS |
635 | * data/clock pairs depending on the output type. |
693 | * data/clock pairs depending on the output type. |
636 | * |
694 | * |
637 | * Additionally the PHY also contains an AUX lane with AUX blocks |
695 | * Additionally the PHY also contains an AUX lane with AUX blocks |
638 | * for each channel. This is used for DP AUX communication, but |
696 | * for each channel. This is used for DP AUX communication, but |
639 | * this fact isn't really relevant for the driver since AUX is |
697 | * this fact isn't really relevant for the driver since AUX is |
640 | * controlled from the display controller side. No DPIO registers |
698 | * controlled from the display controller side. No DPIO registers |
641 | * need to be accessed during AUX communication, |
699 | * need to be accessed during AUX communication, |
642 | * |
700 | * |
643 | * Generally the common lane corresponds to the pipe and |
701 | * Generally the common lane corresponds to the pipe and |
644 | * the spline (PCS/TX) correponds to the port. |
702 | * the spline (PCS/TX) corresponds to the port. |
645 | * |
703 | * |
646 | * For dual channel PHY (VLV/CHV): |
704 | * For dual channel PHY (VLV/CHV): |
647 | * |
705 | * |
648 | * pipe A == CMN/PLL/REF CH0 |
706 | * pipe A == CMN/PLL/REF CH0 |
649 | * |
707 | * |
650 | * pipe B == CMN/PLL/REF CH1 |
708 | * pipe B == CMN/PLL/REF CH1 |
651 | * |
709 | * |
652 | * port B == PCS/TX CH0 |
710 | * port B == PCS/TX CH0 |
653 | * |
711 | * |
654 | * port C == PCS/TX CH1 |
712 | * port C == PCS/TX CH1 |
655 | * |
713 | * |
656 | * This is especially important when we cross the streams |
714 | * This is especially important when we cross the streams |
657 | * ie. drive port B with pipe B, or port C with pipe A. |
715 | * ie. drive port B with pipe B, or port C with pipe A. |
658 | * |
716 | * |
659 | * For single channel PHY (CHV): |
717 | * For single channel PHY (CHV): |
660 | * |
718 | * |
661 | * pipe C == CMN/PLL/REF CH0 |
719 | * pipe C == CMN/PLL/REF CH0 |
662 | * |
720 | * |
663 | * port D == PCS/TX CH0 |
721 | * port D == PCS/TX CH0 |
664 | * |
722 | * |
665 | * Note: digital port B is DDI0, digital port C is DDI1, |
723 | * Note: digital port B is DDI0, digital port C is DDI1, |
666 | * digital port D is DDI2 |
724 | * digital port D is DDI2 |
667 | */ |
725 | */ |
668 | /* |
726 | /* |
669 | * Dual channel PHY (VLV/CHV) |
727 | * Dual channel PHY (VLV/CHV) |
670 | * --------------------------------- |
728 | * --------------------------------- |
671 | * | CH0 | CH1 | |
729 | * | CH0 | CH1 | |
672 | * | CMN/PLL/REF | CMN/PLL/REF | |
730 | * | CMN/PLL/REF | CMN/PLL/REF | |
673 | * |---------------|---------------| Display PHY |
731 | * |---------------|---------------| Display PHY |
674 | * | PCS01 | PCS23 | PCS01 | PCS23 | |
732 | * | PCS01 | PCS23 | PCS01 | PCS23 | |
675 | * |-------|-------|-------|-------| |
733 | * |-------|-------|-------|-------| |
676 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| |
734 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| |
677 | * --------------------------------- |
735 | * --------------------------------- |
678 | * | DDI0 | DDI1 | DP/HDMI ports |
736 | * | DDI0 | DDI1 | DP/HDMI ports |
679 | * --------------------------------- |
737 | * --------------------------------- |
680 | * |
738 | * |
681 | * Single channel PHY (CHV) |
739 | * Single channel PHY (CHV) |
682 | * ----------------- |
740 | * ----------------- |
683 | * | CH0 | |
741 | * | CH0 | |
684 | * | CMN/PLL/REF | |
742 | * | CMN/PLL/REF | |
685 | * |---------------| Display PHY |
743 | * |---------------| Display PHY |
686 | * | PCS01 | PCS23 | |
744 | * | PCS01 | PCS23 | |
687 | * |-------|-------| |
745 | * |-------|-------| |
688 | * |TX0|TX1|TX2|TX3| |
746 | * |TX0|TX1|TX2|TX3| |
689 | * ----------------- |
747 | * ----------------- |
690 | * | DDI2 | DP/HDMI port |
748 | * | DDI2 | DP/HDMI port |
691 | * ----------------- |
749 | * ----------------- |
692 | */ |
750 | */ |
693 | #define DPIO_DEVFN 0 |
751 | #define DPIO_DEVFN 0 |
694 | 752 | ||
695 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) |
753 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) |
696 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
754 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
697 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
755 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
698 | #define DPIO_SFR_BYPASS (1<<1) |
756 | #define DPIO_SFR_BYPASS (1<<1) |
699 | #define DPIO_CMNRST (1<<0) |
757 | #define DPIO_CMNRST (1<<0) |
700 | 758 | ||
701 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
759 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
702 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) |
760 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) |
703 | 761 | ||
704 | /* |
762 | /* |
705 | * Per pipe/PLL DPIO regs |
763 | * Per pipe/PLL DPIO regs |
706 | */ |
764 | */ |
707 | #define _VLV_PLL_DW3_CH0 0x800c |
765 | #define _VLV_PLL_DW3_CH0 0x800c |
708 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
766 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
709 | #define DPIO_POST_DIV_DAC 0 |
767 | #define DPIO_POST_DIV_DAC 0 |
710 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ |
768 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ |
711 | #define DPIO_POST_DIV_LVDS1 2 |
769 | #define DPIO_POST_DIV_LVDS1 2 |
712 | #define DPIO_POST_DIV_LVDS2 3 |
770 | #define DPIO_POST_DIV_LVDS2 3 |
713 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
771 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
714 | #define DPIO_P1_SHIFT (21) /* 3 bits */ |
772 | #define DPIO_P1_SHIFT (21) /* 3 bits */ |
715 | #define DPIO_P2_SHIFT (16) /* 5 bits */ |
773 | #define DPIO_P2_SHIFT (16) /* 5 bits */ |
716 | #define DPIO_N_SHIFT (12) /* 4 bits */ |
774 | #define DPIO_N_SHIFT (12) /* 4 bits */ |
717 | #define DPIO_ENABLE_CALIBRATION (1<<11) |
775 | #define DPIO_ENABLE_CALIBRATION (1<<11) |
718 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
776 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
719 | #define DPIO_M2DIV_MASK 0xff |
777 | #define DPIO_M2DIV_MASK 0xff |
720 | #define _VLV_PLL_DW3_CH1 0x802c |
778 | #define _VLV_PLL_DW3_CH1 0x802c |
721 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) |
779 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) |
722 | 780 | ||
723 | #define _VLV_PLL_DW5_CH0 0x8014 |
781 | #define _VLV_PLL_DW5_CH0 0x8014 |
724 | #define DPIO_REFSEL_OVERRIDE 27 |
782 | #define DPIO_REFSEL_OVERRIDE 27 |
725 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
783 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
726 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
784 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
727 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
785 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
728 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
786 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
729 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
787 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
730 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
788 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
731 | #define _VLV_PLL_DW5_CH1 0x8034 |
789 | #define _VLV_PLL_DW5_CH1 0x8034 |
732 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) |
790 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) |
733 | 791 | ||
734 | #define _VLV_PLL_DW7_CH0 0x801c |
792 | #define _VLV_PLL_DW7_CH0 0x801c |
735 | #define _VLV_PLL_DW7_CH1 0x803c |
793 | #define _VLV_PLL_DW7_CH1 0x803c |
736 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) |
794 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) |
737 | 795 | ||
738 | #define _VLV_PLL_DW8_CH0 0x8040 |
796 | #define _VLV_PLL_DW8_CH0 0x8040 |
739 | #define _VLV_PLL_DW8_CH1 0x8060 |
797 | #define _VLV_PLL_DW8_CH1 0x8060 |
740 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) |
798 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) |
741 | 799 | ||
742 | #define VLV_PLL_DW9_BCAST 0xc044 |
800 | #define VLV_PLL_DW9_BCAST 0xc044 |
743 | #define _VLV_PLL_DW9_CH0 0x8044 |
801 | #define _VLV_PLL_DW9_CH0 0x8044 |
744 | #define _VLV_PLL_DW9_CH1 0x8064 |
802 | #define _VLV_PLL_DW9_CH1 0x8064 |
745 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) |
803 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) |
746 | 804 | ||
747 | #define _VLV_PLL_DW10_CH0 0x8048 |
805 | #define _VLV_PLL_DW10_CH0 0x8048 |
748 | #define _VLV_PLL_DW10_CH1 0x8068 |
806 | #define _VLV_PLL_DW10_CH1 0x8068 |
749 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) |
807 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) |
750 | 808 | ||
751 | #define _VLV_PLL_DW11_CH0 0x804c |
809 | #define _VLV_PLL_DW11_CH0 0x804c |
752 | #define _VLV_PLL_DW11_CH1 0x806c |
810 | #define _VLV_PLL_DW11_CH1 0x806c |
753 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) |
811 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) |
754 | 812 | ||
755 | /* Spec for ref block start counts at DW10 */ |
813 | /* Spec for ref block start counts at DW10 */ |
756 | #define VLV_REF_DW13 0x80ac |
814 | #define VLV_REF_DW13 0x80ac |
757 | 815 | ||
758 | #define VLV_CMN_DW0 0x8100 |
816 | #define VLV_CMN_DW0 0x8100 |
759 | 817 | ||
760 | /* |
818 | /* |
761 | * Per DDI channel DPIO regs |
819 | * Per DDI channel DPIO regs |
762 | */ |
820 | */ |
763 | 821 | ||
764 | #define _VLV_PCS_DW0_CH0 0x8200 |
822 | #define _VLV_PCS_DW0_CH0 0x8200 |
765 | #define _VLV_PCS_DW0_CH1 0x8400 |
823 | #define _VLV_PCS_DW0_CH1 0x8400 |
766 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
824 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
767 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) |
825 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) |
- | 826 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) |
|
- | 827 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) |
|
768 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
828 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
769 | 829 | ||
770 | #define _VLV_PCS01_DW0_CH0 0x200 |
830 | #define _VLV_PCS01_DW0_CH0 0x200 |
771 | #define _VLV_PCS23_DW0_CH0 0x400 |
831 | #define _VLV_PCS23_DW0_CH0 0x400 |
772 | #define _VLV_PCS01_DW0_CH1 0x2600 |
832 | #define _VLV_PCS01_DW0_CH1 0x2600 |
773 | #define _VLV_PCS23_DW0_CH1 0x2800 |
833 | #define _VLV_PCS23_DW0_CH1 0x2800 |
774 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) |
834 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) |
775 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) |
835 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) |
776 | 836 | ||
777 | #define _VLV_PCS_DW1_CH0 0x8204 |
837 | #define _VLV_PCS_DW1_CH0 0x8204 |
778 | #define _VLV_PCS_DW1_CH1 0x8404 |
838 | #define _VLV_PCS_DW1_CH1 0x8404 |
779 | #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) |
839 | #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) |
780 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
840 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
781 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) |
841 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) |
782 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
842 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
783 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) |
843 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) |
784 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
844 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
785 | 845 | ||
786 | #define _VLV_PCS01_DW1_CH0 0x204 |
846 | #define _VLV_PCS01_DW1_CH0 0x204 |
787 | #define _VLV_PCS23_DW1_CH0 0x404 |
847 | #define _VLV_PCS23_DW1_CH0 0x404 |
788 | #define _VLV_PCS01_DW1_CH1 0x2604 |
848 | #define _VLV_PCS01_DW1_CH1 0x2604 |
789 | #define _VLV_PCS23_DW1_CH1 0x2804 |
849 | #define _VLV_PCS23_DW1_CH1 0x2804 |
790 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) |
850 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) |
791 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) |
851 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) |
792 | 852 | ||
793 | #define _VLV_PCS_DW8_CH0 0x8220 |
853 | #define _VLV_PCS_DW8_CH0 0x8220 |
794 | #define _VLV_PCS_DW8_CH1 0x8420 |
854 | #define _VLV_PCS_DW8_CH1 0x8420 |
795 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
855 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
796 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) |
856 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) |
797 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
857 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
798 | 858 | ||
799 | #define _VLV_PCS01_DW8_CH0 0x0220 |
859 | #define _VLV_PCS01_DW8_CH0 0x0220 |
800 | #define _VLV_PCS23_DW8_CH0 0x0420 |
860 | #define _VLV_PCS23_DW8_CH0 0x0420 |
801 | #define _VLV_PCS01_DW8_CH1 0x2620 |
861 | #define _VLV_PCS01_DW8_CH1 0x2620 |
802 | #define _VLV_PCS23_DW8_CH1 0x2820 |
862 | #define _VLV_PCS23_DW8_CH1 0x2820 |
803 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) |
863 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) |
804 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) |
864 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) |
805 | 865 | ||
806 | #define _VLV_PCS_DW9_CH0 0x8224 |
866 | #define _VLV_PCS_DW9_CH0 0x8224 |
807 | #define _VLV_PCS_DW9_CH1 0x8424 |
867 | #define _VLV_PCS_DW9_CH1 0x8424 |
- | 868 | #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) |
|
- | 869 | #define DPIO_PCS_TX2MARGIN_000 (0<<13) |
|
- | 870 | #define DPIO_PCS_TX2MARGIN_101 (1<<13) |
|
- | 871 | #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) |
|
- | 872 | #define DPIO_PCS_TX1MARGIN_000 (0<<10) |
|
- | 873 | #define DPIO_PCS_TX1MARGIN_101 (1<<10) |
|
808 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
874 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
- | 875 | ||
- | 876 | #define _VLV_PCS01_DW9_CH0 0x224 |
|
- | 877 | #define _VLV_PCS23_DW9_CH0 0x424 |
|
- | 878 | #define _VLV_PCS01_DW9_CH1 0x2624 |
|
- | 879 | #define _VLV_PCS23_DW9_CH1 0x2824 |
|
- | 880 | #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) |
|
- | 881 | #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) |
|
809 | 882 | ||
810 | #define _CHV_PCS_DW10_CH0 0x8228 |
883 | #define _CHV_PCS_DW10_CH0 0x8228 |
811 | #define _CHV_PCS_DW10_CH1 0x8428 |
884 | #define _CHV_PCS_DW10_CH1 0x8428 |
812 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) |
885 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) |
813 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) |
886 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) |
- | 887 | #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) |
|
- | 888 | #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) |
|
- | 889 | #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) |
|
- | 890 | #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) |
|
- | 891 | #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) |
|
- | 892 | #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) |
|
814 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
893 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
815 | 894 | ||
816 | #define _VLV_PCS01_DW10_CH0 0x0228 |
895 | #define _VLV_PCS01_DW10_CH0 0x0228 |
817 | #define _VLV_PCS23_DW10_CH0 0x0428 |
896 | #define _VLV_PCS23_DW10_CH0 0x0428 |
818 | #define _VLV_PCS01_DW10_CH1 0x2628 |
897 | #define _VLV_PCS01_DW10_CH1 0x2628 |
819 | #define _VLV_PCS23_DW10_CH1 0x2828 |
898 | #define _VLV_PCS23_DW10_CH1 0x2828 |
820 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
899 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
821 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
900 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
822 | 901 | ||
823 | #define _VLV_PCS_DW11_CH0 0x822c |
902 | #define _VLV_PCS_DW11_CH0 0x822c |
824 | #define _VLV_PCS_DW11_CH1 0x842c |
903 | #define _VLV_PCS_DW11_CH1 0x842c |
- | 904 | #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) |
|
- | 905 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) |
|
- | 906 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) |
|
825 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
907 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
- | 908 | ||
- | 909 | #define _VLV_PCS01_DW11_CH0 0x022c |
|
- | 910 | #define _VLV_PCS23_DW11_CH0 0x042c |
|
- | 911 | #define _VLV_PCS01_DW11_CH1 0x262c |
|
- | 912 | #define _VLV_PCS23_DW11_CH1 0x282c |
|
- | 913 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
|
- | 914 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) |
|
826 | 915 | ||
827 | #define _VLV_PCS_DW12_CH0 0x8230 |
916 | #define _VLV_PCS_DW12_CH0 0x8230 |
828 | #define _VLV_PCS_DW12_CH1 0x8430 |
917 | #define _VLV_PCS_DW12_CH1 0x8430 |
829 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
918 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
830 | 919 | ||
831 | #define _VLV_PCS_DW14_CH0 0x8238 |
920 | #define _VLV_PCS_DW14_CH0 0x8238 |
832 | #define _VLV_PCS_DW14_CH1 0x8438 |
921 | #define _VLV_PCS_DW14_CH1 0x8438 |
833 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) |
922 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) |
834 | 923 | ||
835 | #define _VLV_PCS_DW23_CH0 0x825c |
924 | #define _VLV_PCS_DW23_CH0 0x825c |
836 | #define _VLV_PCS_DW23_CH1 0x845c |
925 | #define _VLV_PCS_DW23_CH1 0x845c |
837 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) |
926 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) |
838 | 927 | ||
839 | #define _VLV_TX_DW2_CH0 0x8288 |
928 | #define _VLV_TX_DW2_CH0 0x8288 |
840 | #define _VLV_TX_DW2_CH1 0x8488 |
929 | #define _VLV_TX_DW2_CH1 0x8488 |
841 | #define DPIO_SWING_MARGIN_SHIFT 16 |
930 | #define DPIO_SWING_MARGIN000_SHIFT 16 |
842 | #define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) |
931 | #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) |
843 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
932 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
844 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
933 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
845 | 934 | ||
846 | #define _VLV_TX_DW3_CH0 0x828c |
935 | #define _VLV_TX_DW3_CH0 0x828c |
847 | #define _VLV_TX_DW3_CH1 0x848c |
936 | #define _VLV_TX_DW3_CH1 0x848c |
848 | /* The following bit for CHV phy */ |
937 | /* The following bit for CHV phy */ |
849 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) |
938 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) |
- | 939 | #define DPIO_SWING_MARGIN101_SHIFT 16 |
|
- | 940 | #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) |
|
850 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
941 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
851 | 942 | ||
852 | #define _VLV_TX_DW4_CH0 0x8290 |
943 | #define _VLV_TX_DW4_CH0 0x8290 |
853 | #define _VLV_TX_DW4_CH1 0x8490 |
944 | #define _VLV_TX_DW4_CH1 0x8490 |
854 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
945 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
855 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) |
946 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) |
- | 947 | #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
|
- | 948 | #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) |
|
856 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
949 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
857 | 950 | ||
858 | #define _VLV_TX3_DW4_CH0 0x690 |
951 | #define _VLV_TX3_DW4_CH0 0x690 |
859 | #define _VLV_TX3_DW4_CH1 0x2a90 |
952 | #define _VLV_TX3_DW4_CH1 0x2a90 |
860 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) |
953 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) |
861 | 954 | ||
862 | #define _VLV_TX_DW5_CH0 0x8294 |
955 | #define _VLV_TX_DW5_CH0 0x8294 |
863 | #define _VLV_TX_DW5_CH1 0x8494 |
956 | #define _VLV_TX_DW5_CH1 0x8494 |
864 | #define DPIO_TX_OCALINIT_EN (1<<31) |
957 | #define DPIO_TX_OCALINIT_EN (1<<31) |
865 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
958 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
866 | 959 | ||
867 | #define _VLV_TX_DW11_CH0 0x82ac |
960 | #define _VLV_TX_DW11_CH0 0x82ac |
868 | #define _VLV_TX_DW11_CH1 0x84ac |
961 | #define _VLV_TX_DW11_CH1 0x84ac |
869 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) |
962 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) |
870 | 963 | ||
871 | #define _VLV_TX_DW14_CH0 0x82b8 |
964 | #define _VLV_TX_DW14_CH0 0x82b8 |
872 | #define _VLV_TX_DW14_CH1 0x84b8 |
965 | #define _VLV_TX_DW14_CH1 0x84b8 |
873 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) |
966 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) |
874 | 967 | ||
875 | /* CHV dpPhy registers */ |
968 | /* CHV dpPhy registers */ |
876 | #define _CHV_PLL_DW0_CH0 0x8000 |
969 | #define _CHV_PLL_DW0_CH0 0x8000 |
877 | #define _CHV_PLL_DW0_CH1 0x8180 |
970 | #define _CHV_PLL_DW0_CH1 0x8180 |
878 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) |
971 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) |
879 | 972 | ||
880 | #define _CHV_PLL_DW1_CH0 0x8004 |
973 | #define _CHV_PLL_DW1_CH0 0x8004 |
881 | #define _CHV_PLL_DW1_CH1 0x8184 |
974 | #define _CHV_PLL_DW1_CH1 0x8184 |
882 | #define DPIO_CHV_N_DIV_SHIFT 8 |
975 | #define DPIO_CHV_N_DIV_SHIFT 8 |
883 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) |
976 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) |
884 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) |
977 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) |
885 | 978 | ||
886 | #define _CHV_PLL_DW2_CH0 0x8008 |
979 | #define _CHV_PLL_DW2_CH0 0x8008 |
887 | #define _CHV_PLL_DW2_CH1 0x8188 |
980 | #define _CHV_PLL_DW2_CH1 0x8188 |
888 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) |
981 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) |
889 | 982 | ||
890 | #define _CHV_PLL_DW3_CH0 0x800c |
983 | #define _CHV_PLL_DW3_CH0 0x800c |
891 | #define _CHV_PLL_DW3_CH1 0x818c |
984 | #define _CHV_PLL_DW3_CH1 0x818c |
892 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
985 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
893 | #define DPIO_CHV_FIRST_MOD (0 << 8) |
986 | #define DPIO_CHV_FIRST_MOD (0 << 8) |
894 | #define DPIO_CHV_SECOND_MOD (1 << 8) |
987 | #define DPIO_CHV_SECOND_MOD (1 << 8) |
895 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
988 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
896 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
989 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
897 | 990 | ||
898 | #define _CHV_PLL_DW6_CH0 0x8018 |
991 | #define _CHV_PLL_DW6_CH0 0x8018 |
899 | #define _CHV_PLL_DW6_CH1 0x8198 |
992 | #define _CHV_PLL_DW6_CH1 0x8198 |
900 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
993 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
901 | #define DPIO_CHV_INT_COEFF_SHIFT 8 |
994 | #define DPIO_CHV_INT_COEFF_SHIFT 8 |
902 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 |
995 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 |
903 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
996 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
904 | 997 | ||
905 | #define _CHV_CMN_DW5_CH0 0x8114 |
998 | #define _CHV_CMN_DW5_CH0 0x8114 |
906 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
999 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
907 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
1000 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
908 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) |
1001 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) |
909 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) |
1002 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) |
910 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) |
1003 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) |
911 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) |
1004 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) |
912 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) |
1005 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) |
913 | #define CHV_BUFLEFTENA1_MASK (3 << 22) |
1006 | #define CHV_BUFLEFTENA1_MASK (3 << 22) |
914 | 1007 | ||
915 | #define _CHV_CMN_DW13_CH0 0x8134 |
1008 | #define _CHV_CMN_DW13_CH0 0x8134 |
916 | #define _CHV_CMN_DW0_CH1 0x8080 |
1009 | #define _CHV_CMN_DW0_CH1 0x8080 |
917 | #define DPIO_CHV_S1_DIV_SHIFT 21 |
1010 | #define DPIO_CHV_S1_DIV_SHIFT 21 |
918 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ |
1011 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ |
919 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ |
1012 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ |
920 | #define DPIO_CHV_K_DIV_SHIFT 4 |
1013 | #define DPIO_CHV_K_DIV_SHIFT 4 |
921 | #define DPIO_PLL_FREQLOCK (1 << 1) |
1014 | #define DPIO_PLL_FREQLOCK (1 << 1) |
922 | #define DPIO_PLL_LOCK (1 << 0) |
1015 | #define DPIO_PLL_LOCK (1 << 0) |
923 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) |
1016 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) |
924 | 1017 | ||
925 | #define _CHV_CMN_DW14_CH0 0x8138 |
1018 | #define _CHV_CMN_DW14_CH0 0x8138 |
926 | #define _CHV_CMN_DW1_CH1 0x8084 |
1019 | #define _CHV_CMN_DW1_CH1 0x8084 |
927 | #define DPIO_AFC_RECAL (1 << 14) |
1020 | #define DPIO_AFC_RECAL (1 << 14) |
928 | #define DPIO_DCLKP_EN (1 << 13) |
1021 | #define DPIO_DCLKP_EN (1 << 13) |
929 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
1022 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
930 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ |
1023 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ |
931 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ |
1024 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ |
932 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ |
1025 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ |
933 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ |
1026 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ |
934 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ |
1027 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ |
935 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ |
1028 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ |
936 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
1029 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
937 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
1030 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
938 | 1031 | ||
939 | #define _CHV_CMN_DW19_CH0 0x814c |
1032 | #define _CHV_CMN_DW19_CH0 0x814c |
940 | #define _CHV_CMN_DW6_CH1 0x8098 |
1033 | #define _CHV_CMN_DW6_CH1 0x8098 |
941 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
1034 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
942 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
1035 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
943 | 1036 | ||
944 | #define CHV_CMN_DW30 0x8178 |
1037 | #define CHV_CMN_DW30 0x8178 |
945 | #define DPIO_LRC_BYPASS (1 << 3) |
1038 | #define DPIO_LRC_BYPASS (1 << 3) |
946 | 1039 | ||
947 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ |
1040 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ |
948 | (lane) * 0x200 + (offset)) |
1041 | (lane) * 0x200 + (offset)) |
949 | 1042 | ||
950 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
1043 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
951 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) |
1044 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) |
952 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) |
1045 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) |
953 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) |
1046 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) |
954 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) |
1047 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) |
955 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) |
1048 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) |
956 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) |
1049 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) |
957 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) |
1050 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) |
958 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) |
1051 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) |
959 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) |
1052 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) |
960 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
1053 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
961 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
1054 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
962 | #define DPIO_FRC_LATENCY_SHFIT 8 |
1055 | #define DPIO_FRC_LATENCY_SHFIT 8 |
963 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
1056 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
964 | #define DPIO_UPAR_SHIFT 30 |
1057 | #define DPIO_UPAR_SHIFT 30 |
965 | /* |
1058 | /* |
966 | * Fence registers |
1059 | * Fence registers |
967 | */ |
1060 | */ |
968 | #define FENCE_REG_830_0 0x2000 |
1061 | #define FENCE_REG_830_0 0x2000 |
969 | #define FENCE_REG_945_8 0x3000 |
1062 | #define FENCE_REG_945_8 0x3000 |
970 | #define I830_FENCE_START_MASK 0x07f80000 |
1063 | #define I830_FENCE_START_MASK 0x07f80000 |
971 | #define I830_FENCE_TILING_Y_SHIFT 12 |
1064 | #define I830_FENCE_TILING_Y_SHIFT 12 |
972 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
1065 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
973 | #define I830_FENCE_PITCH_SHIFT 4 |
1066 | #define I830_FENCE_PITCH_SHIFT 4 |
974 | #define I830_FENCE_REG_VALID (1<<0) |
1067 | #define I830_FENCE_REG_VALID (1<<0) |
975 | #define I915_FENCE_MAX_PITCH_VAL 4 |
1068 | #define I915_FENCE_MAX_PITCH_VAL 4 |
976 | #define I830_FENCE_MAX_PITCH_VAL 6 |
1069 | #define I830_FENCE_MAX_PITCH_VAL 6 |
977 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
1070 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
978 | 1071 | ||
979 | #define I915_FENCE_START_MASK 0x0ff00000 |
1072 | #define I915_FENCE_START_MASK 0x0ff00000 |
980 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
1073 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
981 | 1074 | ||
982 | #define FENCE_REG_965_0 0x03000 |
1075 | #define FENCE_REG_965_0 0x03000 |
983 | #define I965_FENCE_PITCH_SHIFT 2 |
1076 | #define I965_FENCE_PITCH_SHIFT 2 |
984 | #define I965_FENCE_TILING_Y_SHIFT 1 |
1077 | #define I965_FENCE_TILING_Y_SHIFT 1 |
985 | #define I965_FENCE_REG_VALID (1<<0) |
1078 | #define I965_FENCE_REG_VALID (1<<0) |
986 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
1079 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
987 | 1080 | ||
988 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
1081 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
989 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
1082 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
990 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
1083 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
991 | 1084 | ||
992 | 1085 | ||
993 | /* control register for cpu gtt access */ |
1086 | /* control register for cpu gtt access */ |
994 | #define TILECTL 0x101000 |
1087 | #define TILECTL 0x101000 |
995 | #define TILECTL_SWZCTL (1 << 0) |
1088 | #define TILECTL_SWZCTL (1 << 0) |
996 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
1089 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
997 | #define TILECTL_BACKSNOOP_DIS (1 << 3) |
1090 | #define TILECTL_BACKSNOOP_DIS (1 << 3) |
998 | 1091 | ||
999 | /* |
1092 | /* |
1000 | * Instruction and interrupt control regs |
1093 | * Instruction and interrupt control regs |
1001 | */ |
1094 | */ |
1002 | #define PGTBL_CTL 0x02020 |
1095 | #define PGTBL_CTL 0x02020 |
1003 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
1096 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
1004 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
1097 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
1005 | #define PGTBL_ER 0x02024 |
1098 | #define PGTBL_ER 0x02024 |
- | 1099 | #define PRB0_BASE (0x2030-0x30) |
|
- | 1100 | #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ |
|
- | 1101 | #define PRB2_BASE (0x2050-0x30) /* gen3 */ |
|
- | 1102 | #define SRB0_BASE (0x2100-0x30) /* gen2 */ |
|
- | 1103 | #define SRB1_BASE (0x2110-0x30) /* gen2 */ |
|
- | 1104 | #define SRB2_BASE (0x2120-0x30) /* 830 */ |
|
- | 1105 | #define SRB3_BASE (0x2130-0x30) /* 830 */ |
|
1006 | #define RENDER_RING_BASE 0x02000 |
1106 | #define RENDER_RING_BASE 0x02000 |
1007 | #define BSD_RING_BASE 0x04000 |
1107 | #define BSD_RING_BASE 0x04000 |
1008 | #define GEN6_BSD_RING_BASE 0x12000 |
1108 | #define GEN6_BSD_RING_BASE 0x12000 |
1009 | #define GEN8_BSD2_RING_BASE 0x1c000 |
1109 | #define GEN8_BSD2_RING_BASE 0x1c000 |
1010 | #define VEBOX_RING_BASE 0x1a000 |
1110 | #define VEBOX_RING_BASE 0x1a000 |
1011 | #define BLT_RING_BASE 0x22000 |
1111 | #define BLT_RING_BASE 0x22000 |
1012 | #define RING_TAIL(base) ((base)+0x30) |
1112 | #define RING_TAIL(base) ((base)+0x30) |
1013 | #define RING_HEAD(base) ((base)+0x34) |
1113 | #define RING_HEAD(base) ((base)+0x34) |
1014 | #define RING_START(base) ((base)+0x38) |
1114 | #define RING_START(base) ((base)+0x38) |
1015 | #define RING_CTL(base) ((base)+0x3c) |
1115 | #define RING_CTL(base) ((base)+0x3c) |
1016 | #define RING_SYNC_0(base) ((base)+0x40) |
1116 | #define RING_SYNC_0(base) ((base)+0x40) |
1017 | #define RING_SYNC_1(base) ((base)+0x44) |
1117 | #define RING_SYNC_1(base) ((base)+0x44) |
1018 | #define RING_SYNC_2(base) ((base)+0x48) |
1118 | #define RING_SYNC_2(base) ((base)+0x48) |
1019 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
1119 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
1020 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) |
1120 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) |
1021 | #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) |
1121 | #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) |
1022 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) |
1122 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) |
1023 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) |
1123 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) |
1024 | #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) |
1124 | #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) |
1025 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
1125 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
1026 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
1126 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
1027 | #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) |
1127 | #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) |
1028 | #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) |
1128 | #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) |
1029 | #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) |
1129 | #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) |
1030 | #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) |
1130 | #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) |
1031 | #define GEN6_NOSYNC 0 |
1131 | #define GEN6_NOSYNC 0 |
- | 1132 | #define RING_PSMI_CTL(base) ((base)+0x50) |
|
1032 | #define RING_MAX_IDLE(base) ((base)+0x54) |
1133 | #define RING_MAX_IDLE(base) ((base)+0x54) |
1033 | #define RING_HWS_PGA(base) ((base)+0x80) |
1134 | #define RING_HWS_PGA(base) ((base)+0x80) |
1034 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
1135 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
1035 | 1136 | ||
1036 | #define GEN7_WR_WATERMARK 0x4028 |
1137 | #define GEN7_WR_WATERMARK 0x4028 |
1037 | #define GEN7_GFX_PRIO_CTRL 0x402C |
1138 | #define GEN7_GFX_PRIO_CTRL 0x402C |
1038 | #define ARB_MODE 0x4030 |
1139 | #define ARB_MODE 0x4030 |
1039 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
1140 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
1040 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
1141 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
1041 | #define GEN7_GFX_PEND_TLB0 0x4034 |
1142 | #define GEN7_GFX_PEND_TLB0 0x4034 |
1042 | #define GEN7_GFX_PEND_TLB1 0x4038 |
1143 | #define GEN7_GFX_PEND_TLB1 0x4038 |
1043 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
1144 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
1044 | #define GEN7_LRA_LIMITS_BASE 0x403C |
1145 | #define GEN7_LRA_LIMITS_BASE 0x403C |
1045 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
1146 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
1046 | #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 |
1147 | #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 |
1047 | #define GEN7_GFX_MAX_REQ_COUNT 0x4074 |
1148 | #define GEN7_GFX_MAX_REQ_COUNT 0x4074 |
1048 | 1149 | ||
1049 | #define GAMTARBMODE 0x04a08 |
1150 | #define GAMTARBMODE 0x04a08 |
1050 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
1151 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
1051 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
1152 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
1052 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
1153 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
1053 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
1154 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
1054 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
1155 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
1055 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) |
1156 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) |
1056 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) |
1157 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) |
1057 | #define RING_FAULT_VALID (1<<0) |
1158 | #define RING_FAULT_VALID (1<<0) |
1058 | #define DONE_REG 0x40b0 |
1159 | #define DONE_REG 0x40b0 |
1059 | #define GEN8_PRIVATE_PAT 0x40e0 |
1160 | #define GEN8_PRIVATE_PAT 0x40e0 |
1060 | #define BSD_HWS_PGA_GEN7 (0x04180) |
1161 | #define BSD_HWS_PGA_GEN7 (0x04180) |
1061 | #define BLT_HWS_PGA_GEN7 (0x04280) |
1162 | #define BLT_HWS_PGA_GEN7 (0x04280) |
1062 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
1163 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
1063 | #define RING_ACTHD(base) ((base)+0x74) |
1164 | #define RING_ACTHD(base) ((base)+0x74) |
1064 | #define RING_ACTHD_UDW(base) ((base)+0x5c) |
1165 | #define RING_ACTHD_UDW(base) ((base)+0x5c) |
1065 | #define RING_NOPID(base) ((base)+0x94) |
1166 | #define RING_NOPID(base) ((base)+0x94) |
1066 | #define RING_IMR(base) ((base)+0xa8) |
1167 | #define RING_IMR(base) ((base)+0xa8) |
- | 1168 | #define RING_HWSTAM(base) ((base)+0x98) |
|
1067 | #define RING_TIMESTAMP(base) ((base)+0x358) |
1169 | #define RING_TIMESTAMP(base) ((base)+0x358) |
1068 | #define TAIL_ADDR 0x001FFFF8 |
1170 | #define TAIL_ADDR 0x001FFFF8 |
1069 | #define HEAD_WRAP_COUNT 0xFFE00000 |
1171 | #define HEAD_WRAP_COUNT 0xFFE00000 |
1070 | #define HEAD_WRAP_ONE 0x00200000 |
1172 | #define HEAD_WRAP_ONE 0x00200000 |
1071 | #define HEAD_ADDR 0x001FFFFC |
1173 | #define HEAD_ADDR 0x001FFFFC |
1072 | #define RING_NR_PAGES 0x001FF000 |
1174 | #define RING_NR_PAGES 0x001FF000 |
1073 | #define RING_REPORT_MASK 0x00000006 |
1175 | #define RING_REPORT_MASK 0x00000006 |
1074 | #define RING_REPORT_64K 0x00000002 |
1176 | #define RING_REPORT_64K 0x00000002 |
1075 | #define RING_REPORT_128K 0x00000004 |
1177 | #define RING_REPORT_128K 0x00000004 |
1076 | #define RING_NO_REPORT 0x00000000 |
1178 | #define RING_NO_REPORT 0x00000000 |
1077 | #define RING_VALID_MASK 0x00000001 |
1179 | #define RING_VALID_MASK 0x00000001 |
1078 | #define RING_VALID 0x00000001 |
1180 | #define RING_VALID 0x00000001 |
1079 | #define RING_INVALID 0x00000000 |
1181 | #define RING_INVALID 0x00000000 |
1080 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
1182 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
1081 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
1183 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
1082 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
1184 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
1083 | 1185 | ||
1084 | #define GEN7_TLB_RD_ADDR 0x4700 |
1186 | #define GEN7_TLB_RD_ADDR 0x4700 |
1085 | 1187 | ||
1086 | #if 0 |
1188 | #if 0 |
1087 | #define PRB0_TAIL 0x02030 |
1189 | #define PRB0_TAIL 0x02030 |
1088 | #define PRB0_HEAD 0x02034 |
1190 | #define PRB0_HEAD 0x02034 |
1089 | #define PRB0_START 0x02038 |
1191 | #define PRB0_START 0x02038 |
1090 | #define PRB0_CTL 0x0203c |
1192 | #define PRB0_CTL 0x0203c |
1091 | #define PRB1_TAIL 0x02040 /* 915+ only */ |
1193 | #define PRB1_TAIL 0x02040 /* 915+ only */ |
1092 | #define PRB1_HEAD 0x02044 /* 915+ only */ |
1194 | #define PRB1_HEAD 0x02044 /* 915+ only */ |
1093 | #define PRB1_START 0x02048 /* 915+ only */ |
1195 | #define PRB1_START 0x02048 /* 915+ only */ |
1094 | #define PRB1_CTL 0x0204c /* 915+ only */ |
1196 | #define PRB1_CTL 0x0204c /* 915+ only */ |
1095 | #endif |
1197 | #endif |
1096 | #define IPEIR_I965 0x02064 |
1198 | #define IPEIR_I965 0x02064 |
1097 | #define IPEHR_I965 0x02068 |
1199 | #define IPEHR_I965 0x02068 |
1098 | #define INSTDONE_I965 0x0206c |
1200 | #define INSTDONE_I965 0x0206c |
1099 | #define GEN7_INSTDONE_1 0x0206c |
1201 | #define GEN7_INSTDONE_1 0x0206c |
1100 | #define GEN7_SC_INSTDONE 0x07100 |
1202 | #define GEN7_SC_INSTDONE 0x07100 |
1101 | #define GEN7_SAMPLER_INSTDONE 0x0e160 |
1203 | #define GEN7_SAMPLER_INSTDONE 0x0e160 |
1102 | #define GEN7_ROW_INSTDONE 0x0e164 |
1204 | #define GEN7_ROW_INSTDONE 0x0e164 |
1103 | #define I915_NUM_INSTDONE_REG 4 |
1205 | #define I915_NUM_INSTDONE_REG 4 |
1104 | #define RING_IPEIR(base) ((base)+0x64) |
1206 | #define RING_IPEIR(base) ((base)+0x64) |
1105 | #define RING_IPEHR(base) ((base)+0x68) |
1207 | #define RING_IPEHR(base) ((base)+0x68) |
1106 | #define RING_INSTDONE(base) ((base)+0x6c) |
1208 | #define RING_INSTDONE(base) ((base)+0x6c) |
1107 | #define RING_INSTPS(base) ((base)+0x70) |
1209 | #define RING_INSTPS(base) ((base)+0x70) |
1108 | #define RING_DMA_FADD(base) ((base)+0x78) |
1210 | #define RING_DMA_FADD(base) ((base)+0x78) |
1109 | #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ |
1211 | #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ |
1110 | #define RING_INSTPM(base) ((base)+0xc0) |
1212 | #define RING_INSTPM(base) ((base)+0xc0) |
1111 | #define RING_MI_MODE(base) ((base)+0x9c) |
1213 | #define RING_MI_MODE(base) ((base)+0x9c) |
1112 | #define INSTPS 0x02070 /* 965+ only */ |
1214 | #define INSTPS 0x02070 /* 965+ only */ |
1113 | #define INSTDONE1 0x0207c /* 965+ only */ |
1215 | #define INSTDONE1 0x0207c /* 965+ only */ |
1114 | #define ACTHD_I965 0x02074 |
1216 | #define ACTHD_I965 0x02074 |
1115 | #define HWS_PGA 0x02080 |
1217 | #define HWS_PGA 0x02080 |
1116 | #define HWS_ADDRESS_MASK 0xfffff000 |
1218 | #define HWS_ADDRESS_MASK 0xfffff000 |
1117 | #define HWS_START_ADDRESS_SHIFT 4 |
1219 | #define HWS_START_ADDRESS_SHIFT 4 |
1118 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
1220 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
1119 | #define PWRCTX_EN (1<<0) |
1221 | #define PWRCTX_EN (1<<0) |
1120 | #define IPEIR 0x02088 |
1222 | #define IPEIR 0x02088 |
1121 | #define IPEHR 0x0208c |
1223 | #define IPEHR 0x0208c |
1122 | #define INSTDONE 0x02090 |
1224 | #define INSTDONE 0x02090 |
1123 | #define NOPID 0x02094 |
1225 | #define NOPID 0x02094 |
1124 | #define HWSTAM 0x02098 |
1226 | #define HWSTAM 0x02098 |
1125 | #define DMA_FADD_I8XX 0x020d0 |
1227 | #define DMA_FADD_I8XX 0x020d0 |
1126 | #define RING_BBSTATE(base) ((base)+0x110) |
1228 | #define RING_BBSTATE(base) ((base)+0x110) |
1127 | #define RING_BBADDR(base) ((base)+0x140) |
1229 | #define RING_BBADDR(base) ((base)+0x140) |
1128 | #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ |
1230 | #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ |
1129 | 1231 | ||
1130 | #define ERROR_GEN6 0x040a0 |
1232 | #define ERROR_GEN6 0x040a0 |
1131 | #define GEN7_ERR_INT 0x44040 |
1233 | #define GEN7_ERR_INT 0x44040 |
1132 | #define ERR_INT_POISON (1<<31) |
1234 | #define ERR_INT_POISON (1<<31) |
1133 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
1235 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
1134 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
1236 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
1135 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
1237 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
1136 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
1238 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
1137 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
1239 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
1138 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
1240 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
1139 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) |
1241 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) |
1140 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
1242 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
1141 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
1243 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
1142 | 1244 | ||
1143 | #define FPGA_DBG 0x42300 |
1245 | #define FPGA_DBG 0x42300 |
1144 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
1246 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
1145 | 1247 | ||
1146 | #define DERRMR 0x44050 |
1248 | #define DERRMR 0x44050 |
1147 | /* Note that HBLANK events are reserved on bdw+ */ |
1249 | /* Note that HBLANK events are reserved on bdw+ */ |
1148 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
1250 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
1149 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) |
1251 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) |
1150 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) |
1252 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) |
1151 | #define DERRMR_PIPEA_VBLANK (1<<3) |
1253 | #define DERRMR_PIPEA_VBLANK (1<<3) |
1152 | #define DERRMR_PIPEA_HBLANK (1<<5) |
1254 | #define DERRMR_PIPEA_HBLANK (1<<5) |
1153 | #define DERRMR_PIPEB_SCANLINE (1<<8) |
1255 | #define DERRMR_PIPEB_SCANLINE (1<<8) |
1154 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) |
1256 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) |
1155 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) |
1257 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) |
1156 | #define DERRMR_PIPEB_VBLANK (1<<11) |
1258 | #define DERRMR_PIPEB_VBLANK (1<<11) |
1157 | #define DERRMR_PIPEB_HBLANK (1<<13) |
1259 | #define DERRMR_PIPEB_HBLANK (1<<13) |
1158 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ |
1260 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ |
1159 | #define DERRMR_PIPEC_SCANLINE (1<<14) |
1261 | #define DERRMR_PIPEC_SCANLINE (1<<14) |
1160 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) |
1262 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) |
1161 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) |
1263 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) |
1162 | #define DERRMR_PIPEC_VBLANK (1<<21) |
1264 | #define DERRMR_PIPEC_VBLANK (1<<21) |
1163 | #define DERRMR_PIPEC_HBLANK (1<<22) |
1265 | #define DERRMR_PIPEC_HBLANK (1<<22) |
1164 | 1266 | ||
1165 | 1267 | ||
1166 | /* GM45+ chicken bits -- debug workaround bits that may be required |
1268 | /* GM45+ chicken bits -- debug workaround bits that may be required |
1167 | * for various sorts of correct behavior. The top 16 bits of each are |
1269 | * for various sorts of correct behavior. The top 16 bits of each are |
1168 | * the enables for writing to the corresponding low bit. |
1270 | * the enables for writing to the corresponding low bit. |
1169 | */ |
1271 | */ |
1170 | #define _3D_CHICKEN 0x02084 |
1272 | #define _3D_CHICKEN 0x02084 |
1171 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
1273 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
1172 | #define _3D_CHICKEN2 0x0208c |
1274 | #define _3D_CHICKEN2 0x0208c |
1173 | /* Disables pipelining of read flushes past the SF-WIZ interface. |
1275 | /* Disables pipelining of read flushes past the SF-WIZ interface. |
1174 | * Required on all Ironlake steppings according to the B-Spec, but the |
1276 | * Required on all Ironlake steppings according to the B-Spec, but the |
1175 | * particular danger of not doing so is not specified. |
1277 | * particular danger of not doing so is not specified. |
1176 | */ |
1278 | */ |
1177 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
1279 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
1178 | #define _3D_CHICKEN3 0x02090 |
1280 | #define _3D_CHICKEN3 0x02090 |
1179 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
1281 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
1180 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
1282 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
1181 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ |
1283 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ |
1182 | #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ |
1284 | #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ |
1183 | 1285 | ||
1184 | #define MI_MODE 0x0209c |
1286 | #define MI_MODE 0x0209c |
1185 | # define VS_TIMER_DISPATCH (1 << 6) |
1287 | # define VS_TIMER_DISPATCH (1 << 6) |
1186 | # define MI_FLUSH_ENABLE (1 << 12) |
1288 | # define MI_FLUSH_ENABLE (1 << 12) |
1187 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
1289 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
1188 | # define MODE_IDLE (1 << 9) |
1290 | # define MODE_IDLE (1 << 9) |
1189 | # define STOP_RING (1 << 8) |
1291 | # define STOP_RING (1 << 8) |
1190 | 1292 | ||
1191 | #define GEN6_GT_MODE 0x20d0 |
1293 | #define GEN6_GT_MODE 0x20d0 |
1192 | #define GEN7_GT_MODE 0x7008 |
1294 | #define GEN7_GT_MODE 0x7008 |
1193 | #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) |
1295 | #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) |
1194 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) |
1296 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) |
1195 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) |
1297 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) |
1196 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) |
1298 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) |
1197 | #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) |
1299 | #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) |
1198 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
1300 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
1199 | 1301 | ||
1200 | #define GFX_MODE 0x02520 |
1302 | #define GFX_MODE 0x02520 |
1201 | #define GFX_MODE_GEN7 0x0229c |
1303 | #define GFX_MODE_GEN7 0x0229c |
1202 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
1304 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
1203 | #define GFX_RUN_LIST_ENABLE (1<<15) |
1305 | #define GFX_RUN_LIST_ENABLE (1<<15) |
1204 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
1306 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
1205 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
1307 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
1206 | #define GFX_REPLAY_MODE (1<<11) |
1308 | #define GFX_REPLAY_MODE (1<<11) |
1207 | #define GFX_PSMI_GRANULARITY (1<<10) |
1309 | #define GFX_PSMI_GRANULARITY (1<<10) |
1208 | #define GFX_PPGTT_ENABLE (1<<9) |
1310 | #define GFX_PPGTT_ENABLE (1<<9) |
1209 | 1311 | ||
1210 | #define VLV_DISPLAY_BASE 0x180000 |
1312 | #define VLV_DISPLAY_BASE 0x180000 |
1211 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
1313 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
1212 | 1314 | ||
1213 | #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) |
1315 | #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) |
1214 | #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) |
1316 | #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) |
1215 | #define SCPD0 0x0209c /* 915+ only */ |
1317 | #define SCPD0 0x0209c /* 915+ only */ |
1216 | #define IER 0x020a0 |
1318 | #define IER 0x020a0 |
1217 | #define IIR 0x020a4 |
1319 | #define IIR 0x020a4 |
1218 | #define IMR 0x020a8 |
1320 | #define IMR 0x020a8 |
1219 | #define ISR 0x020ac |
1321 | #define ISR 0x020ac |
1220 | #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) |
1322 | #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) |
1221 | #define GINT_DIS (1<<22) |
1323 | #define GINT_DIS (1<<22) |
1222 | #define GCFG_DIS (1<<8) |
1324 | #define GCFG_DIS (1<<8) |
1223 | #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) |
1325 | #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) |
1224 | #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) |
1326 | #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) |
1225 | #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) |
1327 | #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) |
1226 | #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) |
1328 | #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) |
1227 | #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) |
1329 | #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) |
1228 | #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) |
1330 | #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) |
1229 | #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) |
1331 | #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) |
1230 | #define VLV_PCBR_ADDR_SHIFT 12 |
1332 | #define VLV_PCBR_ADDR_SHIFT 12 |
1231 | 1333 | ||
1232 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ |
1334 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ |
1233 | #define EIR 0x020b0 |
1335 | #define EIR 0x020b0 |
1234 | #define EMR 0x020b4 |
1336 | #define EMR 0x020b4 |
1235 | #define ESR 0x020b8 |
1337 | #define ESR 0x020b8 |
1236 | #define GM45_ERROR_PAGE_TABLE (1<<5) |
1338 | #define GM45_ERROR_PAGE_TABLE (1<<5) |
1237 | #define GM45_ERROR_MEM_PRIV (1<<4) |
1339 | #define GM45_ERROR_MEM_PRIV (1<<4) |
1238 | #define I915_ERROR_PAGE_TABLE (1<<4) |
1340 | #define I915_ERROR_PAGE_TABLE (1<<4) |
1239 | #define GM45_ERROR_CP_PRIV (1<<3) |
1341 | #define GM45_ERROR_CP_PRIV (1<<3) |
1240 | #define I915_ERROR_MEMORY_REFRESH (1<<1) |
1342 | #define I915_ERROR_MEMORY_REFRESH (1<<1) |
1241 | #define I915_ERROR_INSTRUCTION (1<<0) |
1343 | #define I915_ERROR_INSTRUCTION (1<<0) |
1242 | #define INSTPM 0x020c0 |
1344 | #define INSTPM 0x020c0 |
1243 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
1345 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
1244 | #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts |
1346 | #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts |
1245 | will not assert AGPBUSY# and will only |
1347 | will not assert AGPBUSY# and will only |
1246 | be delivered when out of C3. */ |
1348 | be delivered when out of C3. */ |
1247 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
1349 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
1248 | #define INSTPM_TLB_INVALIDATE (1<<9) |
1350 | #define INSTPM_TLB_INVALIDATE (1<<9) |
1249 | #define INSTPM_SYNC_FLUSH (1<<5) |
1351 | #define INSTPM_SYNC_FLUSH (1<<5) |
1250 | #define ACTHD 0x020c8 |
1352 | #define ACTHD 0x020c8 |
- | 1353 | #define MEM_MODE 0x020cc |
|
- | 1354 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ |
|
- | 1355 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ |
|
- | 1356 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ |
|
1251 | #define FW_BLC 0x020d8 |
1357 | #define FW_BLC 0x020d8 |
1252 | #define FW_BLC2 0x020dc |
1358 | #define FW_BLC2 0x020dc |
1253 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
1359 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
1254 | #define FW_BLC_SELF_EN_MASK (1<<31) |
1360 | #define FW_BLC_SELF_EN_MASK (1<<31) |
1255 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ |
1361 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ |
1256 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ |
1362 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ |
1257 | #define MM_BURST_LENGTH 0x00700000 |
1363 | #define MM_BURST_LENGTH 0x00700000 |
1258 | #define MM_FIFO_WATERMARK 0x0001F000 |
1364 | #define MM_FIFO_WATERMARK 0x0001F000 |
1259 | #define LM_BURST_LENGTH 0x00000700 |
1365 | #define LM_BURST_LENGTH 0x00000700 |
1260 | #define LM_FIFO_WATERMARK 0x0000001F |
1366 | #define LM_FIFO_WATERMARK 0x0000001F |
1261 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
1367 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
1262 | 1368 | ||
1263 | /* Make render/texture TLB fetches lower priorty than associated data |
1369 | /* Make render/texture TLB fetches lower priorty than associated data |
1264 | * fetches. This is not turned on by default |
1370 | * fetches. This is not turned on by default |
1265 | */ |
1371 | */ |
1266 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) |
1372 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) |
1267 | 1373 | ||
1268 | /* Isoch request wait on GTT enable (Display A/B/C streams). |
1374 | /* Isoch request wait on GTT enable (Display A/B/C streams). |
1269 | * Make isoch requests stall on the TLB update. May cause |
1375 | * Make isoch requests stall on the TLB update. May cause |
1270 | * display underruns (test mode only) |
1376 | * display underruns (test mode only) |
1271 | */ |
1377 | */ |
1272 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) |
1378 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) |
1273 | 1379 | ||
1274 | /* Block grant count for isoch requests when block count is |
1380 | /* Block grant count for isoch requests when block count is |
1275 | * set to a finite value. |
1381 | * set to a finite value. |
1276 | */ |
1382 | */ |
1277 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) |
1383 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) |
1278 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ |
1384 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ |
1279 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ |
1385 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ |
1280 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ |
1386 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ |
1281 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ |
1387 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ |
1282 | 1388 | ||
1283 | /* Enable render writes to complete in C2/C3/C4 power states. |
1389 | /* Enable render writes to complete in C2/C3/C4 power states. |
1284 | * If this isn't enabled, render writes are prevented in low |
1390 | * If this isn't enabled, render writes are prevented in low |
1285 | * power states. That seems bad to me. |
1391 | * power states. That seems bad to me. |
1286 | */ |
1392 | */ |
1287 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) |
1393 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) |
1288 | 1394 | ||
1289 | /* This acknowledges an async flip immediately instead |
1395 | /* This acknowledges an async flip immediately instead |
1290 | * of waiting for 2TLB fetches. |
1396 | * of waiting for 2TLB fetches. |
1291 | */ |
1397 | */ |
1292 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) |
1398 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) |
1293 | 1399 | ||
1294 | /* Enables non-sequential data reads through arbiter |
1400 | /* Enables non-sequential data reads through arbiter |
1295 | */ |
1401 | */ |
1296 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
1402 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
1297 | 1403 | ||
1298 | /* Disable FSB snooping of cacheable write cycles from binner/render |
1404 | /* Disable FSB snooping of cacheable write cycles from binner/render |
1299 | * command stream |
1405 | * command stream |
1300 | */ |
1406 | */ |
1301 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) |
1407 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) |
1302 | 1408 | ||
1303 | /* Arbiter time slice for non-isoch streams */ |
1409 | /* Arbiter time slice for non-isoch streams */ |
1304 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) |
1410 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) |
1305 | #define MI_ARB_TIME_SLICE_1 (0 << 5) |
1411 | #define MI_ARB_TIME_SLICE_1 (0 << 5) |
1306 | #define MI_ARB_TIME_SLICE_2 (1 << 5) |
1412 | #define MI_ARB_TIME_SLICE_2 (1 << 5) |
1307 | #define MI_ARB_TIME_SLICE_4 (2 << 5) |
1413 | #define MI_ARB_TIME_SLICE_4 (2 << 5) |
1308 | #define MI_ARB_TIME_SLICE_6 (3 << 5) |
1414 | #define MI_ARB_TIME_SLICE_6 (3 << 5) |
1309 | #define MI_ARB_TIME_SLICE_8 (4 << 5) |
1415 | #define MI_ARB_TIME_SLICE_8 (4 << 5) |
1310 | #define MI_ARB_TIME_SLICE_10 (5 << 5) |
1416 | #define MI_ARB_TIME_SLICE_10 (5 << 5) |
1311 | #define MI_ARB_TIME_SLICE_14 (6 << 5) |
1417 | #define MI_ARB_TIME_SLICE_14 (6 << 5) |
1312 | #define MI_ARB_TIME_SLICE_16 (7 << 5) |
1418 | #define MI_ARB_TIME_SLICE_16 (7 << 5) |
1313 | 1419 | ||
1314 | /* Low priority grace period page size */ |
1420 | /* Low priority grace period page size */ |
1315 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ |
1421 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ |
1316 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) |
1422 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) |
1317 | 1423 | ||
1318 | /* Disable display A/B trickle feed */ |
1424 | /* Disable display A/B trickle feed */ |
1319 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) |
1425 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) |
1320 | 1426 | ||
1321 | /* Set display plane priority */ |
1427 | /* Set display plane priority */ |
1322 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
1428 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
1323 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
1429 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
1324 | 1430 | ||
1325 | #define MI_STATE 0x020e4 /* gen2 only */ |
1431 | #define MI_STATE 0x020e4 /* gen2 only */ |
1326 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
1432 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
1327 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ |
1433 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ |
1328 | 1434 | ||
1329 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
1435 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
1330 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
1436 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
1331 | #define CM0_IZ_OPT_DISABLE (1<<6) |
1437 | #define CM0_IZ_OPT_DISABLE (1<<6) |
1332 | #define CM0_ZR_OPT_DISABLE (1<<5) |
1438 | #define CM0_ZR_OPT_DISABLE (1<<5) |
1333 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
1439 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
1334 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
1440 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
1335 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
1441 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
1336 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
1442 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
1337 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
1443 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
1338 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
1444 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
1339 | #define GFX_FLSH_CNTL_GEN6 0x101008 |
1445 | #define GFX_FLSH_CNTL_GEN6 0x101008 |
1340 | #define GFX_FLSH_CNTL_EN (1<<0) |
1446 | #define GFX_FLSH_CNTL_EN (1<<0) |
1341 | #define ECOSKPD 0x021d0 |
1447 | #define ECOSKPD 0x021d0 |
1342 | #define ECO_GATING_CX_ONLY (1<<3) |
1448 | #define ECO_GATING_CX_ONLY (1<<3) |
1343 | #define ECO_FLIP_DONE (1<<0) |
1449 | #define ECO_FLIP_DONE (1<<0) |
1344 | 1450 | ||
1345 | #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ |
1451 | #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ |
1346 | #define RC_OP_FLUSH_ENABLE (1<<0) |
1452 | #define RC_OP_FLUSH_ENABLE (1<<0) |
1347 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
1453 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
1348 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
1454 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
1349 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
1455 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
1350 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) |
1456 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) |
1351 | 1457 | ||
1352 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
1458 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
1353 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
1459 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
1354 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
1460 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
1355 | 1461 | ||
1356 | #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
1462 | #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
- | 1463 | #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) |
|
1357 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
1464 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
1358 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
1465 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
1359 | 1466 | ||
1360 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
1467 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
1361 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
1468 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
1362 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) |
1469 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) |
1363 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) |
1470 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) |
1364 | #define GEN6_BSD_GO_INDICATOR (1 << 4) |
1471 | #define GEN6_BSD_GO_INDICATOR (1 << 4) |
1365 | 1472 | ||
1366 | /* On modern GEN architectures interrupt control consists of two sets |
1473 | /* On modern GEN architectures interrupt control consists of two sets |
1367 | * of registers. The first set pertains to the ring generating the |
1474 | * of registers. The first set pertains to the ring generating the |
1368 | * interrupt. The second control is for the functional block generating the |
1475 | * interrupt. The second control is for the functional block generating the |
1369 | * interrupt. These are PM, GT, DE, etc. |
1476 | * interrupt. These are PM, GT, DE, etc. |
1370 | * |
1477 | * |
1371 | * Luckily *knocks on wood* all the ring interrupt bits match up with the |
1478 | * Luckily *knocks on wood* all the ring interrupt bits match up with the |
1372 | * GT interrupt bits, so we don't need to duplicate the defines. |
1479 | * GT interrupt bits, so we don't need to duplicate the defines. |
1373 | * |
1480 | * |
1374 | * These defines should cover us well from SNB->HSW with minor exceptions |
1481 | * These defines should cover us well from SNB->HSW with minor exceptions |
1375 | * it can also work on ILK. |
1482 | * it can also work on ILK. |
1376 | */ |
1483 | */ |
1377 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
1484 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
1378 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) |
1485 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) |
1379 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
1486 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
1380 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
1487 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
1381 | #define GT_BSD_USER_INTERRUPT (1 << 12) |
1488 | #define GT_BSD_USER_INTERRUPT (1 << 12) |
1382 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
1489 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
- | 1490 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
|
1383 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
1491 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
1384 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
1492 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
1385 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) |
1493 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) |
1386 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) |
1494 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) |
1387 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) |
1495 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) |
1388 | #define GT_RENDER_USER_INTERRUPT (1 << 0) |
1496 | #define GT_RENDER_USER_INTERRUPT (1 << 0) |
1389 | 1497 | ||
1390 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
1498 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
1391 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ |
1499 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ |
1392 | 1500 | ||
1393 | #define GT_PARITY_ERROR(dev) \ |
1501 | #define GT_PARITY_ERROR(dev) \ |
1394 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ |
1502 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ |
1395 | (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
1503 | (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
1396 | 1504 | ||
1397 | /* These are all the "old" interrupts */ |
1505 | /* These are all the "old" interrupts */ |
1398 | #define ILK_BSD_USER_INTERRUPT (1<<5) |
1506 | #define ILK_BSD_USER_INTERRUPT (1<<5) |
1399 | 1507 | ||
1400 | #define I915_PM_INTERRUPT (1<<31) |
1508 | #define I915_PM_INTERRUPT (1<<31) |
1401 | #define I915_ISP_INTERRUPT (1<<22) |
1509 | #define I915_ISP_INTERRUPT (1<<22) |
1402 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) |
1510 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) |
1403 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) |
1511 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) |
1404 | #define I915_MIPIB_INTERRUPT (1<<19) |
1512 | #define I915_MIPIB_INTERRUPT (1<<19) |
1405 | #define I915_MIPIA_INTERRUPT (1<<18) |
1513 | #define I915_MIPIA_INTERRUPT (1<<18) |
1406 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
1514 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
1407 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
1515 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
1408 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
1516 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
1409 | #define I915_MASTER_ERROR_INTERRUPT (1<<15) |
1517 | #define I915_MASTER_ERROR_INTERRUPT (1<<15) |
1410 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
1518 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
1411 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) |
1519 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) |
1412 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
1520 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
1413 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) |
1521 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) |
1414 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
1522 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
1415 | #define I915_LPE_PIPE_C_INTERRUPT (1<<12) |
1523 | #define I915_LPE_PIPE_C_INTERRUPT (1<<12) |
1416 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) |
1524 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) |
1417 | #define I915_MISC_INTERRUPT (1<<11) |
1525 | #define I915_MISC_INTERRUPT (1<<11) |
1418 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
1526 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
1419 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) |
1527 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) |
1420 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
1528 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
1421 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) |
1529 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) |
1422 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
1530 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
1423 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) |
1531 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) |
1424 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
1532 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
1425 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) |
1533 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) |
1426 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) |
1534 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) |
1427 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) |
1535 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) |
1428 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) |
1536 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) |
1429 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) |
1537 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) |
1430 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) |
1538 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) |
1431 | #define I915_DEBUG_INTERRUPT (1<<2) |
1539 | #define I915_DEBUG_INTERRUPT (1<<2) |
1432 | #define I915_WINVALID_INTERRUPT (1<<1) |
1540 | #define I915_WINVALID_INTERRUPT (1<<1) |
1433 | #define I915_USER_INTERRUPT (1<<1) |
1541 | #define I915_USER_INTERRUPT (1<<1) |
1434 | #define I915_ASLE_INTERRUPT (1<<0) |
1542 | #define I915_ASLE_INTERRUPT (1<<0) |
1435 | #define I915_BSD_USER_INTERRUPT (1<<25) |
1543 | #define I915_BSD_USER_INTERRUPT (1<<25) |
1436 | 1544 | ||
1437 | #define GEN6_BSD_RNCID 0x12198 |
1545 | #define GEN6_BSD_RNCID 0x12198 |
1438 | 1546 | ||
1439 | #define GEN7_FF_THREAD_MODE 0x20a0 |
1547 | #define GEN7_FF_THREAD_MODE 0x20a0 |
1440 | #define GEN7_FF_SCHED_MASK 0x0077070 |
1548 | #define GEN7_FF_SCHED_MASK 0x0077070 |
1441 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
1549 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
1442 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
1550 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
1443 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
1551 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
1444 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
1552 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
1445 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ |
1553 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ |
1446 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
1554 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
1447 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
1555 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
1448 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) |
1556 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) |
1449 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ |
1557 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ |
1450 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) |
1558 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) |
1451 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) |
1559 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) |
1452 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) |
1560 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) |
1453 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ |
1561 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ |
1454 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) |
1562 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) |
1455 | 1563 | ||
1456 | /* |
1564 | /* |
1457 | * Framebuffer compression (915+ only) |
1565 | * Framebuffer compression (915+ only) |
1458 | */ |
1566 | */ |
1459 | 1567 | ||
1460 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ |
1568 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ |
1461 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ |
1569 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ |
1462 | #define FBC_CONTROL 0x03208 |
1570 | #define FBC_CONTROL 0x03208 |
1463 | #define FBC_CTL_EN (1<<31) |
1571 | #define FBC_CTL_EN (1<<31) |
1464 | #define FBC_CTL_PERIODIC (1<<30) |
1572 | #define FBC_CTL_PERIODIC (1<<30) |
1465 | #define FBC_CTL_INTERVAL_SHIFT (16) |
1573 | #define FBC_CTL_INTERVAL_SHIFT (16) |
1466 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
1574 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
1467 | #define FBC_CTL_C3_IDLE (1<<13) |
1575 | #define FBC_CTL_C3_IDLE (1<<13) |
1468 | #define FBC_CTL_STRIDE_SHIFT (5) |
1576 | #define FBC_CTL_STRIDE_SHIFT (5) |
1469 | #define FBC_CTL_FENCENO_SHIFT (0) |
1577 | #define FBC_CTL_FENCENO_SHIFT (0) |
1470 | #define FBC_COMMAND 0x0320c |
1578 | #define FBC_COMMAND 0x0320c |
1471 | #define FBC_CMD_COMPRESS (1<<0) |
1579 | #define FBC_CMD_COMPRESS (1<<0) |
1472 | #define FBC_STATUS 0x03210 |
1580 | #define FBC_STATUS 0x03210 |
1473 | #define FBC_STAT_COMPRESSING (1<<31) |
1581 | #define FBC_STAT_COMPRESSING (1<<31) |
1474 | #define FBC_STAT_COMPRESSED (1<<30) |
1582 | #define FBC_STAT_COMPRESSED (1<<30) |
1475 | #define FBC_STAT_MODIFIED (1<<29) |
1583 | #define FBC_STAT_MODIFIED (1<<29) |
1476 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) |
1584 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) |
1477 | #define FBC_CONTROL2 0x03214 |
1585 | #define FBC_CONTROL2 0x03214 |
1478 | #define FBC_CTL_FENCE_DBL (0<<4) |
1586 | #define FBC_CTL_FENCE_DBL (0<<4) |
1479 | #define FBC_CTL_IDLE_IMM (0<<2) |
1587 | #define FBC_CTL_IDLE_IMM (0<<2) |
1480 | #define FBC_CTL_IDLE_FULL (1<<2) |
1588 | #define FBC_CTL_IDLE_FULL (1<<2) |
1481 | #define FBC_CTL_IDLE_LINE (2<<2) |
1589 | #define FBC_CTL_IDLE_LINE (2<<2) |
1482 | #define FBC_CTL_IDLE_DEBUG (3<<2) |
1590 | #define FBC_CTL_IDLE_DEBUG (3<<2) |
1483 | #define FBC_CTL_CPU_FENCE (1<<1) |
1591 | #define FBC_CTL_CPU_FENCE (1<<1) |
1484 | #define FBC_CTL_PLANE(plane) ((plane)<<0) |
1592 | #define FBC_CTL_PLANE(plane) ((plane)<<0) |
1485 | #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ |
1593 | #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ |
1486 | #define FBC_TAG 0x03300 |
1594 | #define FBC_TAG 0x03300 |
1487 | 1595 | ||
1488 | #define FBC_LL_SIZE (1536) |
1596 | #define FBC_LL_SIZE (1536) |
1489 | 1597 | ||
1490 | /* Framebuffer compression for GM45+ */ |
1598 | /* Framebuffer compression for GM45+ */ |
1491 | #define DPFC_CB_BASE 0x3200 |
1599 | #define DPFC_CB_BASE 0x3200 |
1492 | #define DPFC_CONTROL 0x3208 |
1600 | #define DPFC_CONTROL 0x3208 |
1493 | #define DPFC_CTL_EN (1<<31) |
1601 | #define DPFC_CTL_EN (1<<31) |
1494 | #define DPFC_CTL_PLANE(plane) ((plane)<<30) |
1602 | #define DPFC_CTL_PLANE(plane) ((plane)<<30) |
1495 | #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) |
1603 | #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) |
1496 | #define DPFC_CTL_FENCE_EN (1<<29) |
1604 | #define DPFC_CTL_FENCE_EN (1<<29) |
1497 | #define IVB_DPFC_CTL_FENCE_EN (1<<28) |
1605 | #define IVB_DPFC_CTL_FENCE_EN (1<<28) |
1498 | #define DPFC_CTL_PERSISTENT_MODE (1<<25) |
1606 | #define DPFC_CTL_PERSISTENT_MODE (1<<25) |
1499 | #define DPFC_SR_EN (1<<10) |
1607 | #define DPFC_SR_EN (1<<10) |
1500 | #define DPFC_CTL_LIMIT_1X (0<<6) |
1608 | #define DPFC_CTL_LIMIT_1X (0<<6) |
1501 | #define DPFC_CTL_LIMIT_2X (1<<6) |
1609 | #define DPFC_CTL_LIMIT_2X (1<<6) |
1502 | #define DPFC_CTL_LIMIT_4X (2<<6) |
1610 | #define DPFC_CTL_LIMIT_4X (2<<6) |
1503 | #define DPFC_RECOMP_CTL 0x320c |
1611 | #define DPFC_RECOMP_CTL 0x320c |
1504 | #define DPFC_RECOMP_STALL_EN (1<<27) |
1612 | #define DPFC_RECOMP_STALL_EN (1<<27) |
1505 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) |
1613 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) |
1506 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) |
1614 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) |
1507 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) |
1615 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) |
1508 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) |
1616 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) |
1509 | #define DPFC_STATUS 0x3210 |
1617 | #define DPFC_STATUS 0x3210 |
1510 | #define DPFC_INVAL_SEG_SHIFT (16) |
1618 | #define DPFC_INVAL_SEG_SHIFT (16) |
1511 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) |
1619 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) |
1512 | #define DPFC_COMP_SEG_SHIFT (0) |
1620 | #define DPFC_COMP_SEG_SHIFT (0) |
1513 | #define DPFC_COMP_SEG_MASK (0x000003ff) |
1621 | #define DPFC_COMP_SEG_MASK (0x000003ff) |
1514 | #define DPFC_STATUS2 0x3214 |
1622 | #define DPFC_STATUS2 0x3214 |
1515 | #define DPFC_FENCE_YOFF 0x3218 |
1623 | #define DPFC_FENCE_YOFF 0x3218 |
1516 | #define DPFC_CHICKEN 0x3224 |
1624 | #define DPFC_CHICKEN 0x3224 |
1517 | #define DPFC_HT_MODIFY (1<<31) |
1625 | #define DPFC_HT_MODIFY (1<<31) |
1518 | 1626 | ||
1519 | /* Framebuffer compression for Ironlake */ |
1627 | /* Framebuffer compression for Ironlake */ |
1520 | #define ILK_DPFC_CB_BASE 0x43200 |
1628 | #define ILK_DPFC_CB_BASE 0x43200 |
1521 | #define ILK_DPFC_CONTROL 0x43208 |
1629 | #define ILK_DPFC_CONTROL 0x43208 |
- | 1630 | #define FBC_CTL_FALSE_COLOR (1<<10) |
|
1522 | /* The bit 28-8 is reserved */ |
1631 | /* The bit 28-8 is reserved */ |
1523 | #define DPFC_RESERVED (0x1FFFFF00) |
1632 | #define DPFC_RESERVED (0x1FFFFF00) |
1524 | #define ILK_DPFC_RECOMP_CTL 0x4320c |
1633 | #define ILK_DPFC_RECOMP_CTL 0x4320c |
1525 | #define ILK_DPFC_STATUS 0x43210 |
1634 | #define ILK_DPFC_STATUS 0x43210 |
1526 | #define ILK_DPFC_FENCE_YOFF 0x43218 |
1635 | #define ILK_DPFC_FENCE_YOFF 0x43218 |
1527 | #define ILK_DPFC_CHICKEN 0x43224 |
1636 | #define ILK_DPFC_CHICKEN 0x43224 |
1528 | #define ILK_FBC_RT_BASE 0x2128 |
1637 | #define ILK_FBC_RT_BASE 0x2128 |
1529 | #define ILK_FBC_RT_VALID (1<<0) |
1638 | #define ILK_FBC_RT_VALID (1<<0) |
1530 | #define SNB_FBC_FRONT_BUFFER (1<<1) |
1639 | #define SNB_FBC_FRONT_BUFFER (1<<1) |
1531 | 1640 | ||
1532 | #define ILK_DISPLAY_CHICKEN1 0x42000 |
1641 | #define ILK_DISPLAY_CHICKEN1 0x42000 |
1533 | #define ILK_FBCQ_DIS (1<<22) |
1642 | #define ILK_FBCQ_DIS (1<<22) |
1534 | #define ILK_PABSTRETCH_DIS (1<<21) |
1643 | #define ILK_PABSTRETCH_DIS (1<<21) |
1535 | 1644 | ||
1536 | 1645 | ||
1537 | /* |
1646 | /* |
1538 | * Framebuffer compression for Sandybridge |
1647 | * Framebuffer compression for Sandybridge |
1539 | * |
1648 | * |
1540 | * The following two registers are of type GTTMMADR |
1649 | * The following two registers are of type GTTMMADR |
1541 | */ |
1650 | */ |
1542 | #define SNB_DPFC_CTL_SA 0x100100 |
1651 | #define SNB_DPFC_CTL_SA 0x100100 |
1543 | #define SNB_CPU_FENCE_ENABLE (1<<29) |
1652 | #define SNB_CPU_FENCE_ENABLE (1<<29) |
1544 | #define DPFC_CPU_FENCE_OFFSET 0x100104 |
1653 | #define DPFC_CPU_FENCE_OFFSET 0x100104 |
1545 | 1654 | ||
1546 | /* Framebuffer compression for Ivybridge */ |
1655 | /* Framebuffer compression for Ivybridge */ |
1547 | #define IVB_FBC_RT_BASE 0x7020 |
1656 | #define IVB_FBC_RT_BASE 0x7020 |
1548 | 1657 | ||
1549 | #define IPS_CTL 0x43408 |
1658 | #define IPS_CTL 0x43408 |
1550 | #define IPS_ENABLE (1 << 31) |
1659 | #define IPS_ENABLE (1 << 31) |
1551 | 1660 | ||
1552 | #define MSG_FBC_REND_STATE 0x50380 |
1661 | #define MSG_FBC_REND_STATE 0x50380 |
1553 | #define FBC_REND_NUKE (1<<2) |
1662 | #define FBC_REND_NUKE (1<<2) |
1554 | #define FBC_REND_CACHE_CLEAN (1<<1) |
1663 | #define FBC_REND_CACHE_CLEAN (1<<1) |
1555 | 1664 | ||
1556 | /* |
1665 | /* |
1557 | * GPIO regs |
1666 | * GPIO regs |
1558 | */ |
1667 | */ |
1559 | #define GPIOA 0x5010 |
1668 | #define GPIOA 0x5010 |
1560 | #define GPIOB 0x5014 |
1669 | #define GPIOB 0x5014 |
1561 | #define GPIOC 0x5018 |
1670 | #define GPIOC 0x5018 |
1562 | #define GPIOD 0x501c |
1671 | #define GPIOD 0x501c |
1563 | #define GPIOE 0x5020 |
1672 | #define GPIOE 0x5020 |
1564 | #define GPIOF 0x5024 |
1673 | #define GPIOF 0x5024 |
1565 | #define GPIOG 0x5028 |
1674 | #define GPIOG 0x5028 |
1566 | #define GPIOH 0x502c |
1675 | #define GPIOH 0x502c |
1567 | # define GPIO_CLOCK_DIR_MASK (1 << 0) |
1676 | # define GPIO_CLOCK_DIR_MASK (1 << 0) |
1568 | # define GPIO_CLOCK_DIR_IN (0 << 1) |
1677 | # define GPIO_CLOCK_DIR_IN (0 << 1) |
1569 | # define GPIO_CLOCK_DIR_OUT (1 << 1) |
1678 | # define GPIO_CLOCK_DIR_OUT (1 << 1) |
1570 | # define GPIO_CLOCK_VAL_MASK (1 << 2) |
1679 | # define GPIO_CLOCK_VAL_MASK (1 << 2) |
1571 | # define GPIO_CLOCK_VAL_OUT (1 << 3) |
1680 | # define GPIO_CLOCK_VAL_OUT (1 << 3) |
1572 | # define GPIO_CLOCK_VAL_IN (1 << 4) |
1681 | # define GPIO_CLOCK_VAL_IN (1 << 4) |
1573 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) |
1682 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) |
1574 | # define GPIO_DATA_DIR_MASK (1 << 8) |
1683 | # define GPIO_DATA_DIR_MASK (1 << 8) |
1575 | # define GPIO_DATA_DIR_IN (0 << 9) |
1684 | # define GPIO_DATA_DIR_IN (0 << 9) |
1576 | # define GPIO_DATA_DIR_OUT (1 << 9) |
1685 | # define GPIO_DATA_DIR_OUT (1 << 9) |
1577 | # define GPIO_DATA_VAL_MASK (1 << 10) |
1686 | # define GPIO_DATA_VAL_MASK (1 << 10) |
1578 | # define GPIO_DATA_VAL_OUT (1 << 11) |
1687 | # define GPIO_DATA_VAL_OUT (1 << 11) |
1579 | # define GPIO_DATA_VAL_IN (1 << 12) |
1688 | # define GPIO_DATA_VAL_IN (1 << 12) |
1580 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
1689 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
1581 | 1690 | ||
1582 | #define GMBUS0 0x5100 /* clock/port select */ |
1691 | #define GMBUS0 0x5100 /* clock/port select */ |
1583 | #define GMBUS_RATE_100KHZ (0<<8) |
1692 | #define GMBUS_RATE_100KHZ (0<<8) |
1584 | #define GMBUS_RATE_50KHZ (1<<8) |
1693 | #define GMBUS_RATE_50KHZ (1<<8) |
1585 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |
1694 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |
1586 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ |
1695 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ |
1587 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ |
1696 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ |
1588 | #define GMBUS_PORT_DISABLED 0 |
1697 | #define GMBUS_PORT_DISABLED 0 |
1589 | #define GMBUS_PORT_SSC 1 |
1698 | #define GMBUS_PORT_SSC 1 |
1590 | #define GMBUS_PORT_VGADDC 2 |
1699 | #define GMBUS_PORT_VGADDC 2 |
1591 | #define GMBUS_PORT_PANEL 3 |
1700 | #define GMBUS_PORT_PANEL 3 |
1592 | #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ |
1701 | #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ |
1593 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
1702 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
1594 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
1703 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
1595 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
1704 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
1596 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
1705 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
1597 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
1706 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
1598 | #define GMBUS1 0x5104 /* command/status */ |
1707 | #define GMBUS1 0x5104 /* command/status */ |
1599 | #define GMBUS_SW_CLR_INT (1<<31) |
1708 | #define GMBUS_SW_CLR_INT (1<<31) |
1600 | #define GMBUS_SW_RDY (1<<30) |
1709 | #define GMBUS_SW_RDY (1<<30) |
1601 | #define GMBUS_ENT (1<<29) /* enable timeout */ |
1710 | #define GMBUS_ENT (1<<29) /* enable timeout */ |
1602 | #define GMBUS_CYCLE_NONE (0<<25) |
1711 | #define GMBUS_CYCLE_NONE (0<<25) |
1603 | #define GMBUS_CYCLE_WAIT (1<<25) |
1712 | #define GMBUS_CYCLE_WAIT (1<<25) |
1604 | #define GMBUS_CYCLE_INDEX (2<<25) |
1713 | #define GMBUS_CYCLE_INDEX (2<<25) |
1605 | #define GMBUS_CYCLE_STOP (4<<25) |
1714 | #define GMBUS_CYCLE_STOP (4<<25) |
1606 | #define GMBUS_BYTE_COUNT_SHIFT 16 |
1715 | #define GMBUS_BYTE_COUNT_SHIFT 16 |
1607 | #define GMBUS_SLAVE_INDEX_SHIFT 8 |
1716 | #define GMBUS_SLAVE_INDEX_SHIFT 8 |
1608 | #define GMBUS_SLAVE_ADDR_SHIFT 1 |
1717 | #define GMBUS_SLAVE_ADDR_SHIFT 1 |
1609 | #define GMBUS_SLAVE_READ (1<<0) |
1718 | #define GMBUS_SLAVE_READ (1<<0) |
1610 | #define GMBUS_SLAVE_WRITE (0<<0) |
1719 | #define GMBUS_SLAVE_WRITE (0<<0) |
1611 | #define GMBUS2 0x5108 /* status */ |
1720 | #define GMBUS2 0x5108 /* status */ |
1612 | #define GMBUS_INUSE (1<<15) |
1721 | #define GMBUS_INUSE (1<<15) |
1613 | #define GMBUS_HW_WAIT_PHASE (1<<14) |
1722 | #define GMBUS_HW_WAIT_PHASE (1<<14) |
1614 | #define GMBUS_STALL_TIMEOUT (1<<13) |
1723 | #define GMBUS_STALL_TIMEOUT (1<<13) |
1615 | #define GMBUS_INT (1<<12) |
1724 | #define GMBUS_INT (1<<12) |
1616 | #define GMBUS_HW_RDY (1<<11) |
1725 | #define GMBUS_HW_RDY (1<<11) |
1617 | #define GMBUS_SATOER (1<<10) |
1726 | #define GMBUS_SATOER (1<<10) |
1618 | #define GMBUS_ACTIVE (1<<9) |
1727 | #define GMBUS_ACTIVE (1<<9) |
1619 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ |
1728 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ |
1620 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ |
1729 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ |
1621 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
1730 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
1622 | #define GMBUS_NAK_EN (1<<3) |
1731 | #define GMBUS_NAK_EN (1<<3) |
1623 | #define GMBUS_IDLE_EN (1<<2) |
1732 | #define GMBUS_IDLE_EN (1<<2) |
1624 | #define GMBUS_HW_WAIT_EN (1<<1) |
1733 | #define GMBUS_HW_WAIT_EN (1<<1) |
1625 | #define GMBUS_HW_RDY_EN (1<<0) |
1734 | #define GMBUS_HW_RDY_EN (1<<0) |
1626 | #define GMBUS5 0x5120 /* byte index */ |
1735 | #define GMBUS5 0x5120 /* byte index */ |
1627 | #define GMBUS_2BYTE_INDEX_EN (1<<31) |
1736 | #define GMBUS_2BYTE_INDEX_EN (1<<31) |
1628 | 1737 | ||
1629 | /* |
1738 | /* |
1630 | * Clock control & power management |
1739 | * Clock control & power management |
1631 | */ |
1740 | */ |
1632 | #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) |
1741 | #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) |
1633 | #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) |
1742 | #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) |
1634 | #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) |
1743 | #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) |
1635 | #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
1744 | #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
1636 | 1745 | ||
1637 | #define VGA0 0x6000 |
1746 | #define VGA0 0x6000 |
1638 | #define VGA1 0x6004 |
1747 | #define VGA1 0x6004 |
1639 | #define VGA_PD 0x6010 |
1748 | #define VGA_PD 0x6010 |
1640 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
1749 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
1641 | #define VGA0_PD_P1_DIV_2 (1 << 5) |
1750 | #define VGA0_PD_P1_DIV_2 (1 << 5) |
1642 | #define VGA0_PD_P1_SHIFT 0 |
1751 | #define VGA0_PD_P1_SHIFT 0 |
1643 | #define VGA0_PD_P1_MASK (0x1f << 0) |
1752 | #define VGA0_PD_P1_MASK (0x1f << 0) |
1644 | #define VGA1_PD_P2_DIV_4 (1 << 15) |
1753 | #define VGA1_PD_P2_DIV_4 (1 << 15) |
1645 | #define VGA1_PD_P1_DIV_2 (1 << 13) |
1754 | #define VGA1_PD_P1_DIV_2 (1 << 13) |
1646 | #define VGA1_PD_P1_SHIFT 8 |
1755 | #define VGA1_PD_P1_SHIFT 8 |
1647 | #define VGA1_PD_P1_MASK (0x1f << 8) |
1756 | #define VGA1_PD_P1_MASK (0x1f << 8) |
1648 | #define DPLL_VCO_ENABLE (1 << 31) |
1757 | #define DPLL_VCO_ENABLE (1 << 31) |
1649 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
1758 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
1650 | #define DPLL_DVO_2X_MODE (1 << 30) |
1759 | #define DPLL_DVO_2X_MODE (1 << 30) |
1651 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
1760 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
1652 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
1761 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
1653 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
1762 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
1654 | #define DPLL_VGA_MODE_DIS (1 << 28) |
1763 | #define DPLL_VGA_MODE_DIS (1 << 28) |
1655 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
1764 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
1656 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
1765 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
1657 | #define DPLL_MODE_MASK (3 << 26) |
1766 | #define DPLL_MODE_MASK (3 << 26) |
1658 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
1767 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
1659 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
1768 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
1660 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
1769 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
1661 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
1770 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
1662 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
1771 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
1663 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
1772 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
1664 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
1773 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
1665 | #define DPLL_LOCK_VLV (1<<15) |
1774 | #define DPLL_LOCK_VLV (1<<15) |
1666 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
1775 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
1667 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
1776 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
1668 | #define DPLL_SSC_REF_CLOCK_CHV (1<<13) |
1777 | #define DPLL_SSC_REF_CLOCK_CHV (1<<13) |
1669 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
1778 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
1670 | #define DPLL_PORTB_READY_MASK (0xf) |
1779 | #define DPLL_PORTB_READY_MASK (0xf) |
1671 | 1780 | ||
1672 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
1781 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
1673 | 1782 | ||
1674 | /* Additional CHV pll/phy registers */ |
1783 | /* Additional CHV pll/phy registers */ |
1675 | #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) |
1784 | #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) |
1676 | #define DPLL_PORTD_READY_MASK (0xf) |
1785 | #define DPLL_PORTD_READY_MASK (0xf) |
1677 | #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
1786 | #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
1678 | #define PHY_COM_LANE_RESET_DEASSERT(phy, val) \ |
1787 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
1679 | ((phy == DPIO_PHY0) ? (val | 1) : (val | 2)) |
- | |
1680 | #define PHY_COM_LANE_RESET_ASSERT(phy, val) \ |
- | |
1681 | ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2)) |
- | |
1682 | #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
1788 | #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
1683 | #define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) : (1<<30)) |
1789 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) |
1684 | 1790 | ||
1685 | /* |
1791 | /* |
1686 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
1792 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
1687 | * this field (only one bit may be set). |
1793 | * this field (only one bit may be set). |
1688 | */ |
1794 | */ |
1689 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
1795 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
1690 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
1796 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
1691 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
1797 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
1692 | /* i830, required in DVO non-gang */ |
1798 | /* i830, required in DVO non-gang */ |
1693 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) |
1799 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) |
1694 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
1800 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
1695 | #define PLL_REF_INPUT_DREFCLK (0 << 13) |
1801 | #define PLL_REF_INPUT_DREFCLK (0 << 13) |
1696 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
1802 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
1697 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
1803 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
1698 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
1804 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
1699 | #define PLL_REF_INPUT_MASK (3 << 13) |
1805 | #define PLL_REF_INPUT_MASK (3 << 13) |
1700 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
1806 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
1701 | /* Ironlake */ |
1807 | /* Ironlake */ |
1702 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
1808 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
1703 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
1809 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
1704 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) |
1810 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) |
1705 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
1811 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
1706 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff |
1812 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff |
1707 | 1813 | ||
1708 | /* |
1814 | /* |
1709 | * Parallel to Serial Load Pulse phase selection. |
1815 | * Parallel to Serial Load Pulse phase selection. |
1710 | * Selects the phase for the 10X DPLL clock for the PCIe |
1816 | * Selects the phase for the 10X DPLL clock for the PCIe |
1711 | * digital display port. The range is 4 to 13; 10 or more |
1817 | * digital display port. The range is 4 to 13; 10 or more |
1712 | * is just a flip delay. The default is 6 |
1818 | * is just a flip delay. The default is 6 |
1713 | */ |
1819 | */ |
1714 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
1820 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
1715 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
1821 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
1716 | /* |
1822 | /* |
1717 | * SDVO multiplier for 945G/GM. Not used on 965. |
1823 | * SDVO multiplier for 945G/GM. Not used on 965. |
1718 | */ |
1824 | */ |
1719 | #define SDVO_MULTIPLIER_MASK 0x000000ff |
1825 | #define SDVO_MULTIPLIER_MASK 0x000000ff |
1720 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
1826 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
1721 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 |
1827 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 |
1722 | 1828 | ||
1723 | #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) |
1829 | #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) |
1724 | #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) |
1830 | #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) |
1725 | #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) |
1831 | #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) |
1726 | #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
1832 | #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
1727 | 1833 | ||
1728 | /* |
1834 | /* |
1729 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. |
1835 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. |
1730 | * |
1836 | * |
1731 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. |
1837 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. |
1732 | */ |
1838 | */ |
1733 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
1839 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
1734 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
1840 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
1735 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ |
1841 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ |
1736 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
1842 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
1737 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
1843 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
1738 | /* |
1844 | /* |
1739 | * SDVO/UDI pixel multiplier. |
1845 | * SDVO/UDI pixel multiplier. |
1740 | * |
1846 | * |
1741 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus |
1847 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus |
1742 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate |
1848 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate |
1743 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing |
1849 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing |
1744 | * dummy bytes in the datastream at an increased clock rate, with both sides of |
1850 | * dummy bytes in the datastream at an increased clock rate, with both sides of |
1745 | * the link knowing how many bytes are fill. |
1851 | * the link knowing how many bytes are fill. |
1746 | * |
1852 | * |
1747 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock |
1853 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock |
1748 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be |
1854 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be |
1749 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and |
1855 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and |
1750 | * through an SDVO command. |
1856 | * through an SDVO command. |
1751 | * |
1857 | * |
1752 | * This register field has values of multiplication factor minus 1, with |
1858 | * This register field has values of multiplication factor minus 1, with |
1753 | * a maximum multiplier of 5 for SDVO. |
1859 | * a maximum multiplier of 5 for SDVO. |
1754 | */ |
1860 | */ |
1755 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
1861 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
1756 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
1862 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
1757 | /* |
1863 | /* |
1758 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. |
1864 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. |
1759 | * This best be set to the default value (3) or the CRT won't work. No, |
1865 | * This best be set to the default value (3) or the CRT won't work. No, |
1760 | * I don't entirely understand what this does... |
1866 | * I don't entirely understand what this does... |
1761 | */ |
1867 | */ |
1762 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
1868 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
1763 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
1869 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
1764 | 1870 | ||
1765 | #define _FPA0 0x06040 |
1871 | #define _FPA0 0x06040 |
1766 | #define _FPA1 0x06044 |
1872 | #define _FPA1 0x06044 |
1767 | #define _FPB0 0x06048 |
1873 | #define _FPB0 0x06048 |
1768 | #define _FPB1 0x0604c |
1874 | #define _FPB1 0x0604c |
1769 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) |
1875 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) |
1770 | #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) |
1876 | #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) |
1771 | #define FP_N_DIV_MASK 0x003f0000 |
1877 | #define FP_N_DIV_MASK 0x003f0000 |
1772 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
1878 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
1773 | #define FP_N_DIV_SHIFT 16 |
1879 | #define FP_N_DIV_SHIFT 16 |
1774 | #define FP_M1_DIV_MASK 0x00003f00 |
1880 | #define FP_M1_DIV_MASK 0x00003f00 |
1775 | #define FP_M1_DIV_SHIFT 8 |
1881 | #define FP_M1_DIV_SHIFT 8 |
1776 | #define FP_M2_DIV_MASK 0x0000003f |
1882 | #define FP_M2_DIV_MASK 0x0000003f |
1777 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
1883 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
1778 | #define FP_M2_DIV_SHIFT 0 |
1884 | #define FP_M2_DIV_SHIFT 0 |
1779 | #define DPLL_TEST 0x606c |
1885 | #define DPLL_TEST 0x606c |
1780 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
1886 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
1781 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
1887 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
1782 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
1888 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
1783 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
1889 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
1784 | #define DPLLB_TEST_N_BYPASS (1 << 19) |
1890 | #define DPLLB_TEST_N_BYPASS (1 << 19) |
1785 | #define DPLLB_TEST_M_BYPASS (1 << 18) |
1891 | #define DPLLB_TEST_M_BYPASS (1 << 18) |
1786 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
1892 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
1787 | #define DPLLA_TEST_N_BYPASS (1 << 3) |
1893 | #define DPLLA_TEST_N_BYPASS (1 << 3) |
1788 | #define DPLLA_TEST_M_BYPASS (1 << 2) |
1894 | #define DPLLA_TEST_M_BYPASS (1 << 2) |
1789 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
1895 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
1790 | #define D_STATE 0x6104 |
1896 | #define D_STATE 0x6104 |
1791 | #define DSTATE_GFX_RESET_I830 (1<<6) |
1897 | #define DSTATE_GFX_RESET_I830 (1<<6) |
1792 | #define DSTATE_PLL_D3_OFF (1<<3) |
1898 | #define DSTATE_PLL_D3_OFF (1<<3) |
1793 | #define DSTATE_GFX_CLOCK_GATING (1<<1) |
1899 | #define DSTATE_GFX_CLOCK_GATING (1<<1) |
1794 | #define DSTATE_DOT_CLOCK_GATING (1<<0) |
1900 | #define DSTATE_DOT_CLOCK_GATING (1<<0) |
1795 | #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) |
1901 | #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) |
1796 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
1902 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
1797 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
1903 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
1798 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
1904 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
1799 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
1905 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
1800 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
1906 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
1801 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
1907 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
1802 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
1908 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
1803 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
1909 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
1804 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
1910 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
1805 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
1911 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
1806 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
1912 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
1807 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
1913 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
1808 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
1914 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
1809 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
1915 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
1810 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
1916 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
1811 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
1917 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
1812 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
1918 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
1813 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
1919 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
1814 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
1920 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
1815 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
1921 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
1816 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
1922 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
1817 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
1923 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
1818 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
1924 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
1819 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
1925 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
1820 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
1926 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
1821 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
1927 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
1822 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
1928 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
1823 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
1929 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
1824 | /* |
1930 | /* |
1825 | * This bit must be set on the 830 to prevent hangs when turning off the |
1931 | * This bit must be set on the 830 to prevent hangs when turning off the |
1826 | * overlay scaler. |
1932 | * overlay scaler. |
1827 | */ |
1933 | */ |
1828 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
1934 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
1829 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
1935 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
1830 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
1936 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
1831 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
1937 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
1832 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
1938 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
1833 | 1939 | ||
1834 | #define RENCLK_GATE_D1 0x6204 |
1940 | #define RENCLK_GATE_D1 0x6204 |
1835 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
1941 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
1836 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
1942 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
1837 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
1943 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
1838 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
1944 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
1839 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
1945 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
1840 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
1946 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
1841 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
1947 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
1842 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
1948 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
1843 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) |
1949 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) |
1844 | /* This bit must be unset on 855,865 */ |
1950 | /* This bit must be unset on 855,865 */ |
1845 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
1951 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
1846 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
1952 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
1847 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) |
1953 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) |
1848 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) |
1954 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) |
1849 | /* This bit must be set on 855,865. */ |
1955 | /* This bit must be set on 855,865. */ |
1850 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
1956 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
1851 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
1957 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
1852 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
1958 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
1853 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
1959 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
1854 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
1960 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
1855 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
1961 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
1856 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
1962 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
1857 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
1963 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
1858 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
1964 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
1859 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
1965 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
1860 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
1966 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
1861 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
1967 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
1862 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
1968 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
1863 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
1969 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
1864 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
1970 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
1865 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
1971 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
1866 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
1972 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
1867 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
1973 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
1868 | 1974 | ||
1869 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
1975 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
1870 | /* This bit must always be set on 965G/965GM */ |
1976 | /* This bit must always be set on 965G/965GM */ |
1871 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
1977 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
1872 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
1978 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
1873 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
1979 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
1874 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
1980 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
1875 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
1981 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
1876 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
1982 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
1877 | /* This bit must always be set on 965G */ |
1983 | /* This bit must always be set on 965G */ |
1878 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
1984 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
1879 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
1985 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
1880 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
1986 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
1881 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
1987 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
1882 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
1988 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
1883 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
1989 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
1884 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
1990 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
1885 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
1991 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
1886 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
1992 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
1887 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
1993 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
1888 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
1994 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
1889 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
1995 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
1890 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
1996 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
1891 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
1997 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
1892 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
1998 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
1893 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
1999 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
1894 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
2000 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
1895 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
2001 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
1896 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
2002 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
1897 | 2003 | ||
1898 | #define RENCLK_GATE_D2 0x6208 |
2004 | #define RENCLK_GATE_D2 0x6208 |
1899 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
2005 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
1900 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
2006 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
1901 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
2007 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
1902 | 2008 | ||
1903 | #define VDECCLK_GATE_D 0x620C /* g4x only */ |
2009 | #define VDECCLK_GATE_D 0x620C /* g4x only */ |
1904 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
2010 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
1905 | 2011 | ||
1906 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
2012 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
1907 | #define DEUC 0x6214 /* CRL only */ |
2013 | #define DEUC 0x6214 /* CRL only */ |
1908 | 2014 | ||
1909 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) |
2015 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) |
1910 | #define FW_CSPWRDWNEN (1<<15) |
2016 | #define FW_CSPWRDWNEN (1<<15) |
1911 | 2017 | ||
1912 | #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) |
2018 | #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) |
1913 | 2019 | ||
1914 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) |
2020 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) |
1915 | #define CDCLK_FREQ_SHIFT 4 |
2021 | #define CDCLK_FREQ_SHIFT 4 |
1916 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
2022 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
1917 | #define CZCLK_FREQ_MASK 0xf |
2023 | #define CZCLK_FREQ_MASK 0xf |
1918 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) |
2024 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) |
1919 | 2025 | ||
1920 | /* |
2026 | /* |
1921 | * Palette regs |
2027 | * Palette regs |
1922 | */ |
2028 | */ |
1923 | #define PALETTE_A_OFFSET 0xa000 |
2029 | #define PALETTE_A_OFFSET 0xa000 |
1924 | #define PALETTE_B_OFFSET 0xa800 |
2030 | #define PALETTE_B_OFFSET 0xa800 |
1925 | #define CHV_PALETTE_C_OFFSET 0xc000 |
2031 | #define CHV_PALETTE_C_OFFSET 0xc000 |
1926 | #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ |
2032 | #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ |
1927 | dev_priv->info.display_mmio_offset) |
2033 | dev_priv->info.display_mmio_offset) |
1928 | 2034 | ||
1929 | /* MCH MMIO space */ |
2035 | /* MCH MMIO space */ |
1930 | 2036 | ||
1931 | /* |
2037 | /* |
1932 | * MCHBAR mirror. |
2038 | * MCHBAR mirror. |
1933 | * |
2039 | * |
1934 | * This mirrors the MCHBAR MMIO space whose location is determined by |
2040 | * This mirrors the MCHBAR MMIO space whose location is determined by |
1935 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
2041 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
1936 | * every way. It is not accessible from the CP register read instructions. |
2042 | * every way. It is not accessible from the CP register read instructions. |
1937 | * |
2043 | * |
1938 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
2044 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
1939 | * just read. |
2045 | * just read. |
1940 | */ |
2046 | */ |
1941 | #define MCHBAR_MIRROR_BASE 0x10000 |
2047 | #define MCHBAR_MIRROR_BASE 0x10000 |
1942 | 2048 | ||
1943 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
2049 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
1944 | 2050 | ||
1945 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
2051 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
1946 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
2052 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
1947 | 2053 | ||
1948 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ |
2054 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ |
1949 | #define DCC 0x10200 |
2055 | #define DCC 0x10200 |
1950 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
2056 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
1951 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) |
2057 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) |
1952 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) |
2058 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) |
1953 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) |
2059 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) |
1954 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) |
2060 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) |
1955 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
2061 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
- | 2062 | #define DCC2 0x10204 |
|
- | 2063 | #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) |
|
1956 | 2064 | ||
1957 | /* Pineview MCH register contains DDR3 setting */ |
2065 | /* Pineview MCH register contains DDR3 setting */ |
1958 | #define CSHRDDR3CTL 0x101a8 |
2066 | #define CSHRDDR3CTL 0x101a8 |
1959 | #define CSHRDDR3CTL_DDR3 (1 << 2) |
2067 | #define CSHRDDR3CTL_DDR3 (1 << 2) |
1960 | 2068 | ||
1961 | /* 965 MCH register controlling DRAM channel configuration */ |
2069 | /* 965 MCH register controlling DRAM channel configuration */ |
1962 | #define C0DRB3 0x10206 |
2070 | #define C0DRB3 0x10206 |
1963 | #define C1DRB3 0x10606 |
2071 | #define C1DRB3 0x10606 |
1964 | 2072 | ||
1965 | /* snb MCH registers for reading the DRAM channel configuration */ |
2073 | /* snb MCH registers for reading the DRAM channel configuration */ |
1966 | #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) |
2074 | #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) |
1967 | #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) |
2075 | #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) |
1968 | #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) |
2076 | #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) |
1969 | #define MAD_DIMM_ECC_MASK (0x3 << 24) |
2077 | #define MAD_DIMM_ECC_MASK (0x3 << 24) |
1970 | #define MAD_DIMM_ECC_OFF (0x0 << 24) |
2078 | #define MAD_DIMM_ECC_OFF (0x0 << 24) |
1971 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) |
2079 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) |
1972 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) |
2080 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) |
1973 | #define MAD_DIMM_ECC_ON (0x3 << 24) |
2081 | #define MAD_DIMM_ECC_ON (0x3 << 24) |
1974 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) |
2082 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) |
1975 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) |
2083 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) |
1976 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ |
2084 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ |
1977 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ |
2085 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ |
1978 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) |
2086 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) |
1979 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) |
2087 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) |
1980 | #define MAD_DIMM_A_SELECT (0x1 << 16) |
2088 | #define MAD_DIMM_A_SELECT (0x1 << 16) |
1981 | /* DIMM sizes are in multiples of 256mb. */ |
2089 | /* DIMM sizes are in multiples of 256mb. */ |
1982 | #define MAD_DIMM_B_SIZE_SHIFT 8 |
2090 | #define MAD_DIMM_B_SIZE_SHIFT 8 |
1983 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) |
2091 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) |
1984 | #define MAD_DIMM_A_SIZE_SHIFT 0 |
2092 | #define MAD_DIMM_A_SIZE_SHIFT 0 |
1985 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) |
2093 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) |
1986 | 2094 | ||
1987 | /* snb MCH registers for priority tuning */ |
2095 | /* snb MCH registers for priority tuning */ |
1988 | #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
2096 | #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
1989 | #define MCH_SSKPD_WM0_MASK 0x3f |
2097 | #define MCH_SSKPD_WM0_MASK 0x3f |
1990 | #define MCH_SSKPD_WM0_VAL 0xc |
2098 | #define MCH_SSKPD_WM0_VAL 0xc |
1991 | 2099 | ||
1992 | #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) |
2100 | #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) |
1993 | 2101 | ||
1994 | /* Clocking configuration register */ |
2102 | /* Clocking configuration register */ |
1995 | #define CLKCFG 0x10c00 |
2103 | #define CLKCFG 0x10c00 |
1996 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
2104 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
1997 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
2105 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
1998 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ |
2106 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ |
1999 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ |
2107 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ |
2000 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ |
2108 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ |
2001 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ |
2109 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ |
2002 | /* Note, below two are guess */ |
2110 | /* Note, below two are guess */ |
2003 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ |
2111 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ |
2004 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ |
2112 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ |
2005 | #define CLKCFG_FSB_MASK (7 << 0) |
2113 | #define CLKCFG_FSB_MASK (7 << 0) |
2006 | #define CLKCFG_MEM_533 (1 << 4) |
2114 | #define CLKCFG_MEM_533 (1 << 4) |
2007 | #define CLKCFG_MEM_667 (2 << 4) |
2115 | #define CLKCFG_MEM_667 (2 << 4) |
2008 | #define CLKCFG_MEM_800 (3 << 4) |
2116 | #define CLKCFG_MEM_800 (3 << 4) |
2009 | #define CLKCFG_MEM_MASK (7 << 4) |
2117 | #define CLKCFG_MEM_MASK (7 << 4) |
2010 | 2118 | ||
2011 | #define TSC1 0x11001 |
2119 | #define TSC1 0x11001 |
2012 | #define TSE (1<<0) |
2120 | #define TSE (1<<0) |
2013 | #define TR1 0x11006 |
2121 | #define TR1 0x11006 |
2014 | #define TSFS 0x11020 |
2122 | #define TSFS 0x11020 |
2015 | #define TSFS_SLOPE_MASK 0x0000ff00 |
2123 | #define TSFS_SLOPE_MASK 0x0000ff00 |
2016 | #define TSFS_SLOPE_SHIFT 8 |
2124 | #define TSFS_SLOPE_SHIFT 8 |
2017 | #define TSFS_INTR_MASK 0x000000ff |
2125 | #define TSFS_INTR_MASK 0x000000ff |
2018 | 2126 | ||
2019 | #define CRSTANDVID 0x11100 |
2127 | #define CRSTANDVID 0x11100 |
2020 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
2128 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
2021 | #define PXVFREQ_PX_MASK 0x7f000000 |
2129 | #define PXVFREQ_PX_MASK 0x7f000000 |
2022 | #define PXVFREQ_PX_SHIFT 24 |
2130 | #define PXVFREQ_PX_SHIFT 24 |
2023 | #define VIDFREQ_BASE 0x11110 |
2131 | #define VIDFREQ_BASE 0x11110 |
2024 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ |
2132 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ |
2025 | #define VIDFREQ2 0x11114 |
2133 | #define VIDFREQ2 0x11114 |
2026 | #define VIDFREQ3 0x11118 |
2134 | #define VIDFREQ3 0x11118 |
2027 | #define VIDFREQ4 0x1111c |
2135 | #define VIDFREQ4 0x1111c |
2028 | #define VIDFREQ_P0_MASK 0x1f000000 |
2136 | #define VIDFREQ_P0_MASK 0x1f000000 |
2029 | #define VIDFREQ_P0_SHIFT 24 |
2137 | #define VIDFREQ_P0_SHIFT 24 |
2030 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 |
2138 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 |
2031 | #define VIDFREQ_P0_CSCLK_SHIFT 20 |
2139 | #define VIDFREQ_P0_CSCLK_SHIFT 20 |
2032 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 |
2140 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 |
2033 | #define VIDFREQ_P0_CRCLK_SHIFT 16 |
2141 | #define VIDFREQ_P0_CRCLK_SHIFT 16 |
2034 | #define VIDFREQ_P1_MASK 0x00001f00 |
2142 | #define VIDFREQ_P1_MASK 0x00001f00 |
2035 | #define VIDFREQ_P1_SHIFT 8 |
2143 | #define VIDFREQ_P1_SHIFT 8 |
2036 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 |
2144 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 |
2037 | #define VIDFREQ_P1_CSCLK_SHIFT 4 |
2145 | #define VIDFREQ_P1_CSCLK_SHIFT 4 |
2038 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f |
2146 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f |
2039 | #define INTTOEXT_BASE_ILK 0x11300 |
2147 | #define INTTOEXT_BASE_ILK 0x11300 |
2040 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ |
2148 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ |
2041 | #define INTTOEXT_MAP3_SHIFT 24 |
2149 | #define INTTOEXT_MAP3_SHIFT 24 |
2042 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) |
2150 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) |
2043 | #define INTTOEXT_MAP2_SHIFT 16 |
2151 | #define INTTOEXT_MAP2_SHIFT 16 |
2044 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) |
2152 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) |
2045 | #define INTTOEXT_MAP1_SHIFT 8 |
2153 | #define INTTOEXT_MAP1_SHIFT 8 |
2046 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) |
2154 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) |
2047 | #define INTTOEXT_MAP0_SHIFT 0 |
2155 | #define INTTOEXT_MAP0_SHIFT 0 |
2048 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) |
2156 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) |
2049 | #define MEMSWCTL 0x11170 /* Ironlake only */ |
2157 | #define MEMSWCTL 0x11170 /* Ironlake only */ |
2050 | #define MEMCTL_CMD_MASK 0xe000 |
2158 | #define MEMCTL_CMD_MASK 0xe000 |
2051 | #define MEMCTL_CMD_SHIFT 13 |
2159 | #define MEMCTL_CMD_SHIFT 13 |
2052 | #define MEMCTL_CMD_RCLK_OFF 0 |
2160 | #define MEMCTL_CMD_RCLK_OFF 0 |
2053 | #define MEMCTL_CMD_RCLK_ON 1 |
2161 | #define MEMCTL_CMD_RCLK_ON 1 |
2054 | #define MEMCTL_CMD_CHFREQ 2 |
2162 | #define MEMCTL_CMD_CHFREQ 2 |
2055 | #define MEMCTL_CMD_CHVID 3 |
2163 | #define MEMCTL_CMD_CHVID 3 |
2056 | #define MEMCTL_CMD_VMMOFF 4 |
2164 | #define MEMCTL_CMD_VMMOFF 4 |
2057 | #define MEMCTL_CMD_VMMON 5 |
2165 | #define MEMCTL_CMD_VMMON 5 |
2058 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears |
2166 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears |
2059 | when command complete */ |
2167 | when command complete */ |
2060 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ |
2168 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ |
2061 | #define MEMCTL_FREQ_SHIFT 8 |
2169 | #define MEMCTL_FREQ_SHIFT 8 |
2062 | #define MEMCTL_SFCAVM (1<<7) |
2170 | #define MEMCTL_SFCAVM (1<<7) |
2063 | #define MEMCTL_TGT_VID_MASK 0x007f |
2171 | #define MEMCTL_TGT_VID_MASK 0x007f |
2064 | #define MEMIHYST 0x1117c |
2172 | #define MEMIHYST 0x1117c |
2065 | #define MEMINTREN 0x11180 /* 16 bits */ |
2173 | #define MEMINTREN 0x11180 /* 16 bits */ |
2066 | #define MEMINT_RSEXIT_EN (1<<8) |
2174 | #define MEMINT_RSEXIT_EN (1<<8) |
2067 | #define MEMINT_CX_SUPR_EN (1<<7) |
2175 | #define MEMINT_CX_SUPR_EN (1<<7) |
2068 | #define MEMINT_CONT_BUSY_EN (1<<6) |
2176 | #define MEMINT_CONT_BUSY_EN (1<<6) |
2069 | #define MEMINT_AVG_BUSY_EN (1<<5) |
2177 | #define MEMINT_AVG_BUSY_EN (1<<5) |
2070 | #define MEMINT_EVAL_CHG_EN (1<<4) |
2178 | #define MEMINT_EVAL_CHG_EN (1<<4) |
2071 | #define MEMINT_MON_IDLE_EN (1<<3) |
2179 | #define MEMINT_MON_IDLE_EN (1<<3) |
2072 | #define MEMINT_UP_EVAL_EN (1<<2) |
2180 | #define MEMINT_UP_EVAL_EN (1<<2) |
2073 | #define MEMINT_DOWN_EVAL_EN (1<<1) |
2181 | #define MEMINT_DOWN_EVAL_EN (1<<1) |
2074 | #define MEMINT_SW_CMD_EN (1<<0) |
2182 | #define MEMINT_SW_CMD_EN (1<<0) |
2075 | #define MEMINTRSTR 0x11182 /* 16 bits */ |
2183 | #define MEMINTRSTR 0x11182 /* 16 bits */ |
2076 | #define MEM_RSEXIT_MASK 0xc000 |
2184 | #define MEM_RSEXIT_MASK 0xc000 |
2077 | #define MEM_RSEXIT_SHIFT 14 |
2185 | #define MEM_RSEXIT_SHIFT 14 |
2078 | #define MEM_CONT_BUSY_MASK 0x3000 |
2186 | #define MEM_CONT_BUSY_MASK 0x3000 |
2079 | #define MEM_CONT_BUSY_SHIFT 12 |
2187 | #define MEM_CONT_BUSY_SHIFT 12 |
2080 | #define MEM_AVG_BUSY_MASK 0x0c00 |
2188 | #define MEM_AVG_BUSY_MASK 0x0c00 |
2081 | #define MEM_AVG_BUSY_SHIFT 10 |
2189 | #define MEM_AVG_BUSY_SHIFT 10 |
2082 | #define MEM_EVAL_CHG_MASK 0x0300 |
2190 | #define MEM_EVAL_CHG_MASK 0x0300 |
2083 | #define MEM_EVAL_BUSY_SHIFT 8 |
2191 | #define MEM_EVAL_BUSY_SHIFT 8 |
2084 | #define MEM_MON_IDLE_MASK 0x00c0 |
2192 | #define MEM_MON_IDLE_MASK 0x00c0 |
2085 | #define MEM_MON_IDLE_SHIFT 6 |
2193 | #define MEM_MON_IDLE_SHIFT 6 |
2086 | #define MEM_UP_EVAL_MASK 0x0030 |
2194 | #define MEM_UP_EVAL_MASK 0x0030 |
2087 | #define MEM_UP_EVAL_SHIFT 4 |
2195 | #define MEM_UP_EVAL_SHIFT 4 |
2088 | #define MEM_DOWN_EVAL_MASK 0x000c |
2196 | #define MEM_DOWN_EVAL_MASK 0x000c |
2089 | #define MEM_DOWN_EVAL_SHIFT 2 |
2197 | #define MEM_DOWN_EVAL_SHIFT 2 |
2090 | #define MEM_SW_CMD_MASK 0x0003 |
2198 | #define MEM_SW_CMD_MASK 0x0003 |
2091 | #define MEM_INT_STEER_GFX 0 |
2199 | #define MEM_INT_STEER_GFX 0 |
2092 | #define MEM_INT_STEER_CMR 1 |
2200 | #define MEM_INT_STEER_CMR 1 |
2093 | #define MEM_INT_STEER_SMI 2 |
2201 | #define MEM_INT_STEER_SMI 2 |
2094 | #define MEM_INT_STEER_SCI 3 |
2202 | #define MEM_INT_STEER_SCI 3 |
2095 | #define MEMINTRSTS 0x11184 |
2203 | #define MEMINTRSTS 0x11184 |
2096 | #define MEMINT_RSEXIT (1<<7) |
2204 | #define MEMINT_RSEXIT (1<<7) |
2097 | #define MEMINT_CONT_BUSY (1<<6) |
2205 | #define MEMINT_CONT_BUSY (1<<6) |
2098 | #define MEMINT_AVG_BUSY (1<<5) |
2206 | #define MEMINT_AVG_BUSY (1<<5) |
2099 | #define MEMINT_EVAL_CHG (1<<4) |
2207 | #define MEMINT_EVAL_CHG (1<<4) |
2100 | #define MEMINT_MON_IDLE (1<<3) |
2208 | #define MEMINT_MON_IDLE (1<<3) |
2101 | #define MEMINT_UP_EVAL (1<<2) |
2209 | #define MEMINT_UP_EVAL (1<<2) |
2102 | #define MEMINT_DOWN_EVAL (1<<1) |
2210 | #define MEMINT_DOWN_EVAL (1<<1) |
2103 | #define MEMINT_SW_CMD (1<<0) |
2211 | #define MEMINT_SW_CMD (1<<0) |
2104 | #define MEMMODECTL 0x11190 |
2212 | #define MEMMODECTL 0x11190 |
2105 | #define MEMMODE_BOOST_EN (1<<31) |
2213 | #define MEMMODE_BOOST_EN (1<<31) |
2106 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ |
2214 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ |
2107 | #define MEMMODE_BOOST_FREQ_SHIFT 24 |
2215 | #define MEMMODE_BOOST_FREQ_SHIFT 24 |
2108 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 |
2216 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 |
2109 | #define MEMMODE_IDLE_MODE_SHIFT 16 |
2217 | #define MEMMODE_IDLE_MODE_SHIFT 16 |
2110 | #define MEMMODE_IDLE_MODE_EVAL 0 |
2218 | #define MEMMODE_IDLE_MODE_EVAL 0 |
2111 | #define MEMMODE_IDLE_MODE_CONT 1 |
2219 | #define MEMMODE_IDLE_MODE_CONT 1 |
2112 | #define MEMMODE_HWIDLE_EN (1<<15) |
2220 | #define MEMMODE_HWIDLE_EN (1<<15) |
2113 | #define MEMMODE_SWMODE_EN (1<<14) |
2221 | #define MEMMODE_SWMODE_EN (1<<14) |
2114 | #define MEMMODE_RCLK_GATE (1<<13) |
2222 | #define MEMMODE_RCLK_GATE (1<<13) |
2115 | #define MEMMODE_HW_UPDATE (1<<12) |
2223 | #define MEMMODE_HW_UPDATE (1<<12) |
2116 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ |
2224 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ |
2117 | #define MEMMODE_FSTART_SHIFT 8 |
2225 | #define MEMMODE_FSTART_SHIFT 8 |
2118 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ |
2226 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ |
2119 | #define MEMMODE_FMAX_SHIFT 4 |
2227 | #define MEMMODE_FMAX_SHIFT 4 |
2120 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ |
2228 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ |
2121 | #define RCBMAXAVG 0x1119c |
2229 | #define RCBMAXAVG 0x1119c |
2122 | #define MEMSWCTL2 0x1119e /* Cantiga only */ |
2230 | #define MEMSWCTL2 0x1119e /* Cantiga only */ |
2123 | #define SWMEMCMD_RENDER_OFF (0 << 13) |
2231 | #define SWMEMCMD_RENDER_OFF (0 << 13) |
2124 | #define SWMEMCMD_RENDER_ON (1 << 13) |
2232 | #define SWMEMCMD_RENDER_ON (1 << 13) |
2125 | #define SWMEMCMD_SWFREQ (2 << 13) |
2233 | #define SWMEMCMD_SWFREQ (2 << 13) |
2126 | #define SWMEMCMD_TARVID (3 << 13) |
2234 | #define SWMEMCMD_TARVID (3 << 13) |
2127 | #define SWMEMCMD_VRM_OFF (4 << 13) |
2235 | #define SWMEMCMD_VRM_OFF (4 << 13) |
2128 | #define SWMEMCMD_VRM_ON (5 << 13) |
2236 | #define SWMEMCMD_VRM_ON (5 << 13) |
2129 | #define CMDSTS (1<<12) |
2237 | #define CMDSTS (1<<12) |
2130 | #define SFCAVM (1<<11) |
2238 | #define SFCAVM (1<<11) |
2131 | #define SWFREQ_MASK 0x0380 /* P0-7 */ |
2239 | #define SWFREQ_MASK 0x0380 /* P0-7 */ |
2132 | #define SWFREQ_SHIFT 7 |
2240 | #define SWFREQ_SHIFT 7 |
2133 | #define TARVID_MASK 0x001f |
2241 | #define TARVID_MASK 0x001f |
2134 | #define MEMSTAT_CTG 0x111a0 |
2242 | #define MEMSTAT_CTG 0x111a0 |
2135 | #define RCBMINAVG 0x111a0 |
2243 | #define RCBMINAVG 0x111a0 |
2136 | #define RCUPEI 0x111b0 |
2244 | #define RCUPEI 0x111b0 |
2137 | #define RCDNEI 0x111b4 |
2245 | #define RCDNEI 0x111b4 |
2138 | #define RSTDBYCTL 0x111b8 |
2246 | #define RSTDBYCTL 0x111b8 |
2139 | #define RS1EN (1<<31) |
2247 | #define RS1EN (1<<31) |
2140 | #define RS2EN (1<<30) |
2248 | #define RS2EN (1<<30) |
2141 | #define RS3EN (1<<29) |
2249 | #define RS3EN (1<<29) |
2142 | #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ |
2250 | #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ |
2143 | #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ |
2251 | #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ |
2144 | #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ |
2252 | #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ |
2145 | #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ |
2253 | #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ |
2146 | #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ |
2254 | #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ |
2147 | #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ |
2255 | #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ |
2148 | #define RSX_STATUS_MASK (7<<20) |
2256 | #define RSX_STATUS_MASK (7<<20) |
2149 | #define RSX_STATUS_ON (0<<20) |
2257 | #define RSX_STATUS_ON (0<<20) |
2150 | #define RSX_STATUS_RC1 (1<<20) |
2258 | #define RSX_STATUS_RC1 (1<<20) |
2151 | #define RSX_STATUS_RC1E (2<<20) |
2259 | #define RSX_STATUS_RC1E (2<<20) |
2152 | #define RSX_STATUS_RS1 (3<<20) |
2260 | #define RSX_STATUS_RS1 (3<<20) |
2153 | #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ |
2261 | #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ |
2154 | #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ |
2262 | #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ |
2155 | #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ |
2263 | #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ |
2156 | #define RSX_STATUS_RSVD2 (7<<20) |
2264 | #define RSX_STATUS_RSVD2 (7<<20) |
2157 | #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ |
2265 | #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ |
2158 | #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ |
2266 | #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ |
2159 | #define JRSC (1<<17) /* rsx coupled to cpu c-state */ |
2267 | #define JRSC (1<<17) /* rsx coupled to cpu c-state */ |
2160 | #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ |
2268 | #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ |
2161 | #define RS1CONTSAV_MASK (3<<14) |
2269 | #define RS1CONTSAV_MASK (3<<14) |
2162 | #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ |
2270 | #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ |
2163 | #define RS1CONTSAV_RSVD (1<<14) |
2271 | #define RS1CONTSAV_RSVD (1<<14) |
2164 | #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ |
2272 | #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ |
2165 | #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ |
2273 | #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ |
2166 | #define NORMSLEXLAT_MASK (3<<12) |
2274 | #define NORMSLEXLAT_MASK (3<<12) |
2167 | #define SLOW_RS123 (0<<12) |
2275 | #define SLOW_RS123 (0<<12) |
2168 | #define SLOW_RS23 (1<<12) |
2276 | #define SLOW_RS23 (1<<12) |
2169 | #define SLOW_RS3 (2<<12) |
2277 | #define SLOW_RS3 (2<<12) |
2170 | #define NORMAL_RS123 (3<<12) |
2278 | #define NORMAL_RS123 (3<<12) |
2171 | #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ |
2279 | #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ |
2172 | #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ |
2280 | #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ |
2173 | #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ |
2281 | #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ |
2174 | #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ |
2282 | #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ |
2175 | #define RS_CSTATE_MASK (3<<4) |
2283 | #define RS_CSTATE_MASK (3<<4) |
2176 | #define RS_CSTATE_C367_RS1 (0<<4) |
2284 | #define RS_CSTATE_C367_RS1 (0<<4) |
2177 | #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) |
2285 | #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) |
2178 | #define RS_CSTATE_RSVD (2<<4) |
2286 | #define RS_CSTATE_RSVD (2<<4) |
2179 | #define RS_CSTATE_C367_RS2 (3<<4) |
2287 | #define RS_CSTATE_C367_RS2 (3<<4) |
2180 | #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ |
2288 | #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ |
2181 | #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ |
2289 | #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ |
2182 | #define VIDCTL 0x111c0 |
2290 | #define VIDCTL 0x111c0 |
2183 | #define VIDSTS 0x111c8 |
2291 | #define VIDSTS 0x111c8 |
2184 | #define VIDSTART 0x111cc /* 8 bits */ |
2292 | #define VIDSTART 0x111cc /* 8 bits */ |
2185 | #define MEMSTAT_ILK 0x111f8 |
2293 | #define MEMSTAT_ILK 0x111f8 |
2186 | #define MEMSTAT_VID_MASK 0x7f00 |
2294 | #define MEMSTAT_VID_MASK 0x7f00 |
2187 | #define MEMSTAT_VID_SHIFT 8 |
2295 | #define MEMSTAT_VID_SHIFT 8 |
2188 | #define MEMSTAT_PSTATE_MASK 0x00f8 |
2296 | #define MEMSTAT_PSTATE_MASK 0x00f8 |
2189 | #define MEMSTAT_PSTATE_SHIFT 3 |
2297 | #define MEMSTAT_PSTATE_SHIFT 3 |
2190 | #define MEMSTAT_MON_ACTV (1<<2) |
2298 | #define MEMSTAT_MON_ACTV (1<<2) |
2191 | #define MEMSTAT_SRC_CTL_MASK 0x0003 |
2299 | #define MEMSTAT_SRC_CTL_MASK 0x0003 |
2192 | #define MEMSTAT_SRC_CTL_CORE 0 |
2300 | #define MEMSTAT_SRC_CTL_CORE 0 |
2193 | #define MEMSTAT_SRC_CTL_TRB 1 |
2301 | #define MEMSTAT_SRC_CTL_TRB 1 |
2194 | #define MEMSTAT_SRC_CTL_THM 2 |
2302 | #define MEMSTAT_SRC_CTL_THM 2 |
2195 | #define MEMSTAT_SRC_CTL_STDBY 3 |
2303 | #define MEMSTAT_SRC_CTL_STDBY 3 |
2196 | #define RCPREVBSYTUPAVG 0x113b8 |
2304 | #define RCPREVBSYTUPAVG 0x113b8 |
2197 | #define RCPREVBSYTDNAVG 0x113bc |
2305 | #define RCPREVBSYTDNAVG 0x113bc |
2198 | #define PMMISC 0x11214 |
2306 | #define PMMISC 0x11214 |
2199 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ |
2307 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ |
2200 | #define SDEW 0x1124c |
2308 | #define SDEW 0x1124c |
2201 | #define CSIEW0 0x11250 |
2309 | #define CSIEW0 0x11250 |
2202 | #define CSIEW1 0x11254 |
2310 | #define CSIEW1 0x11254 |
2203 | #define CSIEW2 0x11258 |
2311 | #define CSIEW2 0x11258 |
2204 | #define PEW 0x1125c |
2312 | #define PEW 0x1125c |
2205 | #define DEW 0x11270 |
2313 | #define DEW 0x11270 |
2206 | #define MCHAFE 0x112c0 |
2314 | #define MCHAFE 0x112c0 |
2207 | #define CSIEC 0x112e0 |
2315 | #define CSIEC 0x112e0 |
2208 | #define DMIEC 0x112e4 |
2316 | #define DMIEC 0x112e4 |
2209 | #define DDREC 0x112e8 |
2317 | #define DDREC 0x112e8 |
2210 | #define PEG0EC 0x112ec |
2318 | #define PEG0EC 0x112ec |
2211 | #define PEG1EC 0x112f0 |
2319 | #define PEG1EC 0x112f0 |
2212 | #define GFXEC 0x112f4 |
2320 | #define GFXEC 0x112f4 |
2213 | #define RPPREVBSYTUPAVG 0x113b8 |
2321 | #define RPPREVBSYTUPAVG 0x113b8 |
2214 | #define RPPREVBSYTDNAVG 0x113bc |
2322 | #define RPPREVBSYTDNAVG 0x113bc |
2215 | #define ECR 0x11600 |
2323 | #define ECR 0x11600 |
2216 | #define ECR_GPFE (1<<31) |
2324 | #define ECR_GPFE (1<<31) |
2217 | #define ECR_IMONE (1<<30) |
2325 | #define ECR_IMONE (1<<30) |
2218 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ |
2326 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ |
2219 | #define OGW0 0x11608 |
2327 | #define OGW0 0x11608 |
2220 | #define OGW1 0x1160c |
2328 | #define OGW1 0x1160c |
2221 | #define EG0 0x11610 |
2329 | #define EG0 0x11610 |
2222 | #define EG1 0x11614 |
2330 | #define EG1 0x11614 |
2223 | #define EG2 0x11618 |
2331 | #define EG2 0x11618 |
2224 | #define EG3 0x1161c |
2332 | #define EG3 0x1161c |
2225 | #define EG4 0x11620 |
2333 | #define EG4 0x11620 |
2226 | #define EG5 0x11624 |
2334 | #define EG5 0x11624 |
2227 | #define EG6 0x11628 |
2335 | #define EG6 0x11628 |
2228 | #define EG7 0x1162c |
2336 | #define EG7 0x1162c |
2229 | #define PXW 0x11664 |
2337 | #define PXW 0x11664 |
2230 | #define PXWL 0x11680 |
2338 | #define PXWL 0x11680 |
2231 | #define LCFUSE02 0x116c0 |
2339 | #define LCFUSE02 0x116c0 |
2232 | #define LCFUSE_HIV_MASK 0x000000ff |
2340 | #define LCFUSE_HIV_MASK 0x000000ff |
2233 | #define CSIPLL0 0x12c10 |
2341 | #define CSIPLL0 0x12c10 |
2234 | #define DDRMPLL1 0X12c20 |
2342 | #define DDRMPLL1 0X12c20 |
2235 | #define PEG_BAND_GAP_DATA 0x14d68 |
2343 | #define PEG_BAND_GAP_DATA 0x14d68 |
2236 | 2344 | ||
2237 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
2345 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
2238 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
2346 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
2239 | #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) |
- | |
2240 | 2347 | ||
2241 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
2348 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
2242 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
2349 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
2243 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
2350 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) |
2244 | 2351 | ||
2245 | /* |
2352 | /* |
2246 | * Logical Context regs |
2353 | * Logical Context regs |
2247 | */ |
2354 | */ |
2248 | #define CCID 0x2180 |
2355 | #define CCID 0x2180 |
2249 | #define CCID_EN (1<<0) |
2356 | #define CCID_EN (1<<0) |
2250 | /* |
2357 | /* |
2251 | * Notes on SNB/IVB/VLV context size: |
2358 | * Notes on SNB/IVB/VLV context size: |
2252 | * - Power context is saved elsewhere (LLC or stolen) |
2359 | * - Power context is saved elsewhere (LLC or stolen) |
2253 | * - Ring/execlist context is saved on SNB, not on IVB |
2360 | * - Ring/execlist context is saved on SNB, not on IVB |
2254 | * - Extended context size already includes render context size |
2361 | * - Extended context size already includes render context size |
2255 | * - We always need to follow the extended context size. |
2362 | * - We always need to follow the extended context size. |
2256 | * SNB BSpec has comments indicating that we should use the |
2363 | * SNB BSpec has comments indicating that we should use the |
2257 | * render context size instead if execlists are disabled, but |
2364 | * render context size instead if execlists are disabled, but |
2258 | * based on empirical testing that's just nonsense. |
2365 | * based on empirical testing that's just nonsense. |
2259 | * - Pipelined/VF state is saved on SNB/IVB respectively |
2366 | * - Pipelined/VF state is saved on SNB/IVB respectively |
2260 | * - GT1 size just indicates how much of render context |
2367 | * - GT1 size just indicates how much of render context |
2261 | * doesn't need saving on GT1 |
2368 | * doesn't need saving on GT1 |
2262 | */ |
2369 | */ |
2263 | #define CXT_SIZE 0x21a0 |
2370 | #define CXT_SIZE 0x21a0 |
2264 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) |
2371 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) |
2265 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) |
2372 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) |
2266 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) |
2373 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) |
2267 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) |
2374 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) |
2268 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) |
2375 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) |
2269 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
2376 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
2270 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
2377 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
2271 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) |
2378 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) |
2272 | #define GEN7_CXT_SIZE 0x21a8 |
2379 | #define GEN7_CXT_SIZE 0x21a8 |
2273 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
2380 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
2274 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) |
2381 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) |
2275 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
2382 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
2276 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) |
2383 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) |
2277 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) |
2384 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) |
2278 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) |
2385 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) |
2279 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
2386 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
2280 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
2387 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
2281 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
2388 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
2282 | * valid. Now, docs explain in dwords what is in the context object. The full |
2389 | * valid. Now, docs explain in dwords what is in the context object. The full |
2283 | * size is 70720 bytes, however, the power context and execlist context will |
2390 | * size is 70720 bytes, however, the power context and execlist context will |
2284 | * never be saved (power context is stored elsewhere, and execlists don't work |
2391 | * never be saved (power context is stored elsewhere, and execlists don't work |
2285 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. |
2392 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. |
2286 | */ |
2393 | */ |
2287 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) |
2394 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) |
2288 | /* Same as Haswell, but 72064 bytes now. */ |
2395 | /* Same as Haswell, but 72064 bytes now. */ |
2289 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) |
2396 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) |
2290 | 2397 | ||
2291 | #define CHV_CLK_CTL1 0x101100 |
2398 | #define CHV_CLK_CTL1 0x101100 |
2292 | #define VLV_CLK_CTL2 0x101104 |
2399 | #define VLV_CLK_CTL2 0x101104 |
2293 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
2400 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
2294 | 2401 | ||
2295 | /* |
2402 | /* |
2296 | * Overlay regs |
2403 | * Overlay regs |
2297 | */ |
2404 | */ |
2298 | 2405 | ||
2299 | #define OVADD 0x30000 |
2406 | #define OVADD 0x30000 |
2300 | #define DOVSTA 0x30008 |
2407 | #define DOVSTA 0x30008 |
2301 | #define OC_BUF (0x3<<20) |
2408 | #define OC_BUF (0x3<<20) |
2302 | #define OGAMC5 0x30010 |
2409 | #define OGAMC5 0x30010 |
2303 | #define OGAMC4 0x30014 |
2410 | #define OGAMC4 0x30014 |
2304 | #define OGAMC3 0x30018 |
2411 | #define OGAMC3 0x30018 |
2305 | #define OGAMC2 0x3001c |
2412 | #define OGAMC2 0x3001c |
2306 | #define OGAMC1 0x30020 |
2413 | #define OGAMC1 0x30020 |
2307 | #define OGAMC0 0x30024 |
2414 | #define OGAMC0 0x30024 |
2308 | 2415 | ||
2309 | /* |
2416 | /* |
2310 | * Display engine regs |
2417 | * Display engine regs |
2311 | */ |
2418 | */ |
2312 | 2419 | ||
2313 | /* Pipe A CRC regs */ |
2420 | /* Pipe A CRC regs */ |
2314 | #define _PIPE_CRC_CTL_A 0x60050 |
2421 | #define _PIPE_CRC_CTL_A 0x60050 |
2315 | #define PIPE_CRC_ENABLE (1 << 31) |
2422 | #define PIPE_CRC_ENABLE (1 << 31) |
2316 | /* ivb+ source selection */ |
2423 | /* ivb+ source selection */ |
2317 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
2424 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
2318 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) |
2425 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) |
2319 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) |
2426 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) |
2320 | /* ilk+ source selection */ |
2427 | /* ilk+ source selection */ |
2321 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
2428 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
2322 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) |
2429 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) |
2323 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) |
2430 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) |
2324 | /* embedded DP port on the north display block, reserved on ivb */ |
2431 | /* embedded DP port on the north display block, reserved on ivb */ |
2325 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) |
2432 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) |
2326 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ |
2433 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ |
2327 | /* vlv source selection */ |
2434 | /* vlv source selection */ |
2328 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) |
2435 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) |
2329 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) |
2436 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) |
2330 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) |
2437 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) |
2331 | /* with DP port the pipe source is invalid */ |
2438 | /* with DP port the pipe source is invalid */ |
2332 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) |
2439 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) |
2333 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) |
2440 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) |
2334 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) |
2441 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) |
2335 | /* gen3+ source selection */ |
2442 | /* gen3+ source selection */ |
2336 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) |
2443 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) |
2337 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) |
2444 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) |
2338 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) |
2445 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) |
2339 | /* with DP/TV port the pipe source is invalid */ |
2446 | /* with DP/TV port the pipe source is invalid */ |
2340 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) |
2447 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) |
2341 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) |
2448 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) |
2342 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) |
2449 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) |
2343 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) |
2450 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) |
2344 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) |
2451 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) |
2345 | /* gen2 doesn't have source selection bits */ |
2452 | /* gen2 doesn't have source selection bits */ |
2346 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) |
2453 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) |
2347 | 2454 | ||
2348 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
2455 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
2349 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 |
2456 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 |
2350 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c |
2457 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c |
2351 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 |
2458 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 |
2352 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 |
2459 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 |
2353 | 2460 | ||
2354 | #define _PIPE_CRC_RES_RED_A 0x60060 |
2461 | #define _PIPE_CRC_RES_RED_A 0x60060 |
2355 | #define _PIPE_CRC_RES_GREEN_A 0x60064 |
2462 | #define _PIPE_CRC_RES_GREEN_A 0x60064 |
2356 | #define _PIPE_CRC_RES_BLUE_A 0x60068 |
2463 | #define _PIPE_CRC_RES_BLUE_A 0x60068 |
2357 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c |
2464 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c |
2358 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 |
2465 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 |
2359 | 2466 | ||
2360 | /* Pipe B CRC regs */ |
2467 | /* Pipe B CRC regs */ |
2361 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
2468 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
2362 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 |
2469 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 |
2363 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c |
2470 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c |
2364 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 |
2471 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 |
2365 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 |
2472 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 |
2366 | 2473 | ||
2367 | #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) |
2474 | #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) |
2368 | #define PIPE_CRC_RES_1_IVB(pipe) \ |
2475 | #define PIPE_CRC_RES_1_IVB(pipe) \ |
2369 | _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) |
2476 | _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) |
2370 | #define PIPE_CRC_RES_2_IVB(pipe) \ |
2477 | #define PIPE_CRC_RES_2_IVB(pipe) \ |
2371 | _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) |
2478 | _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) |
2372 | #define PIPE_CRC_RES_3_IVB(pipe) \ |
2479 | #define PIPE_CRC_RES_3_IVB(pipe) \ |
2373 | _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) |
2480 | _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) |
2374 | #define PIPE_CRC_RES_4_IVB(pipe) \ |
2481 | #define PIPE_CRC_RES_4_IVB(pipe) \ |
2375 | _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) |
2482 | _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) |
2376 | #define PIPE_CRC_RES_5_IVB(pipe) \ |
2483 | #define PIPE_CRC_RES_5_IVB(pipe) \ |
2377 | _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) |
2484 | _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) |
2378 | 2485 | ||
2379 | #define PIPE_CRC_RES_RED(pipe) \ |
2486 | #define PIPE_CRC_RES_RED(pipe) \ |
2380 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) |
2487 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) |
2381 | #define PIPE_CRC_RES_GREEN(pipe) \ |
2488 | #define PIPE_CRC_RES_GREEN(pipe) \ |
2382 | _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) |
2489 | _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) |
2383 | #define PIPE_CRC_RES_BLUE(pipe) \ |
2490 | #define PIPE_CRC_RES_BLUE(pipe) \ |
2384 | _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) |
2491 | _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) |
2385 | #define PIPE_CRC_RES_RES1_I915(pipe) \ |
2492 | #define PIPE_CRC_RES_RES1_I915(pipe) \ |
2386 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) |
2493 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) |
2387 | #define PIPE_CRC_RES_RES2_G4X(pipe) \ |
2494 | #define PIPE_CRC_RES_RES2_G4X(pipe) \ |
2388 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) |
2495 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) |
2389 | 2496 | ||
2390 | /* Pipe A timing regs */ |
2497 | /* Pipe A timing regs */ |
2391 | #define _HTOTAL_A 0x60000 |
2498 | #define _HTOTAL_A 0x60000 |
2392 | #define _HBLANK_A 0x60004 |
2499 | #define _HBLANK_A 0x60004 |
2393 | #define _HSYNC_A 0x60008 |
2500 | #define _HSYNC_A 0x60008 |
2394 | #define _VTOTAL_A 0x6000c |
2501 | #define _VTOTAL_A 0x6000c |
2395 | #define _VBLANK_A 0x60010 |
2502 | #define _VBLANK_A 0x60010 |
2396 | #define _VSYNC_A 0x60014 |
2503 | #define _VSYNC_A 0x60014 |
2397 | #define _PIPEASRC 0x6001c |
2504 | #define _PIPEASRC 0x6001c |
2398 | #define _BCLRPAT_A 0x60020 |
2505 | #define _BCLRPAT_A 0x60020 |
2399 | #define _VSYNCSHIFT_A 0x60028 |
2506 | #define _VSYNCSHIFT_A 0x60028 |
- | 2507 | #define _PIPE_MULT_A 0x6002c |
|
2400 | 2508 | ||
2401 | /* Pipe B timing regs */ |
2509 | /* Pipe B timing regs */ |
2402 | #define _HTOTAL_B 0x61000 |
2510 | #define _HTOTAL_B 0x61000 |
2403 | #define _HBLANK_B 0x61004 |
2511 | #define _HBLANK_B 0x61004 |
2404 | #define _HSYNC_B 0x61008 |
2512 | #define _HSYNC_B 0x61008 |
2405 | #define _VTOTAL_B 0x6100c |
2513 | #define _VTOTAL_B 0x6100c |
2406 | #define _VBLANK_B 0x61010 |
2514 | #define _VBLANK_B 0x61010 |
2407 | #define _VSYNC_B 0x61014 |
2515 | #define _VSYNC_B 0x61014 |
2408 | #define _PIPEBSRC 0x6101c |
2516 | #define _PIPEBSRC 0x6101c |
2409 | #define _BCLRPAT_B 0x61020 |
2517 | #define _BCLRPAT_B 0x61020 |
2410 | #define _VSYNCSHIFT_B 0x61028 |
2518 | #define _VSYNCSHIFT_B 0x61028 |
- | 2519 | #define _PIPE_MULT_B 0x6102c |
|
2411 | 2520 | ||
2412 | #define TRANSCODER_A_OFFSET 0x60000 |
2521 | #define TRANSCODER_A_OFFSET 0x60000 |
2413 | #define TRANSCODER_B_OFFSET 0x61000 |
2522 | #define TRANSCODER_B_OFFSET 0x61000 |
2414 | #define TRANSCODER_C_OFFSET 0x62000 |
2523 | #define TRANSCODER_C_OFFSET 0x62000 |
2415 | #define CHV_TRANSCODER_C_OFFSET 0x63000 |
2524 | #define CHV_TRANSCODER_C_OFFSET 0x63000 |
2416 | #define TRANSCODER_EDP_OFFSET 0x6f000 |
2525 | #define TRANSCODER_EDP_OFFSET 0x6f000 |
2417 | 2526 | ||
2418 | #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ |
2527 | #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ |
2419 | dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ |
2528 | dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ |
2420 | dev_priv->info.display_mmio_offset) |
2529 | dev_priv->info.display_mmio_offset) |
2421 | 2530 | ||
2422 | #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) |
2531 | #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) |
2423 | #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) |
2532 | #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) |
2424 | #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) |
2533 | #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) |
2425 | #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) |
2534 | #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) |
2426 | #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) |
2535 | #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) |
2427 | #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) |
2536 | #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) |
2428 | #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) |
2537 | #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) |
2429 | #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) |
2538 | #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) |
2430 | #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) |
2539 | #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) |
- | 2540 | #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) |
|
2431 | 2541 | ||
2432 | /* HSW+ eDP PSR registers */ |
2542 | /* HSW+ eDP PSR registers */ |
2433 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
2543 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
2434 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
2544 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
2435 | #define EDP_PSR_ENABLE (1<<31) |
2545 | #define EDP_PSR_ENABLE (1<<31) |
2436 | #define BDW_PSR_SINGLE_FRAME (1<<30) |
2546 | #define BDW_PSR_SINGLE_FRAME (1<<30) |
2437 | #define EDP_PSR_LINK_DISABLE (0<<27) |
2547 | #define EDP_PSR_LINK_DISABLE (0<<27) |
2438 | #define EDP_PSR_LINK_STANDBY (1<<27) |
2548 | #define EDP_PSR_LINK_STANDBY (1<<27) |
2439 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) |
2549 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) |
2440 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) |
2550 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) |
2441 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) |
2551 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) |
2442 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) |
2552 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) |
2443 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) |
2553 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) |
2444 | #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 |
2554 | #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 |
2445 | #define EDP_PSR_SKIP_AUX_EXIT (1<<12) |
2555 | #define EDP_PSR_SKIP_AUX_EXIT (1<<12) |
2446 | #define EDP_PSR_TP1_TP2_SEL (0<<11) |
2556 | #define EDP_PSR_TP1_TP2_SEL (0<<11) |
2447 | #define EDP_PSR_TP1_TP3_SEL (1<<11) |
2557 | #define EDP_PSR_TP1_TP3_SEL (1<<11) |
2448 | #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) |
2558 | #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) |
2449 | #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) |
2559 | #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) |
2450 | #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) |
2560 | #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) |
2451 | #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) |
2561 | #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) |
2452 | #define EDP_PSR_TP1_TIME_500us (0<<4) |
2562 | #define EDP_PSR_TP1_TIME_500us (0<<4) |
2453 | #define EDP_PSR_TP1_TIME_100us (1<<4) |
2563 | #define EDP_PSR_TP1_TIME_100us (1<<4) |
2454 | #define EDP_PSR_TP1_TIME_2500us (2<<4) |
2564 | #define EDP_PSR_TP1_TIME_2500us (2<<4) |
2455 | #define EDP_PSR_TP1_TIME_0us (3<<4) |
2565 | #define EDP_PSR_TP1_TIME_0us (3<<4) |
2456 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 |
2566 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 |
2457 | 2567 | ||
2458 | #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) |
2568 | #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) |
2459 | #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) |
2569 | #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) |
2460 | #define EDP_PSR_DPCD_COMMAND 0x80060000 |
- | |
2461 | #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) |
2570 | #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) |
2462 | #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) |
- | |
2463 | #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) |
2571 | #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) |
2464 | #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) |
2572 | #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) |
2465 | #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) |
2573 | #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) |
2466 | 2574 | ||
2467 | #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) |
2575 | #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) |
2468 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) |
2576 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) |
2469 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) |
2577 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) |
2470 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) |
2578 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) |
2471 | #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) |
2579 | #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) |
2472 | #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) |
2580 | #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) |
2473 | #define EDP_PSR_STATUS_STATE_BUFON (4<<29) |
2581 | #define EDP_PSR_STATUS_STATE_BUFON (4<<29) |
2474 | #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) |
2582 | #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) |
2475 | #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) |
2583 | #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) |
2476 | #define EDP_PSR_STATUS_LINK_MASK (3<<26) |
2584 | #define EDP_PSR_STATUS_LINK_MASK (3<<26) |
2477 | #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) |
2585 | #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) |
2478 | #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) |
2586 | #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) |
2479 | #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) |
2587 | #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) |
2480 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 |
2588 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 |
2481 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f |
2589 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f |
2482 | #define EDP_PSR_STATUS_COUNT_SHIFT 16 |
2590 | #define EDP_PSR_STATUS_COUNT_SHIFT 16 |
2483 | #define EDP_PSR_STATUS_COUNT_MASK 0xf |
2591 | #define EDP_PSR_STATUS_COUNT_MASK 0xf |
2484 | #define EDP_PSR_STATUS_AUX_ERROR (1<<15) |
2592 | #define EDP_PSR_STATUS_AUX_ERROR (1<<15) |
2485 | #define EDP_PSR_STATUS_AUX_SENDING (1<<12) |
2593 | #define EDP_PSR_STATUS_AUX_SENDING (1<<12) |
2486 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) |
2594 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) |
2487 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) |
2595 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) |
2488 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) |
2596 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) |
2489 | #define EDP_PSR_STATUS_IDLE_MASK 0xf |
2597 | #define EDP_PSR_STATUS_IDLE_MASK 0xf |
2490 | 2598 | ||
2491 | #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) |
2599 | #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) |
2492 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
2600 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
2493 | 2601 | ||
2494 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) |
2602 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) |
2495 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
2603 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
2496 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) |
2604 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) |
2497 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) |
2605 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) |
2498 | 2606 | ||
2499 | /* VGA port control */ |
2607 | /* VGA port control */ |
2500 | #define ADPA 0x61100 |
2608 | #define ADPA 0x61100 |
2501 | #define PCH_ADPA 0xe1100 |
2609 | #define PCH_ADPA 0xe1100 |
2502 | #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
2610 | #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
2503 | 2611 | ||
2504 | #define ADPA_DAC_ENABLE (1<<31) |
2612 | #define ADPA_DAC_ENABLE (1<<31) |
2505 | #define ADPA_DAC_DISABLE 0 |
2613 | #define ADPA_DAC_DISABLE 0 |
2506 | #define ADPA_PIPE_SELECT_MASK (1<<30) |
2614 | #define ADPA_PIPE_SELECT_MASK (1<<30) |
2507 | #define ADPA_PIPE_A_SELECT 0 |
2615 | #define ADPA_PIPE_A_SELECT 0 |
2508 | #define ADPA_PIPE_B_SELECT (1<<30) |
2616 | #define ADPA_PIPE_B_SELECT (1<<30) |
2509 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
2617 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
2510 | /* CPT uses bits 29:30 for pch transcoder select */ |
2618 | /* CPT uses bits 29:30 for pch transcoder select */ |
2511 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
2619 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
2512 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
2620 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
2513 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
2621 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
2514 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
2622 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
2515 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
2623 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
2516 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
2624 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
2517 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
2625 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
2518 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
2626 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
2519 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
2627 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
2520 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
2628 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
2521 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
2629 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
2522 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
2630 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
2523 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
2631 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
2524 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
2632 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
2525 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
2633 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
2526 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
2634 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
2527 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
2635 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
2528 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
2636 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
2529 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
2637 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
2530 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
2638 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
2531 | #define ADPA_SETS_HVPOLARITY 0 |
2639 | #define ADPA_SETS_HVPOLARITY 0 |
2532 | #define ADPA_VSYNC_CNTL_DISABLE (1<<10) |
2640 | #define ADPA_VSYNC_CNTL_DISABLE (1<<10) |
2533 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
2641 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
2534 | #define ADPA_HSYNC_CNTL_DISABLE (1<<11) |
2642 | #define ADPA_HSYNC_CNTL_DISABLE (1<<11) |
2535 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
2643 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
2536 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) |
2644 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) |
2537 | #define ADPA_VSYNC_ACTIVE_LOW 0 |
2645 | #define ADPA_VSYNC_ACTIVE_LOW 0 |
2538 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) |
2646 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) |
2539 | #define ADPA_HSYNC_ACTIVE_LOW 0 |
2647 | #define ADPA_HSYNC_ACTIVE_LOW 0 |
2540 | #define ADPA_DPMS_MASK (~(3<<10)) |
2648 | #define ADPA_DPMS_MASK (~(3<<10)) |
2541 | #define ADPA_DPMS_ON (0<<10) |
2649 | #define ADPA_DPMS_ON (0<<10) |
2542 | #define ADPA_DPMS_SUSPEND (1<<10) |
2650 | #define ADPA_DPMS_SUSPEND (1<<10) |
2543 | #define ADPA_DPMS_STANDBY (2<<10) |
2651 | #define ADPA_DPMS_STANDBY (2<<10) |
2544 | #define ADPA_DPMS_OFF (3<<10) |
2652 | #define ADPA_DPMS_OFF (3<<10) |
2545 | 2653 | ||
2546 | 2654 | ||
2547 | /* Hotplug control (945+ only) */ |
2655 | /* Hotplug control (945+ only) */ |
2548 | #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) |
2656 | #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) |
2549 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
2657 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
2550 | #define PORTC_HOTPLUG_INT_EN (1 << 28) |
2658 | #define PORTC_HOTPLUG_INT_EN (1 << 28) |
2551 | #define PORTD_HOTPLUG_INT_EN (1 << 27) |
2659 | #define PORTD_HOTPLUG_INT_EN (1 << 27) |
2552 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
2660 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
2553 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
2661 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
2554 | #define TV_HOTPLUG_INT_EN (1 << 18) |
2662 | #define TV_HOTPLUG_INT_EN (1 << 18) |
2555 | #define CRT_HOTPLUG_INT_EN (1 << 9) |
2663 | #define CRT_HOTPLUG_INT_EN (1 << 9) |
2556 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
2664 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
2557 | PORTC_HOTPLUG_INT_EN | \ |
2665 | PORTC_HOTPLUG_INT_EN | \ |
2558 | PORTD_HOTPLUG_INT_EN | \ |
2666 | PORTD_HOTPLUG_INT_EN | \ |
2559 | SDVOC_HOTPLUG_INT_EN | \ |
2667 | SDVOC_HOTPLUG_INT_EN | \ |
2560 | SDVOB_HOTPLUG_INT_EN | \ |
2668 | SDVOB_HOTPLUG_INT_EN | \ |
2561 | CRT_HOTPLUG_INT_EN) |
2669 | CRT_HOTPLUG_INT_EN) |
2562 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
2670 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
2563 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
2671 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
2564 | /* must use period 64 on GM45 according to docs */ |
2672 | /* must use period 64 on GM45 according to docs */ |
2565 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
2673 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
2566 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
2674 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
2567 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
2675 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
2568 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
2676 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
2569 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
2677 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
2570 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
2678 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
2571 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
2679 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
2572 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
2680 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
2573 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
2681 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
2574 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
2682 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
2575 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
2683 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
2576 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
2684 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
2577 | 2685 | ||
2578 | #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) |
2686 | #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) |
2579 | /* |
2687 | /* |
2580 | * HDMI/DP bits are gen4+ |
2688 | * HDMI/DP bits are gen4+ |
2581 | * |
2689 | * |
2582 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. |
2690 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. |
2583 | * Please check the detailed lore in the commit message for for experimental |
2691 | * Please check the detailed lore in the commit message for for experimental |
2584 | * evidence. |
2692 | * evidence. |
2585 | */ |
2693 | */ |
2586 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
2694 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
2587 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
2695 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
2588 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
2696 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
2589 | /* VLV DP/HDMI bits again match Bspec */ |
2697 | /* VLV DP/HDMI bits again match Bspec */ |
2590 | #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) |
2698 | #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) |
2591 | #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) |
2699 | #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) |
2592 | #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) |
2700 | #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) |
2593 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
2701 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
2594 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
2702 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
2595 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
2703 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
2596 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
2704 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
2597 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
2705 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
2598 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) |
2706 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) |
2599 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
2707 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
2600 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
2708 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
2601 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) |
2709 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) |
2602 | /* CRT/TV common between gen3+ */ |
2710 | /* CRT/TV common between gen3+ */ |
2603 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
2711 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
2604 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
2712 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
2605 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
2713 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
2606 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
2714 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
2607 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
2715 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
2608 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
2716 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
2609 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
2717 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
2610 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) |
2718 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) |
2611 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) |
2719 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) |
2612 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
2720 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
2613 | 2721 | ||
2614 | /* SDVO is different across gen3/4 */ |
2722 | /* SDVO is different across gen3/4 */ |
2615 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
2723 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
2616 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
2724 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
2617 | /* |
2725 | /* |
2618 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, |
2726 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, |
2619 | * since reality corrobates that they're the same as on gen3. But keep these |
2727 | * since reality corrobates that they're the same as on gen3. But keep these |
2620 | * bits here (and the comment!) to help any other lost wanderers back onto the |
2728 | * bits here (and the comment!) to help any other lost wanderers back onto the |
2621 | * right tracks. |
2729 | * right tracks. |
2622 | */ |
2730 | */ |
2623 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
2731 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
2624 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
2732 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
2625 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
2733 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
2626 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
2734 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
2627 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
2735 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
2628 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ |
2736 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ |
2629 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ |
2737 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ |
2630 | PORTB_HOTPLUG_INT_STATUS | \ |
2738 | PORTB_HOTPLUG_INT_STATUS | \ |
2631 | PORTC_HOTPLUG_INT_STATUS | \ |
2739 | PORTC_HOTPLUG_INT_STATUS | \ |
2632 | PORTD_HOTPLUG_INT_STATUS) |
2740 | PORTD_HOTPLUG_INT_STATUS) |
2633 | 2741 | ||
2634 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ |
2742 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ |
2635 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ |
2743 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ |
2636 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ |
2744 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ |
2637 | PORTB_HOTPLUG_INT_STATUS | \ |
2745 | PORTB_HOTPLUG_INT_STATUS | \ |
2638 | PORTC_HOTPLUG_INT_STATUS | \ |
2746 | PORTC_HOTPLUG_INT_STATUS | \ |
2639 | PORTD_HOTPLUG_INT_STATUS) |
2747 | PORTD_HOTPLUG_INT_STATUS) |
2640 | 2748 | ||
2641 | /* SDVO and HDMI port control. |
2749 | /* SDVO and HDMI port control. |
2642 | * The same register may be used for SDVO or HDMI */ |
2750 | * The same register may be used for SDVO or HDMI */ |
2643 | #define GEN3_SDVOB 0x61140 |
2751 | #define GEN3_SDVOB 0x61140 |
2644 | #define GEN3_SDVOC 0x61160 |
2752 | #define GEN3_SDVOC 0x61160 |
2645 | #define GEN4_HDMIB GEN3_SDVOB |
2753 | #define GEN4_HDMIB GEN3_SDVOB |
2646 | #define GEN4_HDMIC GEN3_SDVOC |
2754 | #define GEN4_HDMIC GEN3_SDVOC |
2647 | #define CHV_HDMID 0x6116C |
2755 | #define CHV_HDMID 0x6116C |
2648 | #define PCH_SDVOB 0xe1140 |
2756 | #define PCH_SDVOB 0xe1140 |
2649 | #define PCH_HDMIB PCH_SDVOB |
2757 | #define PCH_HDMIB PCH_SDVOB |
2650 | #define PCH_HDMIC 0xe1150 |
2758 | #define PCH_HDMIC 0xe1150 |
2651 | #define PCH_HDMID 0xe1160 |
2759 | #define PCH_HDMID 0xe1160 |
2652 | 2760 | ||
2653 | #define PORT_DFT_I9XX 0x61150 |
2761 | #define PORT_DFT_I9XX 0x61150 |
2654 | #define DC_BALANCE_RESET (1 << 25) |
2762 | #define DC_BALANCE_RESET (1 << 25) |
2655 | #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) |
2763 | #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) |
2656 | #define DC_BALANCE_RESET_VLV (1 << 31) |
2764 | #define DC_BALANCE_RESET_VLV (1 << 31) |
2657 | #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) |
2765 | #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) |
2658 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
2766 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
2659 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) |
2767 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) |
2660 | 2768 | ||
2661 | /* Gen 3 SDVO bits: */ |
2769 | /* Gen 3 SDVO bits: */ |
2662 | #define SDVO_ENABLE (1 << 31) |
2770 | #define SDVO_ENABLE (1 << 31) |
2663 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
2771 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
2664 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
2772 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
2665 | #define SDVO_PIPE_B_SELECT (1 << 30) |
2773 | #define SDVO_PIPE_B_SELECT (1 << 30) |
2666 | #define SDVO_STALL_SELECT (1 << 29) |
2774 | #define SDVO_STALL_SELECT (1 << 29) |
2667 | #define SDVO_INTERRUPT_ENABLE (1 << 26) |
2775 | #define SDVO_INTERRUPT_ENABLE (1 << 26) |
2668 | /* |
2776 | /* |
2669 | * 915G/GM SDVO pixel multiplier. |
2777 | * 915G/GM SDVO pixel multiplier. |
2670 | * Programmed value is multiplier - 1, up to 5x. |
2778 | * Programmed value is multiplier - 1, up to 5x. |
2671 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
2779 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
2672 | */ |
2780 | */ |
2673 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
2781 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
2674 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
2782 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
2675 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
2783 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
2676 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
2784 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
2677 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
2785 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
2678 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ |
2786 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ |
2679 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ |
2787 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ |
2680 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ |
2788 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ |
2681 | #define SDVO_DETECTED (1 << 2) |
2789 | #define SDVO_DETECTED (1 << 2) |
2682 | /* Bits to be preserved when writing */ |
2790 | /* Bits to be preserved when writing */ |
2683 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
2791 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
2684 | SDVO_INTERRUPT_ENABLE) |
2792 | SDVO_INTERRUPT_ENABLE) |
2685 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) |
2793 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) |
2686 | 2794 | ||
2687 | /* Gen 4 SDVO/HDMI bits: */ |
2795 | /* Gen 4 SDVO/HDMI bits: */ |
2688 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
2796 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
2689 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
2797 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
2690 | #define SDVO_ENCODING_SDVO (0 << 10) |
2798 | #define SDVO_ENCODING_SDVO (0 << 10) |
2691 | #define SDVO_ENCODING_HDMI (2 << 10) |
2799 | #define SDVO_ENCODING_HDMI (2 << 10) |
2692 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
2800 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
2693 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ |
2801 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ |
2694 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
2802 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
2695 | #define SDVO_AUDIO_ENABLE (1 << 6) |
2803 | #define SDVO_AUDIO_ENABLE (1 << 6) |
2696 | /* VSYNC/HSYNC bits new with 965, default is to be set */ |
2804 | /* VSYNC/HSYNC bits new with 965, default is to be set */ |
2697 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
2805 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
2698 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
2806 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
2699 | 2807 | ||
2700 | /* Gen 5 (IBX) SDVO/HDMI bits: */ |
2808 | /* Gen 5 (IBX) SDVO/HDMI bits: */ |
2701 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
2809 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
2702 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
2810 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
2703 | 2811 | ||
2704 | /* Gen 6 (CPT) SDVO/HDMI bits: */ |
2812 | /* Gen 6 (CPT) SDVO/HDMI bits: */ |
2705 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
2813 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
2706 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) |
2814 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) |
2707 | 2815 | ||
2708 | /* CHV SDVO/HDMI bits: */ |
2816 | /* CHV SDVO/HDMI bits: */ |
2709 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) |
2817 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) |
2710 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) |
2818 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) |
2711 | 2819 | ||
2712 | 2820 | ||
2713 | /* DVO port control */ |
2821 | /* DVO port control */ |
2714 | #define DVOA 0x61120 |
2822 | #define DVOA 0x61120 |
2715 | #define DVOB 0x61140 |
2823 | #define DVOB 0x61140 |
2716 | #define DVOC 0x61160 |
2824 | #define DVOC 0x61160 |
2717 | #define DVO_ENABLE (1 << 31) |
2825 | #define DVO_ENABLE (1 << 31) |
2718 | #define DVO_PIPE_B_SELECT (1 << 30) |
2826 | #define DVO_PIPE_B_SELECT (1 << 30) |
2719 | #define DVO_PIPE_STALL_UNUSED (0 << 28) |
2827 | #define DVO_PIPE_STALL_UNUSED (0 << 28) |
2720 | #define DVO_PIPE_STALL (1 << 28) |
2828 | #define DVO_PIPE_STALL (1 << 28) |
2721 | #define DVO_PIPE_STALL_TV (2 << 28) |
2829 | #define DVO_PIPE_STALL_TV (2 << 28) |
2722 | #define DVO_PIPE_STALL_MASK (3 << 28) |
2830 | #define DVO_PIPE_STALL_MASK (3 << 28) |
2723 | #define DVO_USE_VGA_SYNC (1 << 15) |
2831 | #define DVO_USE_VGA_SYNC (1 << 15) |
2724 | #define DVO_DATA_ORDER_I740 (0 << 14) |
2832 | #define DVO_DATA_ORDER_I740 (0 << 14) |
2725 | #define DVO_DATA_ORDER_FP (1 << 14) |
2833 | #define DVO_DATA_ORDER_FP (1 << 14) |
2726 | #define DVO_VSYNC_DISABLE (1 << 11) |
2834 | #define DVO_VSYNC_DISABLE (1 << 11) |
2727 | #define DVO_HSYNC_DISABLE (1 << 10) |
2835 | #define DVO_HSYNC_DISABLE (1 << 10) |
2728 | #define DVO_VSYNC_TRISTATE (1 << 9) |
2836 | #define DVO_VSYNC_TRISTATE (1 << 9) |
2729 | #define DVO_HSYNC_TRISTATE (1 << 8) |
2837 | #define DVO_HSYNC_TRISTATE (1 << 8) |
2730 | #define DVO_BORDER_ENABLE (1 << 7) |
2838 | #define DVO_BORDER_ENABLE (1 << 7) |
2731 | #define DVO_DATA_ORDER_GBRG (1 << 6) |
2839 | #define DVO_DATA_ORDER_GBRG (1 << 6) |
2732 | #define DVO_DATA_ORDER_RGGB (0 << 6) |
2840 | #define DVO_DATA_ORDER_RGGB (0 << 6) |
2733 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) |
2841 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) |
2734 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) |
2842 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) |
2735 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) |
2843 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) |
2736 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) |
2844 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) |
2737 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) |
2845 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) |
2738 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ |
2846 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ |
2739 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ |
2847 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ |
2740 | #define DVO_PRESERVE_MASK (0x7<<24) |
2848 | #define DVO_PRESERVE_MASK (0x7<<24) |
2741 | #define DVOA_SRCDIM 0x61124 |
2849 | #define DVOA_SRCDIM 0x61124 |
2742 | #define DVOB_SRCDIM 0x61144 |
2850 | #define DVOB_SRCDIM 0x61144 |
2743 | #define DVOC_SRCDIM 0x61164 |
2851 | #define DVOC_SRCDIM 0x61164 |
2744 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
2852 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
2745 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 |
2853 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 |
2746 | 2854 | ||
2747 | /* LVDS port control */ |
2855 | /* LVDS port control */ |
2748 | #define LVDS 0x61180 |
2856 | #define LVDS 0x61180 |
2749 | /* |
2857 | /* |
2750 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as |
2858 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as |
2751 | * the DPLL semantics change when the LVDS is assigned to that pipe. |
2859 | * the DPLL semantics change when the LVDS is assigned to that pipe. |
2752 | */ |
2860 | */ |
2753 | #define LVDS_PORT_EN (1 << 31) |
2861 | #define LVDS_PORT_EN (1 << 31) |
2754 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ |
2862 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ |
2755 | #define LVDS_PIPEB_SELECT (1 << 30) |
2863 | #define LVDS_PIPEB_SELECT (1 << 30) |
2756 | #define LVDS_PIPE_MASK (1 << 30) |
2864 | #define LVDS_PIPE_MASK (1 << 30) |
2757 | #define LVDS_PIPE(pipe) ((pipe) << 30) |
2865 | #define LVDS_PIPE(pipe) ((pipe) << 30) |
2758 | /* LVDS dithering flag on 965/g4x platform */ |
2866 | /* LVDS dithering flag on 965/g4x platform */ |
2759 | #define LVDS_ENABLE_DITHER (1 << 25) |
2867 | #define LVDS_ENABLE_DITHER (1 << 25) |
2760 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
2868 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
2761 | #define LVDS_VSYNC_POLARITY (1 << 21) |
2869 | #define LVDS_VSYNC_POLARITY (1 << 21) |
2762 | #define LVDS_HSYNC_POLARITY (1 << 20) |
2870 | #define LVDS_HSYNC_POLARITY (1 << 20) |
2763 | 2871 | ||
2764 | /* Enable border for unscaled (or aspect-scaled) display */ |
2872 | /* Enable border for unscaled (or aspect-scaled) display */ |
2765 | #define LVDS_BORDER_ENABLE (1 << 15) |
2873 | #define LVDS_BORDER_ENABLE (1 << 15) |
2766 | /* |
2874 | /* |
2767 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per |
2875 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per |
2768 | * pixel. |
2876 | * pixel. |
2769 | */ |
2877 | */ |
2770 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) |
2878 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) |
2771 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) |
2879 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) |
2772 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) |
2880 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) |
2773 | /* |
2881 | /* |
2774 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit |
2882 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit |
2775 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be |
2883 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be |
2776 | * on. |
2884 | * on. |
2777 | */ |
2885 | */ |
2778 | #define LVDS_A3_POWER_MASK (3 << 6) |
2886 | #define LVDS_A3_POWER_MASK (3 << 6) |
2779 | #define LVDS_A3_POWER_DOWN (0 << 6) |
2887 | #define LVDS_A3_POWER_DOWN (0 << 6) |
2780 | #define LVDS_A3_POWER_UP (3 << 6) |
2888 | #define LVDS_A3_POWER_UP (3 << 6) |
2781 | /* |
2889 | /* |
2782 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP |
2890 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP |
2783 | * is set. |
2891 | * is set. |
2784 | */ |
2892 | */ |
2785 | #define LVDS_CLKB_POWER_MASK (3 << 4) |
2893 | #define LVDS_CLKB_POWER_MASK (3 << 4) |
2786 | #define LVDS_CLKB_POWER_DOWN (0 << 4) |
2894 | #define LVDS_CLKB_POWER_DOWN (0 << 4) |
2787 | #define LVDS_CLKB_POWER_UP (3 << 4) |
2895 | #define LVDS_CLKB_POWER_UP (3 << 4) |
2788 | /* |
2896 | /* |
2789 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 |
2897 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 |
2790 | * setting for whether we are in dual-channel mode. The B3 pair will |
2898 | * setting for whether we are in dual-channel mode. The B3 pair will |
2791 | * additionally only be powered up when LVDS_A3_POWER_UP is set. |
2899 | * additionally only be powered up when LVDS_A3_POWER_UP is set. |
2792 | */ |
2900 | */ |
2793 | #define LVDS_B0B3_POWER_MASK (3 << 2) |
2901 | #define LVDS_B0B3_POWER_MASK (3 << 2) |
2794 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
2902 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
2795 | #define LVDS_B0B3_POWER_UP (3 << 2) |
2903 | #define LVDS_B0B3_POWER_UP (3 << 2) |
2796 | 2904 | ||
2797 | /* Video Data Island Packet control */ |
2905 | /* Video Data Island Packet control */ |
2798 | #define VIDEO_DIP_DATA 0x61178 |
2906 | #define VIDEO_DIP_DATA 0x61178 |
2799 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC |
2907 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC |
2800 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
2908 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
2801 | * of the infoframe structure specified by CEA-861. */ |
2909 | * of the infoframe structure specified by CEA-861. */ |
2802 | #define VIDEO_DIP_DATA_SIZE 32 |
2910 | #define VIDEO_DIP_DATA_SIZE 32 |
2803 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
2911 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
2804 | #define VIDEO_DIP_CTL 0x61170 |
2912 | #define VIDEO_DIP_CTL 0x61170 |
2805 | /* Pre HSW: */ |
2913 | /* Pre HSW: */ |
2806 | #define VIDEO_DIP_ENABLE (1 << 31) |
2914 | #define VIDEO_DIP_ENABLE (1 << 31) |
2807 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
2915 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
2808 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
2916 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
2809 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
2917 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
2810 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
2918 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
2811 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
2919 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
2812 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
2920 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
2813 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
2921 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
2814 | #define VIDEO_DIP_SELECT_AVI (0 << 19) |
2922 | #define VIDEO_DIP_SELECT_AVI (0 << 19) |
2815 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
2923 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
2816 | #define VIDEO_DIP_SELECT_SPD (3 << 19) |
2924 | #define VIDEO_DIP_SELECT_SPD (3 << 19) |
2817 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
2925 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
2818 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
2926 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
2819 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
2927 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
2820 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
2928 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
2821 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
2929 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
2822 | /* HSW and later: */ |
2930 | /* HSW and later: */ |
2823 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
2931 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
2824 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
2932 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
2825 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
2933 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
2826 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
2934 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
2827 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
2935 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
2828 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
2936 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
2829 | 2937 | ||
2830 | /* Panel power sequencing */ |
2938 | /* Panel power sequencing */ |
2831 | #define PP_STATUS 0x61200 |
2939 | #define PP_STATUS 0x61200 |
2832 | #define PP_ON (1 << 31) |
2940 | #define PP_ON (1 << 31) |
2833 | /* |
2941 | /* |
2834 | * Indicates that all dependencies of the panel are on: |
2942 | * Indicates that all dependencies of the panel are on: |
2835 | * |
2943 | * |
2836 | * - PLL enabled |
2944 | * - PLL enabled |
2837 | * - pipe enabled |
2945 | * - pipe enabled |
2838 | * - LVDS/DVOB/DVOC on |
2946 | * - LVDS/DVOB/DVOC on |
2839 | */ |
2947 | */ |
2840 | #define PP_READY (1 << 30) |
2948 | #define PP_READY (1 << 30) |
2841 | #define PP_SEQUENCE_NONE (0 << 28) |
2949 | #define PP_SEQUENCE_NONE (0 << 28) |
2842 | #define PP_SEQUENCE_POWER_UP (1 << 28) |
2950 | #define PP_SEQUENCE_POWER_UP (1 << 28) |
2843 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) |
2951 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) |
2844 | #define PP_SEQUENCE_MASK (3 << 28) |
2952 | #define PP_SEQUENCE_MASK (3 << 28) |
2845 | #define PP_SEQUENCE_SHIFT 28 |
2953 | #define PP_SEQUENCE_SHIFT 28 |
2846 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
2954 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
2847 | #define PP_SEQUENCE_STATE_MASK 0x0000000f |
2955 | #define PP_SEQUENCE_STATE_MASK 0x0000000f |
2848 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
2956 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
2849 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) |
2957 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) |
2850 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) |
2958 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) |
2851 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) |
2959 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) |
2852 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) |
2960 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) |
2853 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) |
2961 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) |
2854 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) |
2962 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) |
2855 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) |
2963 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) |
2856 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) |
2964 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) |
2857 | #define PP_CONTROL 0x61204 |
2965 | #define PP_CONTROL 0x61204 |
2858 | #define POWER_TARGET_ON (1 << 0) |
2966 | #define POWER_TARGET_ON (1 << 0) |
2859 | #define PP_ON_DELAYS 0x61208 |
2967 | #define PP_ON_DELAYS 0x61208 |
2860 | #define PP_OFF_DELAYS 0x6120c |
2968 | #define PP_OFF_DELAYS 0x6120c |
2861 | #define PP_DIVISOR 0x61210 |
2969 | #define PP_DIVISOR 0x61210 |
2862 | 2970 | ||
2863 | /* Panel fitting */ |
2971 | /* Panel fitting */ |
2864 | #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) |
2972 | #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) |
2865 | #define PFIT_ENABLE (1 << 31) |
2973 | #define PFIT_ENABLE (1 << 31) |
2866 | #define PFIT_PIPE_MASK (3 << 29) |
2974 | #define PFIT_PIPE_MASK (3 << 29) |
2867 | #define PFIT_PIPE_SHIFT 29 |
2975 | #define PFIT_PIPE_SHIFT 29 |
2868 | #define VERT_INTERP_DISABLE (0 << 10) |
2976 | #define VERT_INTERP_DISABLE (0 << 10) |
2869 | #define VERT_INTERP_BILINEAR (1 << 10) |
2977 | #define VERT_INTERP_BILINEAR (1 << 10) |
2870 | #define VERT_INTERP_MASK (3 << 10) |
2978 | #define VERT_INTERP_MASK (3 << 10) |
2871 | #define VERT_AUTO_SCALE (1 << 9) |
2979 | #define VERT_AUTO_SCALE (1 << 9) |
2872 | #define HORIZ_INTERP_DISABLE (0 << 6) |
2980 | #define HORIZ_INTERP_DISABLE (0 << 6) |
2873 | #define HORIZ_INTERP_BILINEAR (1 << 6) |
2981 | #define HORIZ_INTERP_BILINEAR (1 << 6) |
2874 | #define HORIZ_INTERP_MASK (3 << 6) |
2982 | #define HORIZ_INTERP_MASK (3 << 6) |
2875 | #define HORIZ_AUTO_SCALE (1 << 5) |
2983 | #define HORIZ_AUTO_SCALE (1 << 5) |
2876 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) |
2984 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) |
2877 | #define PFIT_FILTER_FUZZY (0 << 24) |
2985 | #define PFIT_FILTER_FUZZY (0 << 24) |
2878 | #define PFIT_SCALING_AUTO (0 << 26) |
2986 | #define PFIT_SCALING_AUTO (0 << 26) |
2879 | #define PFIT_SCALING_PROGRAMMED (1 << 26) |
2987 | #define PFIT_SCALING_PROGRAMMED (1 << 26) |
2880 | #define PFIT_SCALING_PILLAR (2 << 26) |
2988 | #define PFIT_SCALING_PILLAR (2 << 26) |
2881 | #define PFIT_SCALING_LETTER (3 << 26) |
2989 | #define PFIT_SCALING_LETTER (3 << 26) |
2882 | #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) |
2990 | #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) |
2883 | /* Pre-965 */ |
2991 | /* Pre-965 */ |
2884 | #define PFIT_VERT_SCALE_SHIFT 20 |
2992 | #define PFIT_VERT_SCALE_SHIFT 20 |
2885 | #define PFIT_VERT_SCALE_MASK 0xfff00000 |
2993 | #define PFIT_VERT_SCALE_MASK 0xfff00000 |
2886 | #define PFIT_HORIZ_SCALE_SHIFT 4 |
2994 | #define PFIT_HORIZ_SCALE_SHIFT 4 |
2887 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
2995 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
2888 | /* 965+ */ |
2996 | /* 965+ */ |
2889 | #define PFIT_VERT_SCALE_SHIFT_965 16 |
2997 | #define PFIT_VERT_SCALE_SHIFT_965 16 |
2890 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 |
2998 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 |
2891 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 |
2999 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 |
2892 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
3000 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
2893 | 3001 | ||
2894 | #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) |
3002 | #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) |
2895 | 3003 | ||
2896 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) |
3004 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) |
2897 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) |
3005 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) |
2898 | #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
3006 | #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
2899 | _VLV_BLC_PWM_CTL2_B) |
3007 | _VLV_BLC_PWM_CTL2_B) |
2900 | 3008 | ||
2901 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) |
3009 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) |
2902 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) |
3010 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) |
2903 | #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
3011 | #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
2904 | _VLV_BLC_PWM_CTL_B) |
3012 | _VLV_BLC_PWM_CTL_B) |
2905 | 3013 | ||
2906 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) |
3014 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) |
2907 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) |
3015 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) |
2908 | #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
3016 | #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
2909 | _VLV_BLC_HIST_CTL_B) |
3017 | _VLV_BLC_HIST_CTL_B) |
2910 | 3018 | ||
2911 | /* Backlight control */ |
3019 | /* Backlight control */ |
2912 | #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ |
3020 | #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ |
2913 | #define BLM_PWM_ENABLE (1 << 31) |
3021 | #define BLM_PWM_ENABLE (1 << 31) |
2914 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
3022 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
2915 | #define BLM_PIPE_SELECT (1 << 29) |
3023 | #define BLM_PIPE_SELECT (1 << 29) |
2916 | #define BLM_PIPE_SELECT_IVB (3 << 29) |
3024 | #define BLM_PIPE_SELECT_IVB (3 << 29) |
2917 | #define BLM_PIPE_A (0 << 29) |
3025 | #define BLM_PIPE_A (0 << 29) |
2918 | #define BLM_PIPE_B (1 << 29) |
3026 | #define BLM_PIPE_B (1 << 29) |
2919 | #define BLM_PIPE_C (2 << 29) /* ivb + */ |
3027 | #define BLM_PIPE_C (2 << 29) /* ivb + */ |
2920 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
3028 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
2921 | #define BLM_TRANSCODER_B BLM_PIPE_B |
3029 | #define BLM_TRANSCODER_B BLM_PIPE_B |
2922 | #define BLM_TRANSCODER_C BLM_PIPE_C |
3030 | #define BLM_TRANSCODER_C BLM_PIPE_C |
2923 | #define BLM_TRANSCODER_EDP (3 << 29) |
3031 | #define BLM_TRANSCODER_EDP (3 << 29) |
2924 | #define BLM_PIPE(pipe) ((pipe) << 29) |
3032 | #define BLM_PIPE(pipe) ((pipe) << 29) |
2925 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
3033 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
2926 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) |
3034 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) |
2927 | #define BLM_PHASE_IN_ENABLE (1 << 25) |
3035 | #define BLM_PHASE_IN_ENABLE (1 << 25) |
2928 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) |
3036 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) |
2929 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) |
3037 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) |
2930 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) |
3038 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) |
2931 | #define BLM_PHASE_IN_COUNT_SHIFT (8) |
3039 | #define BLM_PHASE_IN_COUNT_SHIFT (8) |
2932 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
3040 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
2933 | #define BLM_PHASE_IN_INCR_SHIFT (0) |
3041 | #define BLM_PHASE_IN_INCR_SHIFT (0) |
2934 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) |
3042 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) |
2935 | #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) |
3043 | #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) |
2936 | /* |
3044 | /* |
2937 | * This is the most significant 15 bits of the number of backlight cycles in a |
3045 | * This is the most significant 15 bits of the number of backlight cycles in a |
2938 | * complete cycle of the modulated backlight control. |
3046 | * complete cycle of the modulated backlight control. |
2939 | * |
3047 | * |
2940 | * The actual value is this field multiplied by two. |
3048 | * The actual value is this field multiplied by two. |
2941 | */ |
3049 | */ |
2942 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
3050 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
2943 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
3051 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
2944 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ |
3052 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ |
2945 | /* |
3053 | /* |
2946 | * This is the number of cycles out of the backlight modulation cycle for which |
3054 | * This is the number of cycles out of the backlight modulation cycle for which |
2947 | * the backlight is on. |
3055 | * the backlight is on. |
2948 | * |
3056 | * |
2949 | * This field must be no greater than the number of cycles in the complete |
3057 | * This field must be no greater than the number of cycles in the complete |
2950 | * backlight modulation cycle. |
3058 | * backlight modulation cycle. |
2951 | */ |
3059 | */ |
2952 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
3060 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
2953 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
3061 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
2954 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
3062 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
2955 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
3063 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
2956 | 3064 | ||
2957 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
3065 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
2958 | 3066 | ||
2959 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
3067 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
2960 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
3068 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
2961 | #define BLC_PWM_CPU_CTL2 0x48250 |
3069 | #define BLC_PWM_CPU_CTL2 0x48250 |
2962 | #define BLC_PWM_CPU_CTL 0x48254 |
3070 | #define BLC_PWM_CPU_CTL 0x48254 |
2963 | 3071 | ||
2964 | #define HSW_BLC_PWM2_CTL 0x48350 |
3072 | #define HSW_BLC_PWM2_CTL 0x48350 |
2965 | 3073 | ||
2966 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
3074 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
2967 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ |
3075 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ |
2968 | #define BLC_PWM_PCH_CTL1 0xc8250 |
3076 | #define BLC_PWM_PCH_CTL1 0xc8250 |
2969 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
3077 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
2970 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
3078 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
2971 | #define BLM_PCH_POLARITY (1 << 29) |
3079 | #define BLM_PCH_POLARITY (1 << 29) |
2972 | #define BLC_PWM_PCH_CTL2 0xc8254 |
3080 | #define BLC_PWM_PCH_CTL2 0xc8254 |
2973 | 3081 | ||
2974 | #define UTIL_PIN_CTL 0x48400 |
3082 | #define UTIL_PIN_CTL 0x48400 |
2975 | #define UTIL_PIN_ENABLE (1 << 31) |
3083 | #define UTIL_PIN_ENABLE (1 << 31) |
2976 | 3084 | ||
2977 | #define PCH_GTC_CTL 0xe7000 |
3085 | #define PCH_GTC_CTL 0xe7000 |
2978 | #define PCH_GTC_ENABLE (1 << 31) |
3086 | #define PCH_GTC_ENABLE (1 << 31) |
2979 | 3087 | ||
2980 | /* TV port control */ |
3088 | /* TV port control */ |
2981 | #define TV_CTL 0x68000 |
3089 | #define TV_CTL 0x68000 |
2982 | /* Enables the TV encoder */ |
3090 | /* Enables the TV encoder */ |
2983 | # define TV_ENC_ENABLE (1 << 31) |
3091 | # define TV_ENC_ENABLE (1 << 31) |
2984 | /* Sources the TV encoder input from pipe B instead of A. */ |
3092 | /* Sources the TV encoder input from pipe B instead of A. */ |
2985 | # define TV_ENC_PIPEB_SELECT (1 << 30) |
3093 | # define TV_ENC_PIPEB_SELECT (1 << 30) |
2986 | /* Outputs composite video (DAC A only) */ |
3094 | /* Outputs composite video (DAC A only) */ |
2987 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
3095 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
2988 | /* Outputs SVideo video (DAC B/C) */ |
3096 | /* Outputs SVideo video (DAC B/C) */ |
2989 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
3097 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
2990 | /* Outputs Component video (DAC A/B/C) */ |
3098 | /* Outputs Component video (DAC A/B/C) */ |
2991 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
3099 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
2992 | /* Outputs Composite and SVideo (DAC A/B/C) */ |
3100 | /* Outputs Composite and SVideo (DAC A/B/C) */ |
2993 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
3101 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
2994 | # define TV_TRILEVEL_SYNC (1 << 21) |
3102 | # define TV_TRILEVEL_SYNC (1 << 21) |
2995 | /* Enables slow sync generation (945GM only) */ |
3103 | /* Enables slow sync generation (945GM only) */ |
2996 | # define TV_SLOW_SYNC (1 << 20) |
3104 | # define TV_SLOW_SYNC (1 << 20) |
2997 | /* Selects 4x oversampling for 480i and 576p */ |
3105 | /* Selects 4x oversampling for 480i and 576p */ |
2998 | # define TV_OVERSAMPLE_4X (0 << 18) |
3106 | # define TV_OVERSAMPLE_4X (0 << 18) |
2999 | /* Selects 2x oversampling for 720p and 1080i */ |
3107 | /* Selects 2x oversampling for 720p and 1080i */ |
3000 | # define TV_OVERSAMPLE_2X (1 << 18) |
3108 | # define TV_OVERSAMPLE_2X (1 << 18) |
3001 | /* Selects no oversampling for 1080p */ |
3109 | /* Selects no oversampling for 1080p */ |
3002 | # define TV_OVERSAMPLE_NONE (2 << 18) |
3110 | # define TV_OVERSAMPLE_NONE (2 << 18) |
3003 | /* Selects 8x oversampling */ |
3111 | /* Selects 8x oversampling */ |
3004 | # define TV_OVERSAMPLE_8X (3 << 18) |
3112 | # define TV_OVERSAMPLE_8X (3 << 18) |
3005 | /* Selects progressive mode rather than interlaced */ |
3113 | /* Selects progressive mode rather than interlaced */ |
3006 | # define TV_PROGRESSIVE (1 << 17) |
3114 | # define TV_PROGRESSIVE (1 << 17) |
3007 | /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
3115 | /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
3008 | # define TV_PAL_BURST (1 << 16) |
3116 | # define TV_PAL_BURST (1 << 16) |
3009 | /* Field for setting delay of Y compared to C */ |
3117 | /* Field for setting delay of Y compared to C */ |
3010 | # define TV_YC_SKEW_MASK (7 << 12) |
3118 | # define TV_YC_SKEW_MASK (7 << 12) |
3011 | /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
3119 | /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
3012 | # define TV_ENC_SDP_FIX (1 << 11) |
3120 | # define TV_ENC_SDP_FIX (1 << 11) |
3013 | /* |
3121 | /* |
3014 | * Enables a fix for the 915GM only. |
3122 | * Enables a fix for the 915GM only. |
3015 | * |
3123 | * |
3016 | * Not sure what it does. |
3124 | * Not sure what it does. |
3017 | */ |
3125 | */ |
3018 | # define TV_ENC_C0_FIX (1 << 10) |
3126 | # define TV_ENC_C0_FIX (1 << 10) |
3019 | /* Bits that must be preserved by software */ |
3127 | /* Bits that must be preserved by software */ |
3020 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
3128 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
3021 | # define TV_FUSE_STATE_MASK (3 << 4) |
3129 | # define TV_FUSE_STATE_MASK (3 << 4) |
3022 | /* Read-only state that reports all features enabled */ |
3130 | /* Read-only state that reports all features enabled */ |
3023 | # define TV_FUSE_STATE_ENABLED (0 << 4) |
3131 | # define TV_FUSE_STATE_ENABLED (0 << 4) |
3024 | /* Read-only state that reports that Macrovision is disabled in hardware*/ |
3132 | /* Read-only state that reports that Macrovision is disabled in hardware*/ |
3025 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
3133 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
3026 | /* Read-only state that reports that TV-out is disabled in hardware. */ |
3134 | /* Read-only state that reports that TV-out is disabled in hardware. */ |
3027 | # define TV_FUSE_STATE_DISABLED (2 << 4) |
3135 | # define TV_FUSE_STATE_DISABLED (2 << 4) |
3028 | /* Normal operation */ |
3136 | /* Normal operation */ |
3029 | # define TV_TEST_MODE_NORMAL (0 << 0) |
3137 | # define TV_TEST_MODE_NORMAL (0 << 0) |
3030 | /* Encoder test pattern 1 - combo pattern */ |
3138 | /* Encoder test pattern 1 - combo pattern */ |
3031 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) |
3139 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) |
3032 | /* Encoder test pattern 2 - full screen vertical 75% color bars */ |
3140 | /* Encoder test pattern 2 - full screen vertical 75% color bars */ |
3033 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) |
3141 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) |
3034 | /* Encoder test pattern 3 - full screen horizontal 75% color bars */ |
3142 | /* Encoder test pattern 3 - full screen horizontal 75% color bars */ |
3035 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) |
3143 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) |
3036 | /* Encoder test pattern 4 - random noise */ |
3144 | /* Encoder test pattern 4 - random noise */ |
3037 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) |
3145 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) |
3038 | /* Encoder test pattern 5 - linear color ramps */ |
3146 | /* Encoder test pattern 5 - linear color ramps */ |
3039 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) |
3147 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) |
3040 | /* |
3148 | /* |
3041 | * This test mode forces the DACs to 50% of full output. |
3149 | * This test mode forces the DACs to 50% of full output. |
3042 | * |
3150 | * |
3043 | * This is used for load detection in combination with TVDAC_SENSE_MASK |
3151 | * This is used for load detection in combination with TVDAC_SENSE_MASK |
3044 | */ |
3152 | */ |
3045 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) |
3153 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) |
3046 | # define TV_TEST_MODE_MASK (7 << 0) |
3154 | # define TV_TEST_MODE_MASK (7 << 0) |
3047 | 3155 | ||
3048 | #define TV_DAC 0x68004 |
3156 | #define TV_DAC 0x68004 |
3049 | # define TV_DAC_SAVE 0x00ffff00 |
3157 | # define TV_DAC_SAVE 0x00ffff00 |
3050 | /* |
3158 | /* |
3051 | * Reports that DAC state change logic has reported change (RO). |
3159 | * Reports that DAC state change logic has reported change (RO). |
3052 | * |
3160 | * |
3053 | * This gets cleared when TV_DAC_STATE_EN is cleared |
3161 | * This gets cleared when TV_DAC_STATE_EN is cleared |
3054 | */ |
3162 | */ |
3055 | # define TVDAC_STATE_CHG (1 << 31) |
3163 | # define TVDAC_STATE_CHG (1 << 31) |
3056 | # define TVDAC_SENSE_MASK (7 << 28) |
3164 | # define TVDAC_SENSE_MASK (7 << 28) |
3057 | /* Reports that DAC A voltage is above the detect threshold */ |
3165 | /* Reports that DAC A voltage is above the detect threshold */ |
3058 | # define TVDAC_A_SENSE (1 << 30) |
3166 | # define TVDAC_A_SENSE (1 << 30) |
3059 | /* Reports that DAC B voltage is above the detect threshold */ |
3167 | /* Reports that DAC B voltage is above the detect threshold */ |
3060 | # define TVDAC_B_SENSE (1 << 29) |
3168 | # define TVDAC_B_SENSE (1 << 29) |
3061 | /* Reports that DAC C voltage is above the detect threshold */ |
3169 | /* Reports that DAC C voltage is above the detect threshold */ |
3062 | # define TVDAC_C_SENSE (1 << 28) |
3170 | # define TVDAC_C_SENSE (1 << 28) |
3063 | /* |
3171 | /* |
3064 | * Enables DAC state detection logic, for load-based TV detection. |
3172 | * Enables DAC state detection logic, for load-based TV detection. |
3065 | * |
3173 | * |
3066 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set |
3174 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set |
3067 | * to off, for load detection to work. |
3175 | * to off, for load detection to work. |
3068 | */ |
3176 | */ |
3069 | # define TVDAC_STATE_CHG_EN (1 << 27) |
3177 | # define TVDAC_STATE_CHG_EN (1 << 27) |
3070 | /* Sets the DAC A sense value to high */ |
3178 | /* Sets the DAC A sense value to high */ |
3071 | # define TVDAC_A_SENSE_CTL (1 << 26) |
3179 | # define TVDAC_A_SENSE_CTL (1 << 26) |
3072 | /* Sets the DAC B sense value to high */ |
3180 | /* Sets the DAC B sense value to high */ |
3073 | # define TVDAC_B_SENSE_CTL (1 << 25) |
3181 | # define TVDAC_B_SENSE_CTL (1 << 25) |
3074 | /* Sets the DAC C sense value to high */ |
3182 | /* Sets the DAC C sense value to high */ |
3075 | # define TVDAC_C_SENSE_CTL (1 << 24) |
3183 | # define TVDAC_C_SENSE_CTL (1 << 24) |
3076 | /* Overrides the ENC_ENABLE and DAC voltage levels */ |
3184 | /* Overrides the ENC_ENABLE and DAC voltage levels */ |
3077 | # define DAC_CTL_OVERRIDE (1 << 7) |
3185 | # define DAC_CTL_OVERRIDE (1 << 7) |
3078 | /* Sets the slew rate. Must be preserved in software */ |
3186 | /* Sets the slew rate. Must be preserved in software */ |
3079 | # define ENC_TVDAC_SLEW_FAST (1 << 6) |
3187 | # define ENC_TVDAC_SLEW_FAST (1 << 6) |
3080 | # define DAC_A_1_3_V (0 << 4) |
3188 | # define DAC_A_1_3_V (0 << 4) |
3081 | # define DAC_A_1_1_V (1 << 4) |
3189 | # define DAC_A_1_1_V (1 << 4) |
3082 | # define DAC_A_0_7_V (2 << 4) |
3190 | # define DAC_A_0_7_V (2 << 4) |
3083 | # define DAC_A_MASK (3 << 4) |
3191 | # define DAC_A_MASK (3 << 4) |
3084 | # define DAC_B_1_3_V (0 << 2) |
3192 | # define DAC_B_1_3_V (0 << 2) |
3085 | # define DAC_B_1_1_V (1 << 2) |
3193 | # define DAC_B_1_1_V (1 << 2) |
3086 | # define DAC_B_0_7_V (2 << 2) |
3194 | # define DAC_B_0_7_V (2 << 2) |
3087 | # define DAC_B_MASK (3 << 2) |
3195 | # define DAC_B_MASK (3 << 2) |
3088 | # define DAC_C_1_3_V (0 << 0) |
3196 | # define DAC_C_1_3_V (0 << 0) |
3089 | # define DAC_C_1_1_V (1 << 0) |
3197 | # define DAC_C_1_1_V (1 << 0) |
3090 | # define DAC_C_0_7_V (2 << 0) |
3198 | # define DAC_C_0_7_V (2 << 0) |
3091 | # define DAC_C_MASK (3 << 0) |
3199 | # define DAC_C_MASK (3 << 0) |
3092 | 3200 | ||
3093 | /* |
3201 | /* |
3094 | * CSC coefficients are stored in a floating point format with 9 bits of |
3202 | * CSC coefficients are stored in a floating point format with 9 bits of |
3095 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, |
3203 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, |
3096 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with |
3204 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with |
3097 | * -1 (0x3) being the only legal negative value. |
3205 | * -1 (0x3) being the only legal negative value. |
3098 | */ |
3206 | */ |
3099 | #define TV_CSC_Y 0x68010 |
3207 | #define TV_CSC_Y 0x68010 |
3100 | # define TV_RY_MASK 0x07ff0000 |
3208 | # define TV_RY_MASK 0x07ff0000 |
3101 | # define TV_RY_SHIFT 16 |
3209 | # define TV_RY_SHIFT 16 |
3102 | # define TV_GY_MASK 0x00000fff |
3210 | # define TV_GY_MASK 0x00000fff |
3103 | # define TV_GY_SHIFT 0 |
3211 | # define TV_GY_SHIFT 0 |
3104 | 3212 | ||
3105 | #define TV_CSC_Y2 0x68014 |
3213 | #define TV_CSC_Y2 0x68014 |
3106 | # define TV_BY_MASK 0x07ff0000 |
3214 | # define TV_BY_MASK 0x07ff0000 |
3107 | # define TV_BY_SHIFT 16 |
3215 | # define TV_BY_SHIFT 16 |
3108 | /* |
3216 | /* |
3109 | * Y attenuation for component video. |
3217 | * Y attenuation for component video. |
3110 | * |
3218 | * |
3111 | * Stored in 1.9 fixed point. |
3219 | * Stored in 1.9 fixed point. |
3112 | */ |
3220 | */ |
3113 | # define TV_AY_MASK 0x000003ff |
3221 | # define TV_AY_MASK 0x000003ff |
3114 | # define TV_AY_SHIFT 0 |
3222 | # define TV_AY_SHIFT 0 |
3115 | 3223 | ||
3116 | #define TV_CSC_U 0x68018 |
3224 | #define TV_CSC_U 0x68018 |
3117 | # define TV_RU_MASK 0x07ff0000 |
3225 | # define TV_RU_MASK 0x07ff0000 |
3118 | # define TV_RU_SHIFT 16 |
3226 | # define TV_RU_SHIFT 16 |
3119 | # define TV_GU_MASK 0x000007ff |
3227 | # define TV_GU_MASK 0x000007ff |
3120 | # define TV_GU_SHIFT 0 |
3228 | # define TV_GU_SHIFT 0 |
3121 | 3229 | ||
3122 | #define TV_CSC_U2 0x6801c |
3230 | #define TV_CSC_U2 0x6801c |
3123 | # define TV_BU_MASK 0x07ff0000 |
3231 | # define TV_BU_MASK 0x07ff0000 |
3124 | # define TV_BU_SHIFT 16 |
3232 | # define TV_BU_SHIFT 16 |
3125 | /* |
3233 | /* |
3126 | * U attenuation for component video. |
3234 | * U attenuation for component video. |
3127 | * |
3235 | * |
3128 | * Stored in 1.9 fixed point. |
3236 | * Stored in 1.9 fixed point. |
3129 | */ |
3237 | */ |
3130 | # define TV_AU_MASK 0x000003ff |
3238 | # define TV_AU_MASK 0x000003ff |
3131 | # define TV_AU_SHIFT 0 |
3239 | # define TV_AU_SHIFT 0 |
3132 | 3240 | ||
3133 | #define TV_CSC_V 0x68020 |
3241 | #define TV_CSC_V 0x68020 |
3134 | # define TV_RV_MASK 0x0fff0000 |
3242 | # define TV_RV_MASK 0x0fff0000 |
3135 | # define TV_RV_SHIFT 16 |
3243 | # define TV_RV_SHIFT 16 |
3136 | # define TV_GV_MASK 0x000007ff |
3244 | # define TV_GV_MASK 0x000007ff |
3137 | # define TV_GV_SHIFT 0 |
3245 | # define TV_GV_SHIFT 0 |
3138 | 3246 | ||
3139 | #define TV_CSC_V2 0x68024 |
3247 | #define TV_CSC_V2 0x68024 |
3140 | # define TV_BV_MASK 0x07ff0000 |
3248 | # define TV_BV_MASK 0x07ff0000 |
3141 | # define TV_BV_SHIFT 16 |
3249 | # define TV_BV_SHIFT 16 |
3142 | /* |
3250 | /* |
3143 | * V attenuation for component video. |
3251 | * V attenuation for component video. |
3144 | * |
3252 | * |
3145 | * Stored in 1.9 fixed point. |
3253 | * Stored in 1.9 fixed point. |
3146 | */ |
3254 | */ |
3147 | # define TV_AV_MASK 0x000007ff |
3255 | # define TV_AV_MASK 0x000007ff |
3148 | # define TV_AV_SHIFT 0 |
3256 | # define TV_AV_SHIFT 0 |
3149 | 3257 | ||
3150 | #define TV_CLR_KNOBS 0x68028 |
3258 | #define TV_CLR_KNOBS 0x68028 |
3151 | /* 2s-complement brightness adjustment */ |
3259 | /* 2s-complement brightness adjustment */ |
3152 | # define TV_BRIGHTNESS_MASK 0xff000000 |
3260 | # define TV_BRIGHTNESS_MASK 0xff000000 |
3153 | # define TV_BRIGHTNESS_SHIFT 24 |
3261 | # define TV_BRIGHTNESS_SHIFT 24 |
3154 | /* Contrast adjustment, as a 2.6 unsigned floating point number */ |
3262 | /* Contrast adjustment, as a 2.6 unsigned floating point number */ |
3155 | # define TV_CONTRAST_MASK 0x00ff0000 |
3263 | # define TV_CONTRAST_MASK 0x00ff0000 |
3156 | # define TV_CONTRAST_SHIFT 16 |
3264 | # define TV_CONTRAST_SHIFT 16 |
3157 | /* Saturation adjustment, as a 2.6 unsigned floating point number */ |
3265 | /* Saturation adjustment, as a 2.6 unsigned floating point number */ |
3158 | # define TV_SATURATION_MASK 0x0000ff00 |
3266 | # define TV_SATURATION_MASK 0x0000ff00 |
3159 | # define TV_SATURATION_SHIFT 8 |
3267 | # define TV_SATURATION_SHIFT 8 |
3160 | /* Hue adjustment, as an integer phase angle in degrees */ |
3268 | /* Hue adjustment, as an integer phase angle in degrees */ |
3161 | # define TV_HUE_MASK 0x000000ff |
3269 | # define TV_HUE_MASK 0x000000ff |
3162 | # define TV_HUE_SHIFT 0 |
3270 | # define TV_HUE_SHIFT 0 |
3163 | 3271 | ||
3164 | #define TV_CLR_LEVEL 0x6802c |
3272 | #define TV_CLR_LEVEL 0x6802c |
3165 | /* Controls the DAC level for black */ |
3273 | /* Controls the DAC level for black */ |
3166 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 |
3274 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 |
3167 | # define TV_BLACK_LEVEL_SHIFT 16 |
3275 | # define TV_BLACK_LEVEL_SHIFT 16 |
3168 | /* Controls the DAC level for blanking */ |
3276 | /* Controls the DAC level for blanking */ |
3169 | # define TV_BLANK_LEVEL_MASK 0x000001ff |
3277 | # define TV_BLANK_LEVEL_MASK 0x000001ff |
3170 | # define TV_BLANK_LEVEL_SHIFT 0 |
3278 | # define TV_BLANK_LEVEL_SHIFT 0 |
3171 | 3279 | ||
3172 | #define TV_H_CTL_1 0x68030 |
3280 | #define TV_H_CTL_1 0x68030 |
3173 | /* Number of pixels in the hsync. */ |
3281 | /* Number of pixels in the hsync. */ |
3174 | # define TV_HSYNC_END_MASK 0x1fff0000 |
3282 | # define TV_HSYNC_END_MASK 0x1fff0000 |
3175 | # define TV_HSYNC_END_SHIFT 16 |
3283 | # define TV_HSYNC_END_SHIFT 16 |
3176 | /* Total number of pixels minus one in the line (display and blanking). */ |
3284 | /* Total number of pixels minus one in the line (display and blanking). */ |
3177 | # define TV_HTOTAL_MASK 0x00001fff |
3285 | # define TV_HTOTAL_MASK 0x00001fff |
3178 | # define TV_HTOTAL_SHIFT 0 |
3286 | # define TV_HTOTAL_SHIFT 0 |
3179 | 3287 | ||
3180 | #define TV_H_CTL_2 0x68034 |
3288 | #define TV_H_CTL_2 0x68034 |
3181 | /* Enables the colorburst (needed for non-component color) */ |
3289 | /* Enables the colorburst (needed for non-component color) */ |
3182 | # define TV_BURST_ENA (1 << 31) |
3290 | # define TV_BURST_ENA (1 << 31) |
3183 | /* Offset of the colorburst from the start of hsync, in pixels minus one. */ |
3291 | /* Offset of the colorburst from the start of hsync, in pixels minus one. */ |
3184 | # define TV_HBURST_START_SHIFT 16 |
3292 | # define TV_HBURST_START_SHIFT 16 |
3185 | # define TV_HBURST_START_MASK 0x1fff0000 |
3293 | # define TV_HBURST_START_MASK 0x1fff0000 |
3186 | /* Length of the colorburst */ |
3294 | /* Length of the colorburst */ |
3187 | # define TV_HBURST_LEN_SHIFT 0 |
3295 | # define TV_HBURST_LEN_SHIFT 0 |
3188 | # define TV_HBURST_LEN_MASK 0x0001fff |
3296 | # define TV_HBURST_LEN_MASK 0x0001fff |
3189 | 3297 | ||
3190 | #define TV_H_CTL_3 0x68038 |
3298 | #define TV_H_CTL_3 0x68038 |
3191 | /* End of hblank, measured in pixels minus one from start of hsync */ |
3299 | /* End of hblank, measured in pixels minus one from start of hsync */ |
3192 | # define TV_HBLANK_END_SHIFT 16 |
3300 | # define TV_HBLANK_END_SHIFT 16 |
3193 | # define TV_HBLANK_END_MASK 0x1fff0000 |
3301 | # define TV_HBLANK_END_MASK 0x1fff0000 |
3194 | /* Start of hblank, measured in pixels minus one from start of hsync */ |
3302 | /* Start of hblank, measured in pixels minus one from start of hsync */ |
3195 | # define TV_HBLANK_START_SHIFT 0 |
3303 | # define TV_HBLANK_START_SHIFT 0 |
3196 | # define TV_HBLANK_START_MASK 0x0001fff |
3304 | # define TV_HBLANK_START_MASK 0x0001fff |
3197 | 3305 | ||
3198 | #define TV_V_CTL_1 0x6803c |
3306 | #define TV_V_CTL_1 0x6803c |
3199 | /* XXX */ |
3307 | /* XXX */ |
3200 | # define TV_NBR_END_SHIFT 16 |
3308 | # define TV_NBR_END_SHIFT 16 |
3201 | # define TV_NBR_END_MASK 0x07ff0000 |
3309 | # define TV_NBR_END_MASK 0x07ff0000 |
3202 | /* XXX */ |
3310 | /* XXX */ |
3203 | # define TV_VI_END_F1_SHIFT 8 |
3311 | # define TV_VI_END_F1_SHIFT 8 |
3204 | # define TV_VI_END_F1_MASK 0x00003f00 |
3312 | # define TV_VI_END_F1_MASK 0x00003f00 |
3205 | /* XXX */ |
3313 | /* XXX */ |
3206 | # define TV_VI_END_F2_SHIFT 0 |
3314 | # define TV_VI_END_F2_SHIFT 0 |
3207 | # define TV_VI_END_F2_MASK 0x0000003f |
3315 | # define TV_VI_END_F2_MASK 0x0000003f |
3208 | 3316 | ||
3209 | #define TV_V_CTL_2 0x68040 |
3317 | #define TV_V_CTL_2 0x68040 |
3210 | /* Length of vsync, in half lines */ |
3318 | /* Length of vsync, in half lines */ |
3211 | # define TV_VSYNC_LEN_MASK 0x07ff0000 |
3319 | # define TV_VSYNC_LEN_MASK 0x07ff0000 |
3212 | # define TV_VSYNC_LEN_SHIFT 16 |
3320 | # define TV_VSYNC_LEN_SHIFT 16 |
3213 | /* Offset of the start of vsync in field 1, measured in one less than the |
3321 | /* Offset of the start of vsync in field 1, measured in one less than the |
3214 | * number of half lines. |
3322 | * number of half lines. |
3215 | */ |
3323 | */ |
3216 | # define TV_VSYNC_START_F1_MASK 0x00007f00 |
3324 | # define TV_VSYNC_START_F1_MASK 0x00007f00 |
3217 | # define TV_VSYNC_START_F1_SHIFT 8 |
3325 | # define TV_VSYNC_START_F1_SHIFT 8 |
3218 | /* |
3326 | /* |
3219 | * Offset of the start of vsync in field 2, measured in one less than the |
3327 | * Offset of the start of vsync in field 2, measured in one less than the |
3220 | * number of half lines. |
3328 | * number of half lines. |
3221 | */ |
3329 | */ |
3222 | # define TV_VSYNC_START_F2_MASK 0x0000007f |
3330 | # define TV_VSYNC_START_F2_MASK 0x0000007f |
3223 | # define TV_VSYNC_START_F2_SHIFT 0 |
3331 | # define TV_VSYNC_START_F2_SHIFT 0 |
3224 | 3332 | ||
3225 | #define TV_V_CTL_3 0x68044 |
3333 | #define TV_V_CTL_3 0x68044 |
3226 | /* Enables generation of the equalization signal */ |
3334 | /* Enables generation of the equalization signal */ |
3227 | # define TV_EQUAL_ENA (1 << 31) |
3335 | # define TV_EQUAL_ENA (1 << 31) |
3228 | /* Length of vsync, in half lines */ |
3336 | /* Length of vsync, in half lines */ |
3229 | # define TV_VEQ_LEN_MASK 0x007f0000 |
3337 | # define TV_VEQ_LEN_MASK 0x007f0000 |
3230 | # define TV_VEQ_LEN_SHIFT 16 |
3338 | # define TV_VEQ_LEN_SHIFT 16 |
3231 | /* Offset of the start of equalization in field 1, measured in one less than |
3339 | /* Offset of the start of equalization in field 1, measured in one less than |
3232 | * the number of half lines. |
3340 | * the number of half lines. |
3233 | */ |
3341 | */ |
3234 | # define TV_VEQ_START_F1_MASK 0x0007f00 |
3342 | # define TV_VEQ_START_F1_MASK 0x0007f00 |
3235 | # define TV_VEQ_START_F1_SHIFT 8 |
3343 | # define TV_VEQ_START_F1_SHIFT 8 |
3236 | /* |
3344 | /* |
3237 | * Offset of the start of equalization in field 2, measured in one less than |
3345 | * Offset of the start of equalization in field 2, measured in one less than |
3238 | * the number of half lines. |
3346 | * the number of half lines. |
3239 | */ |
3347 | */ |
3240 | # define TV_VEQ_START_F2_MASK 0x000007f |
3348 | # define TV_VEQ_START_F2_MASK 0x000007f |
3241 | # define TV_VEQ_START_F2_SHIFT 0 |
3349 | # define TV_VEQ_START_F2_SHIFT 0 |
3242 | 3350 | ||
3243 | #define TV_V_CTL_4 0x68048 |
3351 | #define TV_V_CTL_4 0x68048 |
3244 | /* |
3352 | /* |
3245 | * Offset to start of vertical colorburst, measured in one less than the |
3353 | * Offset to start of vertical colorburst, measured in one less than the |
3246 | * number of lines from vertical start. |
3354 | * number of lines from vertical start. |
3247 | */ |
3355 | */ |
3248 | # define TV_VBURST_START_F1_MASK 0x003f0000 |
3356 | # define TV_VBURST_START_F1_MASK 0x003f0000 |
3249 | # define TV_VBURST_START_F1_SHIFT 16 |
3357 | # define TV_VBURST_START_F1_SHIFT 16 |
3250 | /* |
3358 | /* |
3251 | * Offset to the end of vertical colorburst, measured in one less than the |
3359 | * Offset to the end of vertical colorburst, measured in one less than the |
3252 | * number of lines from the start of NBR. |
3360 | * number of lines from the start of NBR. |
3253 | */ |
3361 | */ |
3254 | # define TV_VBURST_END_F1_MASK 0x000000ff |
3362 | # define TV_VBURST_END_F1_MASK 0x000000ff |
3255 | # define TV_VBURST_END_F1_SHIFT 0 |
3363 | # define TV_VBURST_END_F1_SHIFT 0 |
3256 | 3364 | ||
3257 | #define TV_V_CTL_5 0x6804c |
3365 | #define TV_V_CTL_5 0x6804c |
3258 | /* |
3366 | /* |
3259 | * Offset to start of vertical colorburst, measured in one less than the |
3367 | * Offset to start of vertical colorburst, measured in one less than the |
3260 | * number of lines from vertical start. |
3368 | * number of lines from vertical start. |
3261 | */ |
3369 | */ |
3262 | # define TV_VBURST_START_F2_MASK 0x003f0000 |
3370 | # define TV_VBURST_START_F2_MASK 0x003f0000 |
3263 | # define TV_VBURST_START_F2_SHIFT 16 |
3371 | # define TV_VBURST_START_F2_SHIFT 16 |
3264 | /* |
3372 | /* |
3265 | * Offset to the end of vertical colorburst, measured in one less than the |
3373 | * Offset to the end of vertical colorburst, measured in one less than the |
3266 | * number of lines from the start of NBR. |
3374 | * number of lines from the start of NBR. |
3267 | */ |
3375 | */ |
3268 | # define TV_VBURST_END_F2_MASK 0x000000ff |
3376 | # define TV_VBURST_END_F2_MASK 0x000000ff |
3269 | # define TV_VBURST_END_F2_SHIFT 0 |
3377 | # define TV_VBURST_END_F2_SHIFT 0 |
3270 | 3378 | ||
3271 | #define TV_V_CTL_6 0x68050 |
3379 | #define TV_V_CTL_6 0x68050 |
3272 | /* |
3380 | /* |
3273 | * Offset to start of vertical colorburst, measured in one less than the |
3381 | * Offset to start of vertical colorburst, measured in one less than the |
3274 | * number of lines from vertical start. |
3382 | * number of lines from vertical start. |
3275 | */ |
3383 | */ |
3276 | # define TV_VBURST_START_F3_MASK 0x003f0000 |
3384 | # define TV_VBURST_START_F3_MASK 0x003f0000 |
3277 | # define TV_VBURST_START_F3_SHIFT 16 |
3385 | # define TV_VBURST_START_F3_SHIFT 16 |
3278 | /* |
3386 | /* |
3279 | * Offset to the end of vertical colorburst, measured in one less than the |
3387 | * Offset to the end of vertical colorburst, measured in one less than the |
3280 | * number of lines from the start of NBR. |
3388 | * number of lines from the start of NBR. |
3281 | */ |
3389 | */ |
3282 | # define TV_VBURST_END_F3_MASK 0x000000ff |
3390 | # define TV_VBURST_END_F3_MASK 0x000000ff |
3283 | # define TV_VBURST_END_F3_SHIFT 0 |
3391 | # define TV_VBURST_END_F3_SHIFT 0 |
3284 | 3392 | ||
3285 | #define TV_V_CTL_7 0x68054 |
3393 | #define TV_V_CTL_7 0x68054 |
3286 | /* |
3394 | /* |
3287 | * Offset to start of vertical colorburst, measured in one less than the |
3395 | * Offset to start of vertical colorburst, measured in one less than the |
3288 | * number of lines from vertical start. |
3396 | * number of lines from vertical start. |
3289 | */ |
3397 | */ |
3290 | # define TV_VBURST_START_F4_MASK 0x003f0000 |
3398 | # define TV_VBURST_START_F4_MASK 0x003f0000 |
3291 | # define TV_VBURST_START_F4_SHIFT 16 |
3399 | # define TV_VBURST_START_F4_SHIFT 16 |
3292 | /* |
3400 | /* |
3293 | * Offset to the end of vertical colorburst, measured in one less than the |
3401 | * Offset to the end of vertical colorburst, measured in one less than the |
3294 | * number of lines from the start of NBR. |
3402 | * number of lines from the start of NBR. |
3295 | */ |
3403 | */ |
3296 | # define TV_VBURST_END_F4_MASK 0x000000ff |
3404 | # define TV_VBURST_END_F4_MASK 0x000000ff |
3297 | # define TV_VBURST_END_F4_SHIFT 0 |
3405 | # define TV_VBURST_END_F4_SHIFT 0 |
3298 | 3406 | ||
3299 | #define TV_SC_CTL_1 0x68060 |
3407 | #define TV_SC_CTL_1 0x68060 |
3300 | /* Turns on the first subcarrier phase generation DDA */ |
3408 | /* Turns on the first subcarrier phase generation DDA */ |
3301 | # define TV_SC_DDA1_EN (1 << 31) |
3409 | # define TV_SC_DDA1_EN (1 << 31) |
3302 | /* Turns on the first subcarrier phase generation DDA */ |
3410 | /* Turns on the first subcarrier phase generation DDA */ |
3303 | # define TV_SC_DDA2_EN (1 << 30) |
3411 | # define TV_SC_DDA2_EN (1 << 30) |
3304 | /* Turns on the first subcarrier phase generation DDA */ |
3412 | /* Turns on the first subcarrier phase generation DDA */ |
3305 | # define TV_SC_DDA3_EN (1 << 29) |
3413 | # define TV_SC_DDA3_EN (1 << 29) |
3306 | /* Sets the subcarrier DDA to reset frequency every other field */ |
3414 | /* Sets the subcarrier DDA to reset frequency every other field */ |
3307 | # define TV_SC_RESET_EVERY_2 (0 << 24) |
3415 | # define TV_SC_RESET_EVERY_2 (0 << 24) |
3308 | /* Sets the subcarrier DDA to reset frequency every fourth field */ |
3416 | /* Sets the subcarrier DDA to reset frequency every fourth field */ |
3309 | # define TV_SC_RESET_EVERY_4 (1 << 24) |
3417 | # define TV_SC_RESET_EVERY_4 (1 << 24) |
3310 | /* Sets the subcarrier DDA to reset frequency every eighth field */ |
3418 | /* Sets the subcarrier DDA to reset frequency every eighth field */ |
3311 | # define TV_SC_RESET_EVERY_8 (2 << 24) |
3419 | # define TV_SC_RESET_EVERY_8 (2 << 24) |
3312 | /* Sets the subcarrier DDA to never reset the frequency */ |
3420 | /* Sets the subcarrier DDA to never reset the frequency */ |
3313 | # define TV_SC_RESET_NEVER (3 << 24) |
3421 | # define TV_SC_RESET_NEVER (3 << 24) |
3314 | /* Sets the peak amplitude of the colorburst.*/ |
3422 | /* Sets the peak amplitude of the colorburst.*/ |
3315 | # define TV_BURST_LEVEL_MASK 0x00ff0000 |
3423 | # define TV_BURST_LEVEL_MASK 0x00ff0000 |
3316 | # define TV_BURST_LEVEL_SHIFT 16 |
3424 | # define TV_BURST_LEVEL_SHIFT 16 |
3317 | /* Sets the increment of the first subcarrier phase generation DDA */ |
3425 | /* Sets the increment of the first subcarrier phase generation DDA */ |
3318 | # define TV_SCDDA1_INC_MASK 0x00000fff |
3426 | # define TV_SCDDA1_INC_MASK 0x00000fff |
3319 | # define TV_SCDDA1_INC_SHIFT 0 |
3427 | # define TV_SCDDA1_INC_SHIFT 0 |
3320 | 3428 | ||
3321 | #define TV_SC_CTL_2 0x68064 |
3429 | #define TV_SC_CTL_2 0x68064 |
3322 | /* Sets the rollover for the second subcarrier phase generation DDA */ |
3430 | /* Sets the rollover for the second subcarrier phase generation DDA */ |
3323 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
3431 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
3324 | # define TV_SCDDA2_SIZE_SHIFT 16 |
3432 | # define TV_SCDDA2_SIZE_SHIFT 16 |
3325 | /* Sets the increent of the second subcarrier phase generation DDA */ |
3433 | /* Sets the increent of the second subcarrier phase generation DDA */ |
3326 | # define TV_SCDDA2_INC_MASK 0x00007fff |
3434 | # define TV_SCDDA2_INC_MASK 0x00007fff |
3327 | # define TV_SCDDA2_INC_SHIFT 0 |
3435 | # define TV_SCDDA2_INC_SHIFT 0 |
3328 | 3436 | ||
3329 | #define TV_SC_CTL_3 0x68068 |
3437 | #define TV_SC_CTL_3 0x68068 |
3330 | /* Sets the rollover for the third subcarrier phase generation DDA */ |
3438 | /* Sets the rollover for the third subcarrier phase generation DDA */ |
3331 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
3439 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
3332 | # define TV_SCDDA3_SIZE_SHIFT 16 |
3440 | # define TV_SCDDA3_SIZE_SHIFT 16 |
3333 | /* Sets the increent of the third subcarrier phase generation DDA */ |
3441 | /* Sets the increent of the third subcarrier phase generation DDA */ |
3334 | # define TV_SCDDA3_INC_MASK 0x00007fff |
3442 | # define TV_SCDDA3_INC_MASK 0x00007fff |
3335 | # define TV_SCDDA3_INC_SHIFT 0 |
3443 | # define TV_SCDDA3_INC_SHIFT 0 |
3336 | 3444 | ||
3337 | #define TV_WIN_POS 0x68070 |
3445 | #define TV_WIN_POS 0x68070 |
3338 | /* X coordinate of the display from the start of horizontal active */ |
3446 | /* X coordinate of the display from the start of horizontal active */ |
3339 | # define TV_XPOS_MASK 0x1fff0000 |
3447 | # define TV_XPOS_MASK 0x1fff0000 |
3340 | # define TV_XPOS_SHIFT 16 |
3448 | # define TV_XPOS_SHIFT 16 |
3341 | /* Y coordinate of the display from the start of vertical active (NBR) */ |
3449 | /* Y coordinate of the display from the start of vertical active (NBR) */ |
3342 | # define TV_YPOS_MASK 0x00000fff |
3450 | # define TV_YPOS_MASK 0x00000fff |
3343 | # define TV_YPOS_SHIFT 0 |
3451 | # define TV_YPOS_SHIFT 0 |
3344 | 3452 | ||
3345 | #define TV_WIN_SIZE 0x68074 |
3453 | #define TV_WIN_SIZE 0x68074 |
3346 | /* Horizontal size of the display window, measured in pixels*/ |
3454 | /* Horizontal size of the display window, measured in pixels*/ |
3347 | # define TV_XSIZE_MASK 0x1fff0000 |
3455 | # define TV_XSIZE_MASK 0x1fff0000 |
3348 | # define TV_XSIZE_SHIFT 16 |
3456 | # define TV_XSIZE_SHIFT 16 |
3349 | /* |
3457 | /* |
3350 | * Vertical size of the display window, measured in pixels. |
3458 | * Vertical size of the display window, measured in pixels. |
3351 | * |
3459 | * |
3352 | * Must be even for interlaced modes. |
3460 | * Must be even for interlaced modes. |
3353 | */ |
3461 | */ |
3354 | # define TV_YSIZE_MASK 0x00000fff |
3462 | # define TV_YSIZE_MASK 0x00000fff |
3355 | # define TV_YSIZE_SHIFT 0 |
3463 | # define TV_YSIZE_SHIFT 0 |
3356 | 3464 | ||
3357 | #define TV_FILTER_CTL_1 0x68080 |
3465 | #define TV_FILTER_CTL_1 0x68080 |
3358 | /* |
3466 | /* |
3359 | * Enables automatic scaling calculation. |
3467 | * Enables automatic scaling calculation. |
3360 | * |
3468 | * |
3361 | * If set, the rest of the registers are ignored, and the calculated values can |
3469 | * If set, the rest of the registers are ignored, and the calculated values can |
3362 | * be read back from the register. |
3470 | * be read back from the register. |
3363 | */ |
3471 | */ |
3364 | # define TV_AUTO_SCALE (1 << 31) |
3472 | # define TV_AUTO_SCALE (1 << 31) |
3365 | /* |
3473 | /* |
3366 | * Disables the vertical filter. |
3474 | * Disables the vertical filter. |
3367 | * |
3475 | * |
3368 | * This is required on modes more than 1024 pixels wide */ |
3476 | * This is required on modes more than 1024 pixels wide */ |
3369 | # define TV_V_FILTER_BYPASS (1 << 29) |
3477 | # define TV_V_FILTER_BYPASS (1 << 29) |
3370 | /* Enables adaptive vertical filtering */ |
3478 | /* Enables adaptive vertical filtering */ |
3371 | # define TV_VADAPT (1 << 28) |
3479 | # define TV_VADAPT (1 << 28) |
3372 | # define TV_VADAPT_MODE_MASK (3 << 26) |
3480 | # define TV_VADAPT_MODE_MASK (3 << 26) |
3373 | /* Selects the least adaptive vertical filtering mode */ |
3481 | /* Selects the least adaptive vertical filtering mode */ |
3374 | # define TV_VADAPT_MODE_LEAST (0 << 26) |
3482 | # define TV_VADAPT_MODE_LEAST (0 << 26) |
3375 | /* Selects the moderately adaptive vertical filtering mode */ |
3483 | /* Selects the moderately adaptive vertical filtering mode */ |
3376 | # define TV_VADAPT_MODE_MODERATE (1 << 26) |
3484 | # define TV_VADAPT_MODE_MODERATE (1 << 26) |
3377 | /* Selects the most adaptive vertical filtering mode */ |
3485 | /* Selects the most adaptive vertical filtering mode */ |
3378 | # define TV_VADAPT_MODE_MOST (3 << 26) |
3486 | # define TV_VADAPT_MODE_MOST (3 << 26) |
3379 | /* |
3487 | /* |
3380 | * Sets the horizontal scaling factor. |
3488 | * Sets the horizontal scaling factor. |
3381 | * |
3489 | * |
3382 | * This should be the fractional part of the horizontal scaling factor divided |
3490 | * This should be the fractional part of the horizontal scaling factor divided |
3383 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: |
3491 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: |
3384 | * |
3492 | * |
3385 | * (src width - 1) / ((oversample * dest width) - 1) |
3493 | * (src width - 1) / ((oversample * dest width) - 1) |
3386 | */ |
3494 | */ |
3387 | # define TV_HSCALE_FRAC_MASK 0x00003fff |
3495 | # define TV_HSCALE_FRAC_MASK 0x00003fff |
3388 | # define TV_HSCALE_FRAC_SHIFT 0 |
3496 | # define TV_HSCALE_FRAC_SHIFT 0 |
3389 | 3497 | ||
3390 | #define TV_FILTER_CTL_2 0x68084 |
3498 | #define TV_FILTER_CTL_2 0x68084 |
3391 | /* |
3499 | /* |
3392 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
3500 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
3393 | * |
3501 | * |
3394 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) |
3502 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) |
3395 | */ |
3503 | */ |
3396 | # define TV_VSCALE_INT_MASK 0x00038000 |
3504 | # define TV_VSCALE_INT_MASK 0x00038000 |
3397 | # define TV_VSCALE_INT_SHIFT 15 |
3505 | # define TV_VSCALE_INT_SHIFT 15 |
3398 | /* |
3506 | /* |
3399 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
3507 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
3400 | * |
3508 | * |
3401 | * \sa TV_VSCALE_INT_MASK |
3509 | * \sa TV_VSCALE_INT_MASK |
3402 | */ |
3510 | */ |
3403 | # define TV_VSCALE_FRAC_MASK 0x00007fff |
3511 | # define TV_VSCALE_FRAC_MASK 0x00007fff |
3404 | # define TV_VSCALE_FRAC_SHIFT 0 |
3512 | # define TV_VSCALE_FRAC_SHIFT 0 |
3405 | 3513 | ||
3406 | #define TV_FILTER_CTL_3 0x68088 |
3514 | #define TV_FILTER_CTL_3 0x68088 |
3407 | /* |
3515 | /* |
3408 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
3516 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
3409 | * |
3517 | * |
3410 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) |
3518 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) |
3411 | * |
3519 | * |
3412 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
3520 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
3413 | */ |
3521 | */ |
3414 | # define TV_VSCALE_IP_INT_MASK 0x00038000 |
3522 | # define TV_VSCALE_IP_INT_MASK 0x00038000 |
3415 | # define TV_VSCALE_IP_INT_SHIFT 15 |
3523 | # define TV_VSCALE_IP_INT_SHIFT 15 |
3416 | /* |
3524 | /* |
3417 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
3525 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
3418 | * |
3526 | * |
3419 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
3527 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
3420 | * |
3528 | * |
3421 | * \sa TV_VSCALE_IP_INT_MASK |
3529 | * \sa TV_VSCALE_IP_INT_MASK |
3422 | */ |
3530 | */ |
3423 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff |
3531 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff |
3424 | # define TV_VSCALE_IP_FRAC_SHIFT 0 |
3532 | # define TV_VSCALE_IP_FRAC_SHIFT 0 |
3425 | 3533 | ||
3426 | #define TV_CC_CONTROL 0x68090 |
3534 | #define TV_CC_CONTROL 0x68090 |
3427 | # define TV_CC_ENABLE (1 << 31) |
3535 | # define TV_CC_ENABLE (1 << 31) |
3428 | /* |
3536 | /* |
3429 | * Specifies which field to send the CC data in. |
3537 | * Specifies which field to send the CC data in. |
3430 | * |
3538 | * |
3431 | * CC data is usually sent in field 0. |
3539 | * CC data is usually sent in field 0. |
3432 | */ |
3540 | */ |
3433 | # define TV_CC_FID_MASK (1 << 27) |
3541 | # define TV_CC_FID_MASK (1 << 27) |
3434 | # define TV_CC_FID_SHIFT 27 |
3542 | # define TV_CC_FID_SHIFT 27 |
3435 | /* Sets the horizontal position of the CC data. Usually 135. */ |
3543 | /* Sets the horizontal position of the CC data. Usually 135. */ |
3436 | # define TV_CC_HOFF_MASK 0x03ff0000 |
3544 | # define TV_CC_HOFF_MASK 0x03ff0000 |
3437 | # define TV_CC_HOFF_SHIFT 16 |
3545 | # define TV_CC_HOFF_SHIFT 16 |
3438 | /* Sets the vertical position of the CC data. Usually 21 */ |
3546 | /* Sets the vertical position of the CC data. Usually 21 */ |
3439 | # define TV_CC_LINE_MASK 0x0000003f |
3547 | # define TV_CC_LINE_MASK 0x0000003f |
3440 | # define TV_CC_LINE_SHIFT 0 |
3548 | # define TV_CC_LINE_SHIFT 0 |
3441 | 3549 | ||
3442 | #define TV_CC_DATA 0x68094 |
3550 | #define TV_CC_DATA 0x68094 |
3443 | # define TV_CC_RDY (1 << 31) |
3551 | # define TV_CC_RDY (1 << 31) |
3444 | /* Second word of CC data to be transmitted. */ |
3552 | /* Second word of CC data to be transmitted. */ |
3445 | # define TV_CC_DATA_2_MASK 0x007f0000 |
3553 | # define TV_CC_DATA_2_MASK 0x007f0000 |
3446 | # define TV_CC_DATA_2_SHIFT 16 |
3554 | # define TV_CC_DATA_2_SHIFT 16 |
3447 | /* First word of CC data to be transmitted. */ |
3555 | /* First word of CC data to be transmitted. */ |
3448 | # define TV_CC_DATA_1_MASK 0x0000007f |
3556 | # define TV_CC_DATA_1_MASK 0x0000007f |
3449 | # define TV_CC_DATA_1_SHIFT 0 |
3557 | # define TV_CC_DATA_1_SHIFT 0 |
3450 | 3558 | ||
3451 | #define TV_H_LUMA_0 0x68100 |
3559 | #define TV_H_LUMA_0 0x68100 |
3452 | #define TV_H_LUMA_59 0x681ec |
3560 | #define TV_H_LUMA_59 0x681ec |
3453 | #define TV_H_CHROMA_0 0x68200 |
3561 | #define TV_H_CHROMA_0 0x68200 |
3454 | #define TV_H_CHROMA_59 0x682ec |
3562 | #define TV_H_CHROMA_59 0x682ec |
3455 | #define TV_V_LUMA_0 0x68300 |
3563 | #define TV_V_LUMA_0 0x68300 |
3456 | #define TV_V_LUMA_42 0x683a8 |
3564 | #define TV_V_LUMA_42 0x683a8 |
3457 | #define TV_V_CHROMA_0 0x68400 |
3565 | #define TV_V_CHROMA_0 0x68400 |
3458 | #define TV_V_CHROMA_42 0x684a8 |
3566 | #define TV_V_CHROMA_42 0x684a8 |
3459 | 3567 | ||
3460 | /* Display Port */ |
3568 | /* Display Port */ |
3461 | #define DP_A 0x64000 /* eDP */ |
3569 | #define DP_A 0x64000 /* eDP */ |
3462 | #define DP_B 0x64100 |
3570 | #define DP_B 0x64100 |
3463 | #define DP_C 0x64200 |
3571 | #define DP_C 0x64200 |
3464 | #define DP_D 0x64300 |
3572 | #define DP_D 0x64300 |
3465 | 3573 | ||
3466 | #define DP_PORT_EN (1 << 31) |
3574 | #define DP_PORT_EN (1 << 31) |
3467 | #define DP_PIPEB_SELECT (1 << 30) |
3575 | #define DP_PIPEB_SELECT (1 << 30) |
3468 | #define DP_PIPE_MASK (1 << 30) |
3576 | #define DP_PIPE_MASK (1 << 30) |
3469 | #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) |
3577 | #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) |
3470 | #define DP_PIPE_MASK_CHV (3 << 16) |
3578 | #define DP_PIPE_MASK_CHV (3 << 16) |
3471 | 3579 | ||
3472 | /* Link training mode - select a suitable mode for each stage */ |
3580 | /* Link training mode - select a suitable mode for each stage */ |
3473 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) |
3581 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) |
3474 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) |
3582 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) |
3475 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
3583 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
3476 | #define DP_LINK_TRAIN_OFF (3 << 28) |
3584 | #define DP_LINK_TRAIN_OFF (3 << 28) |
3477 | #define DP_LINK_TRAIN_MASK (3 << 28) |
3585 | #define DP_LINK_TRAIN_MASK (3 << 28) |
3478 | #define DP_LINK_TRAIN_SHIFT 28 |
3586 | #define DP_LINK_TRAIN_SHIFT 28 |
- | 3587 | #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) |
|
- | 3588 | #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) |
|
3479 | 3589 | ||
3480 | /* CPT Link training mode */ |
3590 | /* CPT Link training mode */ |
3481 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
3591 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
3482 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
3592 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
3483 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
3593 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
3484 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) |
3594 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) |
3485 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) |
3595 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) |
3486 | #define DP_LINK_TRAIN_SHIFT_CPT 8 |
3596 | #define DP_LINK_TRAIN_SHIFT_CPT 8 |
3487 | 3597 | ||
3488 | /* Signal voltages. These are mostly controlled by the other end */ |
3598 | /* Signal voltages. These are mostly controlled by the other end */ |
3489 | #define DP_VOLTAGE_0_4 (0 << 25) |
3599 | #define DP_VOLTAGE_0_4 (0 << 25) |
3490 | #define DP_VOLTAGE_0_6 (1 << 25) |
3600 | #define DP_VOLTAGE_0_6 (1 << 25) |
3491 | #define DP_VOLTAGE_0_8 (2 << 25) |
3601 | #define DP_VOLTAGE_0_8 (2 << 25) |
3492 | #define DP_VOLTAGE_1_2 (3 << 25) |
3602 | #define DP_VOLTAGE_1_2 (3 << 25) |
3493 | #define DP_VOLTAGE_MASK (7 << 25) |
3603 | #define DP_VOLTAGE_MASK (7 << 25) |
3494 | #define DP_VOLTAGE_SHIFT 25 |
3604 | #define DP_VOLTAGE_SHIFT 25 |
3495 | 3605 | ||
3496 | /* Signal pre-emphasis levels, like voltages, the other end tells us what |
3606 | /* Signal pre-emphasis levels, like voltages, the other end tells us what |
3497 | * they want |
3607 | * they want |
3498 | */ |
3608 | */ |
3499 | #define DP_PRE_EMPHASIS_0 (0 << 22) |
3609 | #define DP_PRE_EMPHASIS_0 (0 << 22) |
3500 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) |
3610 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) |
3501 | #define DP_PRE_EMPHASIS_6 (2 << 22) |
3611 | #define DP_PRE_EMPHASIS_6 (2 << 22) |
3502 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) |
3612 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) |
3503 | #define DP_PRE_EMPHASIS_MASK (7 << 22) |
3613 | #define DP_PRE_EMPHASIS_MASK (7 << 22) |
3504 | #define DP_PRE_EMPHASIS_SHIFT 22 |
3614 | #define DP_PRE_EMPHASIS_SHIFT 22 |
3505 | 3615 | ||
3506 | /* How many wires to use. I guess 3 was too hard */ |
3616 | /* How many wires to use. I guess 3 was too hard */ |
3507 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
3617 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
3508 | #define DP_PORT_WIDTH_MASK (7 << 19) |
3618 | #define DP_PORT_WIDTH_MASK (7 << 19) |
3509 | 3619 | ||
3510 | /* Mystic DPCD version 1.1 special mode */ |
3620 | /* Mystic DPCD version 1.1 special mode */ |
3511 | #define DP_ENHANCED_FRAMING (1 << 18) |
3621 | #define DP_ENHANCED_FRAMING (1 << 18) |
3512 | 3622 | ||
3513 | /* eDP */ |
3623 | /* eDP */ |
3514 | #define DP_PLL_FREQ_270MHZ (0 << 16) |
3624 | #define DP_PLL_FREQ_270MHZ (0 << 16) |
3515 | #define DP_PLL_FREQ_160MHZ (1 << 16) |
3625 | #define DP_PLL_FREQ_160MHZ (1 << 16) |
3516 | #define DP_PLL_FREQ_MASK (3 << 16) |
3626 | #define DP_PLL_FREQ_MASK (3 << 16) |
3517 | 3627 | ||
3518 | /* locked once port is enabled */ |
3628 | /* locked once port is enabled */ |
3519 | #define DP_PORT_REVERSAL (1 << 15) |
3629 | #define DP_PORT_REVERSAL (1 << 15) |
3520 | 3630 | ||
3521 | /* eDP */ |
3631 | /* eDP */ |
3522 | #define DP_PLL_ENABLE (1 << 14) |
3632 | #define DP_PLL_ENABLE (1 << 14) |
3523 | 3633 | ||
3524 | /* sends the clock on lane 15 of the PEG for debug */ |
3634 | /* sends the clock on lane 15 of the PEG for debug */ |
3525 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
3635 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
3526 | 3636 | ||
3527 | #define DP_SCRAMBLING_DISABLE (1 << 12) |
3637 | #define DP_SCRAMBLING_DISABLE (1 << 12) |
3528 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
3638 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
3529 | 3639 | ||
3530 | /* limit RGB values to avoid confusing TVs */ |
3640 | /* limit RGB values to avoid confusing TVs */ |
3531 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
3641 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
3532 | 3642 | ||
3533 | /* Turn on the audio link */ |
3643 | /* Turn on the audio link */ |
3534 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
3644 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
3535 | 3645 | ||
3536 | /* vs and hs sync polarity */ |
3646 | /* vs and hs sync polarity */ |
3537 | #define DP_SYNC_VS_HIGH (1 << 4) |
3647 | #define DP_SYNC_VS_HIGH (1 << 4) |
3538 | #define DP_SYNC_HS_HIGH (1 << 3) |
3648 | #define DP_SYNC_HS_HIGH (1 << 3) |
3539 | 3649 | ||
3540 | /* A fantasy */ |
3650 | /* A fantasy */ |
3541 | #define DP_DETECTED (1 << 2) |
3651 | #define DP_DETECTED (1 << 2) |
3542 | 3652 | ||
3543 | /* The aux channel provides a way to talk to the |
3653 | /* The aux channel provides a way to talk to the |
3544 | * signal sink for DDC etc. Max packet size supported |
3654 | * signal sink for DDC etc. Max packet size supported |
3545 | * is 20 bytes in each direction, hence the 5 fixed |
3655 | * is 20 bytes in each direction, hence the 5 fixed |
3546 | * data registers |
3656 | * data registers |
3547 | */ |
3657 | */ |
3548 | #define DPA_AUX_CH_CTL 0x64010 |
3658 | #define DPA_AUX_CH_CTL 0x64010 |
3549 | #define DPA_AUX_CH_DATA1 0x64014 |
3659 | #define DPA_AUX_CH_DATA1 0x64014 |
3550 | #define DPA_AUX_CH_DATA2 0x64018 |
3660 | #define DPA_AUX_CH_DATA2 0x64018 |
3551 | #define DPA_AUX_CH_DATA3 0x6401c |
3661 | #define DPA_AUX_CH_DATA3 0x6401c |
3552 | #define DPA_AUX_CH_DATA4 0x64020 |
3662 | #define DPA_AUX_CH_DATA4 0x64020 |
3553 | #define DPA_AUX_CH_DATA5 0x64024 |
3663 | #define DPA_AUX_CH_DATA5 0x64024 |
3554 | 3664 | ||
3555 | #define DPB_AUX_CH_CTL 0x64110 |
3665 | #define DPB_AUX_CH_CTL 0x64110 |
3556 | #define DPB_AUX_CH_DATA1 0x64114 |
3666 | #define DPB_AUX_CH_DATA1 0x64114 |
3557 | #define DPB_AUX_CH_DATA2 0x64118 |
3667 | #define DPB_AUX_CH_DATA2 0x64118 |
3558 | #define DPB_AUX_CH_DATA3 0x6411c |
3668 | #define DPB_AUX_CH_DATA3 0x6411c |
3559 | #define DPB_AUX_CH_DATA4 0x64120 |
3669 | #define DPB_AUX_CH_DATA4 0x64120 |
3560 | #define DPB_AUX_CH_DATA5 0x64124 |
3670 | #define DPB_AUX_CH_DATA5 0x64124 |
3561 | 3671 | ||
3562 | #define DPC_AUX_CH_CTL 0x64210 |
3672 | #define DPC_AUX_CH_CTL 0x64210 |
3563 | #define DPC_AUX_CH_DATA1 0x64214 |
3673 | #define DPC_AUX_CH_DATA1 0x64214 |
3564 | #define DPC_AUX_CH_DATA2 0x64218 |
3674 | #define DPC_AUX_CH_DATA2 0x64218 |
3565 | #define DPC_AUX_CH_DATA3 0x6421c |
3675 | #define DPC_AUX_CH_DATA3 0x6421c |
3566 | #define DPC_AUX_CH_DATA4 0x64220 |
3676 | #define DPC_AUX_CH_DATA4 0x64220 |
3567 | #define DPC_AUX_CH_DATA5 0x64224 |
3677 | #define DPC_AUX_CH_DATA5 0x64224 |
3568 | 3678 | ||
3569 | #define DPD_AUX_CH_CTL 0x64310 |
3679 | #define DPD_AUX_CH_CTL 0x64310 |
3570 | #define DPD_AUX_CH_DATA1 0x64314 |
3680 | #define DPD_AUX_CH_DATA1 0x64314 |
3571 | #define DPD_AUX_CH_DATA2 0x64318 |
3681 | #define DPD_AUX_CH_DATA2 0x64318 |
3572 | #define DPD_AUX_CH_DATA3 0x6431c |
3682 | #define DPD_AUX_CH_DATA3 0x6431c |
3573 | #define DPD_AUX_CH_DATA4 0x64320 |
3683 | #define DPD_AUX_CH_DATA4 0x64320 |
3574 | #define DPD_AUX_CH_DATA5 0x64324 |
3684 | #define DPD_AUX_CH_DATA5 0x64324 |
3575 | 3685 | ||
3576 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) |
3686 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) |
3577 | #define DP_AUX_CH_CTL_DONE (1 << 30) |
3687 | #define DP_AUX_CH_CTL_DONE (1 << 30) |
3578 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) |
3688 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) |
3579 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) |
3689 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) |
3580 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) |
3690 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) |
3581 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) |
3691 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) |
3582 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) |
3692 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) |
3583 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) |
3693 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) |
3584 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) |
3694 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) |
3585 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) |
3695 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) |
3586 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) |
3696 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) |
3587 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 |
3697 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 |
3588 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) |
3698 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) |
3589 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 |
3699 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 |
3590 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) |
3700 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) |
3591 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) |
3701 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) |
3592 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
3702 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
3593 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
3703 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
3594 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
3704 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
3595 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
3705 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
3596 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
3706 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
- | 3707 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
|
3597 | 3708 | ||
3598 | /* |
3709 | /* |
3599 | * Computing GMCH M and N values for the Display Port link |
3710 | * Computing GMCH M and N values for the Display Port link |
3600 | * |
3711 | * |
3601 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes |
3712 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes |
3602 | * |
3713 | * |
3603 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) |
3714 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) |
3604 | * |
3715 | * |
3605 | * The GMCH value is used internally |
3716 | * The GMCH value is used internally |
3606 | * |
3717 | * |
3607 | * bytes_per_pixel is the number of bytes coming out of the plane, |
3718 | * bytes_per_pixel is the number of bytes coming out of the plane, |
3608 | * which is after the LUTs, so we want the bytes for our color format. |
3719 | * which is after the LUTs, so we want the bytes for our color format. |
3609 | * For our current usage, this is always 3, one byte for R, G and B. |
3720 | * For our current usage, this is always 3, one byte for R, G and B. |
3610 | */ |
3721 | */ |
3611 | #define _PIPEA_DATA_M_G4X 0x70050 |
3722 | #define _PIPEA_DATA_M_G4X 0x70050 |
3612 | #define _PIPEB_DATA_M_G4X 0x71050 |
3723 | #define _PIPEB_DATA_M_G4X 0x71050 |
3613 | 3724 | ||
3614 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ |
3725 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ |
3615 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
3726 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
3616 | #define TU_SIZE_SHIFT 25 |
3727 | #define TU_SIZE_SHIFT 25 |
3617 | #define TU_SIZE_MASK (0x3f << 25) |
3728 | #define TU_SIZE_MASK (0x3f << 25) |
3618 | 3729 | ||
3619 | #define DATA_LINK_M_N_MASK (0xffffff) |
3730 | #define DATA_LINK_M_N_MASK (0xffffff) |
3620 | #define DATA_LINK_N_MAX (0x800000) |
3731 | #define DATA_LINK_N_MAX (0x800000) |
3621 | 3732 | ||
3622 | #define _PIPEA_DATA_N_G4X 0x70054 |
3733 | #define _PIPEA_DATA_N_G4X 0x70054 |
3623 | #define _PIPEB_DATA_N_G4X 0x71054 |
3734 | #define _PIPEB_DATA_N_G4X 0x71054 |
3624 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
3735 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
3625 | 3736 | ||
3626 | /* |
3737 | /* |
3627 | * Computing Link M and N values for the Display Port link |
3738 | * Computing Link M and N values for the Display Port link |
3628 | * |
3739 | * |
3629 | * Link M / N = pixel_clock / ls_clk |
3740 | * Link M / N = pixel_clock / ls_clk |
3630 | * |
3741 | * |
3631 | * (the DP spec calls pixel_clock the 'strm_clk') |
3742 | * (the DP spec calls pixel_clock the 'strm_clk') |
3632 | * |
3743 | * |
3633 | * The Link value is transmitted in the Main Stream |
3744 | * The Link value is transmitted in the Main Stream |
3634 | * Attributes and VB-ID. |
3745 | * Attributes and VB-ID. |
3635 | */ |
3746 | */ |
3636 | 3747 | ||
3637 | #define _PIPEA_LINK_M_G4X 0x70060 |
3748 | #define _PIPEA_LINK_M_G4X 0x70060 |
3638 | #define _PIPEB_LINK_M_G4X 0x71060 |
3749 | #define _PIPEB_LINK_M_G4X 0x71060 |
3639 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
3750 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
3640 | 3751 | ||
3641 | #define _PIPEA_LINK_N_G4X 0x70064 |
3752 | #define _PIPEA_LINK_N_G4X 0x70064 |
3642 | #define _PIPEB_LINK_N_G4X 0x71064 |
3753 | #define _PIPEB_LINK_N_G4X 0x71064 |
3643 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
3754 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
3644 | 3755 | ||
3645 | #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
3756 | #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
3646 | #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) |
3757 | #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) |
3647 | #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) |
3758 | #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) |
3648 | #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) |
3759 | #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) |
3649 | 3760 | ||
3650 | /* Display & cursor control */ |
3761 | /* Display & cursor control */ |
3651 | 3762 | ||
3652 | /* Pipe A */ |
3763 | /* Pipe A */ |
3653 | #define _PIPEADSL 0x70000 |
3764 | #define _PIPEADSL 0x70000 |
3654 | #define DSL_LINEMASK_GEN2 0x00000fff |
3765 | #define DSL_LINEMASK_GEN2 0x00000fff |
3655 | #define DSL_LINEMASK_GEN3 0x00001fff |
3766 | #define DSL_LINEMASK_GEN3 0x00001fff |
3656 | #define _PIPEACONF 0x70008 |
3767 | #define _PIPEACONF 0x70008 |
3657 | #define PIPECONF_ENABLE (1<<31) |
3768 | #define PIPECONF_ENABLE (1<<31) |
3658 | #define PIPECONF_DISABLE 0 |
3769 | #define PIPECONF_DISABLE 0 |
3659 | #define PIPECONF_DOUBLE_WIDE (1<<30) |
3770 | #define PIPECONF_DOUBLE_WIDE (1<<30) |
3660 | #define I965_PIPECONF_ACTIVE (1<<30) |
3771 | #define I965_PIPECONF_ACTIVE (1<<30) |
3661 | #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ |
3772 | #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ |
3662 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
3773 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
3663 | #define PIPECONF_SINGLE_WIDE 0 |
3774 | #define PIPECONF_SINGLE_WIDE 0 |
3664 | #define PIPECONF_PIPE_UNLOCKED 0 |
3775 | #define PIPECONF_PIPE_UNLOCKED 0 |
3665 | #define PIPECONF_PIPE_LOCKED (1<<25) |
3776 | #define PIPECONF_PIPE_LOCKED (1<<25) |
3666 | #define PIPECONF_PALETTE 0 |
3777 | #define PIPECONF_PALETTE 0 |
3667 | #define PIPECONF_GAMMA (1<<24) |
3778 | #define PIPECONF_GAMMA (1<<24) |
3668 | #define PIPECONF_FORCE_BORDER (1<<25) |
3779 | #define PIPECONF_FORCE_BORDER (1<<25) |
3669 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
3780 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
3670 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
3781 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
3671 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
3782 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
3672 | * fitting must be disabled on pre-ilk for interlaced. */ |
3783 | * fitting must be disabled on pre-ilk for interlaced. */ |
3673 | #define PIPECONF_PROGRESSIVE (0 << 21) |
3784 | #define PIPECONF_PROGRESSIVE (0 << 21) |
3674 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ |
3785 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ |
3675 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ |
3786 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ |
3676 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
3787 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
3677 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ |
3788 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ |
3678 | /* Ironlake and later have a complete new set of values for interlaced. PFIT |
3789 | /* Ironlake and later have a complete new set of values for interlaced. PFIT |
3679 | * means panel fitter required, PF means progressive fetch, DBL means power |
3790 | * means panel fitter required, PF means progressive fetch, DBL means power |
3680 | * saving pixel doubling. */ |
3791 | * saving pixel doubling. */ |
3681 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) |
3792 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) |
3682 | #define PIPECONF_INTERLACED_ILK (3 << 21) |
3793 | #define PIPECONF_INTERLACED_ILK (3 << 21) |
3683 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
3794 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
3684 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
3795 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
3685 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
3796 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
3686 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
3797 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
3687 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
3798 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
3688 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
3799 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
3689 | #define PIPECONF_BPC_MASK (0x7 << 5) |
3800 | #define PIPECONF_BPC_MASK (0x7 << 5) |
3690 | #define PIPECONF_8BPC (0<<5) |
3801 | #define PIPECONF_8BPC (0<<5) |
3691 | #define PIPECONF_10BPC (1<<5) |
3802 | #define PIPECONF_10BPC (1<<5) |
3692 | #define PIPECONF_6BPC (2<<5) |
3803 | #define PIPECONF_6BPC (2<<5) |
3693 | #define PIPECONF_12BPC (3<<5) |
3804 | #define PIPECONF_12BPC (3<<5) |
3694 | #define PIPECONF_DITHER_EN (1<<4) |
3805 | #define PIPECONF_DITHER_EN (1<<4) |
3695 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) |
3806 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) |
3696 | #define PIPECONF_DITHER_TYPE_SP (0<<2) |
3807 | #define PIPECONF_DITHER_TYPE_SP (0<<2) |
3697 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) |
3808 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) |
3698 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) |
3809 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) |
3699 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
3810 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
3700 | #define _PIPEASTAT 0x70024 |
3811 | #define _PIPEASTAT 0x70024 |
3701 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
3812 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
3702 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) |
3813 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) |
3703 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
3814 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
3704 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
3815 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
3705 | #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) |
3816 | #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) |
3706 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
3817 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
3707 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
3818 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
3708 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
3819 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
3709 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
3820 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
3710 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
3821 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
3711 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
3822 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
3712 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) |
3823 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) |
3713 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
3824 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
3714 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
3825 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
3715 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
3826 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
3716 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) |
3827 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) |
3717 | #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) |
3828 | #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) |
3718 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
3829 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
3719 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
3830 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
3720 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) |
3831 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) |
3721 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
3832 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
3722 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
3833 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
3723 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
3834 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
3724 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) |
3835 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) |
3725 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) |
3836 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) |
3726 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
3837 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
3727 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
3838 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
3728 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) |
3839 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) |
3729 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
3840 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
3730 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) |
3841 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) |
3731 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
3842 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
3732 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
3843 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
3733 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
3844 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
3734 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) |
3845 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) |
3735 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
- | |
3736 | #define PIPE_A_PSR_STATUS_VLV (1UL<<6) |
3846 | #define PIPE_A_PSR_STATUS_VLV (1UL<<6) |
3737 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
3847 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
3738 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
3848 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
3739 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
3849 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
3740 | #define PIPE_B_PSR_STATUS_VLV (1UL<<3) |
3850 | #define PIPE_B_PSR_STATUS_VLV (1UL<<3) |
3741 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) |
3851 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) |
3742 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
3852 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
3743 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
3853 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
3744 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) |
3854 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) |
3745 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
3855 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
3746 | #define PIPE_HBLANK_INT_STATUS (1UL<<0) |
3856 | #define PIPE_HBLANK_INT_STATUS (1UL<<0) |
3747 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
3857 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
3748 | 3858 | ||
3749 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
3859 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
3750 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff |
3860 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff |
3751 | 3861 | ||
3752 | #define PIPE_A_OFFSET 0x70000 |
3862 | #define PIPE_A_OFFSET 0x70000 |
3753 | #define PIPE_B_OFFSET 0x71000 |
3863 | #define PIPE_B_OFFSET 0x71000 |
3754 | #define PIPE_C_OFFSET 0x72000 |
3864 | #define PIPE_C_OFFSET 0x72000 |
3755 | #define CHV_PIPE_C_OFFSET 0x74000 |
3865 | #define CHV_PIPE_C_OFFSET 0x74000 |
3756 | /* |
3866 | /* |
3757 | * There's actually no pipe EDP. Some pipe registers have |
3867 | * There's actually no pipe EDP. Some pipe registers have |
3758 | * simply shifted from the pipe to the transcoder, while |
3868 | * simply shifted from the pipe to the transcoder, while |
3759 | * keeping their original offset. Thus we need PIPE_EDP_OFFSET |
3869 | * keeping their original offset. Thus we need PIPE_EDP_OFFSET |
3760 | * to access such registers in transcoder EDP. |
3870 | * to access such registers in transcoder EDP. |
3761 | */ |
3871 | */ |
3762 | #define PIPE_EDP_OFFSET 0x7f000 |
3872 | #define PIPE_EDP_OFFSET 0x7f000 |
3763 | 3873 | ||
3764 | #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ |
3874 | #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ |
3765 | dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ |
3875 | dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ |
3766 | dev_priv->info.display_mmio_offset) |
3876 | dev_priv->info.display_mmio_offset) |
3767 | 3877 | ||
3768 | #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) |
3878 | #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) |
3769 | #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) |
3879 | #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) |
3770 | #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) |
3880 | #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) |
3771 | #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) |
3881 | #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) |
3772 | #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) |
3882 | #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) |
3773 | 3883 | ||
3774 | #define _PIPE_MISC_A 0x70030 |
3884 | #define _PIPE_MISC_A 0x70030 |
3775 | #define _PIPE_MISC_B 0x71030 |
3885 | #define _PIPE_MISC_B 0x71030 |
3776 | #define PIPEMISC_DITHER_BPC_MASK (7<<5) |
3886 | #define PIPEMISC_DITHER_BPC_MASK (7<<5) |
3777 | #define PIPEMISC_DITHER_8_BPC (0<<5) |
3887 | #define PIPEMISC_DITHER_8_BPC (0<<5) |
3778 | #define PIPEMISC_DITHER_10_BPC (1<<5) |
3888 | #define PIPEMISC_DITHER_10_BPC (1<<5) |
3779 | #define PIPEMISC_DITHER_6_BPC (2<<5) |
3889 | #define PIPEMISC_DITHER_6_BPC (2<<5) |
3780 | #define PIPEMISC_DITHER_12_BPC (3<<5) |
3890 | #define PIPEMISC_DITHER_12_BPC (3<<5) |
3781 | #define PIPEMISC_DITHER_ENABLE (1<<4) |
3891 | #define PIPEMISC_DITHER_ENABLE (1<<4) |
3782 | #define PIPEMISC_DITHER_TYPE_MASK (3<<2) |
3892 | #define PIPEMISC_DITHER_TYPE_MASK (3<<2) |
3783 | #define PIPEMISC_DITHER_TYPE_SP (0<<2) |
3893 | #define PIPEMISC_DITHER_TYPE_SP (0<<2) |
3784 | #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) |
3894 | #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) |
3785 | 3895 | ||
3786 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
3896 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
3787 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
3897 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
3788 | #define PIPEB_HLINE_INT_EN (1<<28) |
3898 | #define PIPEB_HLINE_INT_EN (1<<28) |
3789 | #define PIPEB_VBLANK_INT_EN (1<<27) |
3899 | #define PIPEB_VBLANK_INT_EN (1<<27) |
3790 | #define SPRITED_FLIP_DONE_INT_EN (1<<26) |
3900 | #define SPRITED_FLIP_DONE_INT_EN (1<<26) |
3791 | #define SPRITEC_FLIP_DONE_INT_EN (1<<25) |
3901 | #define SPRITEC_FLIP_DONE_INT_EN (1<<25) |
3792 | #define PLANEB_FLIP_DONE_INT_EN (1<<24) |
3902 | #define PLANEB_FLIP_DONE_INT_EN (1<<24) |
3793 | #define PIPE_PSR_INT_EN (1<<22) |
3903 | #define PIPE_PSR_INT_EN (1<<22) |
3794 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
3904 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
3795 | #define PIPEA_HLINE_INT_EN (1<<20) |
3905 | #define PIPEA_HLINE_INT_EN (1<<20) |
3796 | #define PIPEA_VBLANK_INT_EN (1<<19) |
3906 | #define PIPEA_VBLANK_INT_EN (1<<19) |
3797 | #define SPRITEB_FLIP_DONE_INT_EN (1<<18) |
3907 | #define SPRITEB_FLIP_DONE_INT_EN (1<<18) |
3798 | #define SPRITEA_FLIP_DONE_INT_EN (1<<17) |
3908 | #define SPRITEA_FLIP_DONE_INT_EN (1<<17) |
3799 | #define PLANEA_FLIPDONE_INT_EN (1<<16) |
3909 | #define PLANEA_FLIPDONE_INT_EN (1<<16) |
3800 | #define PIPEC_LINE_COMPARE_INT_EN (1<<13) |
3910 | #define PIPEC_LINE_COMPARE_INT_EN (1<<13) |
3801 | #define PIPEC_HLINE_INT_EN (1<<12) |
3911 | #define PIPEC_HLINE_INT_EN (1<<12) |
3802 | #define PIPEC_VBLANK_INT_EN (1<<11) |
3912 | #define PIPEC_VBLANK_INT_EN (1<<11) |
3803 | #define SPRITEF_FLIPDONE_INT_EN (1<<10) |
3913 | #define SPRITEF_FLIPDONE_INT_EN (1<<10) |
3804 | #define SPRITEE_FLIPDONE_INT_EN (1<<9) |
3914 | #define SPRITEE_FLIPDONE_INT_EN (1<<9) |
3805 | #define PLANEC_FLIPDONE_INT_EN (1<<8) |
3915 | #define PLANEC_FLIPDONE_INT_EN (1<<8) |
3806 | 3916 | ||
3807 | #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
3917 | #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
3808 | #define SPRITEF_INVALID_GTT_INT_EN (1<<27) |
3918 | #define SPRITEF_INVALID_GTT_INT_EN (1<<27) |
3809 | #define SPRITEE_INVALID_GTT_INT_EN (1<<26) |
3919 | #define SPRITEE_INVALID_GTT_INT_EN (1<<26) |
3810 | #define PLANEC_INVALID_GTT_INT_EN (1<<25) |
3920 | #define PLANEC_INVALID_GTT_INT_EN (1<<25) |
3811 | #define CURSORC_INVALID_GTT_INT_EN (1<<24) |
3921 | #define CURSORC_INVALID_GTT_INT_EN (1<<24) |
3812 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) |
3922 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) |
3813 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) |
3923 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) |
3814 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) |
3924 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) |
3815 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) |
3925 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) |
3816 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) |
3926 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) |
3817 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) |
3927 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) |
3818 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) |
3928 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) |
3819 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) |
3929 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) |
3820 | #define DPINVGTT_EN_MASK 0xff0000 |
3930 | #define DPINVGTT_EN_MASK 0xff0000 |
3821 | #define DPINVGTT_EN_MASK_CHV 0xfff0000 |
3931 | #define DPINVGTT_EN_MASK_CHV 0xfff0000 |
3822 | #define SPRITEF_INVALID_GTT_STATUS (1<<11) |
3932 | #define SPRITEF_INVALID_GTT_STATUS (1<<11) |
3823 | #define SPRITEE_INVALID_GTT_STATUS (1<<10) |
3933 | #define SPRITEE_INVALID_GTT_STATUS (1<<10) |
3824 | #define PLANEC_INVALID_GTT_STATUS (1<<9) |
3934 | #define PLANEC_INVALID_GTT_STATUS (1<<9) |
3825 | #define CURSORC_INVALID_GTT_STATUS (1<<8) |
3935 | #define CURSORC_INVALID_GTT_STATUS (1<<8) |
3826 | #define CURSORB_INVALID_GTT_STATUS (1<<7) |
3936 | #define CURSORB_INVALID_GTT_STATUS (1<<7) |
3827 | #define CURSORA_INVALID_GTT_STATUS (1<<6) |
3937 | #define CURSORA_INVALID_GTT_STATUS (1<<6) |
3828 | #define SPRITED_INVALID_GTT_STATUS (1<<5) |
3938 | #define SPRITED_INVALID_GTT_STATUS (1<<5) |
3829 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) |
3939 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) |
3830 | #define PLANEB_INVALID_GTT_STATUS (1<<3) |
3940 | #define PLANEB_INVALID_GTT_STATUS (1<<3) |
3831 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) |
3941 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) |
3832 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) |
3942 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) |
3833 | #define PLANEA_INVALID_GTT_STATUS (1<<0) |
3943 | #define PLANEA_INVALID_GTT_STATUS (1<<0) |
3834 | #define DPINVGTT_STATUS_MASK 0xff |
3944 | #define DPINVGTT_STATUS_MASK 0xff |
3835 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
3945 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
3836 | 3946 | ||
3837 | #define DSPARB 0x70030 |
3947 | #define DSPARB 0x70030 |
3838 | #define DSPARB_CSTART_MASK (0x7f << 7) |
3948 | #define DSPARB_CSTART_MASK (0x7f << 7) |
3839 | #define DSPARB_CSTART_SHIFT 7 |
3949 | #define DSPARB_CSTART_SHIFT 7 |
3840 | #define DSPARB_BSTART_MASK (0x7f) |
3950 | #define DSPARB_BSTART_MASK (0x7f) |
3841 | #define DSPARB_BSTART_SHIFT 0 |
3951 | #define DSPARB_BSTART_SHIFT 0 |
3842 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
3952 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
3843 | #define DSPARB_AEND_SHIFT 0 |
3953 | #define DSPARB_AEND_SHIFT 0 |
- | 3954 | ||
3844 | 3955 | /* pnv/gen4/g4x/vlv/chv */ |
|
3845 | #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
3956 | #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
3846 | #define DSPFW_SR_SHIFT 23 |
3957 | #define DSPFW_SR_SHIFT 23 |
3847 | #define DSPFW_SR_MASK (0x1ff<<23) |
3958 | #define DSPFW_SR_MASK (0x1ff<<23) |
3848 | #define DSPFW_CURSORB_SHIFT 16 |
3959 | #define DSPFW_CURSORB_SHIFT 16 |
3849 | #define DSPFW_CURSORB_MASK (0x3f<<16) |
3960 | #define DSPFW_CURSORB_MASK (0x3f<<16) |
3850 | #define DSPFW_PLANEB_SHIFT 8 |
3961 | #define DSPFW_PLANEB_SHIFT 8 |
3851 | #define DSPFW_PLANEB_MASK (0x7f<<8) |
3962 | #define DSPFW_PLANEB_MASK (0x7f<<8) |
- | 3963 | #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ |
|
- | 3964 | #define DSPFW_PLANEA_SHIFT 0 |
|
3852 | #define DSPFW_PLANEA_MASK (0x7f) |
3965 | #define DSPFW_PLANEA_MASK (0x7f<<0) |
- | 3966 | #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ |
|
3853 | #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) |
3967 | #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) |
- | 3968 | #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ |
|
- | 3969 | #define DSPFW_FBC_SR_SHIFT 28 |
|
- | 3970 | #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ |
|
- | 3971 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 |
|
- | 3972 | #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ |
|
3854 | #define DSPFW_CURSORA_MASK 0x00003f00 |
3973 | #define DSPFW_SPRITEB_SHIFT (16) |
- | 3974 | #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ |
|
- | 3975 | #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ |
|
3855 | #define DSPFW_CURSORA_SHIFT 8 |
3976 | #define DSPFW_CURSORA_SHIFT 8 |
- | 3977 | #define DSPFW_CURSORA_MASK (0x3f<<8) |
|
3856 | #define DSPFW_PLANEC_MASK (0x7f) |
3978 | #define DSPFW_PLANEC_SHIFT_OLD 0 |
- | 3979 | #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ |
|
- | 3980 | #define DSPFW_SPRITEA_SHIFT 0 |
|
- | 3981 | #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ |
|
- | 3982 | #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ |
|
3857 | #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
3983 | #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
3858 | #define DSPFW_HPLL_SR_EN (1<<31) |
3984 | #define DSPFW_HPLL_SR_EN (1<<31) |
3859 | #define DSPFW_CURSOR_SR_SHIFT 24 |
- | |
3860 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
3985 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
- | 3986 | #define DSPFW_CURSOR_SR_SHIFT 24 |
|
3861 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
3987 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
3862 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
3988 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
3863 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
3989 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
- | 3990 | #define DSPFW_HPLL_SR_SHIFT 0 |
|
3864 | #define DSPFW_HPLL_SR_MASK (0x1ff) |
3991 | #define DSPFW_HPLL_SR_MASK (0x1ff<<0) |
- | 3992 | ||
- | 3993 | /* vlv/chv */ |
|
3865 | #define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070) |
3994 | #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) |
- | 3995 | #define DSPFW_SPRITEB_WM1_SHIFT 16 |
|
- | 3996 | #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) |
|
- | 3997 | #define DSPFW_CURSORA_WM1_SHIFT 8 |
|
- | 3998 | #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) |
|
- | 3999 | #define DSPFW_SPRITEA_WM1_SHIFT 0 |
|
- | 4000 | #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) |
|
- | 4001 | #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) |
|
- | 4002 | #define DSPFW_PLANEB_WM1_SHIFT 24 |
|
- | 4003 | #define DSPFW_PLANEB_WM1_MASK (0xff<<24) |
|
- | 4004 | #define DSPFW_PLANEA_WM1_SHIFT 16 |
|
- | 4005 | #define DSPFW_PLANEA_WM1_MASK (0xff<<16) |
|
- | 4006 | #define DSPFW_CURSORB_WM1_SHIFT 8 |
|
- | 4007 | #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) |
|
- | 4008 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 |
|
- | 4009 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) |
|
- | 4010 | #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) |
|
- | 4011 | #define DSPFW_SR_WM1_SHIFT 0 |
|
- | 4012 | #define DSPFW_SR_WM1_MASK (0x1ff<<0) |
|
3866 | #define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c) |
4013 | #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) |
- | 4014 | #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
|
- | 4015 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
|
- | 4016 | #define DSPFW_SPRITED_WM1_MASK (0xff<<24) |
|
- | 4017 | #define DSPFW_SPRITED_SHIFT 16 |
|
- | 4018 | #define DSPFW_SPRITED_MASK (0xff<<16) |
|
- | 4019 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
|
- | 4020 | #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) |
|
- | 4021 | #define DSPFW_SPRITEC_SHIFT 0 |
|
- | 4022 | #define DSPFW_SPRITEC_MASK (0xff<<0) |
|
- | 4023 | #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) |
|
- | 4024 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
|
- | 4025 | #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) |
|
- | 4026 | #define DSPFW_SPRITEF_SHIFT 16 |
|
- | 4027 | #define DSPFW_SPRITEF_MASK (0xff<<16) |
|
- | 4028 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
|
- | 4029 | #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) |
|
- | 4030 | #define DSPFW_SPRITEE_SHIFT 0 |
|
- | 4031 | #define DSPFW_SPRITEE_MASK (0xff<<0) |
|
- | 4032 | #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
|
- | 4033 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
|
- | 4034 | #define DSPFW_PLANEC_WM1_MASK (0xff<<24) |
|
- | 4035 | #define DSPFW_PLANEC_SHIFT 16 |
|
- | 4036 | #define DSPFW_PLANEC_MASK (0xff<<16) |
|
- | 4037 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
|
- | 4038 | #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) |
|
- | 4039 | #define DSPFW_CURSORC_SHIFT 0 |
|
- | 4040 | #define DSPFW_CURSORC_MASK (0x3f<<0) |
|
- | 4041 | ||
- | 4042 | /* vlv/chv high order bits */ |
|
- | 4043 | #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) |
|
- | 4044 | #define DSPFW_SR_HI_SHIFT 24 |
|
- | 4045 | #define DSPFW_SR_HI_MASK (1<<24) |
|
- | 4046 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
|
- | 4047 | #define DSPFW_SPRITEF_HI_MASK (1<<23) |
|
- | 4048 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
|
- | 4049 | #define DSPFW_SPRITEE_HI_MASK (1<<22) |
|
- | 4050 | #define DSPFW_PLANEC_HI_SHIFT 21 |
|
- | 4051 | #define DSPFW_PLANEC_HI_MASK (1<<21) |
|
- | 4052 | #define DSPFW_SPRITED_HI_SHIFT 20 |
|
- | 4053 | #define DSPFW_SPRITED_HI_MASK (1<<20) |
|
- | 4054 | #define DSPFW_SPRITEC_HI_SHIFT 16 |
|
- | 4055 | #define DSPFW_SPRITEC_HI_MASK (1<<16) |
|
- | 4056 | #define DSPFW_PLANEB_HI_SHIFT 12 |
|
- | 4057 | #define DSPFW_PLANEB_HI_MASK (1<<12) |
|
- | 4058 | #define DSPFW_SPRITEB_HI_SHIFT 8 |
|
- | 4059 | #define DSPFW_SPRITEB_HI_MASK (1<<8) |
|
- | 4060 | #define DSPFW_SPRITEA_HI_SHIFT 4 |
|
- | 4061 | #define DSPFW_SPRITEA_HI_MASK (1<<4) |
|
- | 4062 | #define DSPFW_PLANEA_HI_SHIFT 0 |
|
- | 4063 | #define DSPFW_PLANEA_HI_MASK (1<<0) |
|
- | 4064 | #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) |
|
- | 4065 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
|
- | 4066 | #define DSPFW_SR_WM1_HI_MASK (1<<24) |
|
- | 4067 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
|
- | 4068 | #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) |
|
- | 4069 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
|
- | 4070 | #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) |
|
- | 4071 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
|
- | 4072 | #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) |
|
- | 4073 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 |
|
- | 4074 | #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) |
|
- | 4075 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 |
|
- | 4076 | #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) |
|
- | 4077 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 |
|
- | 4078 | #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) |
|
- | 4079 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 |
|
- | 4080 | #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) |
|
- | 4081 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 |
|
- | 4082 | #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) |
|
- | 4083 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
|
- | 4084 | #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) |
|
3867 | 4085 | ||
- | 4086 | /* drain latency register values*/ |
|
3868 | /* drain latency register values*/ |
4087 | #define DRAIN_LATENCY_PRECISION_16 16 |
3869 | #define DRAIN_LATENCY_PRECISION_32 32 |
4088 | #define DRAIN_LATENCY_PRECISION_32 32 |
3870 | #define DRAIN_LATENCY_PRECISION_64 64 |
4089 | #define DRAIN_LATENCY_PRECISION_64 64 |
3871 | #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) |
4090 | #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
3872 | #define DDL_CURSORA_PRECISION_64 (1<<31) |
- | |
3873 | #define DDL_CURSORA_PRECISION_32 (0<<31) |
- | |
3874 | #define DDL_CURSORA_SHIFT 24 |
- | |
3875 | #define DDL_SPRITEB_PRECISION_64 (1<<23) |
- | |
3876 | #define DDL_SPRITEB_PRECISION_32 (0<<23) |
- | |
3877 | #define DDL_SPRITEB_SHIFT 16 |
- | |
3878 | #define DDL_SPRITEA_PRECISION_64 (1<<15) |
- | |
3879 | #define DDL_SPRITEA_PRECISION_32 (0<<15) |
- | |
3880 | #define DDL_SPRITEA_SHIFT 8 |
- | |
3881 | #define DDL_PLANEA_PRECISION_64 (1<<7) |
- | |
3882 | #define DDL_PLANEA_PRECISION_32 (0<<7) |
- | |
3883 | #define DDL_PLANEA_SHIFT 0 |
- | |
3884 | - | ||
3885 | #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) |
- | |
3886 | #define DDL_CURSORB_PRECISION_64 (1<<31) |
4091 | #define DDL_CURSOR_PRECISION_HIGH (1<<31) |
3887 | #define DDL_CURSORB_PRECISION_32 (0<<31) |
4092 | #define DDL_CURSOR_PRECISION_LOW (0<<31) |
3888 | #define DDL_CURSORB_SHIFT 24 |
- | |
3889 | #define DDL_SPRITED_PRECISION_64 (1<<23) |
- | |
3890 | #define DDL_SPRITED_PRECISION_32 (0<<23) |
- | |
3891 | #define DDL_SPRITED_SHIFT 16 |
4093 | #define DDL_CURSOR_SHIFT 24 |
3892 | #define DDL_SPRITEC_PRECISION_64 (1<<15) |
4094 | #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite))) |
3893 | #define DDL_SPRITEC_PRECISION_32 (0<<15) |
4095 | #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite))) |
3894 | #define DDL_SPRITEC_SHIFT 8 |
4096 | #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) |
3895 | #define DDL_PLANEB_PRECISION_64 (1<<7) |
4097 | #define DDL_PLANE_PRECISION_HIGH (1<<7) |
3896 | #define DDL_PLANEB_PRECISION_32 (0<<7) |
4098 | #define DDL_PLANE_PRECISION_LOW (0<<7) |
3897 | #define DDL_PLANEB_SHIFT 0 |
- | |
3898 | - | ||
3899 | #define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058) |
- | |
3900 | #define DDL_CURSORC_PRECISION_64 (1<<31) |
- | |
3901 | #define DDL_CURSORC_PRECISION_32 (0<<31) |
- | |
3902 | #define DDL_CURSORC_SHIFT 24 |
- | |
3903 | #define DDL_SPRITEF_PRECISION_64 (1<<23) |
- | |
3904 | #define DDL_SPRITEF_PRECISION_32 (0<<23) |
- | |
3905 | #define DDL_SPRITEF_SHIFT 16 |
- | |
3906 | #define DDL_SPRITEE_PRECISION_64 (1<<15) |
- | |
3907 | #define DDL_SPRITEE_PRECISION_32 (0<<15) |
- | |
3908 | #define DDL_SPRITEE_SHIFT 8 |
- | |
3909 | #define DDL_PLANEC_PRECISION_64 (1<<7) |
- | |
3910 | #define DDL_PLANEC_PRECISION_32 (0<<7) |
4099 | #define DDL_PLANE_SHIFT 0 |
3911 | #define DDL_PLANEC_SHIFT 0 |
4100 | #define DRAIN_LATENCY_MASK 0x7f |
3912 | 4101 | ||
3913 | /* FIFO watermark sizes etc */ |
4102 | /* FIFO watermark sizes etc */ |
3914 | #define G4X_FIFO_LINE_SIZE 64 |
4103 | #define G4X_FIFO_LINE_SIZE 64 |
3915 | #define I915_FIFO_LINE_SIZE 64 |
4104 | #define I915_FIFO_LINE_SIZE 64 |
3916 | #define I830_FIFO_LINE_SIZE 32 |
4105 | #define I830_FIFO_LINE_SIZE 32 |
3917 | 4106 | ||
3918 | #define VALLEYVIEW_FIFO_SIZE 255 |
4107 | #define VALLEYVIEW_FIFO_SIZE 255 |
3919 | #define G4X_FIFO_SIZE 127 |
4108 | #define G4X_FIFO_SIZE 127 |
3920 | #define I965_FIFO_SIZE 512 |
4109 | #define I965_FIFO_SIZE 512 |
3921 | #define I945_FIFO_SIZE 127 |
4110 | #define I945_FIFO_SIZE 127 |
3922 | #define I915_FIFO_SIZE 95 |
4111 | #define I915_FIFO_SIZE 95 |
3923 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
4112 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
3924 | #define I830_FIFO_SIZE 95 |
4113 | #define I830_FIFO_SIZE 95 |
3925 | 4114 | ||
3926 | #define VALLEYVIEW_MAX_WM 0xff |
4115 | #define VALLEYVIEW_MAX_WM 0xff |
3927 | #define G4X_MAX_WM 0x3f |
4116 | #define G4X_MAX_WM 0x3f |
3928 | #define I915_MAX_WM 0x3f |
4117 | #define I915_MAX_WM 0x3f |
3929 | 4118 | ||
3930 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
4119 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
3931 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
4120 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
3932 | #define PINEVIEW_MAX_WM 0x1ff |
4121 | #define PINEVIEW_MAX_WM 0x1ff |
3933 | #define PINEVIEW_DFT_WM 0x3f |
4122 | #define PINEVIEW_DFT_WM 0x3f |
3934 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
4123 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
3935 | #define PINEVIEW_GUARD_WM 10 |
4124 | #define PINEVIEW_GUARD_WM 10 |
3936 | #define PINEVIEW_CURSOR_FIFO 64 |
4125 | #define PINEVIEW_CURSOR_FIFO 64 |
3937 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
4126 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
3938 | #define PINEVIEW_CURSOR_DFT_WM 0 |
4127 | #define PINEVIEW_CURSOR_DFT_WM 0 |
3939 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
4128 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
3940 | 4129 | ||
3941 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
4130 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
3942 | #define I965_CURSOR_FIFO 64 |
4131 | #define I965_CURSOR_FIFO 64 |
3943 | #define I965_CURSOR_MAX_WM 32 |
4132 | #define I965_CURSOR_MAX_WM 32 |
3944 | #define I965_CURSOR_DFT_WM 8 |
4133 | #define I965_CURSOR_DFT_WM 8 |
- | 4134 | ||
- | 4135 | /* Watermark register definitions for SKL */ |
|
- | 4136 | #define CUR_WM_A_0 0x70140 |
|
- | 4137 | #define CUR_WM_B_0 0x71140 |
|
- | 4138 | #define PLANE_WM_1_A_0 0x70240 |
|
- | 4139 | #define PLANE_WM_1_B_0 0x71240 |
|
- | 4140 | #define PLANE_WM_2_A_0 0x70340 |
|
- | 4141 | #define PLANE_WM_2_B_0 0x71340 |
|
- | 4142 | #define PLANE_WM_TRANS_1_A_0 0x70268 |
|
- | 4143 | #define PLANE_WM_TRANS_1_B_0 0x71268 |
|
- | 4144 | #define PLANE_WM_TRANS_2_A_0 0x70368 |
|
- | 4145 | #define PLANE_WM_TRANS_2_B_0 0x71368 |
|
- | 4146 | #define CUR_WM_TRANS_A_0 0x70168 |
|
- | 4147 | #define CUR_WM_TRANS_B_0 0x71168 |
|
- | 4148 | #define PLANE_WM_EN (1 << 31) |
|
- | 4149 | #define PLANE_WM_LINES_SHIFT 14 |
|
- | 4150 | #define PLANE_WM_LINES_MASK 0x1f |
|
- | 4151 | #define PLANE_WM_BLOCKS_MASK 0x3ff |
|
- | 4152 | ||
- | 4153 | #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0) |
|
- | 4154 | #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level))) |
|
- | 4155 | #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0) |
|
- | 4156 | ||
- | 4157 | #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0) |
|
- | 4158 | #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0) |
|
- | 4159 | #define _PLANE_WM_BASE(pipe, plane) \ |
|
- | 4160 | _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) |
|
- | 4161 | #define PLANE_WM(pipe, plane, level) \ |
|
- | 4162 | (_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) |
|
- | 4163 | #define _PLANE_WM_TRANS_1(pipe) \ |
|
- | 4164 | _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0) |
|
- | 4165 | #define _PLANE_WM_TRANS_2(pipe) \ |
|
- | 4166 | _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0) |
|
- | 4167 | #define PLANE_WM_TRANS(pipe, plane) \ |
|
- | 4168 | _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)) |
|
3945 | 4169 | ||
3946 | /* define the Watermark register on Ironlake */ |
4170 | /* define the Watermark register on Ironlake */ |
3947 | #define WM0_PIPEA_ILK 0x45100 |
4171 | #define WM0_PIPEA_ILK 0x45100 |
3948 | #define WM0_PIPE_PLANE_MASK (0xffff<<16) |
4172 | #define WM0_PIPE_PLANE_MASK (0xffff<<16) |
3949 | #define WM0_PIPE_PLANE_SHIFT 16 |
4173 | #define WM0_PIPE_PLANE_SHIFT 16 |
3950 | #define WM0_PIPE_SPRITE_MASK (0xff<<8) |
4174 | #define WM0_PIPE_SPRITE_MASK (0xff<<8) |
3951 | #define WM0_PIPE_SPRITE_SHIFT 8 |
4175 | #define WM0_PIPE_SPRITE_SHIFT 8 |
3952 | #define WM0_PIPE_CURSOR_MASK (0xff) |
4176 | #define WM0_PIPE_CURSOR_MASK (0xff) |
3953 | 4177 | ||
3954 | #define WM0_PIPEB_ILK 0x45104 |
4178 | #define WM0_PIPEB_ILK 0x45104 |
3955 | #define WM0_PIPEC_IVB 0x45200 |
4179 | #define WM0_PIPEC_IVB 0x45200 |
3956 | #define WM1_LP_ILK 0x45108 |
4180 | #define WM1_LP_ILK 0x45108 |
3957 | #define WM1_LP_SR_EN (1<<31) |
4181 | #define WM1_LP_SR_EN (1<<31) |
3958 | #define WM1_LP_LATENCY_SHIFT 24 |
4182 | #define WM1_LP_LATENCY_SHIFT 24 |
3959 | #define WM1_LP_LATENCY_MASK (0x7f<<24) |
4183 | #define WM1_LP_LATENCY_MASK (0x7f<<24) |
3960 | #define WM1_LP_FBC_MASK (0xf<<20) |
4184 | #define WM1_LP_FBC_MASK (0xf<<20) |
3961 | #define WM1_LP_FBC_SHIFT 20 |
4185 | #define WM1_LP_FBC_SHIFT 20 |
3962 | #define WM1_LP_FBC_SHIFT_BDW 19 |
4186 | #define WM1_LP_FBC_SHIFT_BDW 19 |
3963 | #define WM1_LP_SR_MASK (0x7ff<<8) |
4187 | #define WM1_LP_SR_MASK (0x7ff<<8) |
3964 | #define WM1_LP_SR_SHIFT 8 |
4188 | #define WM1_LP_SR_SHIFT 8 |
3965 | #define WM1_LP_CURSOR_MASK (0xff) |
4189 | #define WM1_LP_CURSOR_MASK (0xff) |
3966 | #define WM2_LP_ILK 0x4510c |
4190 | #define WM2_LP_ILK 0x4510c |
3967 | #define WM2_LP_EN (1<<31) |
4191 | #define WM2_LP_EN (1<<31) |
3968 | #define WM3_LP_ILK 0x45110 |
4192 | #define WM3_LP_ILK 0x45110 |
3969 | #define WM3_LP_EN (1<<31) |
4193 | #define WM3_LP_EN (1<<31) |
3970 | #define WM1S_LP_ILK 0x45120 |
4194 | #define WM1S_LP_ILK 0x45120 |
3971 | #define WM2S_LP_IVB 0x45124 |
4195 | #define WM2S_LP_IVB 0x45124 |
3972 | #define WM3S_LP_IVB 0x45128 |
4196 | #define WM3S_LP_IVB 0x45128 |
3973 | #define WM1S_LP_EN (1<<31) |
4197 | #define WM1S_LP_EN (1<<31) |
3974 | 4198 | ||
3975 | #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ |
4199 | #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ |
3976 | (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ |
4200 | (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ |
3977 | ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) |
4201 | ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) |
3978 | 4202 | ||
3979 | /* Memory latency timer register */ |
4203 | /* Memory latency timer register */ |
3980 | #define MLTR_ILK 0x11222 |
4204 | #define MLTR_ILK 0x11222 |
3981 | #define MLTR_WM1_SHIFT 0 |
4205 | #define MLTR_WM1_SHIFT 0 |
3982 | #define MLTR_WM2_SHIFT 8 |
4206 | #define MLTR_WM2_SHIFT 8 |
3983 | /* the unit of memory self-refresh latency time is 0.5us */ |
4207 | /* the unit of memory self-refresh latency time is 0.5us */ |
3984 | #define ILK_SRLT_MASK 0x3f |
4208 | #define ILK_SRLT_MASK 0x3f |
3985 | 4209 | ||
3986 | 4210 | ||
3987 | /* the address where we get all kinds of latency value */ |
4211 | /* the address where we get all kinds of latency value */ |
3988 | #define SSKPD 0x5d10 |
4212 | #define SSKPD 0x5d10 |
3989 | #define SSKPD_WM_MASK 0x3f |
4213 | #define SSKPD_WM_MASK 0x3f |
3990 | #define SSKPD_WM0_SHIFT 0 |
4214 | #define SSKPD_WM0_SHIFT 0 |
3991 | #define SSKPD_WM1_SHIFT 8 |
4215 | #define SSKPD_WM1_SHIFT 8 |
3992 | #define SSKPD_WM2_SHIFT 16 |
4216 | #define SSKPD_WM2_SHIFT 16 |
3993 | #define SSKPD_WM3_SHIFT 24 |
4217 | #define SSKPD_WM3_SHIFT 24 |
3994 | 4218 | ||
3995 | /* |
4219 | /* |
3996 | * The two pipe frame counter registers are not synchronized, so |
4220 | * The two pipe frame counter registers are not synchronized, so |
3997 | * reading a stable value is somewhat tricky. The following code |
4221 | * reading a stable value is somewhat tricky. The following code |
3998 | * should work: |
4222 | * should work: |
3999 | * |
4223 | * |
4000 | * do { |
4224 | * do { |
4001 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
4225 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
4002 | * PIPE_FRAME_HIGH_SHIFT; |
4226 | * PIPE_FRAME_HIGH_SHIFT; |
4003 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> |
4227 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> |
4004 | * PIPE_FRAME_LOW_SHIFT); |
4228 | * PIPE_FRAME_LOW_SHIFT); |
4005 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
4229 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
4006 | * PIPE_FRAME_HIGH_SHIFT); |
4230 | * PIPE_FRAME_HIGH_SHIFT); |
4007 | * } while (high1 != high2); |
4231 | * } while (high1 != high2); |
4008 | * frame = (high1 << 8) | low1; |
4232 | * frame = (high1 << 8) | low1; |
4009 | */ |
4233 | */ |
4010 | #define _PIPEAFRAMEHIGH 0x70040 |
4234 | #define _PIPEAFRAMEHIGH 0x70040 |
4011 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
4235 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
4012 | #define PIPE_FRAME_HIGH_SHIFT 0 |
4236 | #define PIPE_FRAME_HIGH_SHIFT 0 |
4013 | #define _PIPEAFRAMEPIXEL 0x70044 |
4237 | #define _PIPEAFRAMEPIXEL 0x70044 |
4014 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
4238 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
4015 | #define PIPE_FRAME_LOW_SHIFT 24 |
4239 | #define PIPE_FRAME_LOW_SHIFT 24 |
4016 | #define PIPE_PIXEL_MASK 0x00ffffff |
4240 | #define PIPE_PIXEL_MASK 0x00ffffff |
4017 | #define PIPE_PIXEL_SHIFT 0 |
4241 | #define PIPE_PIXEL_SHIFT 0 |
4018 | /* GM45+ just has to be different */ |
4242 | /* GM45+ just has to be different */ |
4019 | #define _PIPEA_FRMCOUNT_GM45 0x70040 |
4243 | #define _PIPEA_FRMCOUNT_GM45 0x70040 |
4020 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 |
4244 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 |
4021 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) |
4245 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) |
4022 | #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) |
4246 | #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) |
4023 | 4247 | ||
4024 | /* Cursor A & B regs */ |
4248 | /* Cursor A & B regs */ |
4025 | #define _CURACNTR 0x70080 |
4249 | #define _CURACNTR 0x70080 |
4026 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
4250 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
4027 | #define CURSOR_ENABLE 0x80000000 |
4251 | #define CURSOR_ENABLE 0x80000000 |
4028 | #define CURSOR_GAMMA_ENABLE 0x40000000 |
4252 | #define CURSOR_GAMMA_ENABLE 0x40000000 |
4029 | #define CURSOR_STRIDE_MASK 0x30000000 |
4253 | #define CURSOR_STRIDE_SHIFT 28 |
- | 4254 | #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ |
|
4030 | #define CURSOR_PIPE_CSC_ENABLE (1<<24) |
4255 | #define CURSOR_PIPE_CSC_ENABLE (1<<24) |
4031 | #define CURSOR_FORMAT_SHIFT 24 |
4256 | #define CURSOR_FORMAT_SHIFT 24 |
4032 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
4257 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
4033 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) |
4258 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) |
4034 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) |
4259 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) |
4035 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) |
4260 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) |
4036 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) |
4261 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) |
4037 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) |
4262 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) |
4038 | /* New style CUR*CNTR flags */ |
4263 | /* New style CUR*CNTR flags */ |
4039 | #define CURSOR_MODE 0x27 |
4264 | #define CURSOR_MODE 0x27 |
4040 | #define CURSOR_MODE_DISABLE 0x00 |
4265 | #define CURSOR_MODE_DISABLE 0x00 |
4041 | #define CURSOR_MODE_128_32B_AX 0x02 |
4266 | #define CURSOR_MODE_128_32B_AX 0x02 |
4042 | #define CURSOR_MODE_256_32B_AX 0x03 |
4267 | #define CURSOR_MODE_256_32B_AX 0x03 |
4043 | #define CURSOR_MODE_64_32B_AX 0x07 |
4268 | #define CURSOR_MODE_64_32B_AX 0x07 |
4044 | #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) |
4269 | #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) |
4045 | #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) |
4270 | #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) |
4046 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
4271 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
4047 | #define MCURSOR_PIPE_SELECT (1 << 28) |
4272 | #define MCURSOR_PIPE_SELECT (1 << 28) |
4048 | #define MCURSOR_PIPE_A 0x00 |
4273 | #define MCURSOR_PIPE_A 0x00 |
4049 | #define MCURSOR_PIPE_B (1 << 28) |
4274 | #define MCURSOR_PIPE_B (1 << 28) |
4050 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
4275 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
- | 4276 | #define CURSOR_ROTATE_180 (1<<15) |
|
4051 | #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
4277 | #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
4052 | #define _CURABASE 0x70084 |
4278 | #define _CURABASE 0x70084 |
4053 | #define _CURAPOS 0x70088 |
4279 | #define _CURAPOS 0x70088 |
4054 | #define CURSOR_POS_MASK 0x007FF |
4280 | #define CURSOR_POS_MASK 0x007FF |
4055 | #define CURSOR_POS_SIGN 0x8000 |
4281 | #define CURSOR_POS_SIGN 0x8000 |
4056 | #define CURSOR_X_SHIFT 0 |
4282 | #define CURSOR_X_SHIFT 0 |
4057 | #define CURSOR_Y_SHIFT 16 |
4283 | #define CURSOR_Y_SHIFT 16 |
4058 | #define CURSIZE 0x700a0 |
4284 | #define CURSIZE 0x700a0 |
4059 | #define _CURBCNTR 0x700c0 |
4285 | #define _CURBCNTR 0x700c0 |
4060 | #define _CURBBASE 0x700c4 |
4286 | #define _CURBBASE 0x700c4 |
4061 | #define _CURBPOS 0x700c8 |
4287 | #define _CURBPOS 0x700c8 |
4062 | 4288 | ||
4063 | #define _CURBCNTR_IVB 0x71080 |
4289 | #define _CURBCNTR_IVB 0x71080 |
4064 | #define _CURBBASE_IVB 0x71084 |
4290 | #define _CURBBASE_IVB 0x71084 |
4065 | #define _CURBPOS_IVB 0x71088 |
4291 | #define _CURBPOS_IVB 0x71088 |
4066 | 4292 | ||
4067 | #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ |
4293 | #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ |
4068 | dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ |
4294 | dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ |
4069 | dev_priv->info.display_mmio_offset) |
4295 | dev_priv->info.display_mmio_offset) |
4070 | 4296 | ||
4071 | #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) |
4297 | #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) |
4072 | #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) |
4298 | #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) |
4073 | #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) |
4299 | #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) |
4074 | 4300 | ||
4075 | #define CURSOR_A_OFFSET 0x70080 |
4301 | #define CURSOR_A_OFFSET 0x70080 |
4076 | #define CURSOR_B_OFFSET 0x700c0 |
4302 | #define CURSOR_B_OFFSET 0x700c0 |
4077 | #define CHV_CURSOR_C_OFFSET 0x700e0 |
4303 | #define CHV_CURSOR_C_OFFSET 0x700e0 |
4078 | #define IVB_CURSOR_B_OFFSET 0x71080 |
4304 | #define IVB_CURSOR_B_OFFSET 0x71080 |
4079 | #define IVB_CURSOR_C_OFFSET 0x72080 |
4305 | #define IVB_CURSOR_C_OFFSET 0x72080 |
4080 | 4306 | ||
4081 | /* Display A control */ |
4307 | /* Display A control */ |
4082 | #define _DSPACNTR 0x70180 |
4308 | #define _DSPACNTR 0x70180 |
4083 | #define DISPLAY_PLANE_ENABLE (1<<31) |
4309 | #define DISPLAY_PLANE_ENABLE (1<<31) |
4084 | #define DISPLAY_PLANE_DISABLE 0 |
4310 | #define DISPLAY_PLANE_DISABLE 0 |
4085 | #define DISPPLANE_GAMMA_ENABLE (1<<30) |
4311 | #define DISPPLANE_GAMMA_ENABLE (1<<30) |
4086 | #define DISPPLANE_GAMMA_DISABLE 0 |
4312 | #define DISPPLANE_GAMMA_DISABLE 0 |
4087 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
4313 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
4088 | #define DISPPLANE_YUV422 (0x0<<26) |
4314 | #define DISPPLANE_YUV422 (0x0<<26) |
4089 | #define DISPPLANE_8BPP (0x2<<26) |
4315 | #define DISPPLANE_8BPP (0x2<<26) |
4090 | #define DISPPLANE_BGRA555 (0x3<<26) |
4316 | #define DISPPLANE_BGRA555 (0x3<<26) |
4091 | #define DISPPLANE_BGRX555 (0x4<<26) |
4317 | #define DISPPLANE_BGRX555 (0x4<<26) |
4092 | #define DISPPLANE_BGRX565 (0x5<<26) |
4318 | #define DISPPLANE_BGRX565 (0x5<<26) |
4093 | #define DISPPLANE_BGRX888 (0x6<<26) |
4319 | #define DISPPLANE_BGRX888 (0x6<<26) |
4094 | #define DISPPLANE_BGRA888 (0x7<<26) |
4320 | #define DISPPLANE_BGRA888 (0x7<<26) |
4095 | #define DISPPLANE_RGBX101010 (0x8<<26) |
4321 | #define DISPPLANE_RGBX101010 (0x8<<26) |
4096 | #define DISPPLANE_RGBA101010 (0x9<<26) |
4322 | #define DISPPLANE_RGBA101010 (0x9<<26) |
4097 | #define DISPPLANE_BGRX101010 (0xa<<26) |
4323 | #define DISPPLANE_BGRX101010 (0xa<<26) |
4098 | #define DISPPLANE_RGBX161616 (0xc<<26) |
4324 | #define DISPPLANE_RGBX161616 (0xc<<26) |
4099 | #define DISPPLANE_RGBX888 (0xe<<26) |
4325 | #define DISPPLANE_RGBX888 (0xe<<26) |
4100 | #define DISPPLANE_RGBA888 (0xf<<26) |
4326 | #define DISPPLANE_RGBA888 (0xf<<26) |
4101 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
4327 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
4102 | #define DISPPLANE_STEREO_DISABLE 0 |
4328 | #define DISPPLANE_STEREO_DISABLE 0 |
4103 | #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) |
4329 | #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) |
4104 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
4330 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
4105 | #define DISPPLANE_SEL_PIPE_MASK (3< |
4331 | #define DISPPLANE_SEL_PIPE_MASK (3< |
4106 | #define DISPPLANE_SEL_PIPE_A 0 |
4332 | #define DISPPLANE_SEL_PIPE_A 0 |
4107 | #define DISPPLANE_SEL_PIPE_B (1< |
4333 | #define DISPPLANE_SEL_PIPE_B (1< |
4108 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
4334 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
4109 | #define DISPPLANE_SRC_KEY_DISABLE 0 |
4335 | #define DISPPLANE_SRC_KEY_DISABLE 0 |
4110 | #define DISPPLANE_LINE_DOUBLE (1<<20) |
4336 | #define DISPPLANE_LINE_DOUBLE (1<<20) |
4111 | #define DISPPLANE_NO_LINE_DOUBLE 0 |
4337 | #define DISPPLANE_NO_LINE_DOUBLE 0 |
4112 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
4338 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
4113 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
4339 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
- | 4340 | #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ |
|
- | 4341 | #define DISPPLANE_ROTATE_180 (1<<15) |
|
4114 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
4342 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
4115 | #define DISPPLANE_TILED (1<<10) |
4343 | #define DISPPLANE_TILED (1<<10) |
- | 4344 | #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ |
|
4116 | #define _DSPAADDR 0x70184 |
4345 | #define _DSPAADDR 0x70184 |
4117 | #define _DSPASTRIDE 0x70188 |
4346 | #define _DSPASTRIDE 0x70188 |
4118 | #define _DSPAPOS 0x7018C /* reserved */ |
4347 | #define _DSPAPOS 0x7018C /* reserved */ |
4119 | #define _DSPASIZE 0x70190 |
4348 | #define _DSPASIZE 0x70190 |
4120 | #define _DSPASURF 0x7019C /* 965+ only */ |
4349 | #define _DSPASURF 0x7019C /* 965+ only */ |
4121 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ |
4350 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ |
4122 | #define _DSPAOFFSET 0x701A4 /* HSW */ |
4351 | #define _DSPAOFFSET 0x701A4 /* HSW */ |
4123 | #define _DSPASURFLIVE 0x701AC |
4352 | #define _DSPASURFLIVE 0x701AC |
4124 | 4353 | ||
4125 | #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) |
4354 | #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) |
4126 | #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) |
4355 | #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) |
4127 | #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) |
4356 | #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) |
4128 | #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) |
4357 | #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) |
4129 | #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) |
4358 | #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) |
4130 | #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) |
4359 | #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) |
4131 | #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) |
4360 | #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) |
4132 | #define DSPLINOFF(plane) DSPADDR(plane) |
4361 | #define DSPLINOFF(plane) DSPADDR(plane) |
4133 | #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) |
4362 | #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) |
4134 | #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) |
4363 | #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) |
- | 4364 | ||
- | 4365 | /* CHV pipe B blender and primary plane */ |
|
- | 4366 | #define _CHV_BLEND_A 0x60a00 |
|
- | 4367 | #define CHV_BLEND_LEGACY (0<<30) |
|
- | 4368 | #define CHV_BLEND_ANDROID (1<<30) |
|
- | 4369 | #define CHV_BLEND_MPO (2<<30) |
|
- | 4370 | #define CHV_BLEND_MASK (3<<30) |
|
- | 4371 | #define _CHV_CANVAS_A 0x60a04 |
|
- | 4372 | #define _PRIMPOS_A 0x60a08 |
|
- | 4373 | #define _PRIMSIZE_A 0x60a0c |
|
- | 4374 | #define _PRIMCNSTALPHA_A 0x60a10 |
|
- | 4375 | #define PRIM_CONST_ALPHA_ENABLE (1<<31) |
|
- | 4376 | ||
- | 4377 | #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A) |
|
- | 4378 | #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A) |
|
- | 4379 | #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A) |
|
- | 4380 | #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A) |
|
- | 4381 | #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A) |
|
4135 | 4382 | ||
4136 | /* Display/Sprite base address macros */ |
4383 | /* Display/Sprite base address macros */ |
4137 | #define DISP_BASEADDR_MASK (0xfffff000) |
4384 | #define DISP_BASEADDR_MASK (0xfffff000) |
4138 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
4385 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
4139 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
4386 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
4140 | 4387 | ||
4141 | /* VBIOS flags */ |
4388 | /* VBIOS flags */ |
4142 | #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) |
4389 | #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) |
4143 | #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) |
4390 | #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) |
4144 | #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) |
4391 | #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) |
4145 | #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) |
4392 | #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) |
4146 | #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) |
4393 | #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) |
4147 | #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) |
4394 | #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) |
4148 | #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) |
4395 | #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) |
4149 | #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) |
4396 | #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) |
4150 | #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) |
4397 | #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) |
4151 | #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) |
4398 | #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) |
4152 | #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) |
4399 | #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) |
4153 | #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) |
4400 | #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) |
4154 | #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) |
4401 | #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) |
4155 | 4402 | ||
4156 | /* Pipe B */ |
4403 | /* Pipe B */ |
4157 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
4404 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
4158 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) |
4405 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) |
4159 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) |
4406 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) |
4160 | #define _PIPEBFRAMEHIGH 0x71040 |
4407 | #define _PIPEBFRAMEHIGH 0x71040 |
4161 | #define _PIPEBFRAMEPIXEL 0x71044 |
4408 | #define _PIPEBFRAMEPIXEL 0x71044 |
4162 | #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) |
4409 | #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) |
4163 | #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) |
4410 | #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) |
4164 | 4411 | ||
4165 | 4412 | ||
4166 | /* Display B control */ |
4413 | /* Display B control */ |
4167 | #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) |
4414 | #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) |
4168 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
4415 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
4169 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
4416 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
4170 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 |
4417 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 |
4171 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
4418 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
4172 | #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) |
4419 | #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) |
4173 | #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) |
4420 | #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) |
4174 | #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) |
4421 | #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) |
4175 | #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) |
4422 | #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) |
4176 | #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) |
4423 | #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) |
4177 | #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) |
4424 | #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) |
4178 | #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) |
4425 | #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) |
4179 | #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) |
4426 | #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) |
4180 | 4427 | ||
4181 | /* Sprite A control */ |
4428 | /* Sprite A control */ |
4182 | #define _DVSACNTR 0x72180 |
4429 | #define _DVSACNTR 0x72180 |
4183 | #define DVS_ENABLE (1<<31) |
4430 | #define DVS_ENABLE (1<<31) |
4184 | #define DVS_GAMMA_ENABLE (1<<30) |
4431 | #define DVS_GAMMA_ENABLE (1<<30) |
4185 | #define DVS_PIXFORMAT_MASK (3<<25) |
4432 | #define DVS_PIXFORMAT_MASK (3<<25) |
4186 | #define DVS_FORMAT_YUV422 (0<<25) |
4433 | #define DVS_FORMAT_YUV422 (0<<25) |
4187 | #define DVS_FORMAT_RGBX101010 (1<<25) |
4434 | #define DVS_FORMAT_RGBX101010 (1<<25) |
4188 | #define DVS_FORMAT_RGBX888 (2<<25) |
4435 | #define DVS_FORMAT_RGBX888 (2<<25) |
4189 | #define DVS_FORMAT_RGBX161616 (3<<25) |
4436 | #define DVS_FORMAT_RGBX161616 (3<<25) |
4190 | #define DVS_PIPE_CSC_ENABLE (1<<24) |
4437 | #define DVS_PIPE_CSC_ENABLE (1<<24) |
4191 | #define DVS_SOURCE_KEY (1<<22) |
4438 | #define DVS_SOURCE_KEY (1<<22) |
4192 | #define DVS_RGB_ORDER_XBGR (1<<20) |
4439 | #define DVS_RGB_ORDER_XBGR (1<<20) |
4193 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
4440 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
4194 | #define DVS_YUV_ORDER_YUYV (0<<16) |
4441 | #define DVS_YUV_ORDER_YUYV (0<<16) |
4195 | #define DVS_YUV_ORDER_UYVY (1<<16) |
4442 | #define DVS_YUV_ORDER_UYVY (1<<16) |
4196 | #define DVS_YUV_ORDER_YVYU (2<<16) |
4443 | #define DVS_YUV_ORDER_YVYU (2<<16) |
4197 | #define DVS_YUV_ORDER_VYUY (3<<16) |
4444 | #define DVS_YUV_ORDER_VYUY (3<<16) |
- | 4445 | #define DVS_ROTATE_180 (1<<15) |
|
4198 | #define DVS_DEST_KEY (1<<2) |
4446 | #define DVS_DEST_KEY (1<<2) |
4199 | #define DVS_TRICKLE_FEED_DISABLE (1<<14) |
4447 | #define DVS_TRICKLE_FEED_DISABLE (1<<14) |
4200 | #define DVS_TILED (1<<10) |
4448 | #define DVS_TILED (1<<10) |
4201 | #define _DVSALINOFF 0x72184 |
4449 | #define _DVSALINOFF 0x72184 |
4202 | #define _DVSASTRIDE 0x72188 |
4450 | #define _DVSASTRIDE 0x72188 |
4203 | #define _DVSAPOS 0x7218c |
4451 | #define _DVSAPOS 0x7218c |
4204 | #define _DVSASIZE 0x72190 |
4452 | #define _DVSASIZE 0x72190 |
4205 | #define _DVSAKEYVAL 0x72194 |
4453 | #define _DVSAKEYVAL 0x72194 |
4206 | #define _DVSAKEYMSK 0x72198 |
4454 | #define _DVSAKEYMSK 0x72198 |
4207 | #define _DVSASURF 0x7219c |
4455 | #define _DVSASURF 0x7219c |
4208 | #define _DVSAKEYMAXVAL 0x721a0 |
4456 | #define _DVSAKEYMAXVAL 0x721a0 |
4209 | #define _DVSATILEOFF 0x721a4 |
4457 | #define _DVSATILEOFF 0x721a4 |
4210 | #define _DVSASURFLIVE 0x721ac |
4458 | #define _DVSASURFLIVE 0x721ac |
4211 | #define _DVSASCALE 0x72204 |
4459 | #define _DVSASCALE 0x72204 |
4212 | #define DVS_SCALE_ENABLE (1<<31) |
4460 | #define DVS_SCALE_ENABLE (1<<31) |
4213 | #define DVS_FILTER_MASK (3<<29) |
4461 | #define DVS_FILTER_MASK (3<<29) |
4214 | #define DVS_FILTER_MEDIUM (0<<29) |
4462 | #define DVS_FILTER_MEDIUM (0<<29) |
4215 | #define DVS_FILTER_ENHANCING (1<<29) |
4463 | #define DVS_FILTER_ENHANCING (1<<29) |
4216 | #define DVS_FILTER_SOFTENING (2<<29) |
4464 | #define DVS_FILTER_SOFTENING (2<<29) |
4217 | #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
4465 | #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
4218 | #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) |
4466 | #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) |
4219 | #define _DVSAGAMC 0x72300 |
4467 | #define _DVSAGAMC 0x72300 |
4220 | 4468 | ||
4221 | #define _DVSBCNTR 0x73180 |
4469 | #define _DVSBCNTR 0x73180 |
4222 | #define _DVSBLINOFF 0x73184 |
4470 | #define _DVSBLINOFF 0x73184 |
4223 | #define _DVSBSTRIDE 0x73188 |
4471 | #define _DVSBSTRIDE 0x73188 |
4224 | #define _DVSBPOS 0x7318c |
4472 | #define _DVSBPOS 0x7318c |
4225 | #define _DVSBSIZE 0x73190 |
4473 | #define _DVSBSIZE 0x73190 |
4226 | #define _DVSBKEYVAL 0x73194 |
4474 | #define _DVSBKEYVAL 0x73194 |
4227 | #define _DVSBKEYMSK 0x73198 |
4475 | #define _DVSBKEYMSK 0x73198 |
4228 | #define _DVSBSURF 0x7319c |
4476 | #define _DVSBSURF 0x7319c |
4229 | #define _DVSBKEYMAXVAL 0x731a0 |
4477 | #define _DVSBKEYMAXVAL 0x731a0 |
4230 | #define _DVSBTILEOFF 0x731a4 |
4478 | #define _DVSBTILEOFF 0x731a4 |
4231 | #define _DVSBSURFLIVE 0x731ac |
4479 | #define _DVSBSURFLIVE 0x731ac |
4232 | #define _DVSBSCALE 0x73204 |
4480 | #define _DVSBSCALE 0x73204 |
4233 | #define _DVSBGAMC 0x73300 |
4481 | #define _DVSBGAMC 0x73300 |
4234 | 4482 | ||
4235 | #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
4483 | #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
4236 | #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) |
4484 | #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) |
4237 | #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) |
4485 | #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) |
4238 | #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) |
4486 | #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) |
4239 | #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) |
4487 | #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) |
4240 | #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
4488 | #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
4241 | #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
4489 | #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
4242 | #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) |
4490 | #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) |
4243 | #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) |
4491 | #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) |
4244 | #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
4492 | #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
4245 | #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) |
4493 | #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) |
4246 | #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
4494 | #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
4247 | 4495 | ||
4248 | #define _SPRA_CTL 0x70280 |
4496 | #define _SPRA_CTL 0x70280 |
4249 | #define SPRITE_ENABLE (1<<31) |
4497 | #define SPRITE_ENABLE (1<<31) |
4250 | #define SPRITE_GAMMA_ENABLE (1<<30) |
4498 | #define SPRITE_GAMMA_ENABLE (1<<30) |
4251 | #define SPRITE_PIXFORMAT_MASK (7<<25) |
4499 | #define SPRITE_PIXFORMAT_MASK (7<<25) |
4252 | #define SPRITE_FORMAT_YUV422 (0<<25) |
4500 | #define SPRITE_FORMAT_YUV422 (0<<25) |
4253 | #define SPRITE_FORMAT_RGBX101010 (1<<25) |
4501 | #define SPRITE_FORMAT_RGBX101010 (1<<25) |
4254 | #define SPRITE_FORMAT_RGBX888 (2<<25) |
4502 | #define SPRITE_FORMAT_RGBX888 (2<<25) |
4255 | #define SPRITE_FORMAT_RGBX161616 (3<<25) |
4503 | #define SPRITE_FORMAT_RGBX161616 (3<<25) |
4256 | #define SPRITE_FORMAT_YUV444 (4<<25) |
4504 | #define SPRITE_FORMAT_YUV444 (4<<25) |
4257 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ |
4505 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ |
4258 | #define SPRITE_PIPE_CSC_ENABLE (1<<24) |
4506 | #define SPRITE_PIPE_CSC_ENABLE (1<<24) |
4259 | #define SPRITE_SOURCE_KEY (1<<22) |
4507 | #define SPRITE_SOURCE_KEY (1<<22) |
4260 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ |
4508 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ |
4261 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) |
4509 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) |
4262 | #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ |
4510 | #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ |
4263 | #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) |
4511 | #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) |
4264 | #define SPRITE_YUV_ORDER_YUYV (0<<16) |
4512 | #define SPRITE_YUV_ORDER_YUYV (0<<16) |
4265 | #define SPRITE_YUV_ORDER_UYVY (1<<16) |
4513 | #define SPRITE_YUV_ORDER_UYVY (1<<16) |
4266 | #define SPRITE_YUV_ORDER_YVYU (2<<16) |
4514 | #define SPRITE_YUV_ORDER_YVYU (2<<16) |
4267 | #define SPRITE_YUV_ORDER_VYUY (3<<16) |
4515 | #define SPRITE_YUV_ORDER_VYUY (3<<16) |
- | 4516 | #define SPRITE_ROTATE_180 (1<<15) |
|
4268 | #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
4517 | #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
4269 | #define SPRITE_INT_GAMMA_ENABLE (1<<13) |
4518 | #define SPRITE_INT_GAMMA_ENABLE (1<<13) |
4270 | #define SPRITE_TILED (1<<10) |
4519 | #define SPRITE_TILED (1<<10) |
4271 | #define SPRITE_DEST_KEY (1<<2) |
4520 | #define SPRITE_DEST_KEY (1<<2) |
4272 | #define _SPRA_LINOFF 0x70284 |
4521 | #define _SPRA_LINOFF 0x70284 |
4273 | #define _SPRA_STRIDE 0x70288 |
4522 | #define _SPRA_STRIDE 0x70288 |
4274 | #define _SPRA_POS 0x7028c |
4523 | #define _SPRA_POS 0x7028c |
4275 | #define _SPRA_SIZE 0x70290 |
4524 | #define _SPRA_SIZE 0x70290 |
4276 | #define _SPRA_KEYVAL 0x70294 |
4525 | #define _SPRA_KEYVAL 0x70294 |
4277 | #define _SPRA_KEYMSK 0x70298 |
4526 | #define _SPRA_KEYMSK 0x70298 |
4278 | #define _SPRA_SURF 0x7029c |
4527 | #define _SPRA_SURF 0x7029c |
4279 | #define _SPRA_KEYMAX 0x702a0 |
4528 | #define _SPRA_KEYMAX 0x702a0 |
4280 | #define _SPRA_TILEOFF 0x702a4 |
4529 | #define _SPRA_TILEOFF 0x702a4 |
4281 | #define _SPRA_OFFSET 0x702a4 |
4530 | #define _SPRA_OFFSET 0x702a4 |
4282 | #define _SPRA_SURFLIVE 0x702ac |
4531 | #define _SPRA_SURFLIVE 0x702ac |
4283 | #define _SPRA_SCALE 0x70304 |
4532 | #define _SPRA_SCALE 0x70304 |
4284 | #define SPRITE_SCALE_ENABLE (1<<31) |
4533 | #define SPRITE_SCALE_ENABLE (1<<31) |
4285 | #define SPRITE_FILTER_MASK (3<<29) |
4534 | #define SPRITE_FILTER_MASK (3<<29) |
4286 | #define SPRITE_FILTER_MEDIUM (0<<29) |
4535 | #define SPRITE_FILTER_MEDIUM (0<<29) |
4287 | #define SPRITE_FILTER_ENHANCING (1<<29) |
4536 | #define SPRITE_FILTER_ENHANCING (1<<29) |
4288 | #define SPRITE_FILTER_SOFTENING (2<<29) |
4537 | #define SPRITE_FILTER_SOFTENING (2<<29) |
4289 | #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
4538 | #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ |
4290 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) |
4539 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) |
4291 | #define _SPRA_GAMC 0x70400 |
4540 | #define _SPRA_GAMC 0x70400 |
4292 | 4541 | ||
4293 | #define _SPRB_CTL 0x71280 |
4542 | #define _SPRB_CTL 0x71280 |
4294 | #define _SPRB_LINOFF 0x71284 |
4543 | #define _SPRB_LINOFF 0x71284 |
4295 | #define _SPRB_STRIDE 0x71288 |
4544 | #define _SPRB_STRIDE 0x71288 |
4296 | #define _SPRB_POS 0x7128c |
4545 | #define _SPRB_POS 0x7128c |
4297 | #define _SPRB_SIZE 0x71290 |
4546 | #define _SPRB_SIZE 0x71290 |
4298 | #define _SPRB_KEYVAL 0x71294 |
4547 | #define _SPRB_KEYVAL 0x71294 |
4299 | #define _SPRB_KEYMSK 0x71298 |
4548 | #define _SPRB_KEYMSK 0x71298 |
4300 | #define _SPRB_SURF 0x7129c |
4549 | #define _SPRB_SURF 0x7129c |
4301 | #define _SPRB_KEYMAX 0x712a0 |
4550 | #define _SPRB_KEYMAX 0x712a0 |
4302 | #define _SPRB_TILEOFF 0x712a4 |
4551 | #define _SPRB_TILEOFF 0x712a4 |
4303 | #define _SPRB_OFFSET 0x712a4 |
4552 | #define _SPRB_OFFSET 0x712a4 |
4304 | #define _SPRB_SURFLIVE 0x712ac |
4553 | #define _SPRB_SURFLIVE 0x712ac |
4305 | #define _SPRB_SCALE 0x71304 |
4554 | #define _SPRB_SCALE 0x71304 |
4306 | #define _SPRB_GAMC 0x71400 |
4555 | #define _SPRB_GAMC 0x71400 |
4307 | 4556 | ||
4308 | #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
4557 | #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
4309 | #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) |
4558 | #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) |
4310 | #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) |
4559 | #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) |
4311 | #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) |
4560 | #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) |
4312 | #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) |
4561 | #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) |
4313 | #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) |
4562 | #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) |
4314 | #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) |
4563 | #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) |
4315 | #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) |
4564 | #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) |
4316 | #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) |
4565 | #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) |
4317 | #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) |
4566 | #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) |
4318 | #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
4567 | #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
4319 | #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
4568 | #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
4320 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) |
4569 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) |
4321 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
4570 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
4322 | 4571 | ||
4323 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
4572 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
4324 | #define SP_ENABLE (1<<31) |
4573 | #define SP_ENABLE (1<<31) |
4325 | #define SP_GAMMA_ENABLE (1<<30) |
4574 | #define SP_GAMMA_ENABLE (1<<30) |
4326 | #define SP_PIXFORMAT_MASK (0xf<<26) |
4575 | #define SP_PIXFORMAT_MASK (0xf<<26) |
4327 | #define SP_FORMAT_YUV422 (0<<26) |
4576 | #define SP_FORMAT_YUV422 (0<<26) |
4328 | #define SP_FORMAT_BGR565 (5<<26) |
4577 | #define SP_FORMAT_BGR565 (5<<26) |
4329 | #define SP_FORMAT_BGRX8888 (6<<26) |
4578 | #define SP_FORMAT_BGRX8888 (6<<26) |
4330 | #define SP_FORMAT_BGRA8888 (7<<26) |
4579 | #define SP_FORMAT_BGRA8888 (7<<26) |
4331 | #define SP_FORMAT_RGBX1010102 (8<<26) |
4580 | #define SP_FORMAT_RGBX1010102 (8<<26) |
4332 | #define SP_FORMAT_RGBA1010102 (9<<26) |
4581 | #define SP_FORMAT_RGBA1010102 (9<<26) |
4333 | #define SP_FORMAT_RGBX8888 (0xe<<26) |
4582 | #define SP_FORMAT_RGBX8888 (0xe<<26) |
4334 | #define SP_FORMAT_RGBA8888 (0xf<<26) |
4583 | #define SP_FORMAT_RGBA8888 (0xf<<26) |
- | 4584 | #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ |
|
4335 | #define SP_SOURCE_KEY (1<<22) |
4585 | #define SP_SOURCE_KEY (1<<22) |
4336 | #define SP_YUV_BYTE_ORDER_MASK (3<<16) |
4586 | #define SP_YUV_BYTE_ORDER_MASK (3<<16) |
4337 | #define SP_YUV_ORDER_YUYV (0<<16) |
4587 | #define SP_YUV_ORDER_YUYV (0<<16) |
4338 | #define SP_YUV_ORDER_UYVY (1<<16) |
4588 | #define SP_YUV_ORDER_UYVY (1<<16) |
4339 | #define SP_YUV_ORDER_YVYU (2<<16) |
4589 | #define SP_YUV_ORDER_YVYU (2<<16) |
4340 | #define SP_YUV_ORDER_VYUY (3<<16) |
4590 | #define SP_YUV_ORDER_VYUY (3<<16) |
- | 4591 | #define SP_ROTATE_180 (1<<15) |
|
4341 | #define SP_TILED (1<<10) |
4592 | #define SP_TILED (1<<10) |
- | 4593 | #define SP_MIRROR (1<<8) /* CHV pipe B */ |
|
4342 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
4594 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
4343 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) |
4595 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) |
4344 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) |
4596 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) |
4345 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) |
4597 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) |
4346 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) |
4598 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) |
4347 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) |
4599 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) |
4348 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) |
4600 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) |
4349 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) |
4601 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) |
4350 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) |
4602 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) |
4351 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) |
4603 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) |
- | 4604 | #define SP_CONST_ALPHA_ENABLE (1<<31) |
|
4352 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) |
4605 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) |
4353 | 4606 | ||
4354 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) |
4607 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) |
4355 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) |
4608 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) |
4356 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) |
4609 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) |
4357 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) |
4610 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) |
4358 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) |
4611 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) |
4359 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) |
4612 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) |
4360 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) |
4613 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) |
4361 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) |
4614 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) |
4362 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) |
4615 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) |
4363 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) |
4616 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) |
4364 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) |
4617 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) |
4365 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) |
4618 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) |
4366 | 4619 | ||
4367 | #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) |
4620 | #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) |
4368 | #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) |
4621 | #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) |
4369 | #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) |
4622 | #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) |
4370 | #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) |
4623 | #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) |
4371 | #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) |
4624 | #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) |
4372 | #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) |
4625 | #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) |
4373 | #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) |
4626 | #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) |
4374 | #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) |
4627 | #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) |
4375 | #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) |
4628 | #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) |
4376 | #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) |
4629 | #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) |
4377 | #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) |
4630 | #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) |
4378 | #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) |
4631 | #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) |
- | 4632 | ||
- | 4633 | /* |
|
- | 4634 | * CHV pipe B sprite CSC |
|
- | 4635 | * |
|
- | 4636 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| |
|
- | 4637 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| |
|
- | 4638 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| |
|
- | 4639 | */ |
|
- | 4640 | #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) |
|
- | 4641 | #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) |
|
- | 4642 | #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) |
|
- | 4643 | #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ |
|
- | 4644 | #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ |
|
- | 4645 | ||
- | 4646 | #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) |
|
- | 4647 | #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) |
|
- | 4648 | #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) |
|
- | 4649 | #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) |
|
- | 4650 | #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) |
|
- | 4651 | #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ |
|
- | 4652 | #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ |
|
- | 4653 | ||
- | 4654 | #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) |
|
- | 4655 | #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) |
|
- | 4656 | #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) |
|
- | 4657 | #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ |
|
- | 4658 | #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ |
|
- | 4659 | ||
- | 4660 | #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) |
|
- | 4661 | #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) |
|
- | 4662 | #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) |
|
- | 4663 | #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ |
|
- | 4664 | #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ |
|
- | 4665 | ||
- | 4666 | /* Skylake plane registers */ |
|
- | 4667 | ||
- | 4668 | #define _PLANE_CTL_1_A 0x70180 |
|
- | 4669 | #define _PLANE_CTL_2_A 0x70280 |
|
- | 4670 | #define _PLANE_CTL_3_A 0x70380 |
|
- | 4671 | #define PLANE_CTL_ENABLE (1 << 31) |
|
- | 4672 | #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) |
|
- | 4673 | #define PLANE_CTL_FORMAT_MASK (0xf << 24) |
|
- | 4674 | #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) |
|
- | 4675 | #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) |
|
- | 4676 | #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) |
|
- | 4677 | #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) |
|
- | 4678 | #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) |
|
- | 4679 | #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) |
|
- | 4680 | #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) |
|
- | 4681 | #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) |
|
- | 4682 | #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) |
|
- | 4683 | #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) |
|
- | 4684 | #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) |
|
- | 4685 | #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) |
|
- | 4686 | #define PLANE_CTL_ORDER_BGRX (0 << 20) |
|
- | 4687 | #define PLANE_CTL_ORDER_RGBX (1 << 20) |
|
- | 4688 | #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) |
|
- | 4689 | #define PLANE_CTL_YUV422_YUYV ( 0 << 16) |
|
- | 4690 | #define PLANE_CTL_YUV422_UYVY ( 1 << 16) |
|
- | 4691 | #define PLANE_CTL_YUV422_YVYU ( 2 << 16) |
|
- | 4692 | #define PLANE_CTL_YUV422_VYUY ( 3 << 16) |
|
- | 4693 | #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) |
|
- | 4694 | #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) |
|
- | 4695 | #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) |
|
- | 4696 | #define PLANE_CTL_TILED_MASK (0x7 << 10) |
|
- | 4697 | #define PLANE_CTL_TILED_LINEAR ( 0 << 10) |
|
- | 4698 | #define PLANE_CTL_TILED_X ( 1 << 10) |
|
- | 4699 | #define PLANE_CTL_TILED_Y ( 4 << 10) |
|
- | 4700 | #define PLANE_CTL_TILED_YF ( 5 << 10) |
|
- | 4701 | #define PLANE_CTL_ALPHA_MASK (0x3 << 4) |
|
- | 4702 | #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) |
|
- | 4703 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) |
|
- | 4704 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) |
|
- | 4705 | #define PLANE_CTL_ROTATE_MASK 0x3 |
|
- | 4706 | #define PLANE_CTL_ROTATE_0 0x0 |
|
- | 4707 | #define PLANE_CTL_ROTATE_180 0x2 |
|
- | 4708 | #define _PLANE_STRIDE_1_A 0x70188 |
|
- | 4709 | #define _PLANE_STRIDE_2_A 0x70288 |
|
- | 4710 | #define _PLANE_STRIDE_3_A 0x70388 |
|
- | 4711 | #define _PLANE_POS_1_A 0x7018c |
|
- | 4712 | #define _PLANE_POS_2_A 0x7028c |
|
- | 4713 | #define _PLANE_POS_3_A 0x7038c |
|
- | 4714 | #define _PLANE_SIZE_1_A 0x70190 |
|
- | 4715 | #define _PLANE_SIZE_2_A 0x70290 |
|
- | 4716 | #define _PLANE_SIZE_3_A 0x70390 |
|
- | 4717 | #define _PLANE_SURF_1_A 0x7019c |
|
- | 4718 | #define _PLANE_SURF_2_A 0x7029c |
|
- | 4719 | #define _PLANE_SURF_3_A 0x7039c |
|
- | 4720 | #define _PLANE_OFFSET_1_A 0x701a4 |
|
- | 4721 | #define _PLANE_OFFSET_2_A 0x702a4 |
|
- | 4722 | #define _PLANE_OFFSET_3_A 0x703a4 |
|
- | 4723 | #define _PLANE_KEYVAL_1_A 0x70194 |
|
- | 4724 | #define _PLANE_KEYVAL_2_A 0x70294 |
|
- | 4725 | #define _PLANE_KEYMSK_1_A 0x70198 |
|
- | 4726 | #define _PLANE_KEYMSK_2_A 0x70298 |
|
- | 4727 | #define _PLANE_KEYMAX_1_A 0x701a0 |
|
- | 4728 | #define _PLANE_KEYMAX_2_A 0x702a0 |
|
- | 4729 | #define _PLANE_BUF_CFG_1_A 0x7027c |
|
- | 4730 | #define _PLANE_BUF_CFG_2_A 0x7037c |
|
- | 4731 | ||
- | 4732 | #define _PLANE_CTL_1_B 0x71180 |
|
- | 4733 | #define _PLANE_CTL_2_B 0x71280 |
|
- | 4734 | #define _PLANE_CTL_3_B 0x71380 |
|
- | 4735 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) |
|
- | 4736 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) |
|
- | 4737 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) |
|
- | 4738 | #define PLANE_CTL(pipe, plane) \ |
|
- | 4739 | _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) |
|
- | 4740 | ||
- | 4741 | #define _PLANE_STRIDE_1_B 0x71188 |
|
- | 4742 | #define _PLANE_STRIDE_2_B 0x71288 |
|
- | 4743 | #define _PLANE_STRIDE_3_B 0x71388 |
|
- | 4744 | #define _PLANE_STRIDE_1(pipe) \ |
|
- | 4745 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) |
|
- | 4746 | #define _PLANE_STRIDE_2(pipe) \ |
|
- | 4747 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) |
|
- | 4748 | #define _PLANE_STRIDE_3(pipe) \ |
|
- | 4749 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) |
|
- | 4750 | #define PLANE_STRIDE(pipe, plane) \ |
|
- | 4751 | _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) |
|
- | 4752 | ||
- | 4753 | #define _PLANE_POS_1_B 0x7118c |
|
- | 4754 | #define _PLANE_POS_2_B 0x7128c |
|
- | 4755 | #define _PLANE_POS_3_B 0x7138c |
|
- | 4756 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) |
|
- | 4757 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) |
|
- | 4758 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) |
|
- | 4759 | #define PLANE_POS(pipe, plane) \ |
|
- | 4760 | _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) |
|
- | 4761 | ||
- | 4762 | #define _PLANE_SIZE_1_B 0x71190 |
|
- | 4763 | #define _PLANE_SIZE_2_B 0x71290 |
|
- | 4764 | #define _PLANE_SIZE_3_B 0x71390 |
|
- | 4765 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) |
|
- | 4766 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) |
|
- | 4767 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) |
|
- | 4768 | #define PLANE_SIZE(pipe, plane) \ |
|
- | 4769 | _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) |
|
- | 4770 | ||
- | 4771 | #define _PLANE_SURF_1_B 0x7119c |
|
- | 4772 | #define _PLANE_SURF_2_B 0x7129c |
|
- | 4773 | #define _PLANE_SURF_3_B 0x7139c |
|
- | 4774 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) |
|
- | 4775 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) |
|
- | 4776 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) |
|
- | 4777 | #define PLANE_SURF(pipe, plane) \ |
|
- | 4778 | _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) |
|
- | 4779 | ||
- | 4780 | #define _PLANE_OFFSET_1_B 0x711a4 |
|
- | 4781 | #define _PLANE_OFFSET_2_B 0x712a4 |
|
- | 4782 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) |
|
- | 4783 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) |
|
- | 4784 | #define PLANE_OFFSET(pipe, plane) \ |
|
- | 4785 | _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) |
|
- | 4786 | ||
- | 4787 | #define _PLANE_KEYVAL_1_B 0x71194 |
|
- | 4788 | #define _PLANE_KEYVAL_2_B 0x71294 |
|
- | 4789 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) |
|
- | 4790 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) |
|
- | 4791 | #define PLANE_KEYVAL(pipe, plane) \ |
|
- | 4792 | _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) |
|
- | 4793 | ||
- | 4794 | #define _PLANE_KEYMSK_1_B 0x71198 |
|
- | 4795 | #define _PLANE_KEYMSK_2_B 0x71298 |
|
- | 4796 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) |
|
- | 4797 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) |
|
- | 4798 | #define PLANE_KEYMSK(pipe, plane) \ |
|
- | 4799 | _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) |
|
- | 4800 | ||
- | 4801 | #define _PLANE_KEYMAX_1_B 0x711a0 |
|
- | 4802 | #define _PLANE_KEYMAX_2_B 0x712a0 |
|
- | 4803 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) |
|
- | 4804 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) |
|
- | 4805 | #define PLANE_KEYMAX(pipe, plane) \ |
|
- | 4806 | _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) |
|
- | 4807 | ||
- | 4808 | #define _PLANE_BUF_CFG_1_B 0x7127c |
|
- | 4809 | #define _PLANE_BUF_CFG_2_B 0x7137c |
|
- | 4810 | #define _PLANE_BUF_CFG_1(pipe) \ |
|
- | 4811 | _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) |
|
- | 4812 | #define _PLANE_BUF_CFG_2(pipe) \ |
|
- | 4813 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) |
|
- | 4814 | #define PLANE_BUF_CFG(pipe, plane) \ |
|
- | 4815 | _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) |
|
- | 4816 | ||
- | 4817 | /* SKL new cursor registers */ |
|
- | 4818 | #define _CUR_BUF_CFG_A 0x7017c |
|
- | 4819 | #define _CUR_BUF_CFG_B 0x7117c |
|
- | 4820 | #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) |
|
4379 | 4821 | ||
4380 | /* VBIOS regs */ |
4822 | /* VBIOS regs */ |
4381 | #define VGACNTRL 0x71400 |
4823 | #define VGACNTRL 0x71400 |
4382 | # define VGA_DISP_DISABLE (1 << 31) |
4824 | # define VGA_DISP_DISABLE (1 << 31) |
4383 | # define VGA_2X_MODE (1 << 30) |
4825 | # define VGA_2X_MODE (1 << 30) |
4384 | # define VGA_PIPE_B_SELECT (1 << 29) |
4826 | # define VGA_PIPE_B_SELECT (1 << 29) |
4385 | 4827 | ||
4386 | #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) |
4828 | #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) |
4387 | 4829 | ||
4388 | /* Ironlake */ |
4830 | /* Ironlake */ |
4389 | 4831 | ||
4390 | #define CPU_VGACNTRL 0x41000 |
4832 | #define CPU_VGACNTRL 0x41000 |
4391 | 4833 | ||
4392 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
4834 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
4393 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
4835 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
4394 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) |
4836 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) |
4395 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) |
4837 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) |
4396 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) |
4838 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) |
4397 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) |
4839 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) |
4398 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) |
4840 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) |
4399 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) |
4841 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) |
4400 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) |
4842 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) |
4401 | 4843 | ||
4402 | /* refresh rate hardware control */ |
4844 | /* refresh rate hardware control */ |
4403 | #define RR_HW_CTL 0x45300 |
4845 | #define RR_HW_CTL 0x45300 |
4404 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
4846 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
4405 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
4847 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
4406 | 4848 | ||
4407 | #define FDI_PLL_BIOS_0 0x46000 |
4849 | #define FDI_PLL_BIOS_0 0x46000 |
4408 | #define FDI_PLL_FB_CLOCK_MASK 0xff |
4850 | #define FDI_PLL_FB_CLOCK_MASK 0xff |
4409 | #define FDI_PLL_BIOS_1 0x46004 |
4851 | #define FDI_PLL_BIOS_1 0x46004 |
4410 | #define FDI_PLL_BIOS_2 0x46008 |
4852 | #define FDI_PLL_BIOS_2 0x46008 |
4411 | #define DISPLAY_PORT_PLL_BIOS_0 0x4600c |
4853 | #define DISPLAY_PORT_PLL_BIOS_0 0x4600c |
4412 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
4854 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
4413 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
4855 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
4414 | 4856 | ||
4415 | #define PCH_3DCGDIS0 0x46020 |
4857 | #define PCH_3DCGDIS0 0x46020 |
4416 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
4858 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
4417 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
4859 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
4418 | 4860 | ||
4419 | #define PCH_3DCGDIS1 0x46024 |
4861 | #define PCH_3DCGDIS1 0x46024 |
4420 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
4862 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
4421 | 4863 | ||
4422 | #define FDI_PLL_FREQ_CTL 0x46030 |
4864 | #define FDI_PLL_FREQ_CTL 0x46030 |
4423 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
4865 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
4424 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
4866 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
4425 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff |
4867 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff |
4426 | 4868 | ||
4427 | 4869 | ||
4428 | #define _PIPEA_DATA_M1 0x60030 |
4870 | #define _PIPEA_DATA_M1 0x60030 |
4429 | #define PIPE_DATA_M1_OFFSET 0 |
4871 | #define PIPE_DATA_M1_OFFSET 0 |
4430 | #define _PIPEA_DATA_N1 0x60034 |
4872 | #define _PIPEA_DATA_N1 0x60034 |
4431 | #define PIPE_DATA_N1_OFFSET 0 |
4873 | #define PIPE_DATA_N1_OFFSET 0 |
4432 | 4874 | ||
4433 | #define _PIPEA_DATA_M2 0x60038 |
4875 | #define _PIPEA_DATA_M2 0x60038 |
4434 | #define PIPE_DATA_M2_OFFSET 0 |
4876 | #define PIPE_DATA_M2_OFFSET 0 |
4435 | #define _PIPEA_DATA_N2 0x6003c |
4877 | #define _PIPEA_DATA_N2 0x6003c |
4436 | #define PIPE_DATA_N2_OFFSET 0 |
4878 | #define PIPE_DATA_N2_OFFSET 0 |
4437 | 4879 | ||
4438 | #define _PIPEA_LINK_M1 0x60040 |
4880 | #define _PIPEA_LINK_M1 0x60040 |
4439 | #define PIPE_LINK_M1_OFFSET 0 |
4881 | #define PIPE_LINK_M1_OFFSET 0 |
4440 | #define _PIPEA_LINK_N1 0x60044 |
4882 | #define _PIPEA_LINK_N1 0x60044 |
4441 | #define PIPE_LINK_N1_OFFSET 0 |
4883 | #define PIPE_LINK_N1_OFFSET 0 |
4442 | 4884 | ||
4443 | #define _PIPEA_LINK_M2 0x60048 |
4885 | #define _PIPEA_LINK_M2 0x60048 |
4444 | #define PIPE_LINK_M2_OFFSET 0 |
4886 | #define PIPE_LINK_M2_OFFSET 0 |
4445 | #define _PIPEA_LINK_N2 0x6004c |
4887 | #define _PIPEA_LINK_N2 0x6004c |
4446 | #define PIPE_LINK_N2_OFFSET 0 |
4888 | #define PIPE_LINK_N2_OFFSET 0 |
4447 | 4889 | ||
4448 | /* PIPEB timing regs are same start from 0x61000 */ |
4890 | /* PIPEB timing regs are same start from 0x61000 */ |
4449 | 4891 | ||
4450 | #define _PIPEB_DATA_M1 0x61030 |
4892 | #define _PIPEB_DATA_M1 0x61030 |
4451 | #define _PIPEB_DATA_N1 0x61034 |
4893 | #define _PIPEB_DATA_N1 0x61034 |
4452 | #define _PIPEB_DATA_M2 0x61038 |
4894 | #define _PIPEB_DATA_M2 0x61038 |
4453 | #define _PIPEB_DATA_N2 0x6103c |
4895 | #define _PIPEB_DATA_N2 0x6103c |
4454 | #define _PIPEB_LINK_M1 0x61040 |
4896 | #define _PIPEB_LINK_M1 0x61040 |
4455 | #define _PIPEB_LINK_N1 0x61044 |
4897 | #define _PIPEB_LINK_N1 0x61044 |
4456 | #define _PIPEB_LINK_M2 0x61048 |
4898 | #define _PIPEB_LINK_M2 0x61048 |
4457 | #define _PIPEB_LINK_N2 0x6104c |
4899 | #define _PIPEB_LINK_N2 0x6104c |
4458 | 4900 | ||
4459 | #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) |
4901 | #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) |
4460 | #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) |
4902 | #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) |
4461 | #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) |
4903 | #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) |
4462 | #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) |
4904 | #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) |
4463 | #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) |
4905 | #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) |
4464 | #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) |
4906 | #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) |
4465 | #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) |
4907 | #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) |
4466 | #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) |
4908 | #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) |
4467 | 4909 | ||
4468 | /* CPU panel fitter */ |
4910 | /* CPU panel fitter */ |
4469 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
4911 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
4470 | #define _PFA_CTL_1 0x68080 |
4912 | #define _PFA_CTL_1 0x68080 |
4471 | #define _PFB_CTL_1 0x68880 |
4913 | #define _PFB_CTL_1 0x68880 |
4472 | #define PF_ENABLE (1<<31) |
4914 | #define PF_ENABLE (1<<31) |
4473 | #define PF_PIPE_SEL_MASK_IVB (3<<29) |
4915 | #define PF_PIPE_SEL_MASK_IVB (3<<29) |
4474 | #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) |
4916 | #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) |
4475 | #define PF_FILTER_MASK (3<<23) |
4917 | #define PF_FILTER_MASK (3<<23) |
4476 | #define PF_FILTER_PROGRAMMED (0<<23) |
4918 | #define PF_FILTER_PROGRAMMED (0<<23) |
4477 | #define PF_FILTER_MED_3x3 (1<<23) |
4919 | #define PF_FILTER_MED_3x3 (1<<23) |
4478 | #define PF_FILTER_EDGE_ENHANCE (2<<23) |
4920 | #define PF_FILTER_EDGE_ENHANCE (2<<23) |
4479 | #define PF_FILTER_EDGE_SOFTEN (3<<23) |
4921 | #define PF_FILTER_EDGE_SOFTEN (3<<23) |
4480 | #define _PFA_WIN_SZ 0x68074 |
4922 | #define _PFA_WIN_SZ 0x68074 |
4481 | #define _PFB_WIN_SZ 0x68874 |
4923 | #define _PFB_WIN_SZ 0x68874 |
4482 | #define _PFA_WIN_POS 0x68070 |
4924 | #define _PFA_WIN_POS 0x68070 |
4483 | #define _PFB_WIN_POS 0x68870 |
4925 | #define _PFB_WIN_POS 0x68870 |
4484 | #define _PFA_VSCALE 0x68084 |
4926 | #define _PFA_VSCALE 0x68084 |
4485 | #define _PFB_VSCALE 0x68884 |
4927 | #define _PFB_VSCALE 0x68884 |
4486 | #define _PFA_HSCALE 0x68090 |
4928 | #define _PFA_HSCALE 0x68090 |
4487 | #define _PFB_HSCALE 0x68890 |
4929 | #define _PFB_HSCALE 0x68890 |
4488 | 4930 | ||
4489 | #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
4931 | #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
4490 | #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) |
4932 | #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) |
4491 | #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) |
4933 | #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) |
4492 | #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
4934 | #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
4493 | #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
4935 | #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
- | 4936 | ||
- | 4937 | #define _PSA_CTL 0x68180 |
|
- | 4938 | #define _PSB_CTL 0x68980 |
|
- | 4939 | #define PS_ENABLE (1<<31) |
|
- | 4940 | #define _PSA_WIN_SZ 0x68174 |
|
- | 4941 | #define _PSB_WIN_SZ 0x68974 |
|
- | 4942 | #define _PSA_WIN_POS 0x68170 |
|
- | 4943 | #define _PSB_WIN_POS 0x68970 |
|
- | 4944 | ||
- | 4945 | #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) |
|
- | 4946 | #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) |
|
- | 4947 | #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) |
|
4494 | 4948 | ||
4495 | /* legacy palette */ |
4949 | /* legacy palette */ |
4496 | #define _LGC_PALETTE_A 0x4a000 |
4950 | #define _LGC_PALETTE_A 0x4a000 |
4497 | #define _LGC_PALETTE_B 0x4a800 |
4951 | #define _LGC_PALETTE_B 0x4a800 |
4498 | #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) |
4952 | #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) |
4499 | 4953 | ||
4500 | #define _GAMMA_MODE_A 0x4a480 |
4954 | #define _GAMMA_MODE_A 0x4a480 |
4501 | #define _GAMMA_MODE_B 0x4ac80 |
4955 | #define _GAMMA_MODE_B 0x4ac80 |
4502 | #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) |
4956 | #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) |
4503 | #define GAMMA_MODE_MODE_MASK (3 << 0) |
4957 | #define GAMMA_MODE_MODE_MASK (3 << 0) |
4504 | #define GAMMA_MODE_MODE_8BIT (0 << 0) |
4958 | #define GAMMA_MODE_MODE_8BIT (0 << 0) |
4505 | #define GAMMA_MODE_MODE_10BIT (1 << 0) |
4959 | #define GAMMA_MODE_MODE_10BIT (1 << 0) |
4506 | #define GAMMA_MODE_MODE_12BIT (2 << 0) |
4960 | #define GAMMA_MODE_MODE_12BIT (2 << 0) |
4507 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
4961 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
4508 | 4962 | ||
4509 | /* interrupts */ |
4963 | /* interrupts */ |
4510 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
4964 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
4511 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
4965 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
4512 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
4966 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
4513 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
4967 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
4514 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
4968 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
4515 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
4969 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
4516 | #define DE_PCU_EVENT (1 << 25) |
4970 | #define DE_PCU_EVENT (1 << 25) |
4517 | #define DE_GTT_FAULT (1 << 24) |
4971 | #define DE_GTT_FAULT (1 << 24) |
4518 | #define DE_POISON (1 << 23) |
4972 | #define DE_POISON (1 << 23) |
4519 | #define DE_PERFORM_COUNTER (1 << 22) |
4973 | #define DE_PERFORM_COUNTER (1 << 22) |
4520 | #define DE_PCH_EVENT (1 << 21) |
4974 | #define DE_PCH_EVENT (1 << 21) |
4521 | #define DE_AUX_CHANNEL_A (1 << 20) |
4975 | #define DE_AUX_CHANNEL_A (1 << 20) |
4522 | #define DE_DP_A_HOTPLUG (1 << 19) |
4976 | #define DE_DP_A_HOTPLUG (1 << 19) |
4523 | #define DE_GSE (1 << 18) |
4977 | #define DE_GSE (1 << 18) |
4524 | #define DE_PIPEB_VBLANK (1 << 15) |
4978 | #define DE_PIPEB_VBLANK (1 << 15) |
4525 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
4979 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
4526 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
4980 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
4527 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
4981 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
4528 | #define DE_PIPEB_VSYNC (1 << 11) |
4982 | #define DE_PIPEB_VSYNC (1 << 11) |
4529 | #define DE_PIPEB_CRC_DONE (1 << 10) |
4983 | #define DE_PIPEB_CRC_DONE (1 << 10) |
4530 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
4984 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
4531 | #define DE_PIPEA_VBLANK (1 << 7) |
4985 | #define DE_PIPEA_VBLANK (1 << 7) |
4532 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) |
4986 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) |
4533 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
4987 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
4534 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
4988 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
4535 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
4989 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
4536 | #define DE_PIPEA_VSYNC (1 << 3) |
4990 | #define DE_PIPEA_VSYNC (1 << 3) |
4537 | #define DE_PIPEA_CRC_DONE (1 << 2) |
4991 | #define DE_PIPEA_CRC_DONE (1 << 2) |
4538 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) |
4992 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) |
4539 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
4993 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
4540 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) |
4994 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) |
4541 | 4995 | ||
4542 | /* More Ivybridge lolz */ |
4996 | /* More Ivybridge lolz */ |
4543 | #define DE_ERR_INT_IVB (1<<30) |
4997 | #define DE_ERR_INT_IVB (1<<30) |
4544 | #define DE_GSE_IVB (1<<29) |
4998 | #define DE_GSE_IVB (1<<29) |
4545 | #define DE_PCH_EVENT_IVB (1<<28) |
4999 | #define DE_PCH_EVENT_IVB (1<<28) |
4546 | #define DE_DP_A_HOTPLUG_IVB (1<<27) |
5000 | #define DE_DP_A_HOTPLUG_IVB (1<<27) |
4547 | #define DE_AUX_CHANNEL_A_IVB (1<<26) |
5001 | #define DE_AUX_CHANNEL_A_IVB (1<<26) |
4548 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
5002 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
4549 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) |
5003 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) |
4550 | #define DE_PIPEC_VBLANK_IVB (1<<10) |
5004 | #define DE_PIPEC_VBLANK_IVB (1<<10) |
4551 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
5005 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
4552 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
5006 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
4553 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
5007 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
4554 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
5008 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
4555 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
5009 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
4556 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
5010 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
4557 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
5011 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
4558 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) |
5012 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) |
4559 | 5013 | ||
4560 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
5014 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
4561 | #define MASTER_INTERRUPT_ENABLE (1<<31) |
5015 | #define MASTER_INTERRUPT_ENABLE (1<<31) |
4562 | 5016 | ||
4563 | #define DEISR 0x44000 |
5017 | #define DEISR 0x44000 |
4564 | #define DEIMR 0x44004 |
5018 | #define DEIMR 0x44004 |
4565 | #define DEIIR 0x44008 |
5019 | #define DEIIR 0x44008 |
4566 | #define DEIER 0x4400c |
5020 | #define DEIER 0x4400c |
4567 | 5021 | ||
4568 | #define GTISR 0x44010 |
5022 | #define GTISR 0x44010 |
4569 | #define GTIMR 0x44014 |
5023 | #define GTIMR 0x44014 |
4570 | #define GTIIR 0x44018 |
5024 | #define GTIIR 0x44018 |
4571 | #define GTIER 0x4401c |
5025 | #define GTIER 0x4401c |
4572 | 5026 | ||
4573 | #define GEN8_MASTER_IRQ 0x44200 |
5027 | #define GEN8_MASTER_IRQ 0x44200 |
4574 | #define GEN8_MASTER_IRQ_CONTROL (1<<31) |
5028 | #define GEN8_MASTER_IRQ_CONTROL (1<<31) |
4575 | #define GEN8_PCU_IRQ (1<<30) |
5029 | #define GEN8_PCU_IRQ (1<<30) |
4576 | #define GEN8_DE_PCH_IRQ (1<<23) |
5030 | #define GEN8_DE_PCH_IRQ (1<<23) |
4577 | #define GEN8_DE_MISC_IRQ (1<<22) |
5031 | #define GEN8_DE_MISC_IRQ (1<<22) |
4578 | #define GEN8_DE_PORT_IRQ (1<<20) |
5032 | #define GEN8_DE_PORT_IRQ (1<<20) |
4579 | #define GEN8_DE_PIPE_C_IRQ (1<<18) |
5033 | #define GEN8_DE_PIPE_C_IRQ (1<<18) |
4580 | #define GEN8_DE_PIPE_B_IRQ (1<<17) |
5034 | #define GEN8_DE_PIPE_B_IRQ (1<<17) |
4581 | #define GEN8_DE_PIPE_A_IRQ (1<<16) |
5035 | #define GEN8_DE_PIPE_A_IRQ (1<<16) |
4582 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) |
5036 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) |
4583 | #define GEN8_GT_VECS_IRQ (1<<6) |
5037 | #define GEN8_GT_VECS_IRQ (1<<6) |
4584 | #define GEN8_GT_PM_IRQ (1<<4) |
5038 | #define GEN8_GT_PM_IRQ (1<<4) |
4585 | #define GEN8_GT_VCS2_IRQ (1<<3) |
5039 | #define GEN8_GT_VCS2_IRQ (1<<3) |
4586 | #define GEN8_GT_VCS1_IRQ (1<<2) |
5040 | #define GEN8_GT_VCS1_IRQ (1<<2) |
4587 | #define GEN8_GT_BCS_IRQ (1<<1) |
5041 | #define GEN8_GT_BCS_IRQ (1<<1) |
4588 | #define GEN8_GT_RCS_IRQ (1<<0) |
5042 | #define GEN8_GT_RCS_IRQ (1<<0) |
4589 | 5043 | ||
4590 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) |
5044 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) |
4591 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) |
5045 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) |
4592 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) |
5046 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) |
4593 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) |
5047 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) |
4594 | 5048 | ||
4595 | #define GEN8_BCS_IRQ_SHIFT 16 |
5049 | #define GEN8_BCS_IRQ_SHIFT 16 |
4596 | #define GEN8_RCS_IRQ_SHIFT 0 |
5050 | #define GEN8_RCS_IRQ_SHIFT 0 |
4597 | #define GEN8_VCS2_IRQ_SHIFT 16 |
5051 | #define GEN8_VCS2_IRQ_SHIFT 16 |
4598 | #define GEN8_VCS1_IRQ_SHIFT 0 |
5052 | #define GEN8_VCS1_IRQ_SHIFT 0 |
4599 | #define GEN8_VECS_IRQ_SHIFT 0 |
5053 | #define GEN8_VECS_IRQ_SHIFT 0 |
4600 | 5054 | ||
4601 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) |
5055 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) |
4602 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) |
5056 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) |
4603 | #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) |
5057 | #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) |
4604 | #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) |
5058 | #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) |
4605 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
5059 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
4606 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
5060 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
4607 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) |
5061 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) |
4608 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) |
5062 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) |
4609 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) |
5063 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) |
4610 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) |
5064 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) |
4611 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) |
5065 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) |
4612 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
5066 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
4613 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
5067 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
4614 | #define GEN8_PIPE_VSYNC (1 << 1) |
5068 | #define GEN8_PIPE_VSYNC (1 << 1) |
4615 | #define GEN8_PIPE_VBLANK (1 << 0) |
5069 | #define GEN8_PIPE_VBLANK (1 << 0) |
- | 5070 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
|
- | 5071 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
|
- | 5072 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) |
|
- | 5073 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) |
|
- | 5074 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
|
- | 5075 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) |
|
- | 5076 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) |
|
- | 5077 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) |
|
4616 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
5078 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
4617 | (GEN8_PIPE_CURSOR_FAULT | \ |
5079 | (GEN8_PIPE_CURSOR_FAULT | \ |
4618 | GEN8_PIPE_SPRITE_FAULT | \ |
5080 | GEN8_PIPE_SPRITE_FAULT | \ |
4619 | GEN8_PIPE_PRIMARY_FAULT) |
5081 | GEN8_PIPE_PRIMARY_FAULT) |
- | 5082 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
|
- | 5083 | (GEN9_PIPE_CURSOR_FAULT | \ |
|
- | 5084 | GEN9_PIPE_PLANE3_FAULT | \ |
|
- | 5085 | GEN9_PIPE_PLANE2_FAULT | \ |
|
- | 5086 | GEN9_PIPE_PLANE1_FAULT) |
|
4620 | 5087 | ||
4621 | #define GEN8_DE_PORT_ISR 0x44440 |
5088 | #define GEN8_DE_PORT_ISR 0x44440 |
4622 | #define GEN8_DE_PORT_IMR 0x44444 |
5089 | #define GEN8_DE_PORT_IMR 0x44444 |
4623 | #define GEN8_DE_PORT_IIR 0x44448 |
5090 | #define GEN8_DE_PORT_IIR 0x44448 |
4624 | #define GEN8_DE_PORT_IER 0x4444c |
5091 | #define GEN8_DE_PORT_IER 0x4444c |
4625 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
5092 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
- | 5093 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
|
- | 5094 | #define GEN9_AUX_CHANNEL_C (1 << 26) |
|
- | 5095 | #define GEN9_AUX_CHANNEL_B (1 << 25) |
|
4626 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
5096 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
4627 | 5097 | ||
4628 | #define GEN8_DE_MISC_ISR 0x44460 |
5098 | #define GEN8_DE_MISC_ISR 0x44460 |
4629 | #define GEN8_DE_MISC_IMR 0x44464 |
5099 | #define GEN8_DE_MISC_IMR 0x44464 |
4630 | #define GEN8_DE_MISC_IIR 0x44468 |
5100 | #define GEN8_DE_MISC_IIR 0x44468 |
4631 | #define GEN8_DE_MISC_IER 0x4446c |
5101 | #define GEN8_DE_MISC_IER 0x4446c |
4632 | #define GEN8_DE_MISC_GSE (1 << 27) |
5102 | #define GEN8_DE_MISC_GSE (1 << 27) |
4633 | 5103 | ||
4634 | #define GEN8_PCU_ISR 0x444e0 |
5104 | #define GEN8_PCU_ISR 0x444e0 |
4635 | #define GEN8_PCU_IMR 0x444e4 |
5105 | #define GEN8_PCU_IMR 0x444e4 |
4636 | #define GEN8_PCU_IIR 0x444e8 |
5106 | #define GEN8_PCU_IIR 0x444e8 |
4637 | #define GEN8_PCU_IER 0x444ec |
5107 | #define GEN8_PCU_IER 0x444ec |
4638 | 5108 | ||
4639 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
5109 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
4640 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
5110 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
4641 | #define ILK_ELPIN_409_SELECT (1 << 25) |
5111 | #define ILK_ELPIN_409_SELECT (1 << 25) |
4642 | #define ILK_DPARB_GATE (1<<22) |
5112 | #define ILK_DPARB_GATE (1<<22) |
4643 | #define ILK_VSDPFD_FULL (1<<21) |
5113 | #define ILK_VSDPFD_FULL (1<<21) |
4644 | #define FUSE_STRAP 0x42014 |
5114 | #define FUSE_STRAP 0x42014 |
4645 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
5115 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
4646 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) |
5116 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) |
4647 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) |
5117 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) |
4648 | #define ILK_HDCP_DISABLE (1 << 25) |
5118 | #define ILK_HDCP_DISABLE (1 << 25) |
4649 | #define ILK_eDP_A_DISABLE (1 << 24) |
5119 | #define ILK_eDP_A_DISABLE (1 << 24) |
4650 | #define HSW_CDCLK_LIMIT (1 << 24) |
5120 | #define HSW_CDCLK_LIMIT (1 << 24) |
4651 | #define ILK_DESKTOP (1 << 23) |
5121 | #define ILK_DESKTOP (1 << 23) |
4652 | 5122 | ||
4653 | #define ILK_DSPCLK_GATE_D 0x42020 |
5123 | #define ILK_DSPCLK_GATE_D 0x42020 |
4654 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
5124 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
4655 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
5125 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
4656 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) |
5126 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) |
4657 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) |
5127 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) |
4658 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) |
5128 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) |
4659 | 5129 | ||
4660 | #define IVB_CHICKEN3 0x4200c |
5130 | #define IVB_CHICKEN3 0x4200c |
4661 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
5131 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
4662 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
5132 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
4663 | 5133 | ||
4664 | #define CHICKEN_PAR1_1 0x42080 |
5134 | #define CHICKEN_PAR1_1 0x42080 |
4665 | #define DPA_MASK_VBLANK_SRD (1 << 15) |
5135 | #define DPA_MASK_VBLANK_SRD (1 << 15) |
4666 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
5136 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
4667 | 5137 | ||
4668 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
5138 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
4669 | #define _CHICKEN_PIPESL_1_B 0x420b4 |
5139 | #define _CHICKEN_PIPESL_1_B 0x420b4 |
4670 | #define HSW_FBCQ_DIS (1 << 22) |
5140 | #define HSW_FBCQ_DIS (1 << 22) |
4671 | #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) |
5141 | #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) |
4672 | #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
5142 | #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
4673 | 5143 | ||
4674 | #define DISP_ARB_CTL 0x45000 |
5144 | #define DISP_ARB_CTL 0x45000 |
4675 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
5145 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
4676 | #define DISP_FBC_WM_DIS (1<<15) |
5146 | #define DISP_FBC_WM_DIS (1<<15) |
4677 | #define DISP_ARB_CTL2 0x45004 |
5147 | #define DISP_ARB_CTL2 0x45004 |
4678 | #define DISP_DATA_PARTITION_5_6 (1<<6) |
5148 | #define DISP_DATA_PARTITION_5_6 (1<<6) |
4679 | #define GEN7_MSG_CTL 0x45010 |
5149 | #define GEN7_MSG_CTL 0x45010 |
4680 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
5150 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
4681 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) |
5151 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) |
4682 | #define HSW_NDE_RSTWRN_OPT 0x46408 |
5152 | #define HSW_NDE_RSTWRN_OPT 0x46408 |
4683 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
5153 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
4684 | 5154 | ||
4685 | /* GEN7 chicken */ |
5155 | /* GEN7 chicken */ |
4686 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
5156 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
4687 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
5157 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
4688 | #define COMMON_SLICE_CHICKEN2 0x7014 |
5158 | #define COMMON_SLICE_CHICKEN2 0x7014 |
4689 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
5159 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
4690 | 5160 | ||
4691 | #define GEN7_L3SQCREG1 0xB010 |
5161 | #define GEN7_L3SQCREG1 0xB010 |
4692 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
5162 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
4693 | 5163 | ||
4694 | #define GEN7_L3CNTLREG1 0xB01C |
5164 | #define GEN7_L3CNTLREG1 0xB01C |
4695 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
5165 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
4696 | #define GEN7_L3AGDIS (1<<19) |
5166 | #define GEN7_L3AGDIS (1<<19) |
4697 | #define GEN7_L3CNTLREG2 0xB020 |
5167 | #define GEN7_L3CNTLREG2 0xB020 |
4698 | #define GEN7_L3CNTLREG3 0xB024 |
5168 | #define GEN7_L3CNTLREG3 0xB024 |
4699 | 5169 | ||
4700 | #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 |
5170 | #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 |
4701 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
5171 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
4702 | 5172 | ||
4703 | #define GEN7_L3SQCREG4 0xb034 |
5173 | #define GEN7_L3SQCREG4 0xb034 |
4704 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
5174 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
4705 | 5175 | ||
4706 | /* GEN8 chicken */ |
5176 | /* GEN8 chicken */ |
4707 | #define HDC_CHICKEN0 0x7300 |
5177 | #define HDC_CHICKEN0 0x7300 |
4708 | #define HDC_FORCE_NON_COHERENT (1<<4) |
5178 | #define HDC_FORCE_NON_COHERENT (1<<4) |
- | 5179 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
|
- | 5180 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
|
4709 | 5181 | ||
4710 | /* WaCatErrorRejectionIssue */ |
5182 | /* WaCatErrorRejectionIssue */ |
4711 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
5183 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
4712 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
5184 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
4713 | 5185 | ||
4714 | #define HSW_SCRATCH1 0xb038 |
5186 | #define HSW_SCRATCH1 0xb038 |
4715 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) |
5187 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) |
4716 | 5188 | ||
4717 | /* PCH */ |
5189 | /* PCH */ |
4718 | 5190 | ||
4719 | /* south display engine interrupt: IBX */ |
5191 | /* south display engine interrupt: IBX */ |
4720 | #define SDE_AUDIO_POWER_D (1 << 27) |
5192 | #define SDE_AUDIO_POWER_D (1 << 27) |
4721 | #define SDE_AUDIO_POWER_C (1 << 26) |
5193 | #define SDE_AUDIO_POWER_C (1 << 26) |
4722 | #define SDE_AUDIO_POWER_B (1 << 25) |
5194 | #define SDE_AUDIO_POWER_B (1 << 25) |
4723 | #define SDE_AUDIO_POWER_SHIFT (25) |
5195 | #define SDE_AUDIO_POWER_SHIFT (25) |
4724 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) |
5196 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) |
4725 | #define SDE_GMBUS (1 << 24) |
5197 | #define SDE_GMBUS (1 << 24) |
4726 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) |
5198 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) |
4727 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) |
5199 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) |
4728 | #define SDE_AUDIO_HDCP_MASK (3 << 22) |
5200 | #define SDE_AUDIO_HDCP_MASK (3 << 22) |
4729 | #define SDE_AUDIO_TRANSB (1 << 21) |
5201 | #define SDE_AUDIO_TRANSB (1 << 21) |
4730 | #define SDE_AUDIO_TRANSA (1 << 20) |
5202 | #define SDE_AUDIO_TRANSA (1 << 20) |
4731 | #define SDE_AUDIO_TRANS_MASK (3 << 20) |
5203 | #define SDE_AUDIO_TRANS_MASK (3 << 20) |
4732 | #define SDE_POISON (1 << 19) |
5204 | #define SDE_POISON (1 << 19) |
4733 | /* 18 reserved */ |
5205 | /* 18 reserved */ |
4734 | #define SDE_FDI_RXB (1 << 17) |
5206 | #define SDE_FDI_RXB (1 << 17) |
4735 | #define SDE_FDI_RXA (1 << 16) |
5207 | #define SDE_FDI_RXA (1 << 16) |
4736 | #define SDE_FDI_MASK (3 << 16) |
5208 | #define SDE_FDI_MASK (3 << 16) |
4737 | #define SDE_AUXD (1 << 15) |
5209 | #define SDE_AUXD (1 << 15) |
4738 | #define SDE_AUXC (1 << 14) |
5210 | #define SDE_AUXC (1 << 14) |
4739 | #define SDE_AUXB (1 << 13) |
5211 | #define SDE_AUXB (1 << 13) |
4740 | #define SDE_AUX_MASK (7 << 13) |
5212 | #define SDE_AUX_MASK (7 << 13) |
4741 | /* 12 reserved */ |
5213 | /* 12 reserved */ |
4742 | #define SDE_CRT_HOTPLUG (1 << 11) |
5214 | #define SDE_CRT_HOTPLUG (1 << 11) |
4743 | #define SDE_PORTD_HOTPLUG (1 << 10) |
5215 | #define SDE_PORTD_HOTPLUG (1 << 10) |
4744 | #define SDE_PORTC_HOTPLUG (1 << 9) |
5216 | #define SDE_PORTC_HOTPLUG (1 << 9) |
4745 | #define SDE_PORTB_HOTPLUG (1 << 8) |
5217 | #define SDE_PORTB_HOTPLUG (1 << 8) |
4746 | #define SDE_SDVOB_HOTPLUG (1 << 6) |
5218 | #define SDE_SDVOB_HOTPLUG (1 << 6) |
4747 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
5219 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
4748 | SDE_SDVOB_HOTPLUG | \ |
5220 | SDE_SDVOB_HOTPLUG | \ |
4749 | SDE_PORTB_HOTPLUG | \ |
5221 | SDE_PORTB_HOTPLUG | \ |
4750 | SDE_PORTC_HOTPLUG | \ |
5222 | SDE_PORTC_HOTPLUG | \ |
4751 | SDE_PORTD_HOTPLUG) |
5223 | SDE_PORTD_HOTPLUG) |
4752 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
5224 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
4753 | #define SDE_TRANSB_CRC_ERR (1 << 4) |
5225 | #define SDE_TRANSB_CRC_ERR (1 << 4) |
4754 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) |
5226 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) |
4755 | #define SDE_TRANSA_CRC_DONE (1 << 2) |
5227 | #define SDE_TRANSA_CRC_DONE (1 << 2) |
4756 | #define SDE_TRANSA_CRC_ERR (1 << 1) |
5228 | #define SDE_TRANSA_CRC_ERR (1 << 1) |
4757 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) |
5229 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) |
4758 | #define SDE_TRANS_MASK (0x3f) |
5230 | #define SDE_TRANS_MASK (0x3f) |
4759 | 5231 | ||
4760 | /* south display engine interrupt: CPT/PPT */ |
5232 | /* south display engine interrupt: CPT/PPT */ |
4761 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) |
5233 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) |
4762 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) |
5234 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) |
4763 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) |
5235 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) |
4764 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 |
5236 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 |
4765 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
5237 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
4766 | #define SDE_AUXD_CPT (1 << 27) |
5238 | #define SDE_AUXD_CPT (1 << 27) |
4767 | #define SDE_AUXC_CPT (1 << 26) |
5239 | #define SDE_AUXC_CPT (1 << 26) |
4768 | #define SDE_AUXB_CPT (1 << 25) |
5240 | #define SDE_AUXB_CPT (1 << 25) |
4769 | #define SDE_AUX_MASK_CPT (7 << 25) |
5241 | #define SDE_AUX_MASK_CPT (7 << 25) |
4770 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
5242 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
4771 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
5243 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
4772 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
5244 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
4773 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
5245 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
4774 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
5246 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
4775 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
5247 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
4776 | SDE_SDVOB_HOTPLUG_CPT | \ |
5248 | SDE_SDVOB_HOTPLUG_CPT | \ |
4777 | SDE_PORTD_HOTPLUG_CPT | \ |
5249 | SDE_PORTD_HOTPLUG_CPT | \ |
4778 | SDE_PORTC_HOTPLUG_CPT | \ |
5250 | SDE_PORTC_HOTPLUG_CPT | \ |
4779 | SDE_PORTB_HOTPLUG_CPT) |
5251 | SDE_PORTB_HOTPLUG_CPT) |
4780 | #define SDE_GMBUS_CPT (1 << 17) |
5252 | #define SDE_GMBUS_CPT (1 << 17) |
4781 | #define SDE_ERROR_CPT (1 << 16) |
5253 | #define SDE_ERROR_CPT (1 << 16) |
4782 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
5254 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
4783 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
5255 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
4784 | #define SDE_FDI_RXC_CPT (1 << 8) |
5256 | #define SDE_FDI_RXC_CPT (1 << 8) |
4785 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
5257 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
4786 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
5258 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
4787 | #define SDE_FDI_RXB_CPT (1 << 4) |
5259 | #define SDE_FDI_RXB_CPT (1 << 4) |
4788 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
5260 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
4789 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
5261 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
4790 | #define SDE_FDI_RXA_CPT (1 << 0) |
5262 | #define SDE_FDI_RXA_CPT (1 << 0) |
4791 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ |
5263 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ |
4792 | SDE_AUDIO_CP_REQ_B_CPT | \ |
5264 | SDE_AUDIO_CP_REQ_B_CPT | \ |
4793 | SDE_AUDIO_CP_REQ_A_CPT) |
5265 | SDE_AUDIO_CP_REQ_A_CPT) |
4794 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ |
5266 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ |
4795 | SDE_AUDIO_CP_CHG_B_CPT | \ |
5267 | SDE_AUDIO_CP_CHG_B_CPT | \ |
4796 | SDE_AUDIO_CP_CHG_A_CPT) |
5268 | SDE_AUDIO_CP_CHG_A_CPT) |
4797 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ |
5269 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ |
4798 | SDE_FDI_RXB_CPT | \ |
5270 | SDE_FDI_RXB_CPT | \ |
4799 | SDE_FDI_RXA_CPT) |
5271 | SDE_FDI_RXA_CPT) |
4800 | 5272 | ||
4801 | #define SDEISR 0xc4000 |
5273 | #define SDEISR 0xc4000 |
4802 | #define SDEIMR 0xc4004 |
5274 | #define SDEIMR 0xc4004 |
4803 | #define SDEIIR 0xc4008 |
5275 | #define SDEIIR 0xc4008 |
4804 | #define SDEIER 0xc400c |
5276 | #define SDEIER 0xc400c |
4805 | 5277 | ||
4806 | #define SERR_INT 0xc4040 |
5278 | #define SERR_INT 0xc4040 |
4807 | #define SERR_INT_POISON (1<<31) |
5279 | #define SERR_INT_POISON (1<<31) |
4808 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
5280 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
4809 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) |
5281 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) |
4810 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) |
5282 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) |
4811 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
5283 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
4812 | 5284 | ||
4813 | /* digital port hotplug */ |
5285 | /* digital port hotplug */ |
4814 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
5286 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
4815 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
5287 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
4816 | #define PORTD_PULSE_DURATION_2ms (0) |
5288 | #define PORTD_PULSE_DURATION_2ms (0) |
4817 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) |
5289 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) |
4818 | #define PORTD_PULSE_DURATION_6ms (2 << 18) |
5290 | #define PORTD_PULSE_DURATION_6ms (2 << 18) |
4819 | #define PORTD_PULSE_DURATION_100ms (3 << 18) |
5291 | #define PORTD_PULSE_DURATION_100ms (3 << 18) |
4820 | #define PORTD_PULSE_DURATION_MASK (3 << 18) |
5292 | #define PORTD_PULSE_DURATION_MASK (3 << 18) |
4821 | #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) |
5293 | #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) |
4822 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
5294 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
4823 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
5295 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
4824 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) |
5296 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) |
4825 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
5297 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
4826 | #define PORTC_PULSE_DURATION_2ms (0) |
5298 | #define PORTC_PULSE_DURATION_2ms (0) |
4827 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) |
5299 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) |
4828 | #define PORTC_PULSE_DURATION_6ms (2 << 10) |
5300 | #define PORTC_PULSE_DURATION_6ms (2 << 10) |
4829 | #define PORTC_PULSE_DURATION_100ms (3 << 10) |
5301 | #define PORTC_PULSE_DURATION_100ms (3 << 10) |
4830 | #define PORTC_PULSE_DURATION_MASK (3 << 10) |
5302 | #define PORTC_PULSE_DURATION_MASK (3 << 10) |
4831 | #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) |
5303 | #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) |
4832 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
5304 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
4833 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
5305 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
4834 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) |
5306 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) |
4835 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
5307 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
4836 | #define PORTB_PULSE_DURATION_2ms (0) |
5308 | #define PORTB_PULSE_DURATION_2ms (0) |
4837 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) |
5309 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) |
4838 | #define PORTB_PULSE_DURATION_6ms (2 << 2) |
5310 | #define PORTB_PULSE_DURATION_6ms (2 << 2) |
4839 | #define PORTB_PULSE_DURATION_100ms (3 << 2) |
5311 | #define PORTB_PULSE_DURATION_100ms (3 << 2) |
4840 | #define PORTB_PULSE_DURATION_MASK (3 << 2) |
5312 | #define PORTB_PULSE_DURATION_MASK (3 << 2) |
4841 | #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) |
5313 | #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) |
4842 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
5314 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
4843 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
5315 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
4844 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) |
5316 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) |
4845 | 5317 | ||
4846 | #define PCH_GPIOA 0xc5010 |
5318 | #define PCH_GPIOA 0xc5010 |
4847 | #define PCH_GPIOB 0xc5014 |
5319 | #define PCH_GPIOB 0xc5014 |
4848 | #define PCH_GPIOC 0xc5018 |
5320 | #define PCH_GPIOC 0xc5018 |
4849 | #define PCH_GPIOD 0xc501c |
5321 | #define PCH_GPIOD 0xc501c |
4850 | #define PCH_GPIOE 0xc5020 |
5322 | #define PCH_GPIOE 0xc5020 |
4851 | #define PCH_GPIOF 0xc5024 |
5323 | #define PCH_GPIOF 0xc5024 |
4852 | 5324 | ||
4853 | #define PCH_GMBUS0 0xc5100 |
5325 | #define PCH_GMBUS0 0xc5100 |
4854 | #define PCH_GMBUS1 0xc5104 |
5326 | #define PCH_GMBUS1 0xc5104 |
4855 | #define PCH_GMBUS2 0xc5108 |
5327 | #define PCH_GMBUS2 0xc5108 |
4856 | #define PCH_GMBUS3 0xc510c |
5328 | #define PCH_GMBUS3 0xc510c |
4857 | #define PCH_GMBUS4 0xc5110 |
5329 | #define PCH_GMBUS4 0xc5110 |
4858 | #define PCH_GMBUS5 0xc5120 |
5330 | #define PCH_GMBUS5 0xc5120 |
4859 | 5331 | ||
4860 | #define _PCH_DPLL_A 0xc6014 |
5332 | #define _PCH_DPLL_A 0xc6014 |
4861 | #define _PCH_DPLL_B 0xc6018 |
5333 | #define _PCH_DPLL_B 0xc6018 |
4862 | #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
5334 | #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
4863 | 5335 | ||
4864 | #define _PCH_FPA0 0xc6040 |
5336 | #define _PCH_FPA0 0xc6040 |
4865 | #define FP_CB_TUNE (0x3<<22) |
5337 | #define FP_CB_TUNE (0x3<<22) |
4866 | #define _PCH_FPA1 0xc6044 |
5338 | #define _PCH_FPA1 0xc6044 |
4867 | #define _PCH_FPB0 0xc6048 |
5339 | #define _PCH_FPB0 0xc6048 |
4868 | #define _PCH_FPB1 0xc604c |
5340 | #define _PCH_FPB1 0xc604c |
4869 | #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
5341 | #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
4870 | #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) |
5342 | #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) |
4871 | 5343 | ||
4872 | #define PCH_DPLL_TEST 0xc606c |
5344 | #define PCH_DPLL_TEST 0xc606c |
4873 | 5345 | ||
4874 | #define PCH_DREF_CONTROL 0xC6200 |
5346 | #define PCH_DREF_CONTROL 0xC6200 |
4875 | #define DREF_CONTROL_MASK 0x7fc3 |
5347 | #define DREF_CONTROL_MASK 0x7fc3 |
4876 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) |
5348 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) |
4877 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) |
5349 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) |
4878 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) |
5350 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) |
4879 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) |
5351 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) |
4880 | #define DREF_SSC_SOURCE_DISABLE (0<<11) |
5352 | #define DREF_SSC_SOURCE_DISABLE (0<<11) |
4881 | #define DREF_SSC_SOURCE_ENABLE (2<<11) |
5353 | #define DREF_SSC_SOURCE_ENABLE (2<<11) |
4882 | #define DREF_SSC_SOURCE_MASK (3<<11) |
5354 | #define DREF_SSC_SOURCE_MASK (3<<11) |
4883 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
5355 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
4884 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) |
5356 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) |
4885 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) |
5357 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) |
4886 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
5358 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
4887 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
5359 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
4888 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) |
5360 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) |
4889 | #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
5361 | #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
4890 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
5362 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
4891 | #define DREF_SSC4_CENTERSPREAD (1<<6) |
5363 | #define DREF_SSC4_CENTERSPREAD (1<<6) |
4892 | #define DREF_SSC1_DISABLE (0<<1) |
5364 | #define DREF_SSC1_DISABLE (0<<1) |
4893 | #define DREF_SSC1_ENABLE (1<<1) |
5365 | #define DREF_SSC1_ENABLE (1<<1) |
4894 | #define DREF_SSC4_DISABLE (0) |
5366 | #define DREF_SSC4_DISABLE (0) |
4895 | #define DREF_SSC4_ENABLE (1) |
5367 | #define DREF_SSC4_ENABLE (1) |
4896 | 5368 | ||
4897 | #define PCH_RAWCLK_FREQ 0xc6204 |
5369 | #define PCH_RAWCLK_FREQ 0xc6204 |
4898 | #define FDL_TP1_TIMER_SHIFT 12 |
5370 | #define FDL_TP1_TIMER_SHIFT 12 |
4899 | #define FDL_TP1_TIMER_MASK (3<<12) |
5371 | #define FDL_TP1_TIMER_MASK (3<<12) |
4900 | #define FDL_TP2_TIMER_SHIFT 10 |
5372 | #define FDL_TP2_TIMER_SHIFT 10 |
4901 | #define FDL_TP2_TIMER_MASK (3<<10) |
5373 | #define FDL_TP2_TIMER_MASK (3<<10) |
4902 | #define RAWCLK_FREQ_MASK 0x3ff |
5374 | #define RAWCLK_FREQ_MASK 0x3ff |
4903 | 5375 | ||
4904 | #define PCH_DPLL_TMR_CFG 0xc6208 |
5376 | #define PCH_DPLL_TMR_CFG 0xc6208 |
4905 | 5377 | ||
4906 | #define PCH_SSC4_PARMS 0xc6210 |
5378 | #define PCH_SSC4_PARMS 0xc6210 |
4907 | #define PCH_SSC4_AUX_PARMS 0xc6214 |
5379 | #define PCH_SSC4_AUX_PARMS 0xc6214 |
4908 | 5380 | ||
4909 | #define PCH_DPLL_SEL 0xc7000 |
5381 | #define PCH_DPLL_SEL 0xc7000 |
4910 | #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) |
5382 | #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) |
4911 | #define TRANS_DPLLA_SEL(pipe) 0 |
5383 | #define TRANS_DPLLA_SEL(pipe) 0 |
4912 | #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) |
5384 | #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) |
4913 | 5385 | ||
4914 | /* transcoder */ |
5386 | /* transcoder */ |
4915 | 5387 | ||
4916 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
5388 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
4917 | #define TRANS_HTOTAL_SHIFT 16 |
5389 | #define TRANS_HTOTAL_SHIFT 16 |
4918 | #define TRANS_HACTIVE_SHIFT 0 |
5390 | #define TRANS_HACTIVE_SHIFT 0 |
4919 | #define _PCH_TRANS_HBLANK_A 0xe0004 |
5391 | #define _PCH_TRANS_HBLANK_A 0xe0004 |
4920 | #define TRANS_HBLANK_END_SHIFT 16 |
5392 | #define TRANS_HBLANK_END_SHIFT 16 |
4921 | #define TRANS_HBLANK_START_SHIFT 0 |
5393 | #define TRANS_HBLANK_START_SHIFT 0 |
4922 | #define _PCH_TRANS_HSYNC_A 0xe0008 |
5394 | #define _PCH_TRANS_HSYNC_A 0xe0008 |
4923 | #define TRANS_HSYNC_END_SHIFT 16 |
5395 | #define TRANS_HSYNC_END_SHIFT 16 |
4924 | #define TRANS_HSYNC_START_SHIFT 0 |
5396 | #define TRANS_HSYNC_START_SHIFT 0 |
4925 | #define _PCH_TRANS_VTOTAL_A 0xe000c |
5397 | #define _PCH_TRANS_VTOTAL_A 0xe000c |
4926 | #define TRANS_VTOTAL_SHIFT 16 |
5398 | #define TRANS_VTOTAL_SHIFT 16 |
4927 | #define TRANS_VACTIVE_SHIFT 0 |
5399 | #define TRANS_VACTIVE_SHIFT 0 |
4928 | #define _PCH_TRANS_VBLANK_A 0xe0010 |
5400 | #define _PCH_TRANS_VBLANK_A 0xe0010 |
4929 | #define TRANS_VBLANK_END_SHIFT 16 |
5401 | #define TRANS_VBLANK_END_SHIFT 16 |
4930 | #define TRANS_VBLANK_START_SHIFT 0 |
5402 | #define TRANS_VBLANK_START_SHIFT 0 |
4931 | #define _PCH_TRANS_VSYNC_A 0xe0014 |
5403 | #define _PCH_TRANS_VSYNC_A 0xe0014 |
4932 | #define TRANS_VSYNC_END_SHIFT 16 |
5404 | #define TRANS_VSYNC_END_SHIFT 16 |
4933 | #define TRANS_VSYNC_START_SHIFT 0 |
5405 | #define TRANS_VSYNC_START_SHIFT 0 |
4934 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 |
5406 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 |
4935 | 5407 | ||
4936 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
5408 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
4937 | #define _PCH_TRANSA_DATA_N1 0xe0034 |
5409 | #define _PCH_TRANSA_DATA_N1 0xe0034 |
4938 | #define _PCH_TRANSA_DATA_M2 0xe0038 |
5410 | #define _PCH_TRANSA_DATA_M2 0xe0038 |
4939 | #define _PCH_TRANSA_DATA_N2 0xe003c |
5411 | #define _PCH_TRANSA_DATA_N2 0xe003c |
4940 | #define _PCH_TRANSA_LINK_M1 0xe0040 |
5412 | #define _PCH_TRANSA_LINK_M1 0xe0040 |
4941 | #define _PCH_TRANSA_LINK_N1 0xe0044 |
5413 | #define _PCH_TRANSA_LINK_N1 0xe0044 |
4942 | #define _PCH_TRANSA_LINK_M2 0xe0048 |
5414 | #define _PCH_TRANSA_LINK_M2 0xe0048 |
4943 | #define _PCH_TRANSA_LINK_N2 0xe004c |
5415 | #define _PCH_TRANSA_LINK_N2 0xe004c |
4944 | 5416 | ||
4945 | /* Per-transcoder DIP controls (PCH) */ |
5417 | /* Per-transcoder DIP controls (PCH) */ |
4946 | #define _VIDEO_DIP_CTL_A 0xe0200 |
5418 | #define _VIDEO_DIP_CTL_A 0xe0200 |
4947 | #define _VIDEO_DIP_DATA_A 0xe0208 |
5419 | #define _VIDEO_DIP_DATA_A 0xe0208 |
4948 | #define _VIDEO_DIP_GCP_A 0xe0210 |
5420 | #define _VIDEO_DIP_GCP_A 0xe0210 |
4949 | 5421 | ||
4950 | #define _VIDEO_DIP_CTL_B 0xe1200 |
5422 | #define _VIDEO_DIP_CTL_B 0xe1200 |
4951 | #define _VIDEO_DIP_DATA_B 0xe1208 |
5423 | #define _VIDEO_DIP_DATA_B 0xe1208 |
4952 | #define _VIDEO_DIP_GCP_B 0xe1210 |
5424 | #define _VIDEO_DIP_GCP_B 0xe1210 |
4953 | 5425 | ||
4954 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
5426 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
4955 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
5427 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
4956 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
5428 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
4957 | 5429 | ||
4958 | /* Per-transcoder DIP controls (VLV) */ |
5430 | /* Per-transcoder DIP controls (VLV) */ |
4959 | #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
5431 | #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
4960 | #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) |
5432 | #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) |
4961 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) |
5433 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) |
4962 | 5434 | ||
4963 | #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
5435 | #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
4964 | #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) |
5436 | #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) |
4965 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) |
5437 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) |
4966 | 5438 | ||
4967 | #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
5439 | #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
4968 | #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) |
5440 | #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) |
4969 | #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) |
5441 | #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) |
4970 | 5442 | ||
4971 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
5443 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
4972 | _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ |
5444 | _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ |
4973 | VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) |
5445 | VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) |
4974 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
5446 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
4975 | _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ |
5447 | _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ |
4976 | VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) |
5448 | VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) |
4977 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
5449 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
4978 | _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
5450 | _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
4979 | VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
5451 | VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
4980 | 5452 | ||
4981 | /* Haswell DIP controls */ |
5453 | /* Haswell DIP controls */ |
4982 | #define HSW_VIDEO_DIP_CTL_A 0x60200 |
5454 | #define HSW_VIDEO_DIP_CTL_A 0x60200 |
4983 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
5455 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
4984 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
5456 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
4985 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
5457 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
4986 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
5458 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
4987 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
5459 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
4988 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
5460 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
4989 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
5461 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
4990 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
5462 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
4991 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
5463 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
4992 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
5464 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
4993 | #define HSW_VIDEO_DIP_GCP_A 0x60210 |
5465 | #define HSW_VIDEO_DIP_GCP_A 0x60210 |
4994 | 5466 | ||
4995 | #define HSW_VIDEO_DIP_CTL_B 0x61200 |
5467 | #define HSW_VIDEO_DIP_CTL_B 0x61200 |
4996 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
5468 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
4997 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
5469 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
4998 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
5470 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
4999 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
5471 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
5000 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
5472 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
5001 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
5473 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
5002 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
5474 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
5003 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
5475 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
5004 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
5476 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
5005 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
5477 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
5006 | #define HSW_VIDEO_DIP_GCP_B 0x61210 |
5478 | #define HSW_VIDEO_DIP_GCP_B 0x61210 |
5007 | 5479 | ||
5008 | #define HSW_TVIDEO_DIP_CTL(trans) \ |
5480 | #define HSW_TVIDEO_DIP_CTL(trans) \ |
5009 | _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) |
5481 | _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) |
5010 | #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ |
5482 | #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ |
5011 | _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) |
5483 | _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) |
5012 | #define HSW_TVIDEO_DIP_VS_DATA(trans) \ |
5484 | #define HSW_TVIDEO_DIP_VS_DATA(trans) \ |
5013 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) |
5485 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) |
5014 | #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ |
5486 | #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ |
5015 | _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) |
5487 | _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) |
5016 | #define HSW_TVIDEO_DIP_GCP(trans) \ |
5488 | #define HSW_TVIDEO_DIP_GCP(trans) \ |
5017 | _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) |
5489 | _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) |
5018 | #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ |
5490 | #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ |
5019 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) |
5491 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) |
5020 | 5492 | ||
5021 | #define HSW_STEREO_3D_CTL_A 0x70020 |
5493 | #define HSW_STEREO_3D_CTL_A 0x70020 |
5022 | #define S3D_ENABLE (1<<31) |
5494 | #define S3D_ENABLE (1<<31) |
5023 | #define HSW_STEREO_3D_CTL_B 0x71020 |
5495 | #define HSW_STEREO_3D_CTL_B 0x71020 |
5024 | 5496 | ||
5025 | #define HSW_STEREO_3D_CTL(trans) \ |
5497 | #define HSW_STEREO_3D_CTL(trans) \ |
5026 | _PIPE2(trans, HSW_STEREO_3D_CTL_A) |
5498 | _PIPE2(trans, HSW_STEREO_3D_CTL_A) |
5027 | 5499 | ||
5028 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
5500 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
5029 | #define _PCH_TRANS_HBLANK_B 0xe1004 |
5501 | #define _PCH_TRANS_HBLANK_B 0xe1004 |
5030 | #define _PCH_TRANS_HSYNC_B 0xe1008 |
5502 | #define _PCH_TRANS_HSYNC_B 0xe1008 |
5031 | #define _PCH_TRANS_VTOTAL_B 0xe100c |
5503 | #define _PCH_TRANS_VTOTAL_B 0xe100c |
5032 | #define _PCH_TRANS_VBLANK_B 0xe1010 |
5504 | #define _PCH_TRANS_VBLANK_B 0xe1010 |
5033 | #define _PCH_TRANS_VSYNC_B 0xe1014 |
5505 | #define _PCH_TRANS_VSYNC_B 0xe1014 |
5034 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 |
5506 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 |
5035 | 5507 | ||
5036 | #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) |
5508 | #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) |
5037 | #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) |
5509 | #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) |
5038 | #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) |
5510 | #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) |
5039 | #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) |
5511 | #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) |
5040 | #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) |
5512 | #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) |
5041 | #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) |
5513 | #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) |
5042 | #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ |
5514 | #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ |
5043 | _PCH_TRANS_VSYNCSHIFT_B) |
5515 | _PCH_TRANS_VSYNCSHIFT_B) |
5044 | 5516 | ||
5045 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
5517 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
5046 | #define _PCH_TRANSB_DATA_N1 0xe1034 |
5518 | #define _PCH_TRANSB_DATA_N1 0xe1034 |
5047 | #define _PCH_TRANSB_DATA_M2 0xe1038 |
5519 | #define _PCH_TRANSB_DATA_M2 0xe1038 |
5048 | #define _PCH_TRANSB_DATA_N2 0xe103c |
5520 | #define _PCH_TRANSB_DATA_N2 0xe103c |
5049 | #define _PCH_TRANSB_LINK_M1 0xe1040 |
5521 | #define _PCH_TRANSB_LINK_M1 0xe1040 |
5050 | #define _PCH_TRANSB_LINK_N1 0xe1044 |
5522 | #define _PCH_TRANSB_LINK_N1 0xe1044 |
5051 | #define _PCH_TRANSB_LINK_M2 0xe1048 |
5523 | #define _PCH_TRANSB_LINK_M2 0xe1048 |
5052 | #define _PCH_TRANSB_LINK_N2 0xe104c |
5524 | #define _PCH_TRANSB_LINK_N2 0xe104c |
5053 | 5525 | ||
5054 | #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) |
5526 | #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) |
5055 | #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) |
5527 | #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) |
5056 | #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) |
5528 | #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) |
5057 | #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) |
5529 | #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) |
5058 | #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) |
5530 | #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) |
5059 | #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) |
5531 | #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) |
5060 | #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) |
5532 | #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) |
5061 | #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) |
5533 | #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) |
5062 | 5534 | ||
5063 | #define _PCH_TRANSACONF 0xf0008 |
5535 | #define _PCH_TRANSACONF 0xf0008 |
5064 | #define _PCH_TRANSBCONF 0xf1008 |
5536 | #define _PCH_TRANSBCONF 0xf1008 |
5065 | #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
5537 | #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
5066 | #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ |
5538 | #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ |
5067 | #define TRANS_DISABLE (0<<31) |
5539 | #define TRANS_DISABLE (0<<31) |
5068 | #define TRANS_ENABLE (1<<31) |
5540 | #define TRANS_ENABLE (1<<31) |
5069 | #define TRANS_STATE_MASK (1<<30) |
5541 | #define TRANS_STATE_MASK (1<<30) |
5070 | #define TRANS_STATE_DISABLE (0<<30) |
5542 | #define TRANS_STATE_DISABLE (0<<30) |
5071 | #define TRANS_STATE_ENABLE (1<<30) |
5543 | #define TRANS_STATE_ENABLE (1<<30) |
5072 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) |
5544 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) |
5073 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) |
5545 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) |
5074 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) |
5546 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) |
5075 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) |
5547 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) |
5076 | #define TRANS_INTERLACE_MASK (7<<21) |
5548 | #define TRANS_INTERLACE_MASK (7<<21) |
5077 | #define TRANS_PROGRESSIVE (0<<21) |
5549 | #define TRANS_PROGRESSIVE (0<<21) |
5078 | #define TRANS_INTERLACED (3<<21) |
5550 | #define TRANS_INTERLACED (3<<21) |
5079 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
5551 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
5080 | #define TRANS_8BPC (0<<5) |
5552 | #define TRANS_8BPC (0<<5) |
5081 | #define TRANS_10BPC (1<<5) |
5553 | #define TRANS_10BPC (1<<5) |
5082 | #define TRANS_6BPC (2<<5) |
5554 | #define TRANS_6BPC (2<<5) |
5083 | #define TRANS_12BPC (3<<5) |
5555 | #define TRANS_12BPC (3<<5) |
5084 | 5556 | ||
5085 | #define _TRANSA_CHICKEN1 0xf0060 |
5557 | #define _TRANSA_CHICKEN1 0xf0060 |
5086 | #define _TRANSB_CHICKEN1 0xf1060 |
5558 | #define _TRANSB_CHICKEN1 0xf1060 |
5087 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
5559 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
5088 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
5560 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
5089 | #define _TRANSA_CHICKEN2 0xf0064 |
5561 | #define _TRANSA_CHICKEN2 0xf0064 |
5090 | #define _TRANSB_CHICKEN2 0xf1064 |
5562 | #define _TRANSB_CHICKEN2 0xf1064 |
5091 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
5563 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
5092 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) |
5564 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) |
5093 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) |
5565 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) |
5094 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) |
5566 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) |
5095 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) |
5567 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) |
5096 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) |
5568 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) |
5097 | 5569 | ||
5098 | #define SOUTH_CHICKEN1 0xc2000 |
5570 | #define SOUTH_CHICKEN1 0xc2000 |
5099 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
5571 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
5100 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 |
5572 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 |
5101 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
5573 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
5102 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
5574 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
5103 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
5575 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
5104 | #define SOUTH_CHICKEN2 0xc2004 |
5576 | #define SOUTH_CHICKEN2 0xc2004 |
5105 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
5577 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
5106 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) |
5578 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) |
5107 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) |
5579 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) |
5108 | 5580 | ||
5109 | #define _FDI_RXA_CHICKEN 0xc200c |
5581 | #define _FDI_RXA_CHICKEN 0xc200c |
5110 | #define _FDI_RXB_CHICKEN 0xc2010 |
5582 | #define _FDI_RXB_CHICKEN 0xc2010 |
5111 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
5583 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
5112 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) |
5584 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) |
5113 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
5585 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
5114 | 5586 | ||
5115 | #define SOUTH_DSPCLK_GATE_D 0xc2020 |
5587 | #define SOUTH_DSPCLK_GATE_D 0xc2020 |
5116 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) |
5588 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) |
5117 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
5589 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
5118 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) |
5590 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) |
5119 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
5591 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
5120 | 5592 | ||
5121 | /* CPU: FDI_TX */ |
5593 | /* CPU: FDI_TX */ |
5122 | #define _FDI_TXA_CTL 0x60100 |
5594 | #define _FDI_TXA_CTL 0x60100 |
5123 | #define _FDI_TXB_CTL 0x61100 |
5595 | #define _FDI_TXB_CTL 0x61100 |
5124 | #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) |
5596 | #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) |
5125 | #define FDI_TX_DISABLE (0<<31) |
5597 | #define FDI_TX_DISABLE (0<<31) |
5126 | #define FDI_TX_ENABLE (1<<31) |
5598 | #define FDI_TX_ENABLE (1<<31) |
5127 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) |
5599 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) |
5128 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) |
5600 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) |
5129 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) |
5601 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) |
5130 | #define FDI_LINK_TRAIN_NONE (3<<28) |
5602 | #define FDI_LINK_TRAIN_NONE (3<<28) |
5131 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) |
5603 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) |
5132 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) |
5604 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) |
5133 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) |
5605 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) |
5134 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) |
5606 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) |
5135 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) |
5607 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) |
5136 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) |
5608 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) |
5137 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) |
5609 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) |
5138 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) |
5610 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) |
5139 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
5611 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
5140 | SNB has different settings. */ |
5612 | SNB has different settings. */ |
5141 | /* SNB A-stepping */ |
5613 | /* SNB A-stepping */ |
5142 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
5614 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
5143 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
5615 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
5144 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
5616 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
5145 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
5617 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
5146 | /* SNB B-stepping */ |
5618 | /* SNB B-stepping */ |
5147 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) |
5619 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) |
5148 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) |
5620 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) |
5149 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) |
5621 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) |
5150 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) |
5622 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) |
5151 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) |
5623 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) |
5152 | #define FDI_DP_PORT_WIDTH_SHIFT 19 |
5624 | #define FDI_DP_PORT_WIDTH_SHIFT 19 |
5153 | #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) |
5625 | #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) |
5154 | #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) |
5626 | #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) |
5155 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
5627 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
5156 | /* Ironlake: hardwired to 1 */ |
5628 | /* Ironlake: hardwired to 1 */ |
5157 | #define FDI_TX_PLL_ENABLE (1<<14) |
5629 | #define FDI_TX_PLL_ENABLE (1<<14) |
5158 | 5630 | ||
5159 | /* Ivybridge has different bits for lolz */ |
5631 | /* Ivybridge has different bits for lolz */ |
5160 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) |
5632 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) |
5161 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) |
5633 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) |
5162 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) |
5634 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) |
5163 | #define FDI_LINK_TRAIN_NONE_IVB (3<<8) |
5635 | #define FDI_LINK_TRAIN_NONE_IVB (3<<8) |
5164 | 5636 | ||
5165 | /* both Tx and Rx */ |
5637 | /* both Tx and Rx */ |
5166 | #define FDI_COMPOSITE_SYNC (1<<11) |
5638 | #define FDI_COMPOSITE_SYNC (1<<11) |
5167 | #define FDI_LINK_TRAIN_AUTO (1<<10) |
5639 | #define FDI_LINK_TRAIN_AUTO (1<<10) |
5168 | #define FDI_SCRAMBLING_ENABLE (0<<7) |
5640 | #define FDI_SCRAMBLING_ENABLE (0<<7) |
5169 | #define FDI_SCRAMBLING_DISABLE (1<<7) |
5641 | #define FDI_SCRAMBLING_DISABLE (1<<7) |
5170 | 5642 | ||
5171 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ |
5643 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ |
5172 | #define _FDI_RXA_CTL 0xf000c |
5644 | #define _FDI_RXA_CTL 0xf000c |
5173 | #define _FDI_RXB_CTL 0xf100c |
5645 | #define _FDI_RXB_CTL 0xf100c |
5174 | #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) |
5646 | #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) |
5175 | #define FDI_RX_ENABLE (1<<31) |
5647 | #define FDI_RX_ENABLE (1<<31) |
5176 | /* train, dp width same as FDI_TX */ |
5648 | /* train, dp width same as FDI_TX */ |
5177 | #define FDI_FS_ERRC_ENABLE (1<<27) |
5649 | #define FDI_FS_ERRC_ENABLE (1<<27) |
5178 | #define FDI_FE_ERRC_ENABLE (1<<26) |
5650 | #define FDI_FE_ERRC_ENABLE (1<<26) |
5179 | #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
5651 | #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
5180 | #define FDI_8BPC (0<<16) |
5652 | #define FDI_8BPC (0<<16) |
5181 | #define FDI_10BPC (1<<16) |
5653 | #define FDI_10BPC (1<<16) |
5182 | #define FDI_6BPC (2<<16) |
5654 | #define FDI_6BPC (2<<16) |
5183 | #define FDI_12BPC (3<<16) |
5655 | #define FDI_12BPC (3<<16) |
5184 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) |
5656 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) |
5185 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
5657 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
5186 | #define FDI_RX_PLL_ENABLE (1<<13) |
5658 | #define FDI_RX_PLL_ENABLE (1<<13) |
5187 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) |
5659 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) |
5188 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) |
5660 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) |
5189 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) |
5661 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) |
5190 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) |
5662 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) |
5191 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) |
5663 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) |
5192 | #define FDI_PCDCLK (1<<4) |
5664 | #define FDI_PCDCLK (1<<4) |
5193 | /* CPT */ |
5665 | /* CPT */ |
5194 | #define FDI_AUTO_TRAINING (1<<10) |
5666 | #define FDI_AUTO_TRAINING (1<<10) |
5195 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
5667 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
5196 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
5668 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
5197 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
5669 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
5198 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
5670 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
5199 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
5671 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
5200 | 5672 | ||
5201 | #define _FDI_RXA_MISC 0xf0010 |
5673 | #define _FDI_RXA_MISC 0xf0010 |
5202 | #define _FDI_RXB_MISC 0xf1010 |
5674 | #define _FDI_RXB_MISC 0xf1010 |
5203 | #define FDI_RX_PWRDN_LANE1_MASK (3<<26) |
5675 | #define FDI_RX_PWRDN_LANE1_MASK (3<<26) |
5204 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) |
5676 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) |
5205 | #define FDI_RX_PWRDN_LANE0_MASK (3<<24) |
5677 | #define FDI_RX_PWRDN_LANE0_MASK (3<<24) |
5206 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) |
5678 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) |
5207 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) |
5679 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) |
5208 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) |
5680 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) |
5209 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) |
5681 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) |
5210 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
5682 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
5211 | 5683 | ||
5212 | #define _FDI_RXA_TUSIZE1 0xf0030 |
5684 | #define _FDI_RXA_TUSIZE1 0xf0030 |
5213 | #define _FDI_RXA_TUSIZE2 0xf0038 |
5685 | #define _FDI_RXA_TUSIZE2 0xf0038 |
5214 | #define _FDI_RXB_TUSIZE1 0xf1030 |
5686 | #define _FDI_RXB_TUSIZE1 0xf1030 |
5215 | #define _FDI_RXB_TUSIZE2 0xf1038 |
5687 | #define _FDI_RXB_TUSIZE2 0xf1038 |
5216 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
5688 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
5217 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) |
5689 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) |
5218 | 5690 | ||
5219 | /* FDI_RX interrupt register format */ |
5691 | /* FDI_RX interrupt register format */ |
5220 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) |
5692 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) |
5221 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ |
5693 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ |
5222 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ |
5694 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ |
5223 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) |
5695 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) |
5224 | #define FDI_RX_FS_CODE_ERR (1<<6) |
5696 | #define FDI_RX_FS_CODE_ERR (1<<6) |
5225 | #define FDI_RX_FE_CODE_ERR (1<<5) |
5697 | #define FDI_RX_FE_CODE_ERR (1<<5) |
5226 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) |
5698 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) |
5227 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) |
5699 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) |
5228 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) |
5700 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) |
5229 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) |
5701 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) |
5230 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) |
5702 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) |
5231 | 5703 | ||
5232 | #define _FDI_RXA_IIR 0xf0014 |
5704 | #define _FDI_RXA_IIR 0xf0014 |
5233 | #define _FDI_RXA_IMR 0xf0018 |
5705 | #define _FDI_RXA_IMR 0xf0018 |
5234 | #define _FDI_RXB_IIR 0xf1014 |
5706 | #define _FDI_RXB_IIR 0xf1014 |
5235 | #define _FDI_RXB_IMR 0xf1018 |
5707 | #define _FDI_RXB_IMR 0xf1018 |
5236 | #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) |
5708 | #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) |
5237 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) |
5709 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) |
5238 | 5710 | ||
5239 | #define FDI_PLL_CTL_1 0xfe000 |
5711 | #define FDI_PLL_CTL_1 0xfe000 |
5240 | #define FDI_PLL_CTL_2 0xfe004 |
5712 | #define FDI_PLL_CTL_2 0xfe004 |
5241 | 5713 | ||
5242 | #define PCH_LVDS 0xe1180 |
5714 | #define PCH_LVDS 0xe1180 |
5243 | #define LVDS_DETECTED (1 << 1) |
5715 | #define LVDS_DETECTED (1 << 1) |
5244 | 5716 | ||
5245 | /* vlv has 2 sets of panel control regs. */ |
5717 | /* vlv has 2 sets of panel control regs. */ |
5246 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
5718 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
5247 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) |
5719 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) |
5248 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) |
5720 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) |
5249 | #define PANEL_PORT_SELECT_DPB_VLV (1 << 30) |
- | |
5250 | #define PANEL_PORT_SELECT_DPC_VLV (2 << 30) |
5721 | #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) |
5251 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
5722 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
5252 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) |
5723 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) |
5253 | 5724 | ||
5254 | #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) |
5725 | #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) |
5255 | #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) |
5726 | #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) |
5256 | #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) |
5727 | #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) |
5257 | #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) |
5728 | #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) |
5258 | #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) |
5729 | #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) |
5259 | 5730 | ||
5260 | #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) |
5731 | #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) |
5261 | #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) |
5732 | #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) |
5262 | #define VLV_PIPE_PP_ON_DELAYS(pipe) \ |
5733 | #define VLV_PIPE_PP_ON_DELAYS(pipe) \ |
5263 | _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) |
5734 | _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) |
5264 | #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ |
5735 | #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ |
5265 | _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) |
5736 | _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) |
5266 | #define VLV_PIPE_PP_DIVISOR(pipe) \ |
5737 | #define VLV_PIPE_PP_DIVISOR(pipe) \ |
5267 | _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) |
5738 | _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) |
5268 | 5739 | ||
5269 | #define PCH_PP_STATUS 0xc7200 |
5740 | #define PCH_PP_STATUS 0xc7200 |
5270 | #define PCH_PP_CONTROL 0xc7204 |
5741 | #define PCH_PP_CONTROL 0xc7204 |
5271 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
5742 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
5272 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
5743 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
5273 | #define EDP_FORCE_VDD (1 << 3) |
5744 | #define EDP_FORCE_VDD (1 << 3) |
5274 | #define EDP_BLC_ENABLE (1 << 2) |
5745 | #define EDP_BLC_ENABLE (1 << 2) |
5275 | #define PANEL_POWER_RESET (1 << 1) |
5746 | #define PANEL_POWER_RESET (1 << 1) |
5276 | #define PANEL_POWER_OFF (0 << 0) |
5747 | #define PANEL_POWER_OFF (0 << 0) |
5277 | #define PANEL_POWER_ON (1 << 0) |
5748 | #define PANEL_POWER_ON (1 << 0) |
5278 | #define PCH_PP_ON_DELAYS 0xc7208 |
5749 | #define PCH_PP_ON_DELAYS 0xc7208 |
5279 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
5750 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
5280 | #define PANEL_PORT_SELECT_LVDS (0 << 30) |
5751 | #define PANEL_PORT_SELECT_LVDS (0 << 30) |
5281 | #define PANEL_PORT_SELECT_DPA (1 << 30) |
5752 | #define PANEL_PORT_SELECT_DPA (1 << 30) |
5282 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
5753 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
5283 | #define PANEL_PORT_SELECT_DPD (3 << 30) |
5754 | #define PANEL_PORT_SELECT_DPD (3 << 30) |
5284 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) |
5755 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) |
5285 | #define PANEL_POWER_UP_DELAY_SHIFT 16 |
5756 | #define PANEL_POWER_UP_DELAY_SHIFT 16 |
5286 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) |
5757 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) |
5287 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 |
5758 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 |
5288 | 5759 | ||
5289 | #define PCH_PP_OFF_DELAYS 0xc720c |
5760 | #define PCH_PP_OFF_DELAYS 0xc720c |
5290 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
5761 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
5291 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 |
5762 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 |
5292 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) |
5763 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) |
5293 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 |
5764 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 |
5294 | 5765 | ||
5295 | #define PCH_PP_DIVISOR 0xc7210 |
5766 | #define PCH_PP_DIVISOR 0xc7210 |
5296 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
5767 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
5297 | #define PP_REFERENCE_DIVIDER_SHIFT 8 |
5768 | #define PP_REFERENCE_DIVIDER_SHIFT 8 |
5298 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) |
5769 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) |
5299 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 |
5770 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 |
5300 | 5771 | ||
5301 | #define PCH_DP_B 0xe4100 |
5772 | #define PCH_DP_B 0xe4100 |
5302 | #define PCH_DPB_AUX_CH_CTL 0xe4110 |
5773 | #define PCH_DPB_AUX_CH_CTL 0xe4110 |
5303 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 |
5774 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 |
5304 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 |
5775 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 |
5305 | #define PCH_DPB_AUX_CH_DATA3 0xe411c |
5776 | #define PCH_DPB_AUX_CH_DATA3 0xe411c |
5306 | #define PCH_DPB_AUX_CH_DATA4 0xe4120 |
5777 | #define PCH_DPB_AUX_CH_DATA4 0xe4120 |
5307 | #define PCH_DPB_AUX_CH_DATA5 0xe4124 |
5778 | #define PCH_DPB_AUX_CH_DATA5 0xe4124 |
5308 | 5779 | ||
5309 | #define PCH_DP_C 0xe4200 |
5780 | #define PCH_DP_C 0xe4200 |
5310 | #define PCH_DPC_AUX_CH_CTL 0xe4210 |
5781 | #define PCH_DPC_AUX_CH_CTL 0xe4210 |
5311 | #define PCH_DPC_AUX_CH_DATA1 0xe4214 |
5782 | #define PCH_DPC_AUX_CH_DATA1 0xe4214 |
5312 | #define PCH_DPC_AUX_CH_DATA2 0xe4218 |
5783 | #define PCH_DPC_AUX_CH_DATA2 0xe4218 |
5313 | #define PCH_DPC_AUX_CH_DATA3 0xe421c |
5784 | #define PCH_DPC_AUX_CH_DATA3 0xe421c |
5314 | #define PCH_DPC_AUX_CH_DATA4 0xe4220 |
5785 | #define PCH_DPC_AUX_CH_DATA4 0xe4220 |
5315 | #define PCH_DPC_AUX_CH_DATA5 0xe4224 |
5786 | #define PCH_DPC_AUX_CH_DATA5 0xe4224 |
5316 | 5787 | ||
5317 | #define PCH_DP_D 0xe4300 |
5788 | #define PCH_DP_D 0xe4300 |
5318 | #define PCH_DPD_AUX_CH_CTL 0xe4310 |
5789 | #define PCH_DPD_AUX_CH_CTL 0xe4310 |
5319 | #define PCH_DPD_AUX_CH_DATA1 0xe4314 |
5790 | #define PCH_DPD_AUX_CH_DATA1 0xe4314 |
5320 | #define PCH_DPD_AUX_CH_DATA2 0xe4318 |
5791 | #define PCH_DPD_AUX_CH_DATA2 0xe4318 |
5321 | #define PCH_DPD_AUX_CH_DATA3 0xe431c |
5792 | #define PCH_DPD_AUX_CH_DATA3 0xe431c |
5322 | #define PCH_DPD_AUX_CH_DATA4 0xe4320 |
5793 | #define PCH_DPD_AUX_CH_DATA4 0xe4320 |
5323 | #define PCH_DPD_AUX_CH_DATA5 0xe4324 |
5794 | #define PCH_DPD_AUX_CH_DATA5 0xe4324 |
5324 | 5795 | ||
5325 | /* CPT */ |
5796 | /* CPT */ |
5326 | #define PORT_TRANS_A_SEL_CPT 0 |
5797 | #define PORT_TRANS_A_SEL_CPT 0 |
5327 | #define PORT_TRANS_B_SEL_CPT (1<<29) |
5798 | #define PORT_TRANS_B_SEL_CPT (1<<29) |
5328 | #define PORT_TRANS_C_SEL_CPT (2<<29) |
5799 | #define PORT_TRANS_C_SEL_CPT (2<<29) |
5329 | #define PORT_TRANS_SEL_MASK (3<<29) |
5800 | #define PORT_TRANS_SEL_MASK (3<<29) |
5330 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
5801 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
5331 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
5802 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
5332 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) |
5803 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) |
5333 | #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) |
5804 | #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) |
5334 | #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) |
5805 | #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) |
5335 | 5806 | ||
5336 | #define TRANS_DP_CTL_A 0xe0300 |
5807 | #define TRANS_DP_CTL_A 0xe0300 |
5337 | #define TRANS_DP_CTL_B 0xe1300 |
5808 | #define TRANS_DP_CTL_B 0xe1300 |
5338 | #define TRANS_DP_CTL_C 0xe2300 |
5809 | #define TRANS_DP_CTL_C 0xe2300 |
5339 | #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) |
5810 | #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) |
5340 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) |
5811 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) |
5341 | #define TRANS_DP_PORT_SEL_B (0<<29) |
5812 | #define TRANS_DP_PORT_SEL_B (0<<29) |
5342 | #define TRANS_DP_PORT_SEL_C (1<<29) |
5813 | #define TRANS_DP_PORT_SEL_C (1<<29) |
5343 | #define TRANS_DP_PORT_SEL_D (2<<29) |
5814 | #define TRANS_DP_PORT_SEL_D (2<<29) |
5344 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
5815 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
5345 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
5816 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
5346 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
5817 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
5347 | #define TRANS_DP_ENH_FRAMING (1<<18) |
5818 | #define TRANS_DP_ENH_FRAMING (1<<18) |
5348 | #define TRANS_DP_8BPC (0<<9) |
5819 | #define TRANS_DP_8BPC (0<<9) |
5349 | #define TRANS_DP_10BPC (1<<9) |
5820 | #define TRANS_DP_10BPC (1<<9) |
5350 | #define TRANS_DP_6BPC (2<<9) |
5821 | #define TRANS_DP_6BPC (2<<9) |
5351 | #define TRANS_DP_12BPC (3<<9) |
5822 | #define TRANS_DP_12BPC (3<<9) |
5352 | #define TRANS_DP_BPC_MASK (3<<9) |
5823 | #define TRANS_DP_BPC_MASK (3<<9) |
5353 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
5824 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
5354 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
5825 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
5355 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
5826 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
5356 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 |
5827 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 |
5357 | #define TRANS_DP_SYNC_MASK (3<<3) |
5828 | #define TRANS_DP_SYNC_MASK (3<<3) |
5358 | 5829 | ||
5359 | /* SNB eDP training params */ |
5830 | /* SNB eDP training params */ |
5360 | /* SNB A-stepping */ |
5831 | /* SNB A-stepping */ |
5361 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
5832 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
5362 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
5833 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
5363 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
5834 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
5364 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
5835 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
5365 | /* SNB B-stepping */ |
5836 | /* SNB B-stepping */ |
5366 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
5837 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
5367 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) |
5838 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) |
5368 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) |
5839 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) |
5369 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) |
5840 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) |
5370 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) |
5841 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) |
5371 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
5842 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
5372 | 5843 | ||
5373 | /* IVB */ |
5844 | /* IVB */ |
5374 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) |
5845 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) |
5375 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) |
5846 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) |
5376 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) |
5847 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) |
5377 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) |
5848 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) |
5378 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) |
5849 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) |
5379 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) |
5850 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) |
5380 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) |
5851 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) |
5381 | 5852 | ||
5382 | /* legacy values */ |
5853 | /* legacy values */ |
5383 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) |
5854 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) |
5384 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) |
5855 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) |
5385 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) |
5856 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) |
5386 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) |
5857 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) |
5387 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) |
5858 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) |
5388 | 5859 | ||
5389 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
5860 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
5390 | 5861 | ||
5391 | #define VLV_PMWGICZ 0x1300a4 |
5862 | #define VLV_PMWGICZ 0x1300a4 |
5392 | 5863 | ||
5393 | #define FORCEWAKE 0xA18C |
5864 | #define FORCEWAKE 0xA18C |
5394 | #define FORCEWAKE_VLV 0x1300b0 |
5865 | #define FORCEWAKE_VLV 0x1300b0 |
5395 | #define FORCEWAKE_ACK_VLV 0x1300b4 |
5866 | #define FORCEWAKE_ACK_VLV 0x1300b4 |
5396 | #define FORCEWAKE_MEDIA_VLV 0x1300b8 |
5867 | #define FORCEWAKE_MEDIA_VLV 0x1300b8 |
5397 | #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc |
5868 | #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc |
5398 | #define FORCEWAKE_ACK_HSW 0x130044 |
5869 | #define FORCEWAKE_ACK_HSW 0x130044 |
5399 | #define FORCEWAKE_ACK 0x130090 |
5870 | #define FORCEWAKE_ACK 0x130090 |
5400 | #define VLV_GTLC_WAKE_CTRL 0x130090 |
5871 | #define VLV_GTLC_WAKE_CTRL 0x130090 |
5401 | #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) |
5872 | #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) |
5402 | #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) |
5873 | #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) |
5403 | #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) |
5874 | #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) |
5404 | 5875 | ||
5405 | #define VLV_GTLC_PW_STATUS 0x130094 |
5876 | #define VLV_GTLC_PW_STATUS 0x130094 |
5406 | #define VLV_GTLC_ALLOWWAKEACK (1 << 0) |
5877 | #define VLV_GTLC_ALLOWWAKEACK (1 << 0) |
5407 | #define VLV_GTLC_ALLOWWAKEERR (1 << 1) |
5878 | #define VLV_GTLC_ALLOWWAKEERR (1 << 1) |
5408 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) |
5879 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) |
5409 | #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) |
5880 | #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) |
5410 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
- | |
5411 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
5881 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
- | 5882 | #define FORCEWAKE_MEDIA_GEN9 0xa270 |
|
- | 5883 | #define FORCEWAKE_RENDER_GEN9 0xa278 |
|
- | 5884 | #define FORCEWAKE_BLITTER_GEN9 0xa188 |
|
- | 5885 | #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88 |
|
- | 5886 | #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84 |
|
- | 5887 | #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044 |
|
5412 | #define FORCEWAKE_KERNEL 0x1 |
5888 | #define FORCEWAKE_KERNEL 0x1 |
5413 | #define FORCEWAKE_USER 0x2 |
5889 | #define FORCEWAKE_USER 0x2 |
5414 | #define FORCEWAKE_MT_ACK 0x130040 |
5890 | #define FORCEWAKE_MT_ACK 0x130040 |
5415 | #define ECOBUS 0xa180 |
5891 | #define ECOBUS 0xa180 |
5416 | #define FORCEWAKE_MT_ENABLE (1<<5) |
5892 | #define FORCEWAKE_MT_ENABLE (1<<5) |
5417 | #define VLV_SPAREG2H 0xA194 |
5893 | #define VLV_SPAREG2H 0xA194 |
5418 | 5894 | ||
5419 | #define GTFIFODBG 0x120000 |
5895 | #define GTFIFODBG 0x120000 |
5420 | #define GT_FIFO_SBDROPERR (1<<6) |
5896 | #define GT_FIFO_SBDROPERR (1<<6) |
5421 | #define GT_FIFO_BLOBDROPERR (1<<5) |
5897 | #define GT_FIFO_BLOBDROPERR (1<<5) |
5422 | #define GT_FIFO_SB_READ_ABORTERR (1<<4) |
5898 | #define GT_FIFO_SB_READ_ABORTERR (1<<4) |
5423 | #define GT_FIFO_DROPERR (1<<3) |
5899 | #define GT_FIFO_DROPERR (1<<3) |
5424 | #define GT_FIFO_OVFERR (1<<2) |
5900 | #define GT_FIFO_OVFERR (1<<2) |
5425 | #define GT_FIFO_IAWRERR (1<<1) |
5901 | #define GT_FIFO_IAWRERR (1<<1) |
5426 | #define GT_FIFO_IARDERR (1<<0) |
5902 | #define GT_FIFO_IARDERR (1<<0) |
5427 | 5903 | ||
5428 | #define GTFIFOCTL 0x120008 |
5904 | #define GTFIFOCTL 0x120008 |
5429 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
5905 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
5430 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
5906 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
5431 | 5907 | ||
5432 | #define HSW_IDICR 0x9008 |
5908 | #define HSW_IDICR 0x9008 |
5433 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
5909 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
5434 | #define HSW_EDRAM_PRESENT 0x120010 |
5910 | #define HSW_EDRAM_PRESENT 0x120010 |
5435 | 5911 | ||
5436 | #define GEN6_UCGCTL1 0x9400 |
5912 | #define GEN6_UCGCTL1 0x9400 |
5437 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
5913 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
5438 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
5914 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
5439 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
5915 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
5440 | 5916 | ||
5441 | #define GEN6_UCGCTL2 0x9404 |
5917 | #define GEN6_UCGCTL2 0x9404 |
5442 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
5918 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
5443 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
5919 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
5444 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
5920 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
5445 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
5921 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
5446 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
5922 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
5447 | 5923 | ||
5448 | #define GEN6_UCGCTL3 0x9408 |
5924 | #define GEN6_UCGCTL3 0x9408 |
5449 | 5925 | ||
5450 | #define GEN7_UCGCTL4 0x940c |
5926 | #define GEN7_UCGCTL4 0x940c |
5451 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
5927 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
5452 | 5928 | ||
5453 | #define GEN6_RCGCTL1 0x9410 |
5929 | #define GEN6_RCGCTL1 0x9410 |
5454 | #define GEN6_RCGCTL2 0x9414 |
5930 | #define GEN6_RCGCTL2 0x9414 |
5455 | #define GEN6_RSTCTL 0x9420 |
5931 | #define GEN6_RSTCTL 0x9420 |
5456 | 5932 | ||
5457 | #define GEN8_UCGCTL6 0x9430 |
5933 | #define GEN8_UCGCTL6 0x9430 |
5458 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) |
5934 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) |
5459 | 5935 | ||
5460 | #define GEN6_GFXPAUSE 0xA000 |
5936 | #define GEN6_GFXPAUSE 0xA000 |
5461 | #define GEN6_RPNSWREQ 0xA008 |
5937 | #define GEN6_RPNSWREQ 0xA008 |
5462 | #define GEN6_TURBO_DISABLE (1<<31) |
5938 | #define GEN6_TURBO_DISABLE (1<<31) |
5463 | #define GEN6_FREQUENCY(x) ((x)<<25) |
5939 | #define GEN6_FREQUENCY(x) ((x)<<25) |
5464 | #define HSW_FREQUENCY(x) ((x)<<24) |
5940 | #define HSW_FREQUENCY(x) ((x)<<24) |
5465 | #define GEN6_OFFSET(x) ((x)<<19) |
5941 | #define GEN6_OFFSET(x) ((x)<<19) |
5466 | #define GEN6_AGGRESSIVE_TURBO (0<<15) |
5942 | #define GEN6_AGGRESSIVE_TURBO (0<<15) |
5467 | #define GEN6_RC_VIDEO_FREQ 0xA00C |
5943 | #define GEN6_RC_VIDEO_FREQ 0xA00C |
5468 | #define GEN6_RC_CONTROL 0xA090 |
5944 | #define GEN6_RC_CONTROL 0xA090 |
5469 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
5945 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
5470 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) |
5946 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) |
5471 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) |
5947 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) |
5472 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) |
5948 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) |
5473 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) |
5949 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) |
5474 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) |
5950 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) |
5475 | #define GEN7_RC_CTL_TO_MODE (1<<28) |
5951 | #define GEN7_RC_CTL_TO_MODE (1<<28) |
5476 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
5952 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
5477 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) |
5953 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) |
5478 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 |
5954 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 |
5479 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
5955 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 |
5480 | #define GEN6_RPSTAT1 0xA01C |
5956 | #define GEN6_RPSTAT1 0xA01C |
5481 | #define GEN6_CAGF_SHIFT 8 |
5957 | #define GEN6_CAGF_SHIFT 8 |
5482 | #define HSW_CAGF_SHIFT 7 |
5958 | #define HSW_CAGF_SHIFT 7 |
5483 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
5959 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
5484 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
5960 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
5485 | #define GEN6_RP_CONTROL 0xA024 |
5961 | #define GEN6_RP_CONTROL 0xA024 |
5486 | #define GEN6_RP_MEDIA_TURBO (1<<11) |
5962 | #define GEN6_RP_MEDIA_TURBO (1<<11) |
5487 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
5963 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
5488 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) |
5964 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) |
5489 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) |
5965 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) |
5490 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) |
5966 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) |
5491 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) |
5967 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) |
5492 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
5968 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
5493 | #define GEN6_RP_ENABLE (1<<7) |
5969 | #define GEN6_RP_ENABLE (1<<7) |
5494 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
5970 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
5495 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
5971 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
5496 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
5972 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
5497 | #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) |
5973 | #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) |
5498 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
5974 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
5499 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
5975 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
5500 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 |
5976 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 |
5501 | #define GEN6_RP_CUR_UP_EI 0xA050 |
5977 | #define GEN6_RP_CUR_UP_EI 0xA050 |
5502 | #define GEN6_CURICONT_MASK 0xffffff |
5978 | #define GEN6_CURICONT_MASK 0xffffff |
5503 | #define GEN6_RP_CUR_UP 0xA054 |
5979 | #define GEN6_RP_CUR_UP 0xA054 |
5504 | #define GEN6_CURBSYTAVG_MASK 0xffffff |
5980 | #define GEN6_CURBSYTAVG_MASK 0xffffff |
5505 | #define GEN6_RP_PREV_UP 0xA058 |
5981 | #define GEN6_RP_PREV_UP 0xA058 |
5506 | #define GEN6_RP_CUR_DOWN_EI 0xA05C |
5982 | #define GEN6_RP_CUR_DOWN_EI 0xA05C |
5507 | #define GEN6_CURIAVG_MASK 0xffffff |
5983 | #define GEN6_CURIAVG_MASK 0xffffff |
5508 | #define GEN6_RP_CUR_DOWN 0xA060 |
5984 | #define GEN6_RP_CUR_DOWN 0xA060 |
5509 | #define GEN6_RP_PREV_DOWN 0xA064 |
5985 | #define GEN6_RP_PREV_DOWN 0xA064 |
5510 | #define GEN6_RP_UP_EI 0xA068 |
5986 | #define GEN6_RP_UP_EI 0xA068 |
5511 | #define GEN6_RP_DOWN_EI 0xA06C |
5987 | #define GEN6_RP_DOWN_EI 0xA06C |
5512 | #define GEN6_RP_IDLE_HYSTERSIS 0xA070 |
5988 | #define GEN6_RP_IDLE_HYSTERSIS 0xA070 |
5513 | #define GEN6_RPDEUHWTC 0xA080 |
5989 | #define GEN6_RPDEUHWTC 0xA080 |
5514 | #define GEN6_RPDEUC 0xA084 |
5990 | #define GEN6_RPDEUC 0xA084 |
5515 | #define GEN6_RPDEUCSW 0xA088 |
5991 | #define GEN6_RPDEUCSW 0xA088 |
5516 | #define GEN6_RC_STATE 0xA094 |
5992 | #define GEN6_RC_STATE 0xA094 |
5517 | #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 |
5993 | #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 |
5518 | #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C |
5994 | #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C |
5519 | #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 |
5995 | #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 |
5520 | #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 |
5996 | #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 |
5521 | #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC |
5997 | #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC |
5522 | #define GEN6_RC_SLEEP 0xA0B0 |
5998 | #define GEN6_RC_SLEEP 0xA0B0 |
5523 | #define GEN6_RCUBMABDTMR 0xA0B0 |
5999 | #define GEN6_RCUBMABDTMR 0xA0B0 |
5524 | #define GEN6_RC1e_THRESHOLD 0xA0B4 |
6000 | #define GEN6_RC1e_THRESHOLD 0xA0B4 |
5525 | #define GEN6_RC6_THRESHOLD 0xA0B8 |
6001 | #define GEN6_RC6_THRESHOLD 0xA0B8 |
5526 | #define GEN6_RC6p_THRESHOLD 0xA0BC |
6002 | #define GEN6_RC6p_THRESHOLD 0xA0BC |
5527 | #define VLV_RCEDATA 0xA0BC |
6003 | #define VLV_RCEDATA 0xA0BC |
5528 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 |
6004 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 |
5529 | #define GEN6_PMINTRMSK 0xA168 |
6005 | #define GEN6_PMINTRMSK 0xA168 |
5530 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
6006 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
5531 | #define VLV_PWRDWNUPCTL 0xA294 |
6007 | #define VLV_PWRDWNUPCTL 0xA294 |
5532 | 6008 | ||
5533 | #define GEN6_PMISR 0x44020 |
6009 | #define GEN6_PMISR 0x44020 |
5534 | #define GEN6_PMIMR 0x44024 /* rps_lock */ |
6010 | #define GEN6_PMIMR 0x44024 /* rps_lock */ |
5535 | #define GEN6_PMIIR 0x44028 |
6011 | #define GEN6_PMIIR 0x44028 |
5536 | #define GEN6_PMIER 0x4402C |
6012 | #define GEN6_PMIER 0x4402C |
5537 | #define GEN6_PM_MBOX_EVENT (1<<25) |
6013 | #define GEN6_PM_MBOX_EVENT (1<<25) |
5538 | #define GEN6_PM_THERMAL_EVENT (1<<24) |
6014 | #define GEN6_PM_THERMAL_EVENT (1<<24) |
5539 | #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) |
6015 | #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) |
5540 | #define GEN6_PM_RP_UP_THRESHOLD (1<<5) |
6016 | #define GEN6_PM_RP_UP_THRESHOLD (1<<5) |
5541 | #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) |
6017 | #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) |
5542 | #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) |
6018 | #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) |
5543 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
6019 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
5544 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
6020 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
5545 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
6021 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
5546 | GEN6_PM_RP_DOWN_TIMEOUT) |
6022 | GEN6_PM_RP_DOWN_TIMEOUT) |
5547 | - | ||
5548 | #define CHV_CZ_CLOCK_FREQ_MODE_200 200 |
- | |
5549 | #define CHV_CZ_CLOCK_FREQ_MODE_267 267 |
- | |
5550 | #define CHV_CZ_CLOCK_FREQ_MODE_320 320 |
- | |
5551 | #define CHV_CZ_CLOCK_FREQ_MODE_333 333 |
- | |
5552 | #define CHV_CZ_CLOCK_FREQ_MODE_400 400 |
- | |
5553 | 6023 | ||
5554 | #define GEN7_GT_SCRATCH_BASE 0x4F100 |
6024 | #define GEN7_GT_SCRATCH_BASE 0x4F100 |
5555 | #define GEN7_GT_SCRATCH_REG_NUM 8 |
6025 | #define GEN7_GT_SCRATCH_REG_NUM 8 |
5556 | 6026 | ||
5557 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
6027 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
5558 | #define VLV_GFX_CLK_STATUS_BIT (1<<3) |
6028 | #define VLV_GFX_CLK_STATUS_BIT (1<<3) |
5559 | #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) |
6029 | #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) |
5560 | 6030 | ||
5561 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
6031 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
5562 | #define VLV_COUNTER_CONTROL 0x138104 |
6032 | #define VLV_COUNTER_CONTROL 0x138104 |
5563 | #define VLV_COUNT_RANGE_HIGH (1<<15) |
6033 | #define VLV_COUNT_RANGE_HIGH (1<<15) |
5564 | #define VLV_MEDIA_RC0_COUNT_EN (1<<5) |
6034 | #define VLV_MEDIA_RC0_COUNT_EN (1<<5) |
5565 | #define VLV_RENDER_RC0_COUNT_EN (1<<4) |
6035 | #define VLV_RENDER_RC0_COUNT_EN (1<<4) |
5566 | #define VLV_MEDIA_RC6_COUNT_EN (1<<1) |
6036 | #define VLV_MEDIA_RC6_COUNT_EN (1<<1) |
5567 | #define VLV_RENDER_RC6_COUNT_EN (1<<0) |
6037 | #define VLV_RENDER_RC6_COUNT_EN (1<<0) |
5568 | #define GEN6_GT_GFX_RC6 0x138108 |
6038 | #define GEN6_GT_GFX_RC6 0x138108 |
5569 | #define VLV_GT_RENDER_RC6 0x138108 |
6039 | #define VLV_GT_RENDER_RC6 0x138108 |
5570 | #define VLV_GT_MEDIA_RC6 0x13810C |
6040 | #define VLV_GT_MEDIA_RC6 0x13810C |
5571 | 6041 | ||
5572 | #define GEN6_GT_GFX_RC6p 0x13810C |
6042 | #define GEN6_GT_GFX_RC6p 0x13810C |
5573 | #define GEN6_GT_GFX_RC6pp 0x138110 |
6043 | #define GEN6_GT_GFX_RC6pp 0x138110 |
5574 | #define VLV_RENDER_C0_COUNT_REG 0x138118 |
6044 | #define VLV_RENDER_C0_COUNT_REG 0x138118 |
5575 | #define VLV_MEDIA_C0_COUNT_REG 0x13811C |
6045 | #define VLV_MEDIA_C0_COUNT_REG 0x13811C |
5576 | 6046 | ||
5577 | #define GEN6_PCODE_MAILBOX 0x138124 |
6047 | #define GEN6_PCODE_MAILBOX 0x138124 |
5578 | #define GEN6_PCODE_READY (1<<31) |
6048 | #define GEN6_PCODE_READY (1<<31) |
5579 | #define GEN6_READ_OC_PARAMS 0xc |
6049 | #define GEN6_READ_OC_PARAMS 0xc |
5580 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
6050 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
5581 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
6051 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
5582 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
6052 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
5583 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
6053 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
5584 | #define GEN6_PCODE_READ_D_COMP 0x10 |
6054 | #define GEN6_PCODE_READ_D_COMP 0x10 |
5585 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
6055 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
5586 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
6056 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
5587 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
6057 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
5588 | #define DISPLAY_IPS_CONTROL 0x19 |
6058 | #define DISPLAY_IPS_CONTROL 0x19 |
- | 6059 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
|
5589 | #define GEN6_PCODE_DATA 0x138128 |
6060 | #define GEN6_PCODE_DATA 0x138128 |
5590 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
6061 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
5591 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
6062 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
- | 6063 | #define GEN6_PCODE_DATA1 0x13812C |
|
- | 6064 | ||
- | 6065 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
|
- | 6066 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF |
|
- | 6067 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 |
|
- | 6068 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 |
|
- | 6069 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 |
|
5592 | 6070 | ||
5593 | #define GEN6_GT_CORE_STATUS 0x138060 |
6071 | #define GEN6_GT_CORE_STATUS 0x138060 |
5594 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) |
6072 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) |
5595 | #define GEN6_RCn_MASK 7 |
6073 | #define GEN6_RCn_MASK 7 |
5596 | #define GEN6_RC0 0 |
6074 | #define GEN6_RC0 0 |
5597 | #define GEN6_RC3 2 |
6075 | #define GEN6_RC3 2 |
5598 | #define GEN6_RC6 3 |
6076 | #define GEN6_RC6 3 |
5599 | #define GEN6_RC7 4 |
6077 | #define GEN6_RC7 4 |
5600 | 6078 | ||
5601 | #define GEN7_MISCCPCTL (0x9424) |
6079 | #define GEN7_MISCCPCTL (0x9424) |
5602 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
6080 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
5603 | 6081 | ||
5604 | /* IVYBRIDGE DPF */ |
6082 | /* IVYBRIDGE DPF */ |
5605 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
6083 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
5606 | #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ |
6084 | #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ |
5607 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
6085 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
5608 | #define GEN7_PARITY_ERROR_VALID (1<<13) |
6086 | #define GEN7_PARITY_ERROR_VALID (1<<13) |
5609 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) |
6087 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) |
5610 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
6088 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
5611 | #define GEN7_PARITY_ERROR_ROW(reg) \ |
6089 | #define GEN7_PARITY_ERROR_ROW(reg) \ |
5612 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
6090 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
5613 | #define GEN7_PARITY_ERROR_BANK(reg) \ |
6091 | #define GEN7_PARITY_ERROR_BANK(reg) \ |
5614 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
6092 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
5615 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
6093 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
5616 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
6094 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
5617 | #define GEN7_L3CDERRST1_ENABLE (1<<7) |
6095 | #define GEN7_L3CDERRST1_ENABLE (1<<7) |
5618 | 6096 | ||
5619 | #define GEN7_L3LOG_BASE 0xB070 |
6097 | #define GEN7_L3LOG_BASE 0xB070 |
5620 | #define HSW_L3LOG_BASE_SLICE1 0xB270 |
6098 | #define HSW_L3LOG_BASE_SLICE1 0xB270 |
5621 | #define GEN7_L3LOG_SIZE 0x80 |
6099 | #define GEN7_L3LOG_SIZE 0x80 |
5622 | 6100 | ||
5623 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
6101 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
5624 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
6102 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 |
5625 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
6103 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
5626 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
6104 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
5627 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
6105 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
- | 6106 | ||
- | 6107 | #define GEN9_HALF_SLICE_CHICKEN5 0xe188 |
|
- | 6108 | #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) |
|
5628 | 6109 | ||
5629 | #define GEN8_ROW_CHICKEN 0xe4f0 |
6110 | #define GEN8_ROW_CHICKEN 0xe4f0 |
5630 | #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) |
6111 | #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) |
5631 | #define STALL_DOP_GATING_DISABLE (1<<5) |
6112 | #define STALL_DOP_GATING_DISABLE (1<<5) |
5632 | 6113 | ||
5633 | #define GEN7_ROW_CHICKEN2 0xe4f4 |
6114 | #define GEN7_ROW_CHICKEN2 0xe4f4 |
5634 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
6115 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
5635 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
6116 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
5636 | 6117 | ||
5637 | #define HSW_ROW_CHICKEN3 0xe49c |
6118 | #define HSW_ROW_CHICKEN3 0xe49c |
5638 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
6119 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
5639 | 6120 | ||
5640 | #define HALF_SLICE_CHICKEN3 0xe184 |
6121 | #define HALF_SLICE_CHICKEN3 0xe184 |
5641 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
6122 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
5642 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
6123 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
- | 6124 | ||
5643 | 6125 | /* Audio */ |
|
5644 | #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
6126 | #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
5645 | #define INTEL_AUDIO_DEVCL 0x808629FB |
6127 | #define INTEL_AUDIO_DEVCL 0x808629FB |
5646 | #define INTEL_AUDIO_DEVBLC 0x80862801 |
6128 | #define INTEL_AUDIO_DEVBLC 0x80862801 |
5647 | #define INTEL_AUDIO_DEVCTG 0x80862802 |
6129 | #define INTEL_AUDIO_DEVCTG 0x80862802 |
5648 | 6130 | ||
5649 | #define G4X_AUD_CNTL_ST 0x620B4 |
6131 | #define G4X_AUD_CNTL_ST 0x620B4 |
5650 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
6132 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
5651 | #define G4X_ELDV_DEVCTG (1 << 14) |
6133 | #define G4X_ELDV_DEVCTG (1 << 14) |
5652 | #define G4X_ELD_ADDR (0xf << 5) |
6134 | #define G4X_ELD_ADDR_MASK (0xf << 5) |
5653 | #define G4X_ELD_ACK (1 << 4) |
6135 | #define G4X_ELD_ACK (1 << 4) |
5654 | #define G4X_HDMIW_HDMIEDID 0x6210C |
6136 | #define G4X_HDMIW_HDMIEDID 0x6210C |
5655 | 6137 | ||
5656 | #define IBX_HDMIW_HDMIEDID_A 0xE2050 |
6138 | #define _IBX_HDMIW_HDMIEDID_A 0xE2050 |
5657 | #define IBX_HDMIW_HDMIEDID_B 0xE2150 |
6139 | #define _IBX_HDMIW_HDMIEDID_B 0xE2150 |
5658 | #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
6140 | #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
5659 | IBX_HDMIW_HDMIEDID_A, \ |
6141 | _IBX_HDMIW_HDMIEDID_A, \ |
5660 | IBX_HDMIW_HDMIEDID_B) |
6142 | _IBX_HDMIW_HDMIEDID_B) |
5661 | #define IBX_AUD_CNTL_ST_A 0xE20B4 |
6143 | #define _IBX_AUD_CNTL_ST_A 0xE20B4 |
5662 | #define IBX_AUD_CNTL_ST_B 0xE21B4 |
6144 | #define _IBX_AUD_CNTL_ST_B 0xE21B4 |
5663 | #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
6145 | #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
5664 | IBX_AUD_CNTL_ST_A, \ |
6146 | _IBX_AUD_CNTL_ST_A, \ |
5665 | IBX_AUD_CNTL_ST_B) |
6147 | _IBX_AUD_CNTL_ST_B) |
5666 | #define IBX_ELD_BUFFER_SIZE (0x1f << 10) |
6148 | #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) |
5667 | #define IBX_ELD_ADDRESS (0x1f << 5) |
6149 | #define IBX_ELD_ADDRESS_MASK (0x1f << 5) |
5668 | #define IBX_ELD_ACK (1 << 4) |
6150 | #define IBX_ELD_ACK (1 << 4) |
5669 | #define IBX_AUD_CNTL_ST2 0xE20C0 |
6151 | #define IBX_AUD_CNTL_ST2 0xE20C0 |
5670 | #define IBX_ELD_VALIDB (1 << 0) |
6152 | #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) |
5671 | #define IBX_CP_READYB (1 << 1) |
6153 | #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) |
5672 | 6154 | ||
5673 | #define CPT_HDMIW_HDMIEDID_A 0xE5050 |
6155 | #define _CPT_HDMIW_HDMIEDID_A 0xE5050 |
5674 | #define CPT_HDMIW_HDMIEDID_B 0xE5150 |
6156 | #define _CPT_HDMIW_HDMIEDID_B 0xE5150 |
5675 | #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
6157 | #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
5676 | CPT_HDMIW_HDMIEDID_A, \ |
6158 | _CPT_HDMIW_HDMIEDID_A, \ |
5677 | CPT_HDMIW_HDMIEDID_B) |
6159 | _CPT_HDMIW_HDMIEDID_B) |
5678 | #define CPT_AUD_CNTL_ST_A 0xE50B4 |
6160 | #define _CPT_AUD_CNTL_ST_A 0xE50B4 |
5679 | #define CPT_AUD_CNTL_ST_B 0xE51B4 |
6161 | #define _CPT_AUD_CNTL_ST_B 0xE51B4 |
5680 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
6162 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
5681 | CPT_AUD_CNTL_ST_A, \ |
6163 | _CPT_AUD_CNTL_ST_A, \ |
5682 | CPT_AUD_CNTL_ST_B) |
6164 | _CPT_AUD_CNTL_ST_B) |
5683 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
6165 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
5684 | 6166 | ||
5685 | #define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
6167 | #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
5686 | #define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) |
6168 | #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) |
5687 | #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
6169 | #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
5688 | VLV_HDMIW_HDMIEDID_A, \ |
6170 | _VLV_HDMIW_HDMIEDID_A, \ |
5689 | VLV_HDMIW_HDMIEDID_B) |
6171 | _VLV_HDMIW_HDMIEDID_B) |
5690 | #define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
6172 | #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
5691 | #define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) |
6173 | #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) |
5692 | #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
6174 | #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
5693 | VLV_AUD_CNTL_ST_A, \ |
6175 | _VLV_AUD_CNTL_ST_A, \ |
5694 | VLV_AUD_CNTL_ST_B) |
6176 | _VLV_AUD_CNTL_ST_B) |
5695 | #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) |
6177 | #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) |
5696 | 6178 | ||
5697 | /* These are the 4 32-bit write offset registers for each stream |
6179 | /* These are the 4 32-bit write offset registers for each stream |
5698 | * output buffer. It determines the offset from the |
6180 | * output buffer. It determines the offset from the |
5699 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
6181 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
5700 | */ |
6182 | */ |
5701 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) |
6183 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) |
5702 | 6184 | ||
5703 | #define IBX_AUD_CONFIG_A 0xe2000 |
6185 | #define _IBX_AUD_CONFIG_A 0xe2000 |
5704 | #define IBX_AUD_CONFIG_B 0xe2100 |
6186 | #define _IBX_AUD_CONFIG_B 0xe2100 |
5705 | #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ |
6187 | #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ |
5706 | IBX_AUD_CONFIG_A, \ |
6188 | _IBX_AUD_CONFIG_A, \ |
5707 | IBX_AUD_CONFIG_B) |
6189 | _IBX_AUD_CONFIG_B) |
5708 | #define CPT_AUD_CONFIG_A 0xe5000 |
6190 | #define _CPT_AUD_CONFIG_A 0xe5000 |
5709 | #define CPT_AUD_CONFIG_B 0xe5100 |
6191 | #define _CPT_AUD_CONFIG_B 0xe5100 |
5710 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
6192 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
5711 | CPT_AUD_CONFIG_A, \ |
6193 | _CPT_AUD_CONFIG_A, \ |
5712 | CPT_AUD_CONFIG_B) |
6194 | _CPT_AUD_CONFIG_B) |
5713 | #define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
6195 | #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
5714 | #define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) |
6196 | #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) |
5715 | #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ |
6197 | #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ |
5716 | VLV_AUD_CONFIG_A, \ |
6198 | _VLV_AUD_CONFIG_A, \ |
5717 | VLV_AUD_CONFIG_B) |
6199 | _VLV_AUD_CONFIG_B) |
5718 | 6200 | ||
5719 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
6201 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
5720 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
6202 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
5721 | #define AUD_CONFIG_UPPER_N_SHIFT 20 |
6203 | #define AUD_CONFIG_UPPER_N_SHIFT 20 |
5722 | #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
6204 | #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) |
5723 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
6205 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
5724 | #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
6206 | #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) |
5725 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
6207 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
5726 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
6208 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
5727 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) |
6209 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) |
5728 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) |
6210 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) |
5729 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) |
6211 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) |
5730 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) |
6212 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) |
5731 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) |
6213 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) |
5732 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) |
6214 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) |
5733 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) |
6215 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) |
5734 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) |
6216 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) |
5735 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) |
6217 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) |
5736 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) |
6218 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) |
5737 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
6219 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
5738 | 6220 | ||
5739 | /* HSW Audio */ |
6221 | /* HSW Audio */ |
5740 | #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
6222 | #define _HSW_AUD_CONFIG_A 0x65000 |
5741 | #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ |
6223 | #define _HSW_AUD_CONFIG_B 0x65100 |
5742 | #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ |
6224 | #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ |
5743 | HSW_AUD_CONFIG_A, \ |
6225 | _HSW_AUD_CONFIG_A, \ |
5744 | HSW_AUD_CONFIG_B) |
6226 | _HSW_AUD_CONFIG_B) |
5745 | 6227 | ||
5746 | #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ |
6228 | #define _HSW_AUD_MISC_CTRL_A 0x65010 |
5747 | #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ |
6229 | #define _HSW_AUD_MISC_CTRL_B 0x65110 |
5748 | #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ |
6230 | #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ |
5749 | HSW_AUD_MISC_CTRL_A, \ |
6231 | _HSW_AUD_MISC_CTRL_A, \ |
5750 | HSW_AUD_MISC_CTRL_B) |
6232 | _HSW_AUD_MISC_CTRL_B) |
5751 | 6233 | ||
5752 | #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ |
6234 | #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 |
5753 | #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ |
6235 | #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 |
5754 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ |
6236 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ |
5755 | HSW_AUD_DIP_ELD_CTRL_ST_A, \ |
6237 | _HSW_AUD_DIP_ELD_CTRL_ST_A, \ |
5756 | HSW_AUD_DIP_ELD_CTRL_ST_B) |
6238 | _HSW_AUD_DIP_ELD_CTRL_ST_B) |
5757 | 6239 | ||
5758 | /* Audio Digital Converter */ |
6240 | /* Audio Digital Converter */ |
5759 | #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ |
6241 | #define _HSW_AUD_DIG_CNVT_1 0x65080 |
5760 | #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ |
6242 | #define _HSW_AUD_DIG_CNVT_2 0x65180 |
5761 | #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ |
6243 | #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ |
5762 | HSW_AUD_DIG_CNVT_1, \ |
6244 | _HSW_AUD_DIG_CNVT_1, \ |
5763 | HSW_AUD_DIG_CNVT_2) |
6245 | _HSW_AUD_DIG_CNVT_2) |
5764 | #define DIP_PORT_SEL_MASK 0x3 |
6246 | #define DIP_PORT_SEL_MASK 0x3 |
5765 | 6247 | ||
5766 | #define HSW_AUD_EDID_DATA_A 0x65050 |
6248 | #define _HSW_AUD_EDID_DATA_A 0x65050 |
5767 | #define HSW_AUD_EDID_DATA_B 0x65150 |
- | |
5768 | #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ |
- | |
5769 | HSW_AUD_EDID_DATA_A, \ |
6249 | #define _HSW_AUD_EDID_DATA_B 0x65150 |
5770 | HSW_AUD_EDID_DATA_B) |
6250 | #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ |
5771 | 6251 | _HSW_AUD_EDID_DATA_A, \ |
|
5772 | #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ |
6252 | _HSW_AUD_EDID_DATA_B) |
5773 | #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ |
- | |
5774 | #define AUDIO_INACTIVE_C (1<<11) |
6253 | |
5775 | #define AUDIO_INACTIVE_B (1<<7) |
- | |
5776 | #define AUDIO_INACTIVE_A (1<<3) |
6254 | #define HSW_AUD_PIPE_CONV_CFG 0x6507c |
5777 | #define AUDIO_OUTPUT_ENABLE_A (1<<2) |
- | |
5778 | #define AUDIO_OUTPUT_ENABLE_B (1<<6) |
- | |
5779 | #define AUDIO_OUTPUT_ENABLE_C (1<<10) |
- | |
5780 | #define AUDIO_ELD_VALID_A (1<<0) |
- | |
5781 | #define AUDIO_ELD_VALID_B (1<<4) |
6255 | #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 |
5782 | #define AUDIO_ELD_VALID_C (1<<8) |
6256 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
5783 | #define AUDIO_CP_READY_A (1<<1) |
6257 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) |
5784 | #define AUDIO_CP_READY_B (1<<5) |
6258 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) |
5785 | #define AUDIO_CP_READY_C (1<<9) |
6259 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) |
5786 | 6260 | ||
5787 | /* HSW Power Wells */ |
6261 | /* HSW Power Wells */ |
5788 | #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ |
6262 | #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ |
5789 | #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ |
6263 | #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ |
5790 | #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ |
6264 | #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ |
5791 | #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ |
6265 | #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ |
5792 | #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) |
6266 | #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) |
5793 | #define HSW_PWR_WELL_STATE_ENABLED (1<<30) |
6267 | #define HSW_PWR_WELL_STATE_ENABLED (1<<30) |
5794 | #define HSW_PWR_WELL_CTL5 0x45410 |
6268 | #define HSW_PWR_WELL_CTL5 0x45410 |
5795 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
6269 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
5796 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
6270 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
5797 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
6271 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
5798 | #define HSW_PWR_WELL_CTL6 0x45414 |
6272 | #define HSW_PWR_WELL_CTL6 0x45414 |
5799 | 6273 | ||
5800 | /* Per-pipe DDI Function Control */ |
6274 | /* Per-pipe DDI Function Control */ |
5801 | #define TRANS_DDI_FUNC_CTL_A 0x60400 |
6275 | #define TRANS_DDI_FUNC_CTL_A 0x60400 |
5802 | #define TRANS_DDI_FUNC_CTL_B 0x61400 |
6276 | #define TRANS_DDI_FUNC_CTL_B 0x61400 |
5803 | #define TRANS_DDI_FUNC_CTL_C 0x62400 |
6277 | #define TRANS_DDI_FUNC_CTL_C 0x62400 |
5804 | #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
6278 | #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
5805 | #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) |
6279 | #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) |
5806 | 6280 | ||
5807 | #define TRANS_DDI_FUNC_ENABLE (1<<31) |
6281 | #define TRANS_DDI_FUNC_ENABLE (1<<31) |
5808 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
6282 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
5809 | #define TRANS_DDI_PORT_MASK (7<<28) |
6283 | #define TRANS_DDI_PORT_MASK (7<<28) |
5810 | #define TRANS_DDI_PORT_SHIFT 28 |
6284 | #define TRANS_DDI_PORT_SHIFT 28 |
5811 | #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) |
6285 | #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) |
5812 | #define TRANS_DDI_PORT_NONE (0<<28) |
6286 | #define TRANS_DDI_PORT_NONE (0<<28) |
5813 | #define TRANS_DDI_MODE_SELECT_MASK (7<<24) |
6287 | #define TRANS_DDI_MODE_SELECT_MASK (7<<24) |
5814 | #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) |
6288 | #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) |
5815 | #define TRANS_DDI_MODE_SELECT_DVI (1<<24) |
6289 | #define TRANS_DDI_MODE_SELECT_DVI (1<<24) |
5816 | #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) |
6290 | #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) |
5817 | #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) |
6291 | #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) |
5818 | #define TRANS_DDI_MODE_SELECT_FDI (4<<24) |
6292 | #define TRANS_DDI_MODE_SELECT_FDI (4<<24) |
5819 | #define TRANS_DDI_BPC_MASK (7<<20) |
6293 | #define TRANS_DDI_BPC_MASK (7<<20) |
5820 | #define TRANS_DDI_BPC_8 (0<<20) |
6294 | #define TRANS_DDI_BPC_8 (0<<20) |
5821 | #define TRANS_DDI_BPC_10 (1<<20) |
6295 | #define TRANS_DDI_BPC_10 (1<<20) |
5822 | #define TRANS_DDI_BPC_6 (2<<20) |
6296 | #define TRANS_DDI_BPC_6 (2<<20) |
5823 | #define TRANS_DDI_BPC_12 (3<<20) |
6297 | #define TRANS_DDI_BPC_12 (3<<20) |
5824 | #define TRANS_DDI_PVSYNC (1<<17) |
6298 | #define TRANS_DDI_PVSYNC (1<<17) |
5825 | #define TRANS_DDI_PHSYNC (1<<16) |
6299 | #define TRANS_DDI_PHSYNC (1<<16) |
5826 | #define TRANS_DDI_EDP_INPUT_MASK (7<<12) |
6300 | #define TRANS_DDI_EDP_INPUT_MASK (7<<12) |
5827 | #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) |
6301 | #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) |
5828 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) |
6302 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) |
5829 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) |
6303 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) |
5830 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) |
6304 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) |
5831 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) |
6305 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) |
5832 | #define TRANS_DDI_BFI_ENABLE (1<<4) |
6306 | #define TRANS_DDI_BFI_ENABLE (1<<4) |
5833 | 6307 | ||
5834 | /* DisplayPort Transport Control */ |
6308 | /* DisplayPort Transport Control */ |
5835 | #define DP_TP_CTL_A 0x64040 |
6309 | #define DP_TP_CTL_A 0x64040 |
5836 | #define DP_TP_CTL_B 0x64140 |
6310 | #define DP_TP_CTL_B 0x64140 |
5837 | #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
6311 | #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
5838 | #define DP_TP_CTL_ENABLE (1<<31) |
6312 | #define DP_TP_CTL_ENABLE (1<<31) |
5839 | #define DP_TP_CTL_MODE_SST (0<<27) |
6313 | #define DP_TP_CTL_MODE_SST (0<<27) |
5840 | #define DP_TP_CTL_MODE_MST (1<<27) |
6314 | #define DP_TP_CTL_MODE_MST (1<<27) |
5841 | #define DP_TP_CTL_FORCE_ACT (1<<25) |
6315 | #define DP_TP_CTL_FORCE_ACT (1<<25) |
5842 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
6316 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
5843 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
6317 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
5844 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
6318 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
5845 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) |
6319 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) |
5846 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) |
6320 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) |
5847 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
6321 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
5848 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) |
6322 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) |
5849 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
6323 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
5850 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
6324 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
5851 | 6325 | ||
5852 | /* DisplayPort Transport Status */ |
6326 | /* DisplayPort Transport Status */ |
5853 | #define DP_TP_STATUS_A 0x64044 |
6327 | #define DP_TP_STATUS_A 0x64044 |
5854 | #define DP_TP_STATUS_B 0x64144 |
6328 | #define DP_TP_STATUS_B 0x64144 |
5855 | #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
6329 | #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
5856 | #define DP_TP_STATUS_IDLE_DONE (1<<25) |
6330 | #define DP_TP_STATUS_IDLE_DONE (1<<25) |
5857 | #define DP_TP_STATUS_ACT_SENT (1<<24) |
6331 | #define DP_TP_STATUS_ACT_SENT (1<<24) |
5858 | #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) |
6332 | #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) |
5859 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
6333 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
5860 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) |
6334 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) |
5861 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) |
6335 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) |
5862 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) |
6336 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) |
5863 | 6337 | ||
5864 | /* DDI Buffer Control */ |
6338 | /* DDI Buffer Control */ |
5865 | #define DDI_BUF_CTL_A 0x64000 |
6339 | #define DDI_BUF_CTL_A 0x64000 |
5866 | #define DDI_BUF_CTL_B 0x64100 |
6340 | #define DDI_BUF_CTL_B 0x64100 |
5867 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
6341 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
5868 | #define DDI_BUF_CTL_ENABLE (1<<31) |
6342 | #define DDI_BUF_CTL_ENABLE (1<<31) |
5869 | #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
- | |
5870 | #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
- | |
5871 | #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
- | |
5872 | #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
- | |
5873 | #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
6343 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
5874 | #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
- | |
5875 | #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
- | |
5876 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
- | |
5877 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
- | |
5878 | #define DDI_BUF_EMP_MASK (0xf<<24) |
6344 | #define DDI_BUF_EMP_MASK (0xf<<24) |
5879 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
6345 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
5880 | #define DDI_BUF_IS_IDLE (1<<7) |
6346 | #define DDI_BUF_IS_IDLE (1<<7) |
5881 | #define DDI_A_4_LANES (1<<4) |
6347 | #define DDI_A_4_LANES (1<<4) |
5882 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
6348 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
5883 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
6349 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
5884 | 6350 | ||
5885 | /* DDI Buffer Translations */ |
6351 | /* DDI Buffer Translations */ |
5886 | #define DDI_BUF_TRANS_A 0x64E00 |
6352 | #define DDI_BUF_TRANS_A 0x64E00 |
5887 | #define DDI_BUF_TRANS_B 0x64E60 |
6353 | #define DDI_BUF_TRANS_B 0x64E60 |
5888 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
6354 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
5889 | 6355 | ||
5890 | /* Sideband Interface (SBI) is programmed indirectly, via |
6356 | /* Sideband Interface (SBI) is programmed indirectly, via |
5891 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
6357 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
5892 | * which contains the payload */ |
6358 | * which contains the payload */ |
5893 | #define SBI_ADDR 0xC6000 |
6359 | #define SBI_ADDR 0xC6000 |
5894 | #define SBI_DATA 0xC6004 |
6360 | #define SBI_DATA 0xC6004 |
5895 | #define SBI_CTL_STAT 0xC6008 |
6361 | #define SBI_CTL_STAT 0xC6008 |
5896 | #define SBI_CTL_DEST_ICLK (0x0<<16) |
6362 | #define SBI_CTL_DEST_ICLK (0x0<<16) |
5897 | #define SBI_CTL_DEST_MPHY (0x1<<16) |
6363 | #define SBI_CTL_DEST_MPHY (0x1<<16) |
5898 | #define SBI_CTL_OP_IORD (0x2<<8) |
6364 | #define SBI_CTL_OP_IORD (0x2<<8) |
5899 | #define SBI_CTL_OP_IOWR (0x3<<8) |
6365 | #define SBI_CTL_OP_IOWR (0x3<<8) |
5900 | #define SBI_CTL_OP_CRRD (0x6<<8) |
6366 | #define SBI_CTL_OP_CRRD (0x6<<8) |
5901 | #define SBI_CTL_OP_CRWR (0x7<<8) |
6367 | #define SBI_CTL_OP_CRWR (0x7<<8) |
5902 | #define SBI_RESPONSE_FAIL (0x1<<1) |
6368 | #define SBI_RESPONSE_FAIL (0x1<<1) |
5903 | #define SBI_RESPONSE_SUCCESS (0x0<<1) |
6369 | #define SBI_RESPONSE_SUCCESS (0x0<<1) |
5904 | #define SBI_BUSY (0x1<<0) |
6370 | #define SBI_BUSY (0x1<<0) |
5905 | #define SBI_READY (0x0<<0) |
6371 | #define SBI_READY (0x0<<0) |
5906 | 6372 | ||
5907 | /* SBI offsets */ |
6373 | /* SBI offsets */ |
5908 | #define SBI_SSCDIVINTPHASE6 0x0600 |
6374 | #define SBI_SSCDIVINTPHASE6 0x0600 |
5909 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
6375 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
5910 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) |
6376 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) |
5911 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) |
6377 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) |
5912 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) |
6378 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) |
5913 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
6379 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
5914 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
6380 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
5915 | #define SBI_SSCCTL 0x020c |
6381 | #define SBI_SSCCTL 0x020c |
5916 | #define SBI_SSCCTL6 0x060C |
6382 | #define SBI_SSCCTL6 0x060C |
5917 | #define SBI_SSCCTL_PATHALT (1<<3) |
6383 | #define SBI_SSCCTL_PATHALT (1<<3) |
5918 | #define SBI_SSCCTL_DISABLE (1<<0) |
6384 | #define SBI_SSCCTL_DISABLE (1<<0) |
5919 | #define SBI_SSCAUXDIV6 0x0610 |
6385 | #define SBI_SSCAUXDIV6 0x0610 |
5920 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) |
6386 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) |
5921 | #define SBI_DBUFF0 0x2a00 |
6387 | #define SBI_DBUFF0 0x2a00 |
5922 | #define SBI_GEN0 0x1f00 |
6388 | #define SBI_GEN0 0x1f00 |
5923 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) |
6389 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) |
5924 | 6390 | ||
5925 | /* LPT PIXCLK_GATE */ |
6391 | /* LPT PIXCLK_GATE */ |
5926 | #define PIXCLK_GATE 0xC6020 |
6392 | #define PIXCLK_GATE 0xC6020 |
5927 | #define PIXCLK_GATE_UNGATE (1<<0) |
6393 | #define PIXCLK_GATE_UNGATE (1<<0) |
5928 | #define PIXCLK_GATE_GATE (0<<0) |
6394 | #define PIXCLK_GATE_GATE (0<<0) |
5929 | 6395 | ||
5930 | /* SPLL */ |
6396 | /* SPLL */ |
5931 | #define SPLL_CTL 0x46020 |
6397 | #define SPLL_CTL 0x46020 |
5932 | #define SPLL_PLL_ENABLE (1<<31) |
6398 | #define SPLL_PLL_ENABLE (1<<31) |
5933 | #define SPLL_PLL_SSC (1<<28) |
6399 | #define SPLL_PLL_SSC (1<<28) |
5934 | #define SPLL_PLL_NON_SSC (2<<28) |
6400 | #define SPLL_PLL_NON_SSC (2<<28) |
5935 | #define SPLL_PLL_LCPLL (3<<28) |
6401 | #define SPLL_PLL_LCPLL (3<<28) |
5936 | #define SPLL_PLL_REF_MASK (3<<28) |
6402 | #define SPLL_PLL_REF_MASK (3<<28) |
5937 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
6403 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
5938 | #define SPLL_PLL_FREQ_1350MHz (1<<26) |
6404 | #define SPLL_PLL_FREQ_1350MHz (1<<26) |
5939 | #define SPLL_PLL_FREQ_2700MHz (2<<26) |
6405 | #define SPLL_PLL_FREQ_2700MHz (2<<26) |
5940 | #define SPLL_PLL_FREQ_MASK (3<<26) |
6406 | #define SPLL_PLL_FREQ_MASK (3<<26) |
5941 | 6407 | ||
5942 | /* WRPLL */ |
6408 | /* WRPLL */ |
5943 | #define WRPLL_CTL1 0x46040 |
6409 | #define WRPLL_CTL1 0x46040 |
5944 | #define WRPLL_CTL2 0x46060 |
6410 | #define WRPLL_CTL2 0x46060 |
5945 | #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) |
6411 | #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) |
5946 | #define WRPLL_PLL_ENABLE (1<<31) |
6412 | #define WRPLL_PLL_ENABLE (1<<31) |
5947 | #define WRPLL_PLL_SSC (1<<28) |
6413 | #define WRPLL_PLL_SSC (1<<28) |
5948 | #define WRPLL_PLL_NON_SSC (2<<28) |
6414 | #define WRPLL_PLL_NON_SSC (2<<28) |
5949 | #define WRPLL_PLL_LCPLL (3<<28) |
6415 | #define WRPLL_PLL_LCPLL (3<<28) |
5950 | #define WRPLL_PLL_REF_MASK (3<<28) |
6416 | #define WRPLL_PLL_REF_MASK (3<<28) |
5951 | /* WRPLL divider programming */ |
6417 | /* WRPLL divider programming */ |
5952 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
6418 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
5953 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
6419 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
5954 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) |
6420 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) |
5955 | #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) |
6421 | #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) |
5956 | #define WRPLL_DIVIDER_POST_SHIFT 8 |
6422 | #define WRPLL_DIVIDER_POST_SHIFT 8 |
5957 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
6423 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
5958 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
6424 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
5959 | #define WRPLL_DIVIDER_FB_MASK (0xff<<16) |
6425 | #define WRPLL_DIVIDER_FB_MASK (0xff<<16) |
5960 | 6426 | ||
5961 | /* Port clock selection */ |
6427 | /* Port clock selection */ |
5962 | #define PORT_CLK_SEL_A 0x46100 |
6428 | #define PORT_CLK_SEL_A 0x46100 |
5963 | #define PORT_CLK_SEL_B 0x46104 |
6429 | #define PORT_CLK_SEL_B 0x46104 |
5964 | #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
6430 | #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
5965 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
6431 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
5966 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) |
6432 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) |
5967 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) |
6433 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) |
5968 | #define PORT_CLK_SEL_SPLL (3<<29) |
6434 | #define PORT_CLK_SEL_SPLL (3<<29) |
5969 | #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) |
6435 | #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) |
5970 | #define PORT_CLK_SEL_WRPLL1 (4<<29) |
6436 | #define PORT_CLK_SEL_WRPLL1 (4<<29) |
5971 | #define PORT_CLK_SEL_WRPLL2 (5<<29) |
6437 | #define PORT_CLK_SEL_WRPLL2 (5<<29) |
5972 | #define PORT_CLK_SEL_NONE (7<<29) |
6438 | #define PORT_CLK_SEL_NONE (7<<29) |
5973 | #define PORT_CLK_SEL_MASK (7<<29) |
6439 | #define PORT_CLK_SEL_MASK (7<<29) |
5974 | 6440 | ||
5975 | /* Transcoder clock selection */ |
6441 | /* Transcoder clock selection */ |
5976 | #define TRANS_CLK_SEL_A 0x46140 |
6442 | #define TRANS_CLK_SEL_A 0x46140 |
5977 | #define TRANS_CLK_SEL_B 0x46144 |
6443 | #define TRANS_CLK_SEL_B 0x46144 |
5978 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
6444 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) |
5979 | /* For each transcoder, we need to select the corresponding port clock */ |
6445 | /* For each transcoder, we need to select the corresponding port clock */ |
5980 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
6446 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
5981 | #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) |
6447 | #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) |
5982 | 6448 | ||
5983 | #define TRANSA_MSA_MISC 0x60410 |
6449 | #define TRANSA_MSA_MISC 0x60410 |
5984 | #define TRANSB_MSA_MISC 0x61410 |
6450 | #define TRANSB_MSA_MISC 0x61410 |
5985 | #define TRANSC_MSA_MISC 0x62410 |
6451 | #define TRANSC_MSA_MISC 0x62410 |
5986 | #define TRANS_EDP_MSA_MISC 0x6f410 |
6452 | #define TRANS_EDP_MSA_MISC 0x6f410 |
5987 | #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) |
6453 | #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) |
5988 | 6454 | ||
5989 | #define TRANS_MSA_SYNC_CLK (1<<0) |
6455 | #define TRANS_MSA_SYNC_CLK (1<<0) |
5990 | #define TRANS_MSA_6_BPC (0<<5) |
6456 | #define TRANS_MSA_6_BPC (0<<5) |
5991 | #define TRANS_MSA_8_BPC (1<<5) |
6457 | #define TRANS_MSA_8_BPC (1<<5) |
5992 | #define TRANS_MSA_10_BPC (2<<5) |
6458 | #define TRANS_MSA_10_BPC (2<<5) |
5993 | #define TRANS_MSA_12_BPC (3<<5) |
6459 | #define TRANS_MSA_12_BPC (3<<5) |
5994 | #define TRANS_MSA_16_BPC (4<<5) |
6460 | #define TRANS_MSA_16_BPC (4<<5) |
5995 | 6461 | ||
5996 | /* LCPLL Control */ |
6462 | /* LCPLL Control */ |
5997 | #define LCPLL_CTL 0x130040 |
6463 | #define LCPLL_CTL 0x130040 |
5998 | #define LCPLL_PLL_DISABLE (1<<31) |
6464 | #define LCPLL_PLL_DISABLE (1<<31) |
5999 | #define LCPLL_PLL_LOCK (1<<30) |
6465 | #define LCPLL_PLL_LOCK (1<<30) |
6000 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
6466 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
6001 | #define LCPLL_CLK_FREQ_450 (0<<26) |
6467 | #define LCPLL_CLK_FREQ_450 (0<<26) |
6002 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
6468 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
6003 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) |
6469 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) |
6004 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) |
6470 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) |
6005 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
6471 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
6006 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
6472 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
6007 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
6473 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
6008 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
6474 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
6009 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
6475 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
- | 6476 | ||
- | 6477 | /* |
|
- | 6478 | * SKL Clocks |
|
- | 6479 | */ |
|
- | 6480 | ||
- | 6481 | /* CDCLK_CTL */ |
|
- | 6482 | #define CDCLK_CTL 0x46000 |
|
- | 6483 | #define CDCLK_FREQ_SEL_MASK (3<<26) |
|
- | 6484 | #define CDCLK_FREQ_450_432 (0<<26) |
|
- | 6485 | #define CDCLK_FREQ_540 (1<<26) |
|
- | 6486 | #define CDCLK_FREQ_337_308 (2<<26) |
|
- | 6487 | #define CDCLK_FREQ_675_617 (3<<26) |
|
- | 6488 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
|
- | 6489 | ||
- | 6490 | /* LCPLL_CTL */ |
|
- | 6491 | #define LCPLL1_CTL 0x46010 |
|
- | 6492 | #define LCPLL2_CTL 0x46014 |
|
- | 6493 | #define LCPLL_PLL_ENABLE (1<<31) |
|
- | 6494 | ||
- | 6495 | /* DPLL control1 */ |
|
- | 6496 | #define DPLL_CTRL1 0x6C058 |
|
- | 6497 | #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) |
|
- | 6498 | #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) |
|
- | 6499 | #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) |
|
- | 6500 | #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) |
|
- | 6501 | #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) |
|
- | 6502 | #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) |
|
- | 6503 | #define DPLL_CRTL1_LINK_RATE_2700 0 |
|
- | 6504 | #define DPLL_CRTL1_LINK_RATE_1350 1 |
|
- | 6505 | #define DPLL_CRTL1_LINK_RATE_810 2 |
|
- | 6506 | #define DPLL_CRTL1_LINK_RATE_1620 3 |
|
- | 6507 | #define DPLL_CRTL1_LINK_RATE_1080 4 |
|
- | 6508 | #define DPLL_CRTL1_LINK_RATE_2160 5 |
|
- | 6509 | ||
- | 6510 | /* DPLL control2 */ |
|
- | 6511 | #define DPLL_CTRL2 0x6C05C |
|
- | 6512 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) |
|
- | 6513 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) |
|
- | 6514 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) |
|
- | 6515 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) |
|
- | 6516 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) |
|
- | 6517 | ||
- | 6518 | /* DPLL Status */ |
|
- | 6519 | #define DPLL_STATUS 0x6C060 |
|
- | 6520 | #define DPLL_LOCK(id) (1<<((id)*8)) |
|
- | 6521 | ||
- | 6522 | /* DPLL cfg */ |
|
- | 6523 | #define DPLL1_CFGCR1 0x6C040 |
|
- | 6524 | #define DPLL2_CFGCR1 0x6C048 |
|
- | 6525 | #define DPLL3_CFGCR1 0x6C050 |
|
- | 6526 | #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) |
|
- | 6527 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) |
|
- | 6528 | #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) |
|
- | 6529 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
|
- | 6530 | ||
- | 6531 | #define DPLL1_CFGCR2 0x6C044 |
|
- | 6532 | #define DPLL2_CFGCR2 0x6C04C |
|
- | 6533 | #define DPLL3_CFGCR2 0x6C054 |
|
- | 6534 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) |
|
- | 6535 | #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) |
|
- | 6536 | #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) |
|
- | 6537 | #define DPLL_CFGCR2_KDIV_MASK (3<<5) |
|
- | 6538 | #define DPLL_CFGCR2_KDIV(x) (x<<5) |
|
- | 6539 | #define DPLL_CFGCR2_KDIV_5 (0<<5) |
|
- | 6540 | #define DPLL_CFGCR2_KDIV_2 (1<<5) |
|
- | 6541 | #define DPLL_CFGCR2_KDIV_3 (2<<5) |
|
- | 6542 | #define DPLL_CFGCR2_KDIV_1 (3<<5) |
|
- | 6543 | #define DPLL_CFGCR2_PDIV_MASK (7<<2) |
|
- | 6544 | #define DPLL_CFGCR2_PDIV(x) (x<<2) |
|
- | 6545 | #define DPLL_CFGCR2_PDIV_1 (0<<2) |
|
- | 6546 | #define DPLL_CFGCR2_PDIV_2 (1<<2) |
|
- | 6547 | #define DPLL_CFGCR2_PDIV_3 (2<<2) |
|
- | 6548 | #define DPLL_CFGCR2_PDIV_7 (4<<2) |
|
- | 6549 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
|
- | 6550 | ||
- | 6551 | #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) |
|
- | 6552 | #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) |
|
6010 | 6553 | ||
6011 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
6554 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
6012 | * since on HSW we can't write to it using I915_WRITE. */ |
6555 | * since on HSW we can't write to it using I915_WRITE. */ |
6013 | #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |
6556 | #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |
6014 | #define D_COMP_BDW 0x138144 |
6557 | #define D_COMP_BDW 0x138144 |
6015 | #define D_COMP_RCOMP_IN_PROGRESS (1<<9) |
6558 | #define D_COMP_RCOMP_IN_PROGRESS (1<<9) |
6016 | #define D_COMP_COMP_FORCE (1<<8) |
6559 | #define D_COMP_COMP_FORCE (1<<8) |
6017 | #define D_COMP_COMP_DISABLE (1<<0) |
6560 | #define D_COMP_COMP_DISABLE (1<<0) |
6018 | 6561 | ||
6019 | /* Pipe WM_LINETIME - watermark line time */ |
6562 | /* Pipe WM_LINETIME - watermark line time */ |
6020 | #define PIPE_WM_LINETIME_A 0x45270 |
6563 | #define PIPE_WM_LINETIME_A 0x45270 |
6021 | #define PIPE_WM_LINETIME_B 0x45274 |
6564 | #define PIPE_WM_LINETIME_B 0x45274 |
6022 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ |
6565 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ |
6023 | PIPE_WM_LINETIME_B) |
6566 | PIPE_WM_LINETIME_B) |
6024 | #define PIPE_WM_LINETIME_MASK (0x1ff) |
6567 | #define PIPE_WM_LINETIME_MASK (0x1ff) |
6025 | #define PIPE_WM_LINETIME_TIME(x) ((x)) |
6568 | #define PIPE_WM_LINETIME_TIME(x) ((x)) |
6026 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
6569 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
6027 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
6570 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
6028 | 6571 | ||
6029 | /* SFUSE_STRAP */ |
6572 | /* SFUSE_STRAP */ |
6030 | #define SFUSE_STRAP 0xc2014 |
6573 | #define SFUSE_STRAP 0xc2014 |
6031 | #define SFUSE_STRAP_FUSE_LOCK (1<<13) |
6574 | #define SFUSE_STRAP_FUSE_LOCK (1<<13) |
6032 | #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) |
6575 | #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) |
6033 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
6576 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
6034 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) |
6577 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) |
6035 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) |
6578 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) |
6036 | 6579 | ||
6037 | #define WM_MISC 0x45260 |
6580 | #define WM_MISC 0x45260 |
6038 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
6581 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
6039 | 6582 | ||
6040 | #define WM_DBG 0x45280 |
6583 | #define WM_DBG 0x45280 |
6041 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) |
6584 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) |
6042 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) |
6585 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) |
6043 | #define WM_DBG_DISALLOW_SPRITE (1<<2) |
6586 | #define WM_DBG_DISALLOW_SPRITE (1<<2) |
6044 | 6587 | ||
6045 | /* pipe CSC */ |
6588 | /* pipe CSC */ |
6046 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 |
6589 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 |
6047 | #define _PIPE_A_CSC_COEFF_BY 0x49014 |
6590 | #define _PIPE_A_CSC_COEFF_BY 0x49014 |
6048 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 |
6591 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 |
6049 | #define _PIPE_A_CSC_COEFF_BU 0x4901c |
6592 | #define _PIPE_A_CSC_COEFF_BU 0x4901c |
6050 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 |
6593 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 |
6051 | #define _PIPE_A_CSC_COEFF_BV 0x49024 |
6594 | #define _PIPE_A_CSC_COEFF_BV 0x49024 |
6052 | #define _PIPE_A_CSC_MODE 0x49028 |
6595 | #define _PIPE_A_CSC_MODE 0x49028 |
6053 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) |
6596 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) |
6054 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) |
6597 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) |
6055 | #define CSC_MODE_YUV_TO_RGB (1 << 0) |
6598 | #define CSC_MODE_YUV_TO_RGB (1 << 0) |
6056 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 |
6599 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 |
6057 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 |
6600 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 |
6058 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 |
6601 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 |
6059 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 |
6602 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 |
6060 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 |
6603 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 |
6061 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 |
6604 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 |
6062 | 6605 | ||
6063 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 |
6606 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 |
6064 | #define _PIPE_B_CSC_COEFF_BY 0x49114 |
6607 | #define _PIPE_B_CSC_COEFF_BY 0x49114 |
6065 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 |
6608 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 |
6066 | #define _PIPE_B_CSC_COEFF_BU 0x4911c |
6609 | #define _PIPE_B_CSC_COEFF_BU 0x4911c |
6067 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 |
6610 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 |
6068 | #define _PIPE_B_CSC_COEFF_BV 0x49124 |
6611 | #define _PIPE_B_CSC_COEFF_BV 0x49124 |
6069 | #define _PIPE_B_CSC_MODE 0x49128 |
6612 | #define _PIPE_B_CSC_MODE 0x49128 |
6070 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 |
6613 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 |
6071 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 |
6614 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 |
6072 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 |
6615 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 |
6073 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 |
6616 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 |
6074 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 |
6617 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 |
6075 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 |
6618 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 |
6076 | 6619 | ||
6077 | #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) |
6620 | #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) |
6078 | #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) |
6621 | #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) |
6079 | #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) |
6622 | #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) |
6080 | #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) |
6623 | #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) |
6081 | #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) |
6624 | #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) |
6082 | #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) |
6625 | #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) |
6083 | #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) |
6626 | #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) |
6084 | #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) |
6627 | #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) |
6085 | #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) |
6628 | #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) |
6086 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) |
6629 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) |
6087 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) |
6630 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) |
6088 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) |
6631 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) |
6089 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) |
6632 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) |
6090 | 6633 | ||
6091 | /* VLV MIPI registers */ |
6634 | /* VLV MIPI registers */ |
6092 | 6635 | ||
6093 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
6636 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
6094 | #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
6637 | #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
6095 | #define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ |
6638 | #define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ |
6096 | _MIPIB_PORT_CTRL) |
6639 | _MIPIB_PORT_CTRL) |
6097 | #define DPI_ENABLE (1 << 31) /* A + B */ |
6640 | #define DPI_ENABLE (1 << 31) /* A + B */ |
6098 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
6641 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
6099 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
6642 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
6100 | #define DUAL_LINK_MODE_MASK (1 << 26) |
6643 | #define DUAL_LINK_MODE_MASK (1 << 26) |
6101 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) |
6644 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) |
6102 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) |
6645 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) |
6103 | #define DITHERING_ENABLE (1 << 25) /* A + B */ |
6646 | #define DITHERING_ENABLE (1 << 25) /* A + B */ |
6104 | #define FLOPPED_HSTX (1 << 23) |
6647 | #define FLOPPED_HSTX (1 << 23) |
6105 | #define DE_INVERT (1 << 19) /* XXX */ |
6648 | #define DE_INVERT (1 << 19) /* XXX */ |
6106 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 |
6649 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 |
6107 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) |
6650 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) |
6108 | #define AFE_LATCHOUT (1 << 17) |
6651 | #define AFE_LATCHOUT (1 << 17) |
6109 | #define LP_OUTPUT_HOLD (1 << 16) |
6652 | #define LP_OUTPUT_HOLD (1 << 16) |
6110 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
6653 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
6111 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) |
6654 | #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) |
6112 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 |
6655 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 |
6113 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) |
6656 | #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) |
6114 | #define CSB_SHIFT 9 |
6657 | #define CSB_SHIFT 9 |
6115 | #define CSB_MASK (3 << 9) |
6658 | #define CSB_MASK (3 << 9) |
6116 | #define CSB_20MHZ (0 << 9) |
6659 | #define CSB_20MHZ (0 << 9) |
6117 | #define CSB_10MHZ (1 << 9) |
6660 | #define CSB_10MHZ (1 << 9) |
6118 | #define CSB_40MHZ (2 << 9) |
6661 | #define CSB_40MHZ (2 << 9) |
6119 | #define BANDGAP_MASK (1 << 8) |
6662 | #define BANDGAP_MASK (1 << 8) |
6120 | #define BANDGAP_PNW_CIRCUIT (0 << 8) |
6663 | #define BANDGAP_PNW_CIRCUIT (0 << 8) |
6121 | #define BANDGAP_LNC_CIRCUIT (1 << 8) |
6664 | #define BANDGAP_LNC_CIRCUIT (1 << 8) |
6122 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
6665 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
6123 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) |
6666 | #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) |
6124 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ |
6667 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ |
6125 | #define TEARING_EFFECT_SHIFT 2 /* A + B */ |
6668 | #define TEARING_EFFECT_SHIFT 2 /* A + B */ |
6126 | #define TEARING_EFFECT_MASK (3 << 2) |
6669 | #define TEARING_EFFECT_MASK (3 << 2) |
6127 | #define TEARING_EFFECT_OFF (0 << 2) |
6670 | #define TEARING_EFFECT_OFF (0 << 2) |
6128 | #define TEARING_EFFECT_DSI (1 << 2) |
6671 | #define TEARING_EFFECT_DSI (1 << 2) |
6129 | #define TEARING_EFFECT_GPIO (2 << 2) |
6672 | #define TEARING_EFFECT_GPIO (2 << 2) |
6130 | #define LANE_CONFIGURATION_SHIFT 0 |
6673 | #define LANE_CONFIGURATION_SHIFT 0 |
6131 | #define LANE_CONFIGURATION_MASK (3 << 0) |
6674 | #define LANE_CONFIGURATION_MASK (3 << 0) |
6132 | #define LANE_CONFIGURATION_4LANE (0 << 0) |
6675 | #define LANE_CONFIGURATION_4LANE (0 << 0) |
6133 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) |
6676 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) |
6134 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) |
6677 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) |
6135 | 6678 | ||
6136 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
6679 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
6137 | #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
6680 | #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
6138 | #define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ |
6681 | #define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ |
6139 | _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) |
6682 | _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) |
6140 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
6683 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
6141 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
6684 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
6142 | 6685 | ||
6143 | /* XXX: all bits reserved */ |
6686 | /* XXX: all bits reserved */ |
6144 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
6687 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
6145 | 6688 | ||
6146 | /* MIPI DSI Controller and D-PHY registers */ |
6689 | /* MIPI DSI Controller and D-PHY registers */ |
6147 | 6690 | ||
6148 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
6691 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
6149 | #define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
6692 | #define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
6150 | #define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ |
6693 | #define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ |
6151 | _MIPIB_DEVICE_READY) |
6694 | _MIPIB_DEVICE_READY) |
6152 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
6695 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
6153 | #define ULPS_STATE_MASK (3 << 1) |
6696 | #define ULPS_STATE_MASK (3 << 1) |
6154 | #define ULPS_STATE_ENTER (2 << 1) |
6697 | #define ULPS_STATE_ENTER (2 << 1) |
6155 | #define ULPS_STATE_EXIT (1 << 1) |
6698 | #define ULPS_STATE_EXIT (1 << 1) |
6156 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
6699 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
6157 | #define DEVICE_READY (1 << 0) |
6700 | #define DEVICE_READY (1 << 0) |
6158 | 6701 | ||
6159 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
6702 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
6160 | #define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
6703 | #define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
6161 | #define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ |
6704 | #define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ |
6162 | _MIPIB_INTR_STAT) |
6705 | _MIPIB_INTR_STAT) |
6163 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
6706 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
6164 | #define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
6707 | #define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
6165 | #define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ |
6708 | #define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ |
6166 | _MIPIB_INTR_EN) |
6709 | _MIPIB_INTR_EN) |
6167 | #define TEARING_EFFECT (1 << 31) |
6710 | #define TEARING_EFFECT (1 << 31) |
6168 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) |
6711 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) |
6169 | #define GEN_READ_DATA_AVAIL (1 << 29) |
6712 | #define GEN_READ_DATA_AVAIL (1 << 29) |
6170 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) |
6713 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) |
6171 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) |
6714 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) |
6172 | #define RX_PROT_VIOLATION (1 << 26) |
6715 | #define RX_PROT_VIOLATION (1 << 26) |
6173 | #define RX_INVALID_TX_LENGTH (1 << 25) |
6716 | #define RX_INVALID_TX_LENGTH (1 << 25) |
6174 | #define ACK_WITH_NO_ERROR (1 << 24) |
6717 | #define ACK_WITH_NO_ERROR (1 << 24) |
6175 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) |
6718 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) |
6176 | #define LP_RX_TIMEOUT (1 << 22) |
6719 | #define LP_RX_TIMEOUT (1 << 22) |
6177 | #define HS_TX_TIMEOUT (1 << 21) |
6720 | #define HS_TX_TIMEOUT (1 << 21) |
6178 | #define DPI_FIFO_UNDERRUN (1 << 20) |
6721 | #define DPI_FIFO_UNDERRUN (1 << 20) |
6179 | #define LOW_CONTENTION (1 << 19) |
6722 | #define LOW_CONTENTION (1 << 19) |
6180 | #define HIGH_CONTENTION (1 << 18) |
6723 | #define HIGH_CONTENTION (1 << 18) |
6181 | #define TXDSI_VC_ID_INVALID (1 << 17) |
6724 | #define TXDSI_VC_ID_INVALID (1 << 17) |
6182 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) |
6725 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) |
6183 | #define TXCHECKSUM_ERROR (1 << 15) |
6726 | #define TXCHECKSUM_ERROR (1 << 15) |
6184 | #define TXECC_MULTIBIT_ERROR (1 << 14) |
6727 | #define TXECC_MULTIBIT_ERROR (1 << 14) |
6185 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) |
6728 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) |
6186 | #define TXFALSE_CONTROL_ERROR (1 << 12) |
6729 | #define TXFALSE_CONTROL_ERROR (1 << 12) |
6187 | #define RXDSI_VC_ID_INVALID (1 << 11) |
6730 | #define RXDSI_VC_ID_INVALID (1 << 11) |
6188 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) |
6731 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) |
6189 | #define RXCHECKSUM_ERROR (1 << 9) |
6732 | #define RXCHECKSUM_ERROR (1 << 9) |
6190 | #define RXECC_MULTIBIT_ERROR (1 << 8) |
6733 | #define RXECC_MULTIBIT_ERROR (1 << 8) |
6191 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) |
6734 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) |
6192 | #define RXFALSE_CONTROL_ERROR (1 << 6) |
6735 | #define RXFALSE_CONTROL_ERROR (1 << 6) |
6193 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) |
6736 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) |
6194 | #define RX_LP_TX_SYNC_ERROR (1 << 4) |
6737 | #define RX_LP_TX_SYNC_ERROR (1 << 4) |
6195 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) |
6738 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) |
6196 | #define RXEOT_SYNC_ERROR (1 << 2) |
6739 | #define RXEOT_SYNC_ERROR (1 << 2) |
6197 | #define RXSOT_SYNC_ERROR (1 << 1) |
6740 | #define RXSOT_SYNC_ERROR (1 << 1) |
6198 | #define RXSOT_ERROR (1 << 0) |
6741 | #define RXSOT_ERROR (1 << 0) |
6199 | 6742 | ||
6200 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
6743 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
6201 | #define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
6744 | #define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
6202 | #define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ |
6745 | #define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ |
6203 | _MIPIB_DSI_FUNC_PRG) |
6746 | _MIPIB_DSI_FUNC_PRG) |
6204 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
6747 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
6205 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) |
6748 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) |
6206 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
6749 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
6207 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) |
6750 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) |
6208 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) |
6751 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) |
6209 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) |
6752 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) |
6210 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) |
6753 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) |
6211 | #define VID_MODE_FORMAT_MASK (0xf << 7) |
6754 | #define VID_MODE_FORMAT_MASK (0xf << 7) |
6212 | #define VID_MODE_NOT_SUPPORTED (0 << 7) |
6755 | #define VID_MODE_NOT_SUPPORTED (0 << 7) |
6213 | #define VID_MODE_FORMAT_RGB565 (1 << 7) |
6756 | #define VID_MODE_FORMAT_RGB565 (1 << 7) |
6214 | #define VID_MODE_FORMAT_RGB666 (2 << 7) |
6757 | #define VID_MODE_FORMAT_RGB666 (2 << 7) |
6215 | #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) |
6758 | #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) |
6216 | #define VID_MODE_FORMAT_RGB888 (4 << 7) |
6759 | #define VID_MODE_FORMAT_RGB888 (4 << 7) |
6217 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 |
6760 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 |
6218 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) |
6761 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) |
6219 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 |
6762 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 |
6220 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) |
6763 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) |
6221 | #define DATA_LANES_PRG_REG_SHIFT 0 |
6764 | #define DATA_LANES_PRG_REG_SHIFT 0 |
6222 | #define DATA_LANES_PRG_REG_MASK (7 << 0) |
6765 | #define DATA_LANES_PRG_REG_MASK (7 << 0) |
6223 | 6766 | ||
6224 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
6767 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
6225 | #define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
6768 | #define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
6226 | #define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ |
6769 | #define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ |
6227 | _MIPIB_HS_TX_TIMEOUT) |
6770 | _MIPIB_HS_TX_TIMEOUT) |
6228 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
6771 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
6229 | 6772 | ||
6230 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
6773 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
6231 | #define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
6774 | #define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
6232 | #define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ |
6775 | #define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ |
6233 | _MIPIB_LP_RX_TIMEOUT) |
6776 | _MIPIB_LP_RX_TIMEOUT) |
6234 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
6777 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
6235 | 6778 | ||
6236 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
6779 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
6237 | #define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
6780 | #define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
6238 | #define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ |
6781 | #define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ |
6239 | _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) |
6782 | _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) |
6240 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
6783 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
6241 | 6784 | ||
6242 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
6785 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
6243 | #define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
6786 | #define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
6244 | #define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ |
6787 | #define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ |
6245 | _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) |
6788 | _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) |
6246 | #define DEVICE_RESET_TIMER_MASK 0xffff |
6789 | #define DEVICE_RESET_TIMER_MASK 0xffff |
6247 | 6790 | ||
6248 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
6791 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
6249 | #define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
6792 | #define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
6250 | #define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ |
6793 | #define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ |
6251 | _MIPIB_DPI_RESOLUTION) |
6794 | _MIPIB_DPI_RESOLUTION) |
6252 | #define VERTICAL_ADDRESS_SHIFT 16 |
6795 | #define VERTICAL_ADDRESS_SHIFT 16 |
6253 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) |
6796 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) |
6254 | #define HORIZONTAL_ADDRESS_SHIFT 0 |
6797 | #define HORIZONTAL_ADDRESS_SHIFT 0 |
6255 | #define HORIZONTAL_ADDRESS_MASK 0xffff |
6798 | #define HORIZONTAL_ADDRESS_MASK 0xffff |
6256 | 6799 | ||
6257 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
6800 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
6258 | #define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
6801 | #define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
6259 | #define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ |
6802 | #define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ |
6260 | _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) |
6803 | _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) |
6261 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
6804 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
6262 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
6805 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
6263 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
6806 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
6264 | 6807 | ||
6265 | /* regs below are bits 15:0 */ |
6808 | /* regs below are bits 15:0 */ |
6266 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
6809 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
6267 | #define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
6810 | #define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
6268 | #define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
6811 | #define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
6269 | _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) |
6812 | _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) |
6270 | 6813 | ||
6271 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
6814 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
6272 | #define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
6815 | #define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
6273 | #define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ |
6816 | #define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ |
6274 | _MIPIB_HBP_COUNT) |
6817 | _MIPIB_HBP_COUNT) |
6275 | 6818 | ||
6276 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
6819 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
6277 | #define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
6820 | #define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
6278 | #define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ |
6821 | #define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ |
6279 | _MIPIB_HFP_COUNT) |
6822 | _MIPIB_HFP_COUNT) |
6280 | 6823 | ||
6281 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
6824 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
6282 | #define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
6825 | #define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
6283 | #define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ |
6826 | #define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ |
6284 | _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) |
6827 | _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) |
6285 | 6828 | ||
6286 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
6829 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
6287 | #define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
6830 | #define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
6288 | #define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
6831 | #define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
6289 | _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) |
6832 | _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) |
6290 | 6833 | ||
6291 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
6834 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
6292 | #define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
6835 | #define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
6293 | #define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ |
6836 | #define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ |
6294 | _MIPIB_VBP_COUNT) |
6837 | _MIPIB_VBP_COUNT) |
6295 | 6838 | ||
6296 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
6839 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
6297 | #define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
6840 | #define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
6298 | #define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ |
6841 | #define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ |
6299 | _MIPIB_VFP_COUNT) |
6842 | _MIPIB_VFP_COUNT) |
6300 | 6843 | ||
6301 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
6844 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
6302 | #define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
6845 | #define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
6303 | #define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ |
6846 | #define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ |
6304 | _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) |
6847 | _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) |
6305 | 6848 | ||
6306 | /* regs above are bits 15:0 */ |
6849 | /* regs above are bits 15:0 */ |
6307 | 6850 | ||
6308 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
6851 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
6309 | #define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
6852 | #define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
6310 | #define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ |
6853 | #define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ |
6311 | _MIPIB_DPI_CONTROL) |
6854 | _MIPIB_DPI_CONTROL) |
6312 | #define DPI_LP_MODE (1 << 6) |
6855 | #define DPI_LP_MODE (1 << 6) |
6313 | #define BACKLIGHT_OFF (1 << 5) |
6856 | #define BACKLIGHT_OFF (1 << 5) |
6314 | #define BACKLIGHT_ON (1 << 4) |
6857 | #define BACKLIGHT_ON (1 << 4) |
6315 | #define COLOR_MODE_OFF (1 << 3) |
6858 | #define COLOR_MODE_OFF (1 << 3) |
6316 | #define COLOR_MODE_ON (1 << 2) |
6859 | #define COLOR_MODE_ON (1 << 2) |
6317 | #define TURN_ON (1 << 1) |
6860 | #define TURN_ON (1 << 1) |
6318 | #define SHUTDOWN (1 << 0) |
6861 | #define SHUTDOWN (1 << 0) |
6319 | 6862 | ||
6320 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
6863 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
6321 | #define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
6864 | #define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
6322 | #define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ |
6865 | #define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ |
6323 | _MIPIB_DPI_DATA) |
6866 | _MIPIB_DPI_DATA) |
6324 | #define COMMAND_BYTE_SHIFT 0 |
6867 | #define COMMAND_BYTE_SHIFT 0 |
6325 | #define COMMAND_BYTE_MASK (0x3f << 0) |
6868 | #define COMMAND_BYTE_MASK (0x3f << 0) |
6326 | 6869 | ||
6327 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
6870 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
6328 | #define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
6871 | #define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
6329 | #define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ |
6872 | #define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ |
6330 | _MIPIB_INIT_COUNT) |
6873 | _MIPIB_INIT_COUNT) |
6331 | #define MASTER_INIT_TIMER_SHIFT 0 |
6874 | #define MASTER_INIT_TIMER_SHIFT 0 |
6332 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) |
6875 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) |
6333 | 6876 | ||
6334 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
6877 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
6335 | #define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
6878 | #define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
6336 | #define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ |
6879 | #define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ |
6337 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) |
6880 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) |
6338 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
6881 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
6339 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
6882 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
6340 | 6883 | ||
6341 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
6884 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
6342 | #define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
6885 | #define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
6343 | #define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ |
6886 | #define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ |
6344 | _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) |
6887 | _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) |
6345 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
6888 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
6346 | #define DISABLE_VIDEO_BTA (1 << 3) |
6889 | #define DISABLE_VIDEO_BTA (1 << 3) |
6347 | #define IP_TG_CONFIG (1 << 2) |
6890 | #define IP_TG_CONFIG (1 << 2) |
6348 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) |
6891 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) |
6349 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
6892 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
6350 | #define VIDEO_MODE_BURST (3 << 0) |
6893 | #define VIDEO_MODE_BURST (3 << 0) |
6351 | 6894 | ||
6352 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
6895 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
6353 | #define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
6896 | #define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
6354 | #define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ |
6897 | #define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ |
6355 | _MIPIB_EOT_DISABLE) |
6898 | _MIPIB_EOT_DISABLE) |
6356 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
6899 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
6357 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
6900 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
6358 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
6901 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
6359 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) |
6902 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) |
6360 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) |
6903 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) |
6361 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) |
6904 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) |
6362 | #define CLOCKSTOP (1 << 1) |
6905 | #define CLOCKSTOP (1 << 1) |
6363 | #define EOT_DISABLE (1 << 0) |
6906 | #define EOT_DISABLE (1 << 0) |
6364 | 6907 | ||
6365 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
6908 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
6366 | #define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
6909 | #define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
6367 | #define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ |
6910 | #define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ |
6368 | _MIPIB_LP_BYTECLK) |
6911 | _MIPIB_LP_BYTECLK) |
6369 | #define LP_BYTECLK_SHIFT 0 |
6912 | #define LP_BYTECLK_SHIFT 0 |
6370 | #define LP_BYTECLK_MASK (0xffff << 0) |
6913 | #define LP_BYTECLK_MASK (0xffff << 0) |
6371 | 6914 | ||
6372 | /* bits 31:0 */ |
6915 | /* bits 31:0 */ |
6373 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
6916 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
6374 | #define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
6917 | #define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
6375 | #define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ |
6918 | #define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ |
6376 | _MIPIB_LP_GEN_DATA) |
6919 | _MIPIB_LP_GEN_DATA) |
6377 | 6920 | ||
6378 | /* bits 31:0 */ |
6921 | /* bits 31:0 */ |
6379 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
6922 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
6380 | #define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
6923 | #define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
6381 | #define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ |
6924 | #define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ |
6382 | _MIPIB_HS_GEN_DATA) |
6925 | _MIPIB_HS_GEN_DATA) |
6383 | 6926 | ||
6384 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
6927 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
6385 | #define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) |
6928 | #define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) |
6386 | #define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ |
6929 | #define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ |
6387 | _MIPIB_LP_GEN_CTRL) |
6930 | _MIPIB_LP_GEN_CTRL) |
6388 | #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) |
6931 | #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) |
6389 | #define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) |
6932 | #define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) |
6390 | #define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ |
6933 | #define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ |
6391 | _MIPIB_HS_GEN_CTRL) |
6934 | _MIPIB_HS_GEN_CTRL) |
6392 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
6935 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
6393 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) |
6936 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) |
6394 | #define SHORT_PACKET_PARAM_SHIFT 8 |
6937 | #define SHORT_PACKET_PARAM_SHIFT 8 |
6395 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) |
6938 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) |
6396 | #define VIRTUAL_CHANNEL_SHIFT 6 |
6939 | #define VIRTUAL_CHANNEL_SHIFT 6 |
6397 | #define VIRTUAL_CHANNEL_MASK (3 << 6) |
6940 | #define VIRTUAL_CHANNEL_MASK (3 << 6) |
6398 | #define DATA_TYPE_SHIFT 0 |
6941 | #define DATA_TYPE_SHIFT 0 |
6399 | #define DATA_TYPE_MASK (3f << 0) |
6942 | #define DATA_TYPE_MASK (3f << 0) |
6400 | /* data type values, see include/video/mipi_display.h */ |
6943 | /* data type values, see include/video/mipi_display.h */ |
6401 | 6944 | ||
6402 | #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) |
6945 | #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) |
6403 | #define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) |
6946 | #define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) |
6404 | #define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ |
6947 | #define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ |
6405 | _MIPIB_GEN_FIFO_STAT) |
6948 | _MIPIB_GEN_FIFO_STAT) |
6406 | #define DPI_FIFO_EMPTY (1 << 28) |
6949 | #define DPI_FIFO_EMPTY (1 << 28) |
6407 | #define DBI_FIFO_EMPTY (1 << 27) |
6950 | #define DBI_FIFO_EMPTY (1 << 27) |
6408 | #define LP_CTRL_FIFO_EMPTY (1 << 26) |
6951 | #define LP_CTRL_FIFO_EMPTY (1 << 26) |
6409 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) |
6952 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) |
6410 | #define LP_CTRL_FIFO_FULL (1 << 24) |
6953 | #define LP_CTRL_FIFO_FULL (1 << 24) |
6411 | #define HS_CTRL_FIFO_EMPTY (1 << 18) |
6954 | #define HS_CTRL_FIFO_EMPTY (1 << 18) |
6412 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) |
6955 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) |
6413 | #define HS_CTRL_FIFO_FULL (1 << 16) |
6956 | #define HS_CTRL_FIFO_FULL (1 << 16) |
6414 | #define LP_DATA_FIFO_EMPTY (1 << 10) |
6957 | #define LP_DATA_FIFO_EMPTY (1 << 10) |
6415 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) |
6958 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) |
6416 | #define LP_DATA_FIFO_FULL (1 << 8) |
6959 | #define LP_DATA_FIFO_FULL (1 << 8) |
6417 | #define HS_DATA_FIFO_EMPTY (1 << 2) |
6960 | #define HS_DATA_FIFO_EMPTY (1 << 2) |
6418 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
6961 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
6419 | #define HS_DATA_FIFO_FULL (1 << 0) |
6962 | #define HS_DATA_FIFO_FULL (1 << 0) |
6420 | 6963 | ||
6421 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
6964 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
6422 | #define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
6965 | #define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
6423 | #define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ |
6966 | #define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ |
6424 | _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) |
6967 | _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) |
6425 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
6968 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
6426 | #define DBI_LP_MODE (1 << 0) |
6969 | #define DBI_LP_MODE (1 << 0) |
6427 | #define DBI_HS_MODE (0 << 0) |
6970 | #define DBI_HS_MODE (0 << 0) |
6428 | 6971 | ||
6429 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
6972 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
6430 | #define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
6973 | #define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
6431 | #define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ |
6974 | #define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ |
6432 | _MIPIB_DPHY_PARAM) |
6975 | _MIPIB_DPHY_PARAM) |
6433 | #define EXIT_ZERO_COUNT_SHIFT 24 |
6976 | #define EXIT_ZERO_COUNT_SHIFT 24 |
6434 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
6977 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
6435 | #define TRAIL_COUNT_SHIFT 16 |
6978 | #define TRAIL_COUNT_SHIFT 16 |
6436 | #define TRAIL_COUNT_MASK (0x1f << 16) |
6979 | #define TRAIL_COUNT_MASK (0x1f << 16) |
6437 | #define CLK_ZERO_COUNT_SHIFT 8 |
6980 | #define CLK_ZERO_COUNT_SHIFT 8 |
6438 | #define CLK_ZERO_COUNT_MASK (0xff << 8) |
6981 | #define CLK_ZERO_COUNT_MASK (0xff << 8) |
6439 | #define PREPARE_COUNT_SHIFT 0 |
6982 | #define PREPARE_COUNT_SHIFT 0 |
6440 | #define PREPARE_COUNT_MASK (0x3f << 0) |
6983 | #define PREPARE_COUNT_MASK (0x3f << 0) |
6441 | 6984 | ||
6442 | /* bits 31:0 */ |
6985 | /* bits 31:0 */ |
6443 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
6986 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
6444 | #define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
6987 | #define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
6445 | #define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ |
6988 | #define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ |
6446 | _MIPIB_DBI_BW_CTRL) |
6989 | _MIPIB_DBI_BW_CTRL) |
6447 | 6990 | ||
6448 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
6991 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
6449 | + 0xb088) |
6992 | + 0xb088) |
6450 | #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
6993 | #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
6451 | + 0xb888) |
6994 | + 0xb888) |
6452 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ |
6995 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ |
6453 | _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) |
6996 | _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) |
6454 | #define LP_HS_SSW_CNT_SHIFT 16 |
6997 | #define LP_HS_SSW_CNT_SHIFT 16 |
6455 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) |
6998 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) |
6456 | #define HS_LP_PWR_SW_CNT_SHIFT 0 |
6999 | #define HS_LP_PWR_SW_CNT_SHIFT 0 |
6457 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
7000 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
6458 | 7001 | ||
6459 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
7002 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
6460 | #define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
7003 | #define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
6461 | #define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ |
7004 | #define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ |
6462 | _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) |
7005 | _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) |
6463 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
7006 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
6464 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
7007 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
6465 | 7008 | ||
6466 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
7009 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
6467 | #define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
7010 | #define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
6468 | #define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ |
7011 | #define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ |
6469 | _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) |
7012 | _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) |
6470 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
7013 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
6471 | #define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
7014 | #define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
6472 | #define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ |
7015 | #define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ |
6473 | _MIPIB_INTR_EN_REG_1) |
7016 | _MIPIB_INTR_EN_REG_1) |
6474 | #define RX_CONTENTION_DETECTED (1 << 0) |
7017 | #define RX_CONTENTION_DETECTED (1 << 0) |
6475 | 7018 | ||
6476 | /* XXX: only pipe A ?!? */ |
7019 | /* XXX: only pipe A ?!? */ |
6477 | #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) |
7020 | #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) |
6478 | #define DBI_TYPEC_ENABLE (1 << 31) |
7021 | #define DBI_TYPEC_ENABLE (1 << 31) |
6479 | #define DBI_TYPEC_WIP (1 << 30) |
7022 | #define DBI_TYPEC_WIP (1 << 30) |
6480 | #define DBI_TYPEC_OPTION_SHIFT 28 |
7023 | #define DBI_TYPEC_OPTION_SHIFT 28 |
6481 | #define DBI_TYPEC_OPTION_MASK (3 << 28) |
7024 | #define DBI_TYPEC_OPTION_MASK (3 << 28) |
6482 | #define DBI_TYPEC_FREQ_SHIFT 24 |
7025 | #define DBI_TYPEC_FREQ_SHIFT 24 |
6483 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) |
7026 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) |
6484 | #define DBI_TYPEC_OVERRIDE (1 << 8) |
7027 | #define DBI_TYPEC_OVERRIDE (1 << 8) |
6485 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 |
7028 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 |
6486 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) |
7029 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) |
6487 | 7030 | ||
6488 | 7031 | ||
6489 | /* MIPI adapter registers */ |
7032 | /* MIPI adapter registers */ |
6490 | 7033 | ||
6491 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
7034 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
6492 | #define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
7035 | #define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
6493 | #define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ |
7036 | #define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ |
6494 | _MIPIB_CTRL) |
7037 | _MIPIB_CTRL) |
6495 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
7038 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
6496 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
7039 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
6497 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) |
7040 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) |
6498 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) |
7041 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) |
6499 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) |
7042 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) |
6500 | #define READ_REQUEST_PRIORITY_SHIFT 3 |
7043 | #define READ_REQUEST_PRIORITY_SHIFT 3 |
6501 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) |
7044 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) |
6502 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) |
7045 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) |
6503 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
7046 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
6504 | #define RGB_FLIP_TO_BGR (1 << 2) |
7047 | #define RGB_FLIP_TO_BGR (1 << 2) |
6505 | 7048 | ||
6506 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
7049 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
6507 | #define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
7050 | #define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
6508 | #define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ |
7051 | #define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ |
6509 | _MIPIB_DATA_ADDRESS) |
7052 | _MIPIB_DATA_ADDRESS) |
6510 | #define DATA_MEM_ADDRESS_SHIFT 5 |
7053 | #define DATA_MEM_ADDRESS_SHIFT 5 |
6511 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
7054 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
6512 | #define DATA_VALID (1 << 0) |
7055 | #define DATA_VALID (1 << 0) |
6513 | 7056 | ||
6514 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
7057 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
6515 | #define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
7058 | #define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
6516 | #define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ |
7059 | #define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ |
6517 | _MIPIB_DATA_LENGTH) |
7060 | _MIPIB_DATA_LENGTH) |
6518 | #define DATA_LENGTH_SHIFT 0 |
7061 | #define DATA_LENGTH_SHIFT 0 |
6519 | #define DATA_LENGTH_MASK (0xfffff << 0) |
7062 | #define DATA_LENGTH_MASK (0xfffff << 0) |
6520 | 7063 | ||
6521 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
7064 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
6522 | #define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
7065 | #define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
6523 | #define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ |
7066 | #define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ |
6524 | _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) |
7067 | _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) |
6525 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
7068 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
6526 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
7069 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
6527 | #define AUTO_PWG_ENABLE (1 << 2) |
7070 | #define AUTO_PWG_ENABLE (1 << 2) |
6528 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
7071 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
6529 | #define COMMAND_VALID (1 << 0) |
7072 | #define COMMAND_VALID (1 << 0) |
6530 | 7073 | ||
6531 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
7074 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
6532 | #define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
7075 | #define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
6533 | #define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ |
7076 | #define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ |
6534 | _MIPIB_COMMAND_LENGTH) |
7077 | _MIPIB_COMMAND_LENGTH) |
6535 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
7078 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
6536 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
7079 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
6537 | 7080 | ||
6538 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
7081 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
6539 | #define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
7082 | #define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
6540 | #define MIPI_READ_DATA_RETURN(tc, n) \ |
7083 | #define MIPI_READ_DATA_RETURN(tc, n) \ |
6541 | (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ |
7084 | (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ |
6542 | + 4 * (n)) /* n: 0...7 */ |
7085 | + 4 * (n)) /* n: 0...7 */ |
6543 | 7086 | ||
6544 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
7087 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
6545 | #define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
7088 | #define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
6546 | #define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ |
7089 | #define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ |
6547 | _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) |
7090 | _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) |
6548 | #define READ_DATA_VALID(n) (1 << (n)) |
7091 | #define READ_DATA_VALID(n) (1 << (n)) |
6549 | 7092 | ||
6550 | /* For UMS only (deprecated): */ |
7093 | /* For UMS only (deprecated): */ |
6551 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
7094 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
6552 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) |
7095 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) |
6553 | 7096 | ||
6554 | #endif /* _I915_REG_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>2) |
7097 | #endif /* _I915_REG_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>2) |
6555 | 7098 | ||
6556 | /*><2) |
7099 | /*><2) |
6557 | 7100 | ||
6558 | /*>1) |
7101 | /*>1) |
6559 | #define><1) |
7102 | #define><1) |
6560 | #define>0) |
7103 | #define>0) |
6561 | #define><0) |
7104 | #define><0) |
6562 | #define>><>0) |
7105 | #define>><>0) |
6563 | 7106 | ||
6564 | #define><0) |
7107 | #define><0) |
6565 | 7108 | ||
6566 | #define>1) |
7109 | #define>1) |
6567 | #define><1) |
7110 | #define><1) |
6568 | #define>2) |
7111 | #define>2) |
6569 | #define><2) |
7112 | #define><2) |
6570 | #define>7) |
7113 | #define>7) |
6571 | #define><7) |
7114 | #define><7) |
6572 | #define>13) |
7115 | #define>13) |
6573 | #define><13) |
7116 | #define><13) |
6574 | #define>16) |
7117 | #define>16) |
6575 | 7118 | ||
6576 | /*><16) |
7119 | /*><16) |
6577 | 7120 | ||
6578 | /*>16) |
7121 | /*>16) |
6579 | #define><16) |
7122 | #define><16) |
6580 | #define>0) |
7123 | #define>0) |
6581 | 7124 | ||
6582 | /*><0) |
7125 | /*><0) |
6583 | 7126 | ||
6584 | /*>8) |
7127 | /*>8) |
6585 | #define><8) |
7128 | #define><8) |
6586 | #define>9) |
7129 | #define>9) |
6587 | #define><9) |
7130 | #define><9) |
6588 | #define>19) |
7131 | #define>2) |
6589 | 7132 | #define><2) |
|
6590 | /*><19) |
7133 | #define>2) |
6591 | 7134 | #define><2) |
|
6592 | /*>21) |
7135 | #define>2) |
6593 | #define><21) |
7136 | #define><2) |
6594 | #define>22) |
7137 | #define>2) |
6595 | #define><22) |
7138 | #define><2) |
6596 | #define>23) |
7139 | #define>2) |
6597 | #define><23) |
7140 | #define><2) |
6598 | #define>25) |
7141 | #define>2) |
6599 | #define><25) |
7142 | #define><2) |
6600 | #define>26) |
7143 | #define>5) |
6601 | #define><26) |
7144 | #define><5) |
6602 | #define>26) |
7145 | #define>5) |
6603 | #define><26) |
7146 | #define><5) |
6604 | #define>26) |
7147 | #define>5) |
6605 | #define><26) |
7148 | #define><5) |
6606 | #define>26) |
7149 | #define>5) |
6607 | #define><26) |
7150 | #define><5) |
6608 | #define>26) |
7151 | #define>5) |
6609 | #define><26) |
7152 | #define><5) |
6610 | #define>30) |
7153 | #define>5) |
6611 | #define><30) |
7154 | #define><5) |
6612 | #define>31) |
7155 | #define>7) |
6613 | #define><31) |
7156 | #define><7) |
6614 | #define>5) |
7157 | #define>8) |
6615 | 7158 | #define><8) |
|
6616 | /*><5) |
7159 | #define>8) |
6617 | 7160 | #define><8) |
|
6618 | /*>5) |
7161 | #define>9) |
6619 | #define><5) |
7162 | #define><9) |
6620 | #define>5) |
7163 | #define>9) |
6621 | #define><5) |
7164 | #define><9) |
6622 | #define>5) |
7165 | #define>31) |
6623 | #define><5) |
7166 | #define><31) |
6624 | #define>5) |
7167 | #define>((id)*8)) |
6625 | #define><5) |
7168 | |
6626 | #define>0) |
7169 | /*><((id)*8)) |
6627 | #define><0) |
7170 | |
6628 | #define>29) |
7171 | /*>((port)*3)) |
6629 | 7172 | ||
6630 | #define><29) |
7173 | /*><((port)*3)) |
6631 | 7174 | ||
6632 | #define>29) |
7175 | /*>((port)*3+1)) |
6633 | #define><29) |
7176 | #define><((port)*3+1)) |
6634 | #define>29) |
7177 | #define>((port)*3+1)) |
6635 | 7178 | #define><((port)*3+1)) |
|
6636 | /*><29) |
7179 | #define>(port+15)) |
6637 | 7180 | #define><(port+15)) |
|
6638 | /*>29) |
7181 | #define>((id)*6)) |
6639 | #define><29) |
7182 | #define><((id)*6)) |
6640 | #define>29) |
7183 | #define>((id)*6+1)) |
6641 | #define><29) |
7184 | #define><((id)*6+1)) |
6642 | #define>29) |
7185 | #define>((id)*6+1)) |
6643 | #define><29) |
7186 | #define><((id)*6+1)) |
6644 | #define>29) |
7187 | #define>((id)*6+4)) |
6645 | #define><29) |
7188 | #define><((id)*6+4)) |
6646 | #define>29) |
7189 | #define>((id)*6+5)) |
6647 | #define><29) |
7190 | #define><((id)*6+5)) |
6648 | #define>29) |
7191 | #define>31) |
6649 | #define><29) |
7192 | |
6650 | #define>29) |
7193 | /*><31) |
6651 | #define><29) |
7194 | |
6652 | #define>29) |
7195 | /*>26) |
6653 | #define><29) |
7196 | #define><26) |
6654 | #define>16) |
7197 | #define>26) |
6655 | 7198 | #define><26) |
|
6656 | /*><16) |
7199 | #define>26) |
6657 | 7200 | #define><26) |
|
6658 | /*>16) |
7201 | #define>26) |
6659 | #define><16) |
7202 | #define><26) |
6660 | #define>8) |
7203 | #define>26) |
6661 | #define><8) |
7204 | #define><26) |
6662 | #define>8) |
7205 | #define>19) |
6663 | #define><8) |
7206 | |
6664 | #define>0) |
7207 | /* |
6665 | #define><0) |
7208 | ><19) |
6666 | #define>28) |
7209 | |
6667 | /*><28) |
7210 | /* |
6668 | /*>28) |
7211 | >21) |
6669 | #define><28) |
7212 | #define><21) |
6670 | #define>28) |
7213 | #define>22) |
6671 | #define><28) |
7214 | #define><22) |
6672 | #define>28) |
7215 | #define>23) |
6673 | #define><28) |
7216 | #define><23) |
6674 | #define>31) |
7217 | #define>25) |
6675 | #define><31) |
7218 | #define><25) |
6676 | #define>26) |
7219 | #define>26) |
6677 | 7220 | #define><26) |
|
6678 | /*><26) |
7221 | #define>26) |
6679 | 7222 | #define><26) |
|
6680 | /*>26) |
7223 | #define>26) |
6681 | #define><26) |
7224 | #define><26) |
6682 | #define>26) |
7225 | #define>26) |
6683 | #define><26) |
7226 | #define><26) |
6684 | #define>26) |
7227 | #define>26) |
6685 | #define><26) |
7228 | #define><26) |
6686 | #define>28) |
7229 | #define>30) |
6687 | #define><28) |
7230 | #define><30) |
6688 | #define>28) |
7231 | #define>31) |
6689 | #define><28) |
7232 | #define><31) |
6690 | #define>28) |
7233 | #define>5) |
6691 | #define><28) |
7234 | |
6692 | #define>28) |
7235 | /*><5) |
6693 | #define><28) |
7236 | |
6694 | #define>31) |
7237 | /*>5) |
6695 | #define><31) |
7238 | #define><5) |
6696 | #define>0) |
7239 | #define>5) |
6697 | 7240 | #define><5) |
|
6698 | /*><0) |
7241 | #define>5) |
6699 | 7242 | #define><5) |
|
6700 | /*>0) |
7243 | #define>5) |
6701 | #define><0) |
7244 | #define><5) |
6702 | #define>0) |
7245 | #define>0) |
6703 | 7246 | #define><0) |
|
6704 | /*><0) |
7247 | #define>29) |
6705 | 7248 | ||
6706 | /*>4) |
7249 | #define><29) |
6707 | #define><4) |
7250 | |
6708 | #define>0) |
7251 | #define>29) |
6709 | #define><0) |
7252 | #define><29) |
6710 | #define>3) |
7253 | #define>29) |
6711 | #define><3) |
7254 | |
6712 | #define>0) |
7255 | /*><29) |
6713 | #define><0) |
7256 | |
6714 | #define>15) |
7257 | /*>29) |
6715 | #define><15) |
7258 | #define><29) |
6716 | #define>8) |
7259 | #define>29) |
6717 | #define><8) |
7260 | #define><29) |
6718 | #define>8) |
7261 | #define>29) |
6719 | #define><8) |
7262 | #define><29) |
6720 | #define>1) |
7263 | #define>29) |
6721 | #define><1) |
7264 | #define><29) |
6722 | #define>1) |
7265 | #define>29) |
6723 | #define><1) |
7266 | #define><29) |
6724 | #define>0) |
7267 | #define>29) |
6725 | 7268 | #define><29) |
|
6726 | /*><0) |
7269 | #define>29) |
6727 | 7270 | #define><29) |
|
6728 | /*>0) |
7271 | #define>29) |
6729 | #define><0) |
7272 | #define><29) |
6730 | #define>1) |
7273 | #define>16) |
6731 | #define><1) |
7274 | |
6732 | #define>1) |
7275 | /*><16) |
6733 | #define><1) |
7276 | |
6734 | #define>8) |
7277 | /*>16) |
6735 | #define><8) |
7278 | #define><16) |
6736 | #define>8) |
7279 | #define>8) |
6737 | #define><8) |
7280 | #define><8) |
6738 | #define>8) |
7281 | #define>8) |
6739 | #define><8) |
7282 | #define><8) |
6740 | #define>8) |
7283 | #define>0) |
6741 | #define><8) |
7284 | #define><0) |
6742 | #define>16) |
7285 | #define>28) |
6743 | #define><16) |
7286 | /*><28) |
6744 | #define>16) |
7287 | /*>28) |
6745 | #define><16) |
7288 | #define><28) |
6746 | #define>0) |
7289 | #define>28) |
6747 | 7290 | #define><28) |
|
6748 | /*><0) |
7291 | #define>28) |
6749 | 7292 | #define><28) |
|
6750 | /*>><>4) |
7293 | #define>31) |
6751 | #define><4) |
7294 | #define><31) |
6752 | #define>7) |
7295 | #define>26) |
6753 | #define><7) |
7296 | |
6754 | #define>16) |
7297 | /*><26) |
6755 | #define><16) |
7298 | |
6756 | #define>24) |
7299 | /*>26) |
6757 | #define><24) |
7300 | #define><26) |
6758 | #define>24)><24)>24)><24)>24)><24)>24)><24)>24)><24)>24)><24)>24)><24)>24)><24)>24)><24)>31) |
7301 | #define>26) |
6759 | #define><31) |
7302 | #define><26) |
6760 | #define>><>><>><>12) |
7303 | #define>26) |
6761 | #define><12) |
7304 | #define><26) |
6762 | #define>23) |
7305 | #define>28) |
6763 | #define><23) |
7306 | #define><28) |
6764 | #define>24) |
7307 | #define>28) |
6765 | #define><24) |
7308 | #define><28) |
6766 | #define>25) |
7309 | #define>28) |
6767 | #define><25) |
7310 | #define><28) |
6768 | #define>7) |
7311 | #define>28) |
6769 | 7312 | #define><28) |
|
6770 | /*><7) |
7313 | #define>31) |
6771 | 7314 | #define><31) |
|
6772 | /*>8) |
7315 | #define>0) |
6773 | #define><8) |
7316 | |
6774 | #define>8) |
7317 | /*><0) |
6775 | #define><8) |
7318 | |
6776 | #define>8) |
7319 | /*>0) |
6777 | #define><8) |
7320 | #define><0) |
6778 | #define>8) |
7321 | #define>0) |
6779 | #define><8) |
7322 | |
6780 | #define>8) |
7323 | /*><0) |
6781 | #define><8) |
7324 | |
6782 | #define>8) |
7325 | /*>4) |
6783 | #define><8) |
7326 | #define><4) |
6784 | #define>15) |
7327 | #define>0) |
6785 | #define><15) |
7328 | #define><0) |
6786 | #define>18) |
7329 | #define>3) |
6787 | #define><18) |
7330 | #define><3) |
6788 | #define>25) |
7331 | #define>0) |
6789 | #define><25) |
7332 | #define><0) |
6790 | #define>27) |
7333 | #define>15) |
6791 | #define><27) |
7334 | #define><15) |
6792 | #define>27) |
7335 | #define>8) |
6793 | #define><27) |
7336 | #define><8) |
6794 | #define>31) |
7337 | #define>8) |
6795 | #define><31) |
7338 | #define><8) |
6796 | #define>4) |
7339 | #define>1) |
6797 | 7340 | #define><1) |
|
6798 | /*><4) |
7341 | #define>1) |
6799 | 7342 | #define><1) |
|
6800 | /*>8) |
7343 | #define>0) |
6801 | #define><8) |
7344 | |
6802 | #define>12) |
7345 | /*><0) |
6803 | #define><12) |
7346 | |
6804 | #define>12) |
7347 | /*>0) |
6805 | #define><12) |
7348 | #define><0) |
6806 | #define>12) |
7349 | #define>1) |
6807 | #define><12) |
7350 | #define><1) |
6808 | #define>12) |
7351 | #define>1) |
6809 | #define><12) |
7352 | #define><1) |
6810 | #define>12) |
7353 | #define>8) |
6811 | #define><12) |
7354 | #define><8) |
6812 | #define>16) |
7355 | #define>8) |
6813 | #define><16) |
7356 | #define><8) |
6814 | #define>17) |
7357 | #define>8) |
6815 | #define><17) |
7358 | #define><8) |
6816 | #define>20) |
7359 | #define>8) |
6817 | #define><20) |
7360 | #define><8) |
6818 | #define>20) |
7361 | #define>16) |
6819 | #define><20) |
7362 | #define><16) |
6820 | #define>20) |
7363 | #define>16) |
6821 | #define><20) |
7364 | #define><16) |
6822 | #define>20) |
7365 | #define>0) |
6823 | #define><20) |
7366 | |
6824 | #define>20) |
7367 | /*><0) |
6825 | #define><20) |
7368 | |
6826 | #define>24) |
7369 | /*>><>4) |
6827 | #define><24) |
7370 | #define><4) |
6828 | #define>24) |
7371 | #define>7) |
6829 | #define><24) |
7372 | #define><7) |
6830 | #define>24) |
7373 | #define>16) |
6831 | #define><24) |
7374 | #define><16) |
6832 | #define>24) |
7375 | #define>24) |
6833 | #define><24) |
7376 | #define><24) |
6834 | #define>24) |
7377 | #define>><>31) |
6835 | #define><24) |
7378 | #define><31) |
6836 | #define>24) |
7379 | #define>><>><>><>12) |
6837 | #define><24) |
7380 | #define><12) |
6838 | #define>28) |
7381 | #define>23) |
6839 | #define><28) |
7382 | #define><23) |
6840 | #define>28) |
7383 | #define>24) |
6841 | #define><28) |
7384 | #define><24) |
6842 | #define>28) |
7385 | #define>25) |
6843 | #define><28) |
7386 | #define><25) |
6844 | #define>31) |
7387 | #define>7) |
6845 | /*><31) |
7388 | |
6846 | /*>19) |
7389 | /*><7) |
6847 | #define><19) |
7390 | |
6848 | #define>20) |
7391 | /*>8) |
6849 | #define><20) |
7392 | #define><8) |
6850 | #define>31) |
7393 | #define>8) |
6851 | #define><31) |
7394 | #define><8) |
6852 | #define>30) |
7395 | #define>8) |
6853 | #define><30) |
7396 | #define><8) |
6854 | #define>31) |
7397 | #define>8) |
6855 | #define><31) |
7398 | #define><8) |
6856 | #define>9) |
7399 | #define>8) |
6857 | 7400 | #define><8) |
|
6858 | /*><9) |
7401 | #define>8) |
6859 | 7402 | #define><8) |
|
6860 | /*>5) |
7403 | #define>15) |
6861 | #define><5) |
7404 | #define><15) |
6862 | #define>1) |
7405 | #define>18) |
6863 | #define><1) |
7406 | #define><18) |
6864 | #define>8) |
7407 | #define>25) |
6865 | #define><8) |
7408 | #define><25) |
6866 | #define>4) |
7409 | #define>27) |
6867 | #define><4) |
7410 | #define><27) |
6868 | #define>0) |
7411 | #define>27) |
6869 | #define><0) |
7412 | #define><27) |
6870 | #define>10) |
7413 | #define>31) |
6871 | #define><10) |
7414 | #define><31) |
6872 | #define>6) |
7415 | #define>4) |
6873 | #define><6) |
7416 | |
6874 | #define>2) |
7417 | /*><4) |
6875 | #define><2) |
7418 | |
6876 | #define>3) |
7419 | /*>8) |
6877 | #define><3) |
7420 | #define><8) |
6878 | #define>7) |
7421 | #define>12) |
6879 | #define><7) |
7422 | #define><12) |
6880 | #define>11) |
7423 | #define>12) |
6881 | #define><11) |
7424 | #define><12) |
6882 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>1) |
7425 | #define>12) |
6883 | 7426 | #define><12) |
|
6884 | #define><1) |
7427 | #define>12) |
6885 | 7428 | #define><12) |
|
6886 | #define>8) |
7429 | #define>12) |
6887 | #define><8) |
7430 | #define><12) |
6888 | #define>><>0) |
7431 | #define>16) |
6889 | 7432 | #define><16) |
|
6890 | #define><0) |
7433 | #define>17) |
6891 | 7434 | #define><17) |
|
6892 | #define>5) |
7435 | #define>20) |
6893 | 7436 | #define><20) |
|
6894 | #define><5) |
7437 | #define>20) |
6895 | 7438 | #define><20) |
|
6896 | #define>8) |
7439 | #define>20) |
6897 | #define><8) |
7440 | #define><20) |
6898 | #define>3) |
7441 | #define>20) |
6899 | 7442 | #define><20) |
|
6900 | #define><3) |
7443 | #define>20) |
6901 | 7444 | #define><20) |
|
6902 | #define>10) |
7445 | #define>24) |
6903 | #define><10) |
7446 | #define><24) |
6904 | #define>12) |
7447 | #define>24) |
6905 | #define><12) |
7448 | #define><24) |
6906 | #define>7) |
7449 | #define>24) |
6907 | 7450 | #define><24) |
|
6908 | #define><7) |
7451 | #define>24) |
6909 | 7452 | #define><24) |
|
6910 | #define>8) |
7453 | #define>24) |
6911 | #define><8) |
7454 | #define><24) |
6912 | #define>11) |
7455 | #define>24) |
6913 | #define><11) |
7456 | #define><24) |
6914 | #define>13) |
7457 | #define>28) |
6915 | #define><13) |
7458 | #define><28) |
6916 | #define>14) |
7459 | #define>28) |
6917 | #define><14) |
7460 | #define><28) |
6918 | #define>0) |
7461 | #define>28) |
6919 | 7462 | #define><28) |
|
6920 | /*><0) |
7463 | #define>31) |
6921 | 7464 | /*><31) |
|
6922 | /*>4) |
7465 | /*>19) |
6923 | #define><4) |
7466 | #define><19) |
6924 | #define>31) |
7467 | #define>20) |
6925 | #define><31) |
7468 | #define><20) |
6926 | #define>0) |
7469 | #define>31) |
6927 | #define><0) |
7470 | #define><31) |
6928 | #define>1) |
7471 | #define>30) |
6929 | #define><1) |
7472 | #define><30) |
6930 | #define>4) |
7473 | #define>31) |
6931 | #define><4) |
7474 | #define><31) |
6932 | #define>5) |
7475 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>1) |
6933 | #define><5) |
7476 | |
6934 | #define>15) |
7477 | /*><1) |
6935 | #define><15) |
7478 | |
6936 | #define>2) |
7479 | /*>8) |
6937 | 7480 | #define><8) |
|
6938 | #define><2) |
7481 | #define>><>0) |
6939 | 7482 | ||
6940 | #define>3) |
7483 | #define><0) |
6941 | #define><3) |
7484 | |
6942 | #define>1) |
7485 | #define>5) |
6943 | #define><1) |
7486 | |
6944 | #define>2) |
7487 | #define><5) |
6945 | #define><2) |
7488 | |
6946 | #define>4) |
7489 | #define>8) |
6947 | #define><4) |
7490 | #define><8) |
6948 | #define>5) |
7491 | #define>5) |
6949 | #define><5) |
7492 | |
6950 | #define>6) |
7493 | #define><5) |
6951 | #define><6) |
7494 | |
6952 | #define>24) |
7495 | #define>3) |
6953 | #define><24) |
7496 | |
6954 | #define>25) |
7497 | #define><3) |
6955 | #define><25) |
7498 | |
6956 | #define>31) |
7499 | #define>10) |
6957 | #define><31) |
7500 | #define><10) |
6958 | #define>0) |
7501 | #define>12) |
6959 | #define><0) |
7502 | #define><12) |
6960 | #define>0) |
7503 | #define>7) |
6961 | #define><0) |
7504 | |
6962 | #define>3) |
7505 | #define><7) |
6963 | #define><3) |
7506 | |
6964 | #define>3) |
7507 | #define>8) |
6965 | #define><3) |
7508 | #define><8) |
6966 | #define>3) |
7509 | #define>11) |
6967 | #define><3) |
7510 | #define><11) |
6968 | #define>7) |
7511 | #define>13) |
6969 | #define><7) |
7512 | #define><13) |
6970 | #define>8) |
7513 | #define>14) |
6971 | #define><8) |
7514 | #define><14) |
6972 | #define>9) |
7515 | #define>0) |
6973 | #define><9) |
7516 | |
6974 | #define>9) |
7517 | /*><0) |
6975 | #define><9) |
7518 | |
6976 | #define>9) |
7519 | /*>4) |
6977 | #define><9) |
7520 | #define><4) |
6978 | #define>9) |
7521 | #define>31) |
6979 | #define><9) |
7522 | #define><31) |
6980 | #define>9) |
7523 | #define>0) |
6981 | #define><9) |
7524 | #define><0) |
6982 | #define>11) |
7525 | #define>1) |
6983 | #define><11) |
7526 | #define><1) |
6984 | #define>><>><>31) |
7527 | #define>4) |
6985 | #define><31) |
7528 | #define><4) |
6986 | #define>27) |
7529 | #define>5) |
6987 | #define><27) |
7530 | #define><5) |
6988 | #define>28) |
7531 | #define>15) |
6989 | #define><28) |
7532 | #define><15) |
6990 | #define>24) |
7533 | #define>2) |
6991 | #define><24) |
7534 | |
6992 | #define>22) |
7535 | #define><2) |
6993 | #define><22) |
7536 | |
6994 | #define>20) |
7537 | #define>3) |
6995 | #define><20) |
7538 | #define><3) |
6996 | #define>18) |
7539 | #define>1) |
6997 | #define><18) |
7540 | #define><1) |
6998 | #define>17) |
7541 | #define>2) |
6999 | #define><17) |
7542 | #define><2) |
7000 | #define>16) |
7543 | #define>4) |
7001 | #define><16) |
7544 | #define><4) |
7002 | #define>15) |
7545 | #define>5) |
7003 | #define><15) |
7546 | #define><5) |
7004 | #define>19) |
7547 | #define>6) |
7005 | #define><19) |
7548 | #define><6) |
7006 | #define>24) |
7549 | #define>24) |
7007 | #define><24) |
7550 | #define><24) |
7008 | #define>25) |
7551 | #define>25) |
7009 | #define><25) |
7552 | #define><25) |
7010 | #define>31) |
7553 | #define>31) |
7011 | #define><31) |
7554 | #define><31) |
7012 | #define>14) |
7555 | #define>0) |
7013 | 7556 | #define><0) |
|
7014 | #define><14) |
7557 | #define>0) |
7015 | 7558 | #define><0) |
|
7016 | #define>25) |
7559 | #define>3) |
7017 | 7560 | #define><3) |
|
7018 | #define><25) |
7561 | #define>3) |
7019 | 7562 | #define><3) |
|
7020 | #define>><>><>><>><>><>><>><>><>><>0) |
7563 | #define>3) |
7021 | 7564 | #define><3) |
|
7022 | #define><0) |
7565 | #define>7) |
7023 | 7566 | #define><7) |
|
7024 | #define>1) |
7567 | #define>8) |
7025 | #define><1) |
7568 | #define><8) |
7026 | #define>2) |
7569 | #define>9) |
7027 | #define><2) |
7570 | #define><9) |
7028 | #define>3) |
7571 | #define>9) |
7029 | #define><3) |
7572 | #define><9) |
7030 | #define>4) |
7573 | #define>9) |
7031 | #define><4) |
7574 | #define><9) |
7032 | #define>5) |
7575 | #define>9) |
7033 | #define><5) |
7576 | #define><9) |
7034 | #define>6) |
7577 | #define>9) |
7035 | #define><6) |
7578 | #define><9) |
7036 | #define>5) |
7579 | #define>11) |
7037 | #define><5) |
7580 | #define><11) |
7038 | #define>><>><>><>><>><>><>><>22) |
7581 | #define>><>><>31) |
7039 | 7582 | #define><31) |
|
7040 | #define><22) |
7583 | #define>27) |
7041 | 7584 | #define><27) |
|
7042 | #define>22) |
7585 | #define>28) |
7043 | 7586 | #define><28) |
|
7044 | #define><22) |
7587 | #define>24) |
7045 | 7588 | #define><24) |
|
7046 | #define>22) |
7589 | #define>22) |
7047 | #define><22) |
7590 | #define><22) |
7048 | #define>22) |
7591 | #define>20) |
7049 | #define><22) |
7592 | #define><20) |
7050 | #define>22) |
7593 | #define>18) |
7051 | #define><22) |
7594 | #define><18) |
7052 | #define>22) |
7595 | #define>17) |
7053 | #define><22) |
7596 | #define><17) |
7054 | #define>22) |
7597 | #define>16) |
7055 | 7598 | #define><16) |
|
7056 | /*><22) |
7599 | #define>15) |
7057 | 7600 | #define><15) |
|
7058 | /*>22) |
7601 | #define>19) |
7059 | #define><22) |
7602 | #define><19) |
7060 | #define>22) |
7603 | #define>24) |
7061 | #define><22) |
7604 | #define><24) |
7062 | #define>22) |
7605 | #define>25) |
7063 | #define><22) |
7606 | #define><25) |
7064 | #define>22) |
7607 | #define>31) |
7065 | #define><22) |
7608 | #define><31) |
7066 | #define>22) |
7609 | #define>14) |
7067 | #define><22) |
7610 | |
7068 | #define>22) |
7611 | #define><14) |
7069 | #define><22) |
7612 | |
7070 | #define>22) |
7613 | #define>25) |
7071 | 7614 | ||
7072 | /*><22) |
7615 | #define><25) |
7073 | 7616 | ||
7074 | /*>22) |
7617 | #define>><>><>><>><>><>><>><>><>><>0) |
7075 | #define><22) |
7618 | |
7076 | #define>22) |
7619 | #define><0) |
7077 | #define><22) |
7620 | |
7078 | #define>22) |
7621 | #define>1) |
7079 | #define><22) |
7622 | #define><1) |
7080 | #define>22) |
7623 | #define>2) |
7081 | #define><22) |
7624 | #define><2) |
7082 | #define>22) |
7625 | #define>3) |
7083 | #define><22) |
7626 | #define><3) |
7084 | #define>22) |
7627 | #define>4) |
7085 | /*><22) |
7628 | #define><4) |
7086 | /*>22) |
7629 | #define>5) |
7087 | #define><22) |
7630 | #define><5) |
7088 | #define>22) |
7631 | #define>6) |
7089 | #define><22) |
7632 | #define><6) |
7090 | #define>22) |
7633 | #define>5) |
7091 | #define><22) |
7634 | #define><5) |
7092 | #define>3) |
7635 | #define>><>><>><>><>><>><>><>22) |
7093 | 7636 | ||
7094 | /*><3) |
7637 | #define><22) |
7095 | 7638 | ||
7096 | /*>3) |
7639 | #define>22) |
7097 | #define><3) |
7640 | |
7098 | #define>4) |
7641 | #define><22) |
7099 | #define><4) |
7642 | |
7100 | #define>9) |
7643 | #define>22) |
7101 | #define><9) |
7644 | #define><22) |
7102 | #define>9) |
7645 | #define>22) |
7103 | #define><9) |
7646 | #define><22) |
7104 | #define>9) |
7647 | #define>22) |
7105 | #define><9) |
7648 | #define><22) |
7106 | #define>9) |
7649 | #define>22) |
7107 | #define><9) |
7650 | #define><22) |
7108 | #define>9) |
7651 | #define>22) |
7109 | #define><9) |
7652 | |
7110 | #define>18) |
7653 | /*><22) |
7111 | #define><18) |
7654 | |
7112 | #define>26) |
7655 | /*>22) |
7113 | #define><26) |
7656 | #define><22) |
7114 | #define>29) |
7657 | #define>22) |
7115 | #define><29) |
7658 | #define><22) |
7116 | #define>29) |
7659 | #define>22) |
7117 | #define><29) |
7660 | #define><22) |
7118 | #define>29) |
7661 | #define>22) |
7119 | #define><29) |
7662 | #define><22) |
7120 | #define>29) |
7663 | #define>22) |
7121 | #define><29) |
7664 | #define><22) |
7122 | #define>29) |
7665 | #define>22) |
7123 | #define><29) |
7666 | #define><22) |
7124 | #define>31) |
7667 | #define>22) |
7125 | #define><31) |
7668 | |
7126 | #define>16))><16))>24))><24))>30))><30))>><>29) |
7669 | /*><22) |
7127 | #define><29) |
7670 | |
7128 | #define>29) |
7671 | /*>22) |
7129 | #define><29) |
7672 | #define><22) |
7130 | #define>29) |
7673 | #define>22) |
7131 | #define><29) |
7674 | #define><22) |
7132 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
7675 | #define>22) |
7133 | 7676 | #define><22) |
|
7134 | #define><0) |
7677 | #define>22) |
7135 | 7678 | #define><22) |
|
7136 | #define>1) |
7679 | #define>22) |
7137 | #define><1) |
7680 | #define><22) |
7138 | #define>2) |
7681 | #define>22) |
7139 | #define><2) |
7682 | /*><22) |
7140 | #define>3) |
7683 | /*>22) |
7141 | #define><3) |
7684 | #define><22) |
7142 | #define>4) |
7685 | #define>22) |
7143 | #define><4) |
7686 | #define><22) |
7144 | #define>5) |
7687 | #define>22) |
7145 | #define><5) |
7688 | #define><22) |
7146 | #define>6) |
7689 | #define>3) |
7147 | #define><6) |
7690 | |
7148 | #define>7) |
7691 | /*><3) |
7149 | #define><7) |
7692 | |
7150 | #define>8)><8)>9)><9)>10) |
7693 | /*>3) |
7151 | #define><10) |
7694 | #define><3) |
7152 | #define>0) |
7695 | #define>4) |
7153 | #define><0) |
7696 | #define><4) |
7154 | #define>20) |
7697 | #define>9) |
7155 | #define><20) |
7698 | #define><9) |
7156 | #define>20) |
7699 | #define>9) |
7157 | #define><20) |
7700 | #define><9) |
7158 | #define>24) |
7701 | #define>9) |
7159 | #define><24) |
7702 | #define><9) |
7160 | #define>24) |
7703 | #define>9) |
7161 | #define><24) |
7704 | #define><9) |
7162 | #define>26) |
7705 | #define>9) |
7163 | #define><26) |
7706 | #define><9) |
7164 | #define>26) |
7707 | #define>18) |
7165 | #define><26) |
7708 | #define><18) |
7166 | #define>8) |
7709 | #define>26) |
7167 | 7710 | #define><26) |
|
7168 | #define><8) |
7711 | #define>29) |
7169 | 7712 | #define><29) |
|
7170 | #define>8) |
7713 | #define>29) |
7171 | #define><8) |
7714 | #define><29) |
7172 | #define>8) |
7715 | #define>29) |
7173 | #define><8) |
7716 | #define><29) |
7174 | #define>8) |
7717 | #define>29) |
7175 | #define><8) |
7718 | #define><29) |
7176 | #define>8) |
7719 | #define>29) |
7177 | #define><8) |
7720 | #define><29) |
7178 | #define>10) |
7721 | #define>31) |
7179 | #define><10) |
7722 | #define><31) |
7180 | #define>4) |
7723 | #define>16))><16))>24))><24))>30))><30))>><>29) |
7181 | /*><4) |
7724 | #define><29) |
7182 | /*>6) |
7725 | #define>29) |
7183 | #define><6) |
7726 | #define><29) |
7184 | #define>8) |
7727 | #define>29) |
7185 | #define><8) |
7728 | #define><29) |
7186 | #define>9) |
7729 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
7187 | #define><9) |
7730 | |
7188 | #define>10) |
7731 | #define><0) |
7189 | #define><10) |
7732 | |
7190 | #define>11) |
7733 | #define>1) |
7191 | #define><11) |
7734 | #define><1) |
7192 | #define>13) |
7735 | #define>2) |
7193 | #define><13) |
7736 | #define><2) |
7194 | #define>14) |
7737 | #define>3) |
7195 | #define><14) |
7738 | #define><3) |
7196 | #define>15) |
7739 | #define>4) |
7197 | #define><15) |
7740 | #define><4) |
7198 | #define>16) |
7741 | #define>5) |
7199 | #define><16) |
7742 | #define><5) |
7200 | #define>16) |
7743 | #define>6) |
7201 | #define><16) |
7744 | #define><6) |
7202 | #define>16) |
7745 | #define>7) |
7203 | #define><16) |
7746 | #define><7) |
7204 | #define>16) |
7747 | #define>8)><8)>9)><9)>10) |
7205 | #define><16) |
7748 | #define><10) |
7206 | #define>16) |
7749 | #define>0) |
7207 | #define><16) |
7750 | #define><0) |
7208 | #define>26) |
7751 | #define>20) |
7209 | #define><26) |
7752 | #define><20) |
7210 | #define>27) |
7753 | #define>20) |
7211 | #define><27) |
7754 | #define><20) |
7212 | #define>31) |
7755 | #define>24) |
7213 | /*><31) |
7756 | #define><24) |
7214 | /*>7) |
7757 | #define>24) |
7215 | 7758 | #define><24) |
|
7216 | /*><7) |
7759 | #define>26) |
7217 | 7760 | #define><26) |
|
7218 | /*>7) |
7761 | #define>26) |
7219 | #define><7) |
7762 | #define><26) |
7220 | #define>10) |
7763 | #define>8) |
7221 | #define><10) |
7764 | |
7222 | #define>11) |
7765 | #define><8) |
7223 | #define><11) |
7766 | |
7224 | #define>8) |
7767 | #define>8) |
7225 | 7768 | #define><8) |
|
7226 | /*><8) |
7769 | #define>8) |
7227 | 7770 | #define><8) |
|
7228 | /*>8) |
7771 | #define>8) |
7229 | #define><8) |
7772 | #define><8) |
7230 | #define>8) |
7773 | #define>8) |
7231 | #define><8) |
7774 | #define><8) |
7232 | #define>8) |
7775 | #define>10) |
7233 | #define><8) |
7776 | #define><10) |
7234 | #define>14) |
7777 | #define>4) |
7235 | 7778 | /*><4) |
|
7236 | /*><14) |
7779 | /*>6) |
7237 | 7780 | #define><6) |
|
7238 | /*>18) |
7781 | #define>8) |
7239 | /*><18) |
7782 | #define><8) |
7240 | /*>><>><>22) |
7783 | #define>9) |
7241 | #define><22) |
7784 | #define><9) |
7242 | #define>22) |
7785 | #define>10) |
7243 | #define><22) |
7786 | #define><10) |
7244 | #define>22) |
7787 | #define>11) |
7245 | #define><22) |
7788 | #define><11) |
7246 | #define>22) |
7789 | #define>13) |
7247 | #define><22) |
7790 | #define><13) |
7248 | #define>22) |
7791 | #define>14) |
7249 | #define><22) |
7792 | #define><14) |
7250 | #define>22) |
7793 | #define>15) |
7251 | /*><22) |
7794 | #define><15) |
7252 | /*>22) |
7795 | #define>16) |
7253 | #define><22) |
7796 | #define><16) |
7254 | #define>22) |
7797 | #define>16) |
7255 | #define><22) |
7798 | #define><16) |
7256 | #define>22) |
7799 | #define>16) |
7257 | #define><22) |
7800 | #define><16) |
7258 | #define>22) |
7801 | #define>16) |
7259 | /*><22) |
7802 | #define><16) |
7260 | /*>22) |
7803 | #define>16) |
7261 | #define><22) |
7804 | #define><16) |
7262 | #define>22) |
7805 | #define>26) |
7263 | #define><22) |
7806 | #define><26) |
7264 | #define>22) |
7807 | #define>27) |
7265 | #define><22) |
7808 | #define><27) |
7266 | #define>25) |
7809 | #define>31) |
7267 | #define><25) |
7810 | /*><31) |
7268 | #define>25) |
7811 | /*>7) |
7269 | #define><25) |
7812 | |
7270 | #define>25) |
7813 | /*><7) |
7271 | #define><25) |
7814 | |
7272 | #define>25) |
7815 | /*>7) |
7273 | #define><25) |
7816 | #define><7) |
7274 | #define>28) |
7817 | #define>10) |
7275 | #define><28) |
7818 | #define><10) |
7276 | #define>28) |
7819 | #define>11) |
7277 | #define><28) |
7820 | #define><11) |
7278 | #define>28) |
7821 | #define>8) |
7279 | #define><28) |
7822 | |
7280 | #define>28) |
7823 | /*><8) |
7281 | #define><28) |
7824 | |
7282 | #define>31) |
7825 | /*>8) |
7283 | #define><31) |
7826 | #define><8) |
7284 | #define>31) |
7827 | #define>8) |
7285 | #define><31) |
7828 | #define><8) |
7286 | #define>12) |
7829 | #define>8) |
7287 | 7830 | #define><8) |
|
7288 | /*><12) |
7831 | #define>14) |
7289 | 7832 | ||
7290 | /*>14) |
7833 | /*><14) |
7291 | #define><14) |
7834 | |
7292 | #define>29) |
7835 | /*>18) |
7293 | #define><29) |
7836 | /*><18) |
7294 | #define>30) |
7837 | /*>><>><>22) |
7295 | #define><30) |
7838 | #define><22) |
7296 | #define>0) |
7839 | #define>22) |
7297 | #define><0) |
7840 | #define><22) |
7298 | #define>1) |
7841 | #define>22) |
7299 | #define><1) |
7842 | #define><22) |
7300 | #define>0) |
7843 | #define>22) |
7301 | 7844 | #define><22) |
|
7302 | #define><0) |
7845 | #define>22) |
7303 | 7846 | #define><22) |
|
7304 | #define>12) |
7847 | #define>22) |
7305 | #define><12) |
7848 | /*><22) |
7306 | #define>13) |
7849 | /*>22) |
7307 | #define><13) |
7850 | #define><22) |
7308 | #define>><>(FDIA_PHASE_SYNC_SHIFT_EN><(FDIA_PHASE_SYNC_SHIFT_EN>(FDIA_PHASE_SYNC_SHIFT_OVR><(FDIA_PHASE_SYNC_SHIFT_OVR>25) |
7851 | #define>22) |
7309 | 7852 | #define><22) |
|
7310 | #define><25) |
7853 | #define>22) |
7311 | 7854 | #define><22) |
|
7312 | #define>26) |
7855 | #define>22) |
7313 | #define><26) |
7856 | /*><22) |
7314 | #define>27) |
7857 | /*>22) |
7315 | #define><27) |
7858 | #define><22) |
7316 | #define>29) |
7859 | #define>22) |
7317 | #define><29) |
7860 | #define><22) |
7318 | #define>31) |
7861 | #define>22) |
7319 | #define><31) |
7862 | #define><22) |
7320 | #define>4) |
7863 | #define>25) |
7321 | #define><4) |
7864 | #define><25) |
7322 | #define>5) |
7865 | #define>25) |
7323 | 7866 | #define><25) |
|
7324 | #define><5) |
7867 | #define>25) |
7325 | 7868 | #define><25) |
|
7326 | #define>5) |
7869 | #define>25) |
7327 | #define><5) |
7870 | #define><25) |
7328 | #define>5) |
7871 | #define>28) |
7329 | #define><5) |
7872 | #define><28) |
7330 | #define>5) |
7873 | #define>28) |
7331 | #define><5) |
7874 | #define><28) |
7332 | #define>21) |
7875 | #define>28) |
7333 | #define><21) |
7876 | #define><28) |
7334 | #define>21) |
7877 | #define>28) |
7335 | #define><21) |
7878 | #define><28) |
7336 | #define>21) |
7879 | #define>31) |
7337 | #define><21) |
7880 | #define><31) |
7338 | #define>21) |
7881 | #define>31) |
7339 | #define><21) |
7882 | #define><31) |
7340 | #define>27) |
7883 | #define>12) |
7341 | #define><27) |
7884 | |
7342 | #define>27) |
7885 | /*><12) |
7343 | #define><27) |
7886 | |
7344 | #define>27) |
7887 | /*>14) |
7345 | #define><27) |
7888 | #define><14) |
7346 | #define>27) |
7889 | #define>29) |
7347 | #define><27) |
7890 | #define><29) |
7348 | #define>30) |
7891 | #define>30) |
7349 | #define><30) |
7892 | #define><30) |
7350 | #define>30) |
7893 | #define>0) |
7351 | #define><30) |
7894 | #define><0) |
7352 | #define>30) |
7895 | #define>1) |
7353 | #define><30) |
7896 | #define><1) |
7354 | #define>31) |
7897 | #define>0) |
7355 | #define><31) |
7898 | |
7356 | #define>31) |
7899 | #define><0) |
7357 | #define><31) |
7900 | |
7358 | #define>31) |
7901 | #define>12) |
7359 | #define><31) |
7902 | #define><12) |
7360 | #define>><>><>10) |
7903 | #define>13) |
7361 | #define><10) |
7904 | #define><13) |
7362 | #define>12) |
7905 | #define>><>(FDIA_PHASE_SYNC_SHIFT_EN><(FDIA_PHASE_SYNC_SHIFT_EN>(FDIA_PHASE_SYNC_SHIFT_OVR><(FDIA_PHASE_SYNC_SHIFT_OVR>25) |
7363 | #define><12) |
7906 | |
7364 | #define>1) |
7907 | #define><25) |
7365 | #define><1) |
7908 | |
7366 | #define>1) |
7909 | #define>26) |
7367 | #define><1) |
7910 | #define><26) |
7368 | #define>6) |
7911 | #define>27) |
7369 | #define><6) |
7912 | #define><27) |
7370 | #define>6) |
7913 | #define>29) |
7371 | #define><6) |
7914 | #define><29) |
7372 | #define>7) |
7915 | #define>31) |
7373 | #define><7) |
7916 | #define><31) |
7374 | #define>7) |
7917 | #define>4) |
7375 | #define><7) |
7918 | #define><4) |
7376 | #define>7) |
7919 | #define>5) |
7377 | #define><7) |
7920 | |
7378 | #define>9) |
7921 | #define><5) |
7379 | #define><9) |
7922 | |
7380 | #define>9) |
7923 | #define>5) |
7381 | #define><9) |
7924 | #define><5) |
7382 | #define>9) |
7925 | #define>5) |
7383 | #define><9) |
7926 | #define><5) |
7384 | #define>9) |
7927 | #define>5) |
7385 | #define><9) |
7928 | #define><5) |
7386 | #define>11) |
7929 | #define>21) |
7387 | #define><11) |
7930 | #define><21) |
7388 | #define>11) |
7931 | #define>21) |
7389 | #define><11) |
7932 | #define><21) |
7390 | #define>11) |
7933 | #define>21) |
7391 | #define><11) |
7934 | #define><21) |
7392 | #define>13) |
7935 | #define>21) |
7393 | #define><13) |
7936 | #define><21) |
7394 | #define>13) |
7937 | #define>27) |
7395 | #define><13) |
7938 | #define><27) |
7396 | #define>13) |
7939 | #define>27) |
7397 | #define><13) |
7940 | #define><27) |
7398 | #define>13) |
7941 | #define>27) |
7399 | #define><13) |
7942 | #define><27) |
7400 | #define>22) |
7943 | #define>27) |
7401 | #define><22) |
7944 | #define><27) |
7402 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>(pipe*3)) |
7945 | #define>30) |
7403 | 7946 | #define><30) |
|
7404 | /*><(pipe*3)) |
7947 | #define>30) |
7405 | 7948 | #define><30) |
|
7406 | /*>0) |
7949 | #define>30) |
7407 | #define><0) |
7950 | #define><30) |
7408 | #define>3) |
7951 | #define>31) |
7409 | #define><3) |
7952 | #define><31) |
7410 | #define>6) |
7953 | #define>31) |
7411 | #define><6) |
7954 | #define><31) |
7412 | #define>31) |
7955 | #define>31) |
7413 | #define><31) |
7956 | #define><31) |
7414 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>27) |
7957 | #define>><>><>10) |
7415 | 7958 | #define><10) |
|
7416 | /*><27) |
7959 | #define>12) |
7417 | 7960 | #define><12) |
|
7418 | /*>11) |
7961 | #define>1) |
7419 | 7962 | #define><1) |
|
7420 | #define><11) |
7963 | #define>1) |
7421 | 7964 | #define><1) |
|
7422 | #define>4) |
7965 | #define>6) |
7423 | 7966 | #define><6) |
|
7424 | /*><4) |
7967 | #define>6) |
7425 | 7968 | #define><6) |
|
7426 | /*>27) |
7969 | #define>7) |
7427 | 7970 | #define><7) |
|
7428 | /*><27) |
7971 | #define>7) |
7429 | 7972 | #define><7) |
|
7430 | /*>19) |
7973 | #define>7) |
7431 | #define><19) |
7974 | #define><7) |
7432 | #define>0) |
7975 | #define>9) |
7433 | 7976 | #define><9) |
|
7434 | #define><0) |
7977 | #define>9) |
7435 | 7978 | #define><9) |
|
7436 | #define>26)) |
7979 | #define>9) |
7437 | #define><26)) |
7980 | #define><9) |
7438 | #define>10)><10)>4) |
7981 | #define>9) |
7439 | 7982 | #define><9) |
|
7440 | /*><4) |
7983 | #define>11) |
7441 | 7984 | #define><11) |
|
7442 | /*>0) |
7985 | #define>11) |
7443 | #define><0) |
7986 | #define><11) |
7444 | #define>1) |
7987 | #define>11) |
7445 | #define><1) |
7988 | #define><11) |
7446 | #define>6) |
7989 | #define>13) |
7447 | #define><6) |
7990 | #define><13) |
7448 | #define>15) |
7991 | #define>13) |
7449 | #define><15) |
7992 | #define><13) |
7450 | #define>13) |
7993 | #define>13) |
7451 | #define><13) |
7994 | #define><13) |
7452 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>21) |
7995 | #define>13) |
7453 | #define><21) |
7996 | #define><13) |
7454 | #define>22) |
7997 | #define>22) |
7455 | #define><22) |
7998 | #define><22) |
7456 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
7999 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>(pipe*3)) |
7457 | 8000 | ||
7458 | #define><0) |
8001 | /*><(pipe*3)) |
7459 | 8002 | ||
7460 | #define>1) |
8003 | /*>0) |
7461 | #define><1) |
8004 | #define><0) |
7462 | #define>2) |
8005 | #define>3) |
7463 | #define><2) |
8006 | #define><3) |
7464 | #define>3) |
8007 | #define>6) |
7465 | #define><3) |
8008 | #define><6) |
7466 | #define>4) |
8009 | #define>31) |
7467 | #define><4) |
8010 | #define><31) |
7468 | #define>6) |
8011 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>27) |
7469 | #define><6) |
8012 | |
7470 | #define>(16+pipe)) |
8013 | /*><27) |
7471 | #define><(16+pipe)) |
8014 | |
7472 | #define>16) |
8015 | /*>11) |
7473 | #define><16) |
8016 | |
7474 | #define>17) |
8017 | #define><11) |
7475 | #define><17) |
8018 | |
7476 | #define>18) |
8019 | #define>14) |
7477 | #define><18) |
8020 | |
7478 | #define>20) |
8021 | /*><14) |
7479 | #define><20) |
8022 | |
7480 | #define>22) |
8023 | /*>11) |
7481 | #define><22) |
8024 | #define><11) |
7482 | #define>23) |
8025 | #define>4) |
7483 | #define><23) |
8026 | #define><4) |
7484 | #define>30) |
8027 | #define>27) |
7485 | #define><30) |
8028 | |
7486 | #define>31) |
8029 | /*><27) |
7487 | #define><31) |
8030 | |
7488 | #define>31) |
8031 | /*>19) |
7489 | 8032 | #define><19) |
|
7490 | #define><31) |
8033 | #define>0) |
7491 | 8034 | ||
7492 | #define>><>0) |
8035 | #define><0) |
7493 | #define><0) |
8036 | |
7494 | #define>><>3) |
8037 | #define>26)) |
7495 | #define><3) |
8038 | #define><26)) |
7496 | #define>4) |
8039 | #define>10)><10)>4) |
7497 | #define><4) |
8040 | |
7498 | #define>5) |
8041 | /*><4) |
7499 | #define><5) |
8042 | |
7500 | #define>8) |
8043 | /*>0) |
7501 | #define><8) |
8044 | #define><0) |
7502 | #define>9) |
8045 | #define>1) |
7503 | #define><9) |
8046 | #define><1) |
7504 | #define>10) |
8047 | #define>6) |
7505 | #define><10) |
8048 | #define><6) |
7506 | #define>13) |
8049 | #define>15) |
7507 | #define><13) |
8050 | #define><15) |
7508 | #define>14) |
8051 | #define>13) |
7509 | #define><14) |
8052 | #define><13) |
7510 | #define>26) |
8053 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>21) |
7511 | #define><26) |
8054 | #define><21) |
7512 | #define>27) |
8055 | #define>22) |
7513 | #define><27) |
8056 | #define><22) |
7514 | #define>28) |
8057 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
7515 | #define><28) |
8058 | |
7516 | #define>29) |
8059 | #define><0) |
7517 | #define><29) |
8060 | |
7518 | #define>30) |
8061 | #define>1) |
7519 | #define><30) |
8062 | #define><1) |
7520 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>23) |
8063 | #define>2) |
7521 | #define><23) |
8064 | #define><2) |
7522 | #define>23) |
8065 | #define>3) |
7523 | #define><23) |
8066 | #define><3) |
7524 | #define>23) |
8067 | #define>4) |
7525 | #define><23) |
8068 | #define><4) |
7526 | #define>23) |
8069 | #define>6) |
7527 | #define><23) |
8070 | #define><6) |
7528 | #define>23) |
8071 | #define>(16+pipe)) |
7529 | #define><23) |
8072 | #define><(16+pipe)) |
7530 | #define>29) |
8073 | #define>16) |
7531 | #define><29) |
8074 | #define><16) |
7532 | #define>29) |
8075 | #define>17) |
7533 | #define><29) |
8076 | #define><17) |
7534 | #define>31) |
8077 | #define>18) |
7535 | #define><31) |
8078 | #define><18) |
7536 | #define>24) |
8079 | #define>20) |
7537 | #define><24) |
8080 | #define><20) |
7538 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>10) |
8081 | #define>22) |
7539 | #define><10) |
8082 | #define><22) |
7540 | #define>16) |
8083 | #define>23) |
7541 | #define><16) |
8084 | #define><23) |
7542 | #define>16) |
8085 | #define>30) |
7543 | #define><16) |
8086 | #define><30) |
7544 | #define>16) |
8087 | #define>31) |
7545 | #define><16) |
8088 | #define><31) |
7546 | #define>16) |
8089 | #define>31) |
7547 | #define><16) |
8090 | |
7548 | #define>16) |
8091 | #define><31) |
7549 | #define><16) |
8092 | |
7550 | #define>22) |
8093 | #define>><>0) |
7551 | #define><22) |
8094 | #define><0) |
7552 | #define>26) |
8095 | #define>><>3) |
7553 | #define><26) |
8096 | #define><3) |
7554 | #define>26) |
8097 | #define>4) |
7555 | #define><26) |
8098 | #define><4) |
7556 | #define>26) |
8099 | #define>5) |
7557 | #define><26) |
8100 | #define><5) |
7558 | #define>26) |
8101 | #define>8) |
7559 | #define><26) |
8102 | #define><8) |
7560 | #define>26) |
8103 | #define>9) |
7561 | #define><26) |
8104 | #define><9) |
7562 | #define>26) |
8105 | #define>10) |
7563 | #define><26) |
8106 | #define><10) |
7564 | #define>26) |
8107 | #define>13) |
7565 | #define><26) |
8108 | #define><13) |
7566 | #define>26) |
8109 | #define>14) |
7567 | #define><26) |
8110 | #define><14) |
7568 | #define>26) |
8111 | #define>26) |
7569 | #define><26) |
8112 | #define><26) |
7570 | #define>30) |
8113 | #define>27) |
7571 | #define><30) |
8114 | #define><27) |
7572 | #define>31) |
8115 | #define>28) |
7573 | #define><31) |
8116 | #define><28) |
7574 | #define>27) |
8117 | #define>29) |
7575 | #define><27) |
8118 | #define><29) |
7576 | #define>28)><28)>29) |
8119 | #define>30) |
7577 | #define><29) |
8120 | #define><30) |
7578 | #define>29) |
8121 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
7579 | #define><29) |
8122 | #define><31) |
7580 | #define>29) |
8123 | #define>23) |
7581 | #define><29) |
8124 | #define><23) |
7582 | #define>29) |
8125 | #define>23) |
7583 | #define><29) |
8126 | #define><23) |
7584 | #define>31) |
8127 | #define>23) |
7585 | #define><31) |
8128 | #define><23) |
7586 | #define>2) |
8129 | #define>23) |
7587 | #define><2) |
8130 | #define><23) |
7588 | #define>10) |
8131 | #define>23) |
7589 | #define><10) |
8132 | #define><23) |
7590 | #define>13) |
8133 | #define>29) |
7591 | #define><13) |
8134 | #define><29) |
7592 | #define>14) |
8135 | #define>29) |
7593 | #define><14) |
8136 | #define><29) |
7594 | #define>16) |
8137 | #define>31) |
7595 | #define><16) |
8138 | #define><31) |
7596 | #define>16) |
8139 | #define>24) |
7597 | #define><16) |
8140 | #define><24) |
7598 | #define>16) |
8141 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
7599 | #define><16) |
8142 | #define><31) |
7600 | #define>16) |
8143 | #define>8)><8)>10) |
7601 | #define><16) |
8144 | #define><10) |
7602 | #define>16) |
8145 | #define>15) |
7603 | #define><16) |
8146 | #define><15) |
7604 | #define>18)><18)>19) |
8147 | #define>16) |
7605 | #define><19) |
8148 | #define><16) |
7606 | #define>20)><20)>22) |
8149 | #define>16) |
7607 | #define><22) |
8150 | #define><16) |
7608 | #define>24) |
8151 | #define>16) |
7609 | #define><24) |
8152 | #define><16) |
7610 | #define>25)><25)>25) |
8153 | #define>16) |
7611 | #define><25) |
8154 | #define><16) |
7612 | #define>25) |
8155 | #define>16) |
7613 | #define><25) |
8156 | #define><16) |
7614 | #define>25) |
8157 | #define>22) |
7615 | #define><25) |
8158 | #define><22) |
7616 | #define>25) |
8159 | #define>23)><23)>26) |
7617 | #define><25) |
8160 | #define><26) |
7618 | #define>25) |
8161 | #define>26) |
7619 | #define><25) |
8162 | #define><26) |
7620 | #define>25) |
8163 | #define>26) |
7621 | #define><25) |
8164 | #define><26) |
7622 | #define>30) |
8165 | #define>26) |
7623 | #define><30) |
8166 | #define><26) |
7624 | #define>31) |
8167 | #define>26) |
7625 | #define><31) |
8168 | #define><26) |
7626 | #define>27) |
8169 | #define>26) |
7627 | #define><27) |
8170 | #define><26) |
7628 | #define>28)><28)>29) |
8171 | #define>26) |
7629 | #define><29) |
8172 | #define><26) |
7630 | #define>29) |
8173 | #define>26) |
7631 | #define><29) |
8174 | #define><26) |
7632 | #define>29) |
8175 | #define>26) |
7633 | #define><29) |
8176 | #define><26) |
7634 | #define>29) |
8177 | #define>30) |
7635 | #define><29) |
8178 | #define><30) |
7636 | #define>31) |
8179 | #define>31) |
7637 | #define><31) |
8180 | #define><31) |
7638 | #define>10) |
8181 | #define>27) |
7639 | #define><10) |
8182 | #define><27) |
7640 | #define>14) |
8183 | #define>28)><28)>29) |
7641 | #define><14) |
8184 | #define><29) |
7642 | #define>2) |
8185 | #define>29) |
7643 | #define><2) |
8186 | #define><29) |
7644 | #define>16) |
8187 | #define>29) |
7645 | #define><16) |
8188 | #define><29) |
7646 | #define>16) |
8189 | #define>29) |
7647 | #define><16) |
8190 | #define><29) |
7648 | #define>16) |
8191 | #define>31) |
7649 | #define><16) |
8192 | #define><31) |
7650 | #define>16) |
8193 | #define>2) |
7651 | #define><16) |
8194 | #define><2) |
7652 | #define>16) |
8195 | #define>10) |
7653 | #define><16) |
8196 | #define><10) |
7654 | #define>20) |
8197 | #define>13) |
7655 | #define><20) |
8198 | #define><13) |
7656 | #define>22) |
8199 | #define>14) |
7657 | #define><22) |
8200 | #define><14) |
7658 | #define>24) |
8201 | #define>15) |
7659 | #define><24) |
8202 | #define><15) |
7660 | #define>25) |
8203 | #define>16) |
7661 | #define><25) |
8204 | #define><16) |
7662 | #define>25) |
8205 | #define>16) |
7663 | #define><25) |
8206 | #define><16) |
7664 | #define>25) |
8207 | #define>16) |
7665 | #define><25) |
8208 | #define><16) |
7666 | #define>25) |
8209 | #define>16) |
7667 | #define><25) |
8210 | #define><16) |
7668 | #define>25) |
8211 | #define>16) |
7669 | #define><25) |
8212 | #define><16) |
7670 | #define>30) |
8213 | #define>18)><18)>19) |
7671 | #define><30) |
8214 | #define><19) |
7672 | #define>31) |
8215 | #define>20)><20)>22) |
7673 | #define><31) |
8216 | #define><22) |
7674 | #define>15) |
8217 | #define>24) |
7675 | #define><15) |
8218 | #define><24) |
7676 | #define>10) |
8219 | #define>25)><25)>25) |
7677 | #define><10) |
8220 | #define><25) |
7678 | #define>14)><14)>18) |
8221 | #define>25) |
7679 | #define><18) |
8222 | #define><25) |
7680 | #define>20) |
8223 | #define>25) |
7681 | #define><20) |
8224 | #define><25) |
7682 | #define>22) |
8225 | #define>25) |
7683 | #define><22) |
8226 | #define><25) |
7684 | #define> |
8227 | #define>25) |
7685 | #define> |
8228 | #define><25) |
7686 | #define> |
8229 | #define>25) |
7687 | #define> |
8230 | #define><25) |
7688 | #define>24) |
8231 | #define>30) |
7689 | #define><24) |
8232 | #define><30) |
7690 | #define>25) |
8233 | #define>31) |
7691 | #define><25) |
8234 | #define><31) |
7692 | #define>26) |
8235 | #define>27) |
7693 | #define><26) |
8236 | #define><27) |
7694 | #define>26) |
8237 | #define>28)><28)>29) |
7695 | #define><26) |
8238 | #define><29) |
7696 | #define>26) |
8239 | #define>29) |
7697 | #define><26) |
8240 | #define><29) |
7698 | #define>26) |
8241 | #define>29) |
7699 | #define><26) |
8242 | #define><29) |
7700 | #define>26) |
8243 | #define>29) |
7701 | #define><26) |
8244 | #define><29) |
7702 | #define>26) |
8245 | #define>31) |
7703 | #define><26) |
8246 | #define><31) |
7704 | #define>26) |
8247 | #define>10) |
7705 | #define><26) |
8248 | #define><10) |
7706 | #define>26) |
8249 | #define>14) |
7707 | #define><26) |
8250 | #define><14) |
7708 | #define>26) |
8251 | #define>2) |
7709 | #define><26) |
8252 | #define><2) |
7710 | #define>26) |
8253 | #define>15) |
7711 | #define><26) |
8254 | #define><15) |
7712 | #define>26) |
8255 | #define>16) |
7713 | #define><26) |
8256 | #define><16) |
7714 | #define>26) |
8257 | #define>16) |
7715 | #define><26) |
8258 | #define><16) |
7716 | #define>26) |
8259 | #define>16) |
7717 | #define><26) |
8260 | #define><16) |
7718 | #define>26) |
8261 | #define>16) |
7719 | #define><26) |
8262 | #define><16) |
7720 | #define>30) |
8263 | #define>16) |
7721 | #define><30) |
8264 | #define><16) |
7722 | #define>31) |
8265 | #define>20) |
7723 | #define><31) |
8266 | #define><20) |
7724 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>24) |
8267 | #define>22) |
7725 | #define><24) |
8268 | #define><22) |
7726 | #define>><>><>><>><>31) |
8269 | #define>24) |
7727 | 8270 | #define><24) |
|
7728 | #define><31) |
8271 | #define>25) |
7729 | 8272 | #define><25) |
|
7730 | #define>31) |
8273 | #define>25) |
7731 | #define><31) |
8274 | #define><25) |
7732 | #define>31) |
8275 | #define>25) |
7733 | #define><31) |
8276 | #define><25) |
7734 | #define>8) |
8277 | #define>25) |
7735 | #define><8) |
8278 | #define><25) |
7736 | #define>20) |
8279 | #define>25) |
7737 | #define><20) |
8280 | #define><25) |
7738 | #define>24) |
8281 | #define>30) |
7739 | #define><24) |
8282 | #define><30) |
7740 | #define>31) |
8283 | #define>31) |
7741 | #define><31) |
8284 | #define><31) |
7742 | #define>8) |
8285 | #define>15) |
7743 | #define><8) |
8286 | #define><15) |
7744 | #define>16) |
8287 | #define>31) |
7745 | #define><16) |
8288 | |
7746 | #define>7) |
8289 | #define><31) |
7747 | #define><7) |
8290 | |
7748 | #define>7) |
8291 | #define>30) |
7749 | #define><7) |
8292 | #define><30) |
7750 | #define>15) |
8293 | #define>30) |
7751 | #define><15) |
8294 | #define><30) |
7752 | #define>15) |
8295 | #define>30) |
7753 | #define><15) |
8296 | #define><30) |
7754 | #define>23) |
8297 | #define>30) |
7755 | #define><23) |
8298 | #define><30) |
7756 | #define>23) |
8299 | #define>8)><8)>10) |
7757 | #define><23) |
8300 | #define><10) |
7758 | #define>31) |
8301 | #define>14)><14)>15) |
7759 | #define><31) |
8302 | #define><15) |
7760 | #define>31) |
8303 | #define>16)><16)>18) |
7761 | #define><31) |
8304 | #define><18) |
7762 | #define>7) |
8305 | #define>20) |
7763 | #define><7) |
8306 | #define><20) |
7764 | #define>7) |
8307 | #define>22) |
7765 | #define><7) |
8308 | #define><22) |
7766 | #define>15) |
8309 | #define> |
7767 | #define><15) |
8310 | #define> |
7768 | #define>15) |
8311 | #define> |
7769 | #define><15) |
8312 | #define> |
7770 | #define>23) |
8313 | #define>24) |
7771 | #define><23) |
8314 | #define><24) |
7772 | #define>23) |
8315 | #define>25) |
7773 | #define><23) |
8316 | #define><25) |
7774 | #define>31) |
8317 | #define>26) |
7775 | #define><31) |
8318 | #define><26) |
7776 | #define>31) |
8319 | #define>26) |
7777 | #define><31) |
8320 | #define><26) |
7778 | #define>7) |
8321 | #define>26) |
7779 | #define><7) |
8322 | #define><26) |
7780 | #define>7) |
8323 | #define>26) |
7781 | #define><7) |
8324 | #define><26) |
7782 | #define>15) |
8325 | #define>26) |
7783 | #define><15) |
8326 | #define><26) |
7784 | #define>15) |
8327 | #define>26) |
7785 | #define><15) |
8328 | #define><26) |
7786 | #define>23) |
8329 | #define>26) |
7787 | #define><23) |
8330 | #define><26) |
7788 | #define>23) |
8331 | #define>26) |
7789 | #define><23) |
8332 | #define><26) |
7790 | #define>31) |
8333 | #define>26) |
7791 | #define><31) |
8334 | #define><26) |
7792 | #define>31) |
8335 | #define>26) |
7793 | #define><31) |
8336 | #define><26) |
7794 | #define>16) |
8337 | #define>26) |
7795 | #define><16) |
8338 | #define><26) |
7796 | #define>24) |
8339 | #define>26) |
7797 | #define><24) |
8340 | #define><26) |
7798 | #define>30) |
8341 | #define>26) |
7799 | #define><30) |
8342 | #define><26) |
7800 | #define>31) |
8343 | #define>26) |
7801 | #define><31) |
8344 | #define><26) |
7802 | #define>8) |
8345 | #define>30) |
7803 | #define><8) |
8346 | #define><30) |
7804 | #define>16) |
8347 | #define>31) |
7805 | #define><16) |
8348 | #define><31) |
7806 | #define>23) |
8349 | #define>><>15) |
7807 | #define><23) |
8350 | #define><15) |
7808 | #define>><>0) |
8351 | #define>><>><>><>><>><>><>><>><>><>><>><>><>24) |
7809 | #define><0) |
8352 | #define><24) |
7810 | #define>1) |
8353 | #define>><>><>><>><>><>31) |
7811 | #define><1) |
8354 | |
7812 | #define>2) |
8355 | #define><31) |
7813 | #define><2) |
8356 | |
7814 | #define>3) |
8357 | #define>31) |
7815 | #define><3) |
8358 | #define><31) |
7816 | #define>4) |
8359 | #define>31) |
7817 | #define><4) |
8360 | #define><31) |
7818 | #define>5) |
8361 | #define>8) |
7819 | #define><5) |
8362 | #define><8) |
7820 | #define>6) |
8363 | #define>20) |
7821 | #define><6) |
8364 | #define><20) |
7822 | #define>7) |
8365 | #define>24) |
7823 | #define><7) |
8366 | #define><24) |
7824 | #define>8) |
8367 | #define>31) |
7825 | #define><8) |
8368 | #define><31) |
7826 | #define>9) |
8369 | #define>8) |
7827 | #define><9) |
8370 | #define><8) |
7828 | #define>10) |
8371 | #define>16) |
7829 | #define><10) |
8372 | #define><16) |
7830 | #define>11) |
8373 | #define>><>7) |
7831 | #define><11) |
8374 | #define><7) |
7832 | #define>16) |
8375 | #define>7) |
7833 | #define><16) |
8376 | #define><7) |
7834 | #define>17) |
8377 | #define>(15+8*(sprite))) |
7835 | #define><17) |
8378 | #define><(15+8*(sprite))) |
7836 | #define>18) |
8379 | #define>(15+8*(sprite))) |
7837 | #define><18) |
8380 | #define><(15+8*(sprite))) |
7838 | #define>19) |
8381 | #define>31) |
7839 | #define><19) |
8382 | #define><31) |
7840 | #define>20) |
8383 | #define>31) |
7841 | #define><20) |
8384 | #define><31) |
7842 | #define>21) |
8385 | #define>0) |
7843 | #define><21) |
8386 | |
7844 | #define>22) |
8387 | /*><0) |
7845 | #define><22) |
8388 | |
7846 | #define>23) |
8389 | /*>4) |
7847 | #define><23) |
8390 | #define><4) |
7848 | #define>24) |
8391 | #define>8) |
7849 | #define><24) |
8392 | #define><8) |
7850 | #define>25) |
8393 | #define>12) |
7851 | #define><25) |
8394 | #define><12) |
7852 | #define>26) |
8395 | #define>16) |
7853 | #define><26) |
8396 | #define><16) |
7854 | #define>27) |
8397 | #define>20) |
7855 | #define><27) |
8398 | #define><20) |
7856 | #define>8) |
8399 | #define>21) |
7857 | 8400 | #define><21) |
|
7858 | #define><8) |
8401 | #define>22) |
7859 | 8402 | #define><22) |
|
7860 | #define>9) |
8403 | #define>23) |
7861 | #define><9) |
8404 | #define><23) |
7862 | #define>10) |
8405 | #define>24) |
7863 | #define><10) |
8406 | #define><24) |
7864 | #define>11) |
8407 | #define>0) |
7865 | #define><11) |
8408 | #define><0) |
7866 | #define>12) |
8409 | #define>4) |
7867 | #define><12) |
8410 | #define><4) |
7868 | #define>13) |
8411 | #define>8) |
7869 | #define><13) |
8412 | #define><8) |
7870 | #define>16) |
8413 | #define>12) |
7871 | #define><16) |
8414 | #define><12) |
7872 | #define>17) |
8415 | #define>16) |
7873 | #define><17) |
8416 | #define><16) |
7874 | #define>18) |
8417 | #define>20) |
7875 | #define><18) |
8418 | #define><20) |
7876 | #define>19) |
8419 | #define>21) |
7877 | #define><19) |
8420 | #define><21) |
7878 | #define>20) |
8421 | #define>22) |
7879 | #define><20) |
8422 | #define><22) |
7880 | #define>21) |
8423 | #define>23) |
7881 | #define><21) |
8424 | #define><23) |
7882 | #define>22) |
8425 | #define>24) |
7883 | #define><22) |
8426 | #define><24) |
7884 | #define>24) |
8427 | #define>0) |
7885 | #define><24) |
8428 | |
7886 | #define>25) |
8429 | /*><0) |
7887 | #define><25) |
8430 | |
7888 | #define>26) |
8431 | /*>16) |
7889 | #define><26) |
8432 | #define><16) |
7890 | #define>27) |
8433 | #define>16) |
7891 | #define><27) |
8434 | #define><16) |
7892 | #define>28) |
8435 | #define>24) |
7893 | #define><28) |
8436 | #define><24) |
7894 | #define>29) |
8437 | #define>0) |
7895 | #define><29) |
8438 | #define><0) |
7896 | #define>2) |
8439 | #define>8) |
7897 | #define><2) |
8440 | #define><8) |
7898 | #define>2) |
8441 | #define>16) |
7899 | #define><2) |
8442 | #define><16) |
7900 | #define>4) |
8443 | #define>24) |
7901 | #define><4) |
8444 | #define><24) |
7902 | #define>5) |
8445 | #define>0) |
7903 | #define><5) |
8446 | #define><0) |
7904 | #define>5) |
8447 | #define>8) |
7905 | #define><5) |
8448 | #define><8) |
7906 | #define>5) |
8449 | #define>16) |
7907 | #define><5) |
8450 | #define><16) |
7908 | #define>5) |
8451 | #define>24) |
7909 | #define><5) |
8452 | #define><24) |
7910 | #define>5) |
8453 | #define>0) |
7911 | #define><5) |
8454 | #define><0) |
7912 | #define>0) |
8455 | #define>0) |
7913 | 8456 | #define><0) |
|
7914 | #define><0) |
8457 | #define>8) |
7915 | 8458 | #define><8) |
|
7916 | #define>0) |
8459 | #define>16) |
7917 | #define><0) |
8460 | #define><16) |
7918 | #define>1) |
8461 | #define>24) |
7919 | #define><1) |
8462 | #define><24) |
7920 | #define>1) |
8463 | #define>0) |
7921 | #define><1) |
8464 | #define><0) |
7922 | #define>2)><2)>2)><2)>3) |
8465 | #define>8) |
7923 | #define><3) |
8466 | #define><8) |
7924 | #define>3) |
8467 | #define>16) |
7925 | #define><3) |
8468 | #define><16) |
7926 | #define>4) |
8469 | #define>0) |
7927 | #define><4) |
8470 | |
7928 | #define>5) |
8471 | /*><0) |
7929 | #define><5) |
8472 | |
7930 | #define>6) |
8473 | /*>16) |
7931 | #define><6) |
8474 | #define><16) |
7932 | #define>6) |
8475 | #define>24) |
7933 | #define><6) |
8476 | #define><24) |
7934 | #define>6) |
8477 | #define>30) |
7935 | #define><6) |
8478 | #define><30) |
7936 | #define>7) |
8479 | #define>31) |
7937 | #define><7) |
8480 | #define><31) |
7938 | #define>8) |
8481 | #define>0)><0)>0)><0)>0)><0)>8) |
7939 | #define><8) |
8482 | #define><8) |
7940 | #define>9) |
8483 | #define>16)><16)>16)><16)>24)><24)>28)><28)>31)><31)>0)><0)>0) |
7941 | #define><9) |
8484 | #define><0) |
7942 | #define>10) |
8485 | #define>8)><8)>8) |
7943 | #define><10) |
8486 | #define><8) |
7944 | #define>10) |
8487 | #define>16) |
7945 | #define><10) |
8488 | #define><16) |
7946 | #define>11) |
8489 | #define>23) |
7947 | #define><11) |
8490 | #define><23) |
7948 | #define>11) |
8491 | #define>><>0) |
7949 | #define><11) |
8492 | #define><0) |
7950 | #define>12) |
8493 | #define>1) |
7951 | #define><12) |
8494 | #define><1) |
7952 | #define>13) |
8495 | #define>2) |
7953 | #define><13) |
8496 | #define><2) |
7954 | #define>14) |
8497 | #define>3) |
7955 | #define><14) |
8498 | #define><3) |
7956 | #define>15) |
8499 | #define>4) |
7957 | #define><15) |
8500 | #define><4) |
7958 | #define>16) |
8501 | #define>5) |
7959 | #define><16) |
8502 | #define><5) |
7960 | #define>16) |
8503 | #define>6) |
7961 | #define><16) |
8504 | #define><6) |
7962 | #define>17) |
8505 | #define>7) |
7963 | #define><17) |
8506 | #define><7) |
7964 | #define>17) |
8507 | #define>8) |
7965 | #define><17) |
8508 | #define><8) |
7966 | #define>18)><18)>18)><18)>19) |
8509 | #define>9) |
7967 | #define><19) |
8510 | #define><9) |
7968 | #define>19) |
8511 | #define>10) |
7969 | #define><19) |
8512 | #define><10) |
7970 | #define>20) |
8513 | #define>11) |
7971 | #define><20) |
8514 | #define><11) |
7972 | #define>21) |
8515 | #define>16) |
7973 | #define><21) |
8516 | #define><16) |
7974 | #define>22) |
8517 | #define>17) |
7975 | #define><22) |
8518 | #define><17) |
7976 | #define>22) |
8519 | #define>18) |
7977 | #define><22) |
8520 | #define><18) |
7978 | #define>23) |
8521 | #define>19) |
7979 | #define><23) |
8522 | #define><19) |
7980 | #define>24) |
8523 | #define>20) |
7981 | #define><24) |
8524 | #define><20) |
7982 | #define>25) |
8525 | #define>21) |
7983 | #define><25) |
8526 | #define><21) |
7984 | #define>26) |
8527 | #define>22) |
7985 | #define><26) |
8528 | #define><22) |
7986 | #define>26) |
8529 | #define>23) |
7987 | #define><26) |
8530 | #define><23) |
7988 | #define>27) |
8531 | #define>24) |
7989 | #define><27) |
8532 | #define><24) |
7990 | #define>27) |
8533 | #define>25) |
7991 | #define><27) |
8534 | #define><25) |
7992 | #define>28) |
8535 | #define>26) |
7993 | #define><28) |
8536 | #define><26) |
7994 | #define>29) |
8537 | #define>27) |
7995 | #define><29) |
8538 | #define><27) |
7996 | #define>30) |
8539 | #define>8) |
7997 | #define><30) |
8540 | |
7998 | #define>31) |
8541 | #define><8) |
7999 | #define><31) |
8542 | |
8000 | #define>2) |
8543 | #define>9) |
8001 | #define><2) |
8544 | #define><9) |
8002 | #define>2) |
8545 | #define>10) |
8003 | #define><2) |
8546 | #define><10) |
8004 | #define>2) |
8547 | #define>11) |
8005 | #define><2) |
8548 | #define><11) |
8006 | #define>2) |
8549 | #define>12) |
8007 | #define><2) |
8550 | #define><12) |
8008 | #define>4) |
8551 | #define>13) |
8009 | #define><4) |
8552 | #define><13) |
8010 | #define>5) |
8553 | #define>16) |
8011 | #define><5) |
8554 | #define><16) |
8012 | #define>5) |
8555 | #define>17) |
8013 | #define><5) |
8556 | #define><17) |
8014 | #define>5) |
8557 | #define>18) |
8015 | #define><5) |
8558 | #define><18) |
8016 | #define>5) |
8559 | #define>19) |
8017 | #define><5) |
8560 | #define><19) |
8018 | #define>><>><>16) |
8561 | #define>20) |
8019 | #define><16) |
8562 | #define><20) |
8020 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>25) |
8563 | #define>21) |
8021 | #define><25) |
8564 | #define><21) |
8022 | #define>24) |
8565 | #define>22) |
8023 | #define><24) |
8566 | #define><22) |
8024 | #define>25) |
8567 | #define>24) |
8025 | #define><25) |
8568 | #define><24) |
8026 | #define>27) |
8569 | #define>25) |
8027 | #define><27) |
8570 | #define><25) |
8028 | #define>29)><29)>30) |
8571 | #define>26) |
8029 | #define><30) |
8572 | #define><26) |
8030 | #define>30) |
8573 | #define>27) |
8031 | #define><30) |
8574 | #define><27) |
8032 | #define>31) |
8575 | #define>28) |
8033 | #define><31) |
8576 | #define><28) |
8034 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>24) |
8577 | #define>29) |
8035 | #define><24) |
8578 | #define><29) |
8036 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>10) |
8579 | #define>2) |
8037 | 8580 | #define><2) |
|
8038 | 8581 | #define>2) |
|
8039 | /*><10) |
8582 | #define><2) |
8040 | 8583 | #define>4) |
|
8041 | 8584 | #define><4) |
|
8042 | /*>10) |
8585 | #define>5) |
8043 | #define><10) |
8586 | #define><5) |
8044 | #define>10) |
8587 | #define>5) |
8045 | #define><10) |
8588 | #define><5) |
8046 | #define>10) |
8589 | #define>5) |
8047 | #define><10) |
8590 | #define><5) |
8048 | #define>10)) |
8591 | #define>5) |
8049 | #define><10)) |
8592 | #define><5) |
8050 | #define>3) |
8593 | #define>5) |
8051 | #define><3) |
8594 | #define><5) |
8052 | #define>4) |
8595 | #define>0) |
8053 | #define><4) |
8596 | |
8054 | #define>11) |
8597 | #define><0) |
8055 | #define><11) |
8598 | |
8056 | #define>10) |
8599 | #define>0) |
8057 | #define><10) |
8600 | #define><0) |
8058 | #define>15) |
8601 | #define>1) |
8059 | #define><15) |
8602 | #define><1) |
8060 | #define>16) |
8603 | #define>1) |
8061 | #define><16) |
8604 | #define><1) |
8062 | #define>17) |
8605 | #define>2)><2)>2)><2)>3) |
8063 | #define><17) |
8606 | #define><3) |
8064 | #define>17) |
8607 | #define>3) |
8065 | #define><17) |
8608 | #define><3) |
8066 | #define>18) |
8609 | #define>4) |
8067 | #define><18) |
8610 | #define><4) |
8068 | #define>18) |
8611 | #define>5) |
8069 | #define><18) |
8612 | #define><5) |
8070 | #define>18) |
8613 | #define>6) |
8071 | #define><18) |
8614 | #define><6) |
8072 | #define>18) |
8615 | #define>6) |
8073 | #define><18) |
8616 | #define><6) |
8074 | #define>20) |
8617 | #define>7) |
8075 | #define><20) |
8618 | #define><7) |
8076 | #define>20) |
8619 | #define>8) |
8077 | #define><20) |
8620 | #define><8) |
8078 | #define>21) |
8621 | #define>9) |
8079 | #define><21) |
8622 | #define><9) |
8080 | #define>21) |
8623 | #define>10) |
8081 | #define><21) |
8624 | #define><10) |
8082 | #define>22) |
8625 | #define>10) |
8083 | #define><22) |
8626 | #define><10) |
8084 | #define>22) |
8627 | #define>11) |
8085 | #define><22) |
8628 | #define><11) |
8086 | #define>23) |
8629 | #define>11) |
8087 | #define><23) |
8630 | #define><11) |
8088 | #define>24) |
8631 | #define>12) |
8089 | #define><24) |
8632 | #define><12) |
8090 | #define>24) |
8633 | #define>13) |
8091 | #define><24) |
8634 | #define><13) |
8092 | #define>24) |
8635 | #define>14) |
8093 | #define><24) |
8636 | #define><14) |
8094 | #define>24) |
8637 | #define>15) |
8095 | #define><24) |
8638 | #define><15) |
8096 | #define>><>30) |
8639 | #define>16) |
8097 | #define><30) |
8640 | #define><16) |
8098 | #define>30) |
8641 | #define>16) |
8099 | #define><30) |
8642 | #define><16) |
8100 | #define>31) |
8643 | #define>17) |
8101 | #define><31) |
8644 | #define><17) |
8102 | #define>25) |
8645 | #define>17) |
8103 | 8646 | #define><17) |
|
8104 | /*><25) |
8647 | #define>18)><18)>18)><18)>19) |
8105 | 8648 | #define><19) |
|
8106 | /*>26) |
8649 | #define>19) |
8107 | #define><26) |
8650 | #define><19) |
8108 | #define>27) |
8651 | #define>20) |
8109 | #define><27) |
8652 | #define><20) |
8110 | #define>4) |
8653 | #define>21) |
8111 | #define><4) |
8654 | #define><21) |
8112 | #define>8) |
8655 | #define>22) |
8113 | #define><8) |
8656 | #define><22) |
8114 | #define>9) |
8657 | #define>22) |
8115 | #define><9) |
8658 | #define><22) |
8116 | #define>12) |
8659 | #define>23) |
8117 | #define><12) |
8660 | #define><23) |
8118 | #define>15) |
8661 | #define>24) |
8119 | #define><15) |
8662 | #define><24) |
8120 | #define>26) |
8663 | #define>25) |
8121 | #define><26) |
8664 | #define><25) |
8122 | #define>26) |
8665 | #define>26) |
8123 | #define><26) |
8666 | #define><26) |
8124 | #define>26) |
8667 | #define>26) |
8125 | #define><26) |
8668 | #define><26) |
8126 | #define>26) |
8669 | #define>27) |
8127 | #define><26) |
8670 | #define><27) |
8128 | #define>29) |
8671 | #define>27) |
8129 | #define><29) |
8672 | #define><27) |
8130 | #define>29) |
8673 | #define>28) |
8131 | #define><29) |
8674 | #define><28) |
8132 | #define>29) |
8675 | #define>29) |
8133 | #define><29) |
8676 | #define><29) |
8134 | #define>29) |
8677 | #define>30) |
8135 | #define><29) |
8678 | #define><30) |
8136 | #define>29) |
8679 | #define>31) |
8137 | #define><29) |
8680 | #define><31) |
8138 | #define>29) |
8681 | #define>2) |
8139 | #define><29) |
8682 | #define><2) |
8140 | #define>29) |
8683 | #define>2) |
8141 | #define><29) |
8684 | #define><2) |
8142 | #define>29) |
8685 | #define>2) |
8143 | #define><29) |
8686 | #define><2) |
8144 | #define>24) |
8687 | #define>2) |
8145 | #define><24) |
8688 | #define><2) |
8146 | #define>4) |
8689 | #define>4) |
8147 | #define><4) |
8690 | #define><4) |
8148 | #define>4) |
8691 | #define>5) |
8149 | #define><4) |
8692 | #define><5) |
8150 | #define>4) |
8693 | #define>5) |
8151 | #define><4) |
8694 | #define><5) |
8152 | #define>4) |
8695 | #define>5) |
8153 | #define><4) |
8696 | #define><5) |
8154 | #define>8) |
8697 | #define>5) |
8155 | #define><8) |
8698 | #define><5) |
8156 | #define>8) |
8699 | #define>><>><>16) |
8157 | #define><8) |
8700 | #define><16) |
8158 | #define>8) |
8701 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>25) |
8159 | #define><8) |
8702 | #define><25) |
8160 | #define>8) |
8703 | #define>24) |
8161 | #define><8) |
8704 | #define><24) |
8162 | #define>11) |
8705 | #define>25) |
8163 | #define><11) |
8706 | #define><25) |
8164 | #define>11) |
8707 | #define>27) |
8165 | #define><11) |
8708 | #define><27) |
8166 | #define>12) |
8709 | #define>29)><29)>30) |
8167 | #define><12) |
8710 | #define><30) |
8168 | #define>25) |
8711 | #define>30) |
8169 | #define><25) |
8712 | #define><30) |
8170 | #define>25) |
8713 | #define>31) |
8171 | #define><25) |
8714 | #define><31) |
8172 | #define>25) |
8715 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>14)) |
8173 | #define><25) |
8716 | |
8174 | #define>25) |
8717 | /*><14)) |
8175 | #define><25) |
8718 | |
8176 | #define>25) |
8719 | /*>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>24) |
8177 | #define><25) |
8720 | #define><24) |
8178 | #define>27) |
8721 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>10) |
8179 | #define><27) |
8722 | |
8180 | #define>27) |
8723 | |
8181 | #define><27) |
8724 | /*><10) |
8182 | #define>30) |
8725 | |
8183 | #define><30) |
8726 | |
8184 | #define>31) |
8727 | /*>10) |
8185 | #define><31) |
8728 | #define><10) |
8186 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>20) |
8729 | #define>10) |
8187 | #define><20) |
8730 | #define><10) |
8188 | #define>0) |
8731 | #define>10) |
8189 | /* |
8732 | #define><10) |
8190 | ><0) |
8733 | #define>10)) |
8191 | /* |
8734 | #define><10)) |
8192 | >><>30) |
8735 | #define>3) |
8193 | #define><30) |
8736 | #define><3) |
8194 | #define>31) |
8737 | #define>4) |
8195 | #define><31) |
8738 | #define><4) |
8196 | #define>0)><0)>2) |
8739 | #define>11) |
8197 | #define><2) |
8740 | #define><11) |
8198 | #define>2)><2)>3)><3)>4) |
8741 | #define>10) |
8199 | #define><4) |
8742 | #define><10) |
8200 | #define>4) |
8743 | #define>15) |
8201 | #define><4) |
8744 | #define><15) |
8202 | #define>4) |
8745 | #define>16) |
8203 | #define><4) |
8746 | #define><16) |
8204 | #define>4) |
8747 | #define>17) |
8205 | #define><4) |
8748 | #define><17) |
8206 | #define>4) |
8749 | #define>17) |
8207 | #define><4) |
8750 | #define><17) |
8208 | #define>7)><7)>9)><9)>10)><10)>11)><11)>12) |
8751 | #define>18) |
8209 | #define><12) |
8752 | #define><18) |
8210 | #define>12) |
8753 | #define>18) |
8211 | #define><12) |
8754 | #define><18) |
8212 | #define>12) |
8755 | #define>18) |
8213 | #define><12) |
8756 | #define><18) |
8214 | #define>12) |
8757 | #define>18) |
8215 | #define><12) |
8758 | #define><18) |
8216 | #define>12) |
8759 | #define>20) |
8217 | #define><12) |
8760 | #define><20) |
8218 | #define>14)><14)>14)><14)>14) |
8761 | #define>20) |
8219 | #define><14) |
8762 | #define><20) |
8220 | #define>14)><14)>14) |
8763 | #define>21) |
8221 | #define><14) |
8764 | #define><21) |
8222 | #define>16)><16)>17)><17)>18)><18)>19)><19)>20) |
8765 | #define>21) |
8223 | #define><20) |
8766 | #define><21) |
8224 | #define>20)><20)>20)><20)>20)><20)>20) |
8767 | #define>22) |
8225 | #define><20) |
8768 | #define><22) |
8226 | #define>20) |
8769 | #define>22) |
8227 | #define><20) |
8770 | #define><22) |
8228 | #define>20) |
8771 | #define>23) |
8229 | #define><20) |
8772 | #define><23) |
8230 | #define>20) |
8773 | #define>24) |
8231 | #define><20) |
8774 | #define><24) |
8232 | #define>20) |
8775 | #define>24) |
8233 | #define><20) |
8776 | #define><24) |
8234 | #define>23)><23)>24)><24)>25)><25)>26)><26)>27)><27)>28)><28)>29) |
8777 | #define>24) |
8235 | #define><29) |
8778 | #define><24) |
8236 | #define>30) |
8779 | #define>24) |
8237 | #define><30) |
8780 | #define><24) |
8238 | #define>31) |
8781 | #define>><>30) |
8239 | #define><31) |
8782 | #define><30) |
8240 | #define>11) |
8783 | #define>30) |
8241 | #define><11) |
8784 | #define><30) |
8242 | #define>12) |
8785 | #define>31) |
8243 | #define><12) |
8786 | #define><31) |
8244 | #define>><>><>><>><>><>><>12) |
8787 | #define>25) |
8245 | #define><12) |
8788 | |
8246 | #define>13) |
8789 | /*><25) |
8247 | #define><13) |
8790 | |
8248 | #define>14) |
8791 | /*>26) |
8249 | #define><14) |
8792 | #define><26) |
8250 | #define>15) |
8793 | #define>27) |
8251 | #define><15) |
8794 | #define><27) |
8252 | #define>31) |
8795 | #define>4) |
8253 | #define><31) |
8796 | #define><4) |
8254 | #define>0) |
8797 | #define>8) |
8255 | #define><0) |
8798 | #define><8) |
8256 | #define>1) |
8799 | #define>9) |
8257 | #define><1) |
8800 | #define><9) |
8258 | #define>2) |
8801 | #define>12) |
8259 | #define><2) |
8802 | #define><12) |
8260 | #define>3) |
8803 | #define>15) |
8261 | #define><3) |
8804 | #define><15) |
8262 | #define>4) |
8805 | #define>26) |
8263 | #define><4) |
8806 | #define><26) |
8264 | #define>5) |
8807 | #define>26) |
8265 | #define><5) |
8808 | #define><26) |
8266 | #define>6) |
8809 | #define>26) |
8267 | #define><6) |
8810 | #define><26) |
8268 | #define>7) |
8811 | #define>26) |
8269 | #define><7) |
8812 | #define><26) |
8270 | #define>0) |
8813 | #define>29) |
8271 | #define><0) |
8814 | #define><29) |
8272 | #define>1) |
8815 | #define>29) |
8273 | #define><1) |
8816 | #define><29) |
8274 | #define>2) |
8817 | #define>29) |
8275 | #define><2) |
8818 | #define><29) |
8276 | #define>3) |
8819 | #define>29) |
8277 | #define><3) |
8820 | #define><29) |
8278 | #define>4) |
8821 | #define>29) |
8279 | #define><4) |
8822 | #define><29) |
8280 | #define>5) |
8823 | #define>29) |
8281 | #define><5) |
8824 | #define><29) |
8282 | #define>6) |
8825 | #define>29) |
8283 | #define><6) |
8826 | #define><29) |
8284 | #define>7) |
8827 | #define>29) |
8285 | #define><7) |
8828 | #define><29) |
8286 | #define>8) |
8829 | #define>4) |
8287 | #define><8) |
8830 | #define><4) |
8288 | #define>7) |
8831 | #define>4) |
8289 | #define><7) |
8832 | #define><4) |
8290 | #define>12)><12)>><>><>><>><>0) |
8833 | #define>4) |
8291 | #define><0) |
8834 | #define><4) |
8292 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>15) |
8835 | #define>4) |
8293 | 8836 | #define><4) |
|
8294 | #define><15) |
8837 | #define>8) |
8295 | 8838 | #define><8) |
|
8296 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
8839 | #define>8) |
8297 | #define><0) |
8840 | #define><8) |
8298 | #define>1) |
8841 | #define>8) |
8299 | #define><1) |
8842 | #define><8) |
8300 | #define>3) |
8843 | #define>8) |
8301 | #define><3) |
8844 | #define><8) |
8302 | #define>6) |
8845 | #define>11) |
8303 | #define><6) |
8846 | #define><11) |
8304 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>30)) |
8847 | #define>11) |
8305 | 8848 | #define><11) |
|
8306 | /* |
8849 | #define>12) |
8307 | ><30)) |
8850 | #define><12) |
8308 | 8851 | #define>25) |
|
8309 | /* |
8852 | #define><25) |
8310 | >31)><31)>><>13) |
8853 | #define>25) |
8311 | #define><13) |
8854 | #define><25) |
8312 | #define>13) |
8855 | #define>25) |
8313 | #define><13) |
8856 | #define><25) |
8314 | #define>14) |
8857 | #define>25) |
8315 | #define><14) |
8858 | #define><25) |
8316 | #define>15) |
8859 | #define>25) |
8317 | #define><15) |
8860 | #define><25) |
8318 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
8861 | #define>27) |
8319 | 8862 | #define><27) |
|
8320 | /* |
8863 | #define>27) |
8321 | ><31) |
8864 | #define><27) |
8322 | 8865 | #define>30) |
|
8323 | /* |
8866 | #define><30) |
8324 | >0) |
8867 | #define>31) |
8325 | #define><0) |
8868 | #define><31) |
8326 | #define>1) |
8869 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>20) |
8327 | #define><1) |
8870 | #define><20) |
8328 | #define>2) |
8871 | #define>0) |
8329 | #define><2) |
8872 | /* |
8330 | #define>3) |
8873 | ><0) |
8331 | #define><3) |
8874 | /* |
8332 | #define>4) |
8875 | >30) |
8333 | #define><4) |
8876 | #define><30) |
8334 | #define>9) |
8877 | #define>31) |
8335 | #define><9) |
8878 | #define><31) |
8336 | #define>10) |
8879 | #define>0)><0)>2) |
8337 | #define><10) |
8880 | #define><2) |
8338 | #define>11) |
8881 | #define>2)><2)>3)><3)>4) |
8339 | #define><11) |
8882 | #define><4) |
8340 | #define>12) |
8883 | #define>4) |
8341 | #define><12) |
8884 | #define><4) |
8342 | #define>13) |
8885 | #define>4) |
8343 | #define><13) |
8886 | #define><4) |
8344 | #define>14) |
8887 | #define>4) |
8345 | #define><14) |
8888 | #define><4) |
8346 | #define>15) |
8889 | #define>4) |
8347 | #define><15) |
8890 | #define><4) |
8348 | #define>0) |
8891 | #define>7)><7)>9)><9)>10)><10)>11)><11)>12) |
8349 | #define><0) |
8892 | #define><12) |
8350 | #define>0) |
8893 | #define>12) |
8351 | #define><0) |
8894 | #define><12) |
8352 | #define>25) |
8895 | #define>12) |
8353 | #define><25) |
8896 | #define><12) |
8354 | #define>25) |
8897 | #define>12) |
8355 | #define><25) |
8898 | #define><12) |
8356 | #define>25) |
8899 | #define>12) |
8357 | #define><25) |
8900 | #define><12) |
8358 | #define>25) |
8901 | #define>14)><14)>14)><14)>14) |
8359 | #define><25) |
8902 | #define><14) |
8360 | #define>29)><29)>30) |
8903 | #define>14)><14)>14) |
8361 | #define><30) |
8904 | #define><14) |
8362 | #define>31) |
8905 | #define>16)><16)>17)><17)>18)><18)>19)><19)>20) |
8363 | #define><31) |
8906 | #define><20) |
8364 | #define>7)><7)>8)><8)>8)><8)>8) |
8907 | #define>20)><20)>20)><20)>20)><20)>20) |
8365 | #define><8) |
8908 | #define><20) |
8366 | #define>8) |
8909 | #define>20) |
8367 | #define><8) |
8910 | #define><20) |
8368 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>1) |
8911 | #define>20) |
8369 | 8912 | #define><20) |
|
8370 | /* |
8913 | #define>20) |
8371 | ><1) |
8914 | #define><20) |
8372 | 8915 | #define>20) |
|
8373 | /* |
8916 | #define><20) |
8374 | >2) |
8917 | #define>23)><23)>24)><24)>25)><25)>26)><26)>27)><27)>28)><28)>29) |
8375 | #define><2) |
8918 | #define><29) |
8376 | #define>><>29) |
8919 | #define>30) |
8377 | #define><29) |
8920 | #define><30) |
8378 | #define>21) |
8921 | #define>31) |
8379 | 8922 | #define><31) |
|
8380 | 8923 | #define>11) |
|
8381 | /* |
8924 | #define><11) |
8382 | ><21) |
8925 | #define>12) |
8383 | 8926 | #define><12) |
|
8384 | 8927 | #define>><>><>><>><>><>><>12) |
|
8385 | /* |
8928 | #define><12) |
8386 | >22) |
8929 | #define>13) |
8387 | #define><22) |
8930 | #define><13) |
8388 | #define>1) |
8931 | #define>14) |
8389 | 8932 | #define><14) |
|
8390 | #define><1) |
8933 | #define>15) |
8391 | 8934 | #define><15) |
|
8392 | #define>0) |
8935 | #define>31) |
8393 | #define><0) |
8936 | #define><31) |
8394 | #define>31) |
8937 | #define>0) |
8395 | 8938 | #define><0) |
|
8396 | /*><31) |
8939 | #define>1) |
8397 | 8940 | #define><1) |
|
8398 | /*>27) |
8941 | #define>2) |
8399 | #define><27) |
8942 | #define><2) |
8400 | #define>6) |
8943 | #define>3) |
8401 | #define><6) |
8944 | #define><3) |
8402 | #define>6) |
8945 | #define>4) |
8403 | #define><6) |
8946 | #define><4) |
8404 | #define>6) |
8947 | #define>5) |
8405 | #define><6) |
8948 | #define><5) |
8406 | #define>10) |
8949 | #define>6) |
8407 | #define><10) |
8950 | #define><6) |
8408 | #define>25) |
8951 | #define>7) |
8409 | #define><25) |
8952 | #define><7) |
8410 | #define>28) |
8953 | #define>0) |
8411 | #define><28) |
8954 | #define><0) |
8412 | #define>29) |
8955 | #define>1) |
8413 | #define><29) |
8956 | #define><1) |
8414 | #define>29) |
8957 | #define>2) |
8415 | #define><29) |
8958 | #define><2) |
8416 | #define>30) |
8959 | #define>3) |
8417 | #define><30) |
8960 | #define><3) |
8418 | #define>31) |
8961 | #define>4) |
8419 | #define><31) |
8962 | #define><4) |
8420 | #define>0) |
8963 | #define>5) |
8421 | #define><0) |
8964 | #define><5) |
8422 | #define>1) |
8965 | #define>6) |
8423 | #define><1) |
8966 | #define><6) |
8424 | #define>2) |
8967 | #define>7) |
8425 | #define><2) |
8968 | #define><7) |
8426 | #define>2) |
8969 | #define>8) |
8427 | #define><2) |
8970 | #define><8) |
8428 | #define>2) |
8971 | #define>7) |
8429 | #define><2) |
8972 | #define><7) |
8430 | #define>2) |
8973 | #define>12)><12)>><>><>><>><>0) |
8431 | #define><2) |
8974 | #define><0) |
8432 | #define>4) |
8975 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>15) |
8433 | #define><4) |
8976 | |
8434 | #define>29) |
8977 | #define><15) |
8435 | #define><29) |
8978 | |
8436 | #define>30) |
8979 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
8437 | #define><30) |
8980 | #define><0) |
8438 | #define>31) |
8981 | #define>1) |
8439 | #define><31) |
8982 | #define><1) |
8440 | #define>0) |
8983 | #define>3) |
8441 | #define><0) |
8984 | #define><3) |
8442 | #define>13) |
8985 | #define>6) |
8443 | #define><13) |
8986 | #define><6) |
8444 | #define>14) |
8987 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>30)) |
8445 | #define><14) |
8988 | |
8446 | #define>30) |
8989 | /* |
8447 | #define><30) |
8990 | ><30)) |
8448 | #define>31) |
8991 | |
8449 | #define><31) |
8992 | /* |
8450 | #define>4) |
8993 | >31)><31)>><>><>13) |
8451 | 8994 | #define><13) |
|
8452 | /* |
8995 | #define>13) |
8453 | ><4) |
8996 | #define><13) |
8454 | 8997 | #define>14) |
|
8455 | /* |
8998 | #define><14) |
8456 | >4)><4)>4) |
8999 | #define>15) |
8457 | #define><4) |
9000 | #define><15) |
8458 | #define>4) |
9001 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
8459 | #define><4) |
9002 | |
8460 | #define>12) |
9003 | /* |
8461 | #define><12) |
9004 | ><31) |
8462 | #define>12)><12)>12) |
9005 | |
8463 | #define><12) |
9006 | /* |
8464 | #define>12) |
9007 | >0) |
8465 | #define><12) |
9008 | #define><0) |
8466 | #define>><>16)><16)>16) |
9009 | #define>1) |
8467 | #define><16) |
9010 | #define><1) |
8468 | #define>16) |
9011 | #define>2) |
8469 | #define><16) |
9012 | #define><2) |
8470 | #define>16) |
9013 | #define>3) |
8471 | #define><16) |
9014 | #define><3) |
8472 | #define>><>25) |
9015 | #define>4) |
8473 | 9016 | #define><4) |
|
8474 | #define><25) |
9017 | #define>9) |
8475 | 9018 | #define><9) |
|
8476 | #define>0) |
9019 | #define>10) |
8477 | #define><0) |
9020 | #define><10) |
8478 | #define>1) |
9021 | #define>11) |
8479 | #define><1) |
9022 | #define><11) |
8480 | #define>1) |
9023 | #define>12) |
8481 | #define><1) |
9024 | #define><12) |
8482 | #define>2) |
9025 | #define>13) |
8483 | #define><2) |
9026 | #define><13) |
8484 | #define>2) |
9027 | #define>14) |
8485 | #define><2) |
9028 | #define><14) |
8486 | #define>3) |
9029 | #define>15) |
8487 | #define><3) |
9030 | #define><15) |
8488 | #define>4) |
9031 | #define>0) |
8489 | #define><4) |
9032 | #define><0) |
8490 | #define>5) |
9033 | #define>0) |
8491 | #define><5) |
9034 | #define><0) |
8492 | #define>6) |
9035 | #define>25) |
8493 | #define><6) |
9036 | #define><25) |
8494 | #define>7) |
9037 | #define>25) |
8495 | #define><7) |
9038 | #define><25) |
8496 | #define>8) |
9039 | #define>25) |
8497 | #define><8) |
9040 | #define><25) |
8498 | #define>8) |
9041 | #define>25) |
8499 | #define><8) |
9042 | #define><25) |
8500 | #define>9) |
9043 | #define>29)><29)>30) |
8501 | #define><9) |
9044 | #define><30) |
8502 | #define>9) |
9045 | #define>31) |
8503 | #define><9) |
9046 | #define><31) |
8504 | #define>10) |
9047 | #define>7)><7)>8)><8)>8)><8)>8) |
8505 | #define><10) |
9048 | #define><8) |
8506 | #define>10) |
9049 | #define>8) |
8507 | #define><10) |
9050 | #define><8) |
8508 | #define>11) |
9051 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>1) |
8509 | #define><11) |
9052 | |
8510 | #define>11) |
9053 | /* |
8511 | #define><11) |
9054 | ><1) |
8512 | #define>12) |
9055 | |
8513 | #define><12) |
9056 | /* |
8514 | #define>12) |
9057 | >2) |
8515 | #define><12) |
9058 | #define><2) |
8516 | #define>13) |
9059 | #define>><>29) |
8517 | #define><13) |
9060 | #define><29) |
8518 | #define>13) |
9061 | #define>21) |
8519 | #define><13) |
9062 | |
8520 | #define>14)><14)>14) |
9063 | |
8521 | #define><14) |
9064 | /* |
8522 | #define>15) |
9065 | ><21) |
8523 | #define><15) |
9066 | |
8524 | #define>15) |
9067 | |
8525 | #define><15) |
9068 | /* |
8526 | #define>16) |
9069 | >22) |
8527 | #define><16) |
9070 | #define><22) |
8528 | #define>17) |
9071 | #define>1) |
8529 | #define><17) |
9072 | |
8530 | #define>18) |
9073 | #define><1) |
8531 | #define><18) |
9074 | |
8532 | #define>18) |
9075 | #define>0) |
8533 | #define><18) |
9076 | #define><0) |
8534 | #define>19) |
9077 | #define>10) |
8535 | #define><19) |
9078 | /*><10) |
8536 | #define>20) |
9079 | /*>31) |
8537 | #define><20) |
9080 | |
8538 | #define>21) |
9081 | /*><31) |
8539 | #define><21) |
9082 | |
8540 | #define>22) |
9083 | /*>27) |
8541 | #define><22) |
9084 | #define><27) |
8542 | #define>31) |
9085 | #define>6) |
8543 | #define><31) |
9086 | #define><6) |
8544 | #define>5) |
9087 | #define>6) |
8545 | 9088 | #define><6) |
|
8546 | #define><5) |
9089 | #define>6) |
8547 | 9090 | #define><6) |
|
8548 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>10) |
9091 | #define>10) |
8549 | 9092 | #define><10) |
|
8550 | #define><10) |
9093 | #define>25) |
8551 | 9094 | #define><25) |
|
8552 | #define>><>3) |
9095 | #define>28) |
8553 | 9096 | #define><28) |
|
8554 | #define><3) |
9097 | #define>29) |
8555 | 9098 | #define><29) |
|
8556 | #define>6) |
9099 | #define>29) |
8557 | 9100 | #define><29) |
|
8558 | #define><6) |
9101 | #define>30) |
8559 | 9102 | #define><30) |
|
8560 | #define>6) |
9103 | #define>31) |
8561 | #define><6) |
9104 | #define><31) |
8562 | #define>2) |
9105 | #define>0) |
8563 | #define><2) |
9106 | #define><0) |
8564 | #define>0) |
9107 | #define>1) |
8565 | #define><0) |
9108 | #define><1) |
8566 | #define>0) |
9109 | #define>2) |
8567 | 9110 | #define><2) |
|
8568 | #define><0) |
9111 | #define>2) |
8569 | 9112 | #define><2) |
|
8570 | #define>3) |
9113 | #define>2) |
8571 | #define><3) |
9114 | #define><2) |
8572 | #define>0) |
9115 | #define>2) |
8573 | #define><0) |
9116 | #define><2) |
8574 | #define>0) |
9117 | #define>4) |
8575 | #define><0) |
9118 | #define><4) |
8576 | #define>1) |
9119 | #define>29) |
8577 | #define><1) |
9120 | #define><29) |
8578 | #define>3) |
9121 | #define>30) |
8579 | #define><3) |
9122 | #define><30) |
8580 | #define>4) |
9123 | #define>31) |
8581 | #define><4) |
9124 | #define><31) |
8582 | #define>5) |
9125 | #define>0) |
8583 | #define><5) |
9126 | #define><0) |
8584 | #define>5) |
9127 | #define>13) |
8585 | #define><5) |
9128 | #define><13) |
8586 | #define>6) |
9129 | #define>14) |
8587 | #define><6) |
9130 | #define><14) |
8588 | #define>8) |
9131 | #define>30) |
8589 | #define><8) |
9132 | #define><30) |
8590 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>15)><15)>16)><16)>31) |
9133 | #define>31) |
8591 | #define><31) |
9134 | #define><31) |
8592 | #define>5) |
9135 | #define>4) |
8593 | #define><5) |
9136 | |
8594 | #define>9) |
9137 | /* |
8595 | #define><9) |
9138 | ><4) |
8596 | #define>7)><7)>11)><11)>12)><12)>0) |
9139 | |
8597 | #define><0) |
9140 | /* |
8598 | #define>1) |
9141 | >4)><4)>4) |
8599 | #define><1) |
9142 | #define><4) |
8600 | #define>3) |
9143 | #define>4) |
8601 | #define><3) |
9144 | #define><4) |
8602 | #define>4) |
9145 | #define>12) |
8603 | #define><4) |
9146 | #define><12) |
8604 | #define>4) |
9147 | #define>12)><12)>12) |
8605 | #define><4) |
9148 | #define><12) |
8606 | #define>5) |
9149 | #define>12) |
8607 | #define><5) |
9150 | #define><12) |
8608 | #define>(11-(plane)))><(11-(plane)))>8) |
9151 | #define>><>16)><16)>16) |
8609 | #define><8) |
9152 | #define><16) |
8610 | #define>22) |
9153 | #define>16) |
8611 | #define><22) |
9154 | #define><16) |
8612 | #define>9) |
9155 | #define>16) |
8613 | 9156 | #define><16) |
|
8614 | #define><9) |
9157 | #define>><>25) |
8615 | 9158 | ||
8616 | #define>10) |
9159 | #define><25) |
8617 | #define><10) |
9160 | |
8618 | #define>11) |
9161 | #define>0) |
8619 | #define><11) |
9162 | #define><0) |
8620 | #define>12) |
9163 | #define>1) |
8621 | #define><12) |
9164 | #define><1) |
8622 | #define>13) |
9165 | #define>1) |
8623 | #define><13) |
9166 | #define><1) |
8624 | #define>15) |
9167 | #define>2) |
8625 | #define><15) |
9168 | #define><2) |
8626 | #define>><>><>><>><>><>><>><>><>><>><>1)><1)>><>><>><>><>22) |
9169 | #define>2) |
8627 | 9170 | #define><2) |
|
8628 | 9171 | #define>3) |
|
8629 | /*><22) |
9172 | #define><3) |
8630 | 9173 | #define>4) |
|
8631 | 9174 | #define><4) |
|
8632 | /*>21) |
9175 | #define>5) |
8633 | #define><21) |
9176 | #define><5) |
8634 | #define>20) |
9177 | #define>6) |
8635 | #define><20) |
9178 | #define><6) |
8636 | #define>15) |
9179 | #define>7) |
8637 | #define><15) |
9180 | #define><7) |
8638 | #define>14) |
9181 | #define>8) |
8639 | #define><14) |
9182 | #define><8) |
8640 | #define>13) |
9183 | #define>8) |
8641 | /*><13) |
9184 | #define><8) |
8642 | /*>11) |
9185 | #define>9) |
8643 | #define><11) |
9186 | #define><9) |
8644 | #define>10) |
9187 | #define>9) |
8645 | #define><10) |
9188 | #define><9) |
8646 | #define>9) |
9189 | #define>10) |
8647 | #define><9) |
9190 | #define><10) |
8648 | #define>8) |
9191 | #define>10) |
8649 | #define><8) |
9192 | #define><10) |
8650 | #define>5) |
9193 | #define>11) |
8651 | #define><5) |
9194 | #define><11) |
8652 | #define>3) |
9195 | #define>11) |
8653 | #define><3) |
9196 | #define><11) |
8654 | #define>2) |
9197 | #define>12) |
8655 | #define><2) |
9198 | #define><12) |
8656 | #define>1) |
9199 | #define>12) |
8657 | #define><1) |
9200 | #define><12) |
8658 | #define>0) |
9201 | #define>13) |
8659 | #define><0) |
9202 | #define><13) |
8660 | #define>31) |
9203 | #define>13) |
8661 | 9204 | #define><13) |
|
8662 | #define><31) |
9205 | #define>14)><14)>14) |
8663 | 9206 | #define><14) |
|
8664 | #define>(pipe*3)) |
9207 | #define>15) |
8665 | 9208 | #define><15) |
|
8666 | #define><(pipe*3)) |
9209 | #define>15) |
8667 | 9210 | #define><15) |
|
8668 | #define>0) |
9211 | #define>16) |
8669 | #define><0) |
9212 | #define><16) |
8670 | #define>(2><(2>2) |
9213 | #define>17) |
8671 | #define><2) |
9214 | #define><17) |
8672 | #define>3) |
9215 | #define>18) |
8673 | #define><3) |
9216 | #define><18) |
8674 | #define>5) |
9217 | #define>18) |
8675 | #define><5) |
9218 | #define><18) |
8676 | #define>6) |
9219 | #define>19) |
8677 | #define><6) |
9220 | #define><19) |
8678 | #define>8) |
9221 | #define>20) |
8679 | #define><8) |
9222 | #define><20) |
8680 | #define>13) |
9223 | #define>21) |
8681 | #define><13) |
9224 | #define><21) |
8682 | #define>31) |
9225 | #define>22) |
8683 | #define><31) |
9226 | #define><22) |
8684 | #define>0) |
9227 | #define>31) |
8685 | #define><0) |
9228 | #define><31) |
8686 | #define>10)><10)>11)><11)>0)><0)>0) |
9229 | #define>5) |
8687 | #define><0) |
9230 | |
8688 | #define>11) |
9231 | #define><5) |
8689 | #define><11) |
9232 | |
8690 | #define>1) |
9233 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>10) |
8691 | #define><1) |
9234 | |
8692 | #define>9) |
9235 | #define><10) |
8693 | #define><9) |
9236 | |
8694 | #define>5) |
9237 | #define>><>><>3) |
8695 | #define><5) |
9238 | |
8696 | #define>4) |
9239 | #define><3) |
8697 | #define><4) |
9240 | |
8698 | #define>><>><>><>0) |
9241 | #define>6) |
8699 | #define><0) |
9242 | |
8700 | #define>><>8) |
9243 | #define><6) |
8701 | 9244 | ||
8702 | #define><8) |
9245 | #define>6) |
8703 | 9246 | #define><6) |
|
8704 | #define>0) |
9247 | #define>2) |
8705 | #define><0) |
9248 | #define><2) |
8706 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
9249 | #define>0) |
8707 | #define><31) |
9250 | #define><0) |
8708 | #define>><>27) |
9251 | #define>0) |
8709 | #define><27) |
9252 | |
8710 | #define>><>31) |
9253 | #define><0) |
8711 | #define><31) |
9254 | |
8712 | #define>30) |
9255 | #define>3) |
8713 | #define><30) |
9256 | #define><3) |
8714 | #define>><>><>5) |
9257 | #define>0) |
8715 | #define><5) |
9258 | #define><0) |
8716 | #define>21) |
9259 | #define>0) |
8717 | #define><21) |
9260 | #define><0) |
8718 | #define>22) |
9261 | #define>1) |
8719 | #define><22) |
9262 | #define><1) |
8720 | #define>23) |
9263 | #define>3) |
8721 | #define><23) |
9264 | #define><3) |
8722 | #define>7) |
9265 | #define>4) |
8723 | #define><7) |
9266 | #define><4) |
8724 | #define>16) |
9267 | #define>5) |
8725 | #define><16) |
9268 | #define><5) |
8726 | #define>11) |
9269 | #define>5) |
8727 | #define><11) |
9270 | #define><5) |
8728 | #define>0) |
9271 | #define>6) |
8729 | 9272 | #define><6) |
|
8730 | #define><0) |
9273 | #define>8) |
8731 | 9274 | #define><8) |
|
8732 | #define>1) |
9275 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>15)><15)>16)><16)>31) |
8733 | #define><1) |
9276 | #define><31) |
8734 | #define>2)><2)>3)><3)>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
9277 | #define>2)><2)>2)><2)>3)><3)>5) |
8735 | #define><0) |
9278 | #define><5) |
8736 | #define>><>><>><>><>><>><>><>0) |
9279 | #define>9) |
8737 | #define><0) |
9280 | #define><9) |
8738 | #define>9) |
9281 | #define>7)><7)>11)><11)>12)><12)>0) |
8739 | 9282 | #define><0) |
|
8740 | /* |
9283 | #define>1) |
8741 | ><9) |
9284 | #define><1) |
8742 | 9285 | #define>3) |
|
8743 | /* |
9286 | #define><3) |
8744 | >8) |
9287 | #define>4) |
8745 | #define><8) |
9288 | #define><4) |
8746 | #define>7) |
9289 | #define>4) |
8747 | #define><7) |
9290 | #define><4) |
8748 | #define>22)) |
9291 | #define>5) |
8749 | 9292 | #define><5) |
|
8750 | /* |
9293 | #define>(11-(plane)))><(11-(plane)))>8) |
8751 | ><22)) |
9294 | #define><8) |
8752 | 9295 | #define>22) |
|
8753 | /* |
9296 | #define><22) |
8754 | >29)|(0x43<<22)) |
9297 | #define>9) |
8755 | 9298 | ||
8756 | /* |
9299 | #define><9) |
8757 | ><29)|(0x43<<22)) |
9300 | |
8758 | 9301 | #define>10) |
|
8759 | /* |
9302 | #define><10) |
8760 | >22)) |
9303 | #define>11) |
8761 | #define><22)) |
9304 | #define><11) |
8762 | #define>29)|(0x40<<22)) |
9305 | #define>12) |
8763 | #define><29)|(0x40<<22)) |
9306 | #define><12) |
8764 | #define>16)) |
9307 | #define>13) |
8765 | 9308 | #define><13) |
|
8766 | #define><16)) |
9309 | #define>15) |
8767 | 9310 | #define><15) |
|
8768 | #define>27)|(0x0<<16)) |
9311 | #define>><>><>><>><>><>><>><>><>><>1)><1)>><>><>><>><>22) |
8769 | 9312 | ||
8770 | #define><27)|(0x0<<16)) |
9313 | |
8771 | 9314 | /*><22) |
|
8772 | #define>29)|(0x1<<27)|(0x0<<16)) |
9315 | |
8773 | 9316 | ||
8774 | #define><29)|(0x1<<27)|(0x0<<16)) |
9317 | /*>21) |
8775 | 9318 | #define><21) |
|
8776 | #define>16)) |
9319 | #define>20) |
8777 | 9320 | #define><20) |
|
8778 | #define><16)) |
9321 | #define>15) |
8779 | 9322 | #define><15) |
|
8780 | #define>24)|(0x47<<16)) |
9323 | #define>14) |
8781 | 9324 | #define><14) |
|
8782 | #define><24)|(0x47<<16)) |
9325 | #define>13) |
8783 | 9326 | /*><13) |
|
8784 | #define>27)|(0x0<<24)|(0x47<<16)) |
9327 | /*>11) |
8785 | 9328 | #define><11) |
|
8786 | #define><27)|(0x0<<24)|(0x47<<16)) |
9329 | #define>10) |
8787 | 9330 | #define><10) |
|
8788 | #define>29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
9331 | #define>9) |
8789 | 9332 | #define><9) |
|
8790 | #define><29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
9333 | #define>8) |
8791 | 9334 | #define><8) |
|
8792 | #define>16)) |
9335 | #define>5) |
8793 | #define><16)) |
9336 | #define><5) |
8794 | #define>24)|(0x46<<16)) |
9337 | #define>3) |
8795 | #define><24)|(0x46<<16)) |
9338 | #define><3) |
8796 | #define>27)|(0x0<<24)|(0x46<<16)) |
9339 | #define>2) |
8797 | #define><27)|(0x0<<24)|(0x46<<16)) |
9340 | #define><2) |
8798 | #define>29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
9341 | #define>1) |
8799 | #define><29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
9342 | #define><1) |
8800 | #define>16)) |
9343 | #define>0) |
8801 | #define><16)) |
9344 | #define><0) |
8802 | #define>24)|(0x45<<16)) |
9345 | #define>31) |
8803 | #define><24)|(0x45<<16)) |
9346 | |
8804 | #define>27)|(0x0<<24)|(0x45<<16)) |
9347 | #define><31) |
8805 | #define><27)|(0x0<<24)|(0x45<<16)) |
9348 | |
8806 | #define>29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
9349 | #define>(pipe*3)) |
8807 | #define><29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
9350 | |
8808 | #define>16)) |
9351 | #define><(pipe*3)) |
8809 | #define><16)) |
9352 | |
8810 | #define>24)|(0x44<<16)) |
9353 | #define>0) |
8811 | #define><24)|(0x44<<16)) |
9354 | #define><0) |
8812 | #define>27)|(0x0<<24)|(0x44<<16)) |
9355 | #define>(2><(2>2) |
8813 | #define><27)|(0x0<<24)|(0x44<<16)) |
9356 | #define><2) |
8814 | #define>29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
9357 | #define>3) |
8815 | #define><29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
9358 | #define><3) |
8816 | #define>16)) |
9359 | #define>5) |
8817 | #define><16)) |
9360 | #define><5) |
8818 | #define>24)|(0x43<<16)) |
9361 | #define>6) |
8819 | #define><24)|(0x43<<16)) |
9362 | #define><6) |
8820 | #define>27)|(0x0<<24)|(0x43<<16)) |
9363 | #define>8) |
8821 | #define><27)|(0x0<<24)|(0x43<<16)) |
9364 | #define><8) |
8822 | #define>29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
9365 | #define>13) |
8823 | #define><29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
9366 | #define><13) |
8824 | #define>16)) |
9367 | #define>31) |
8825 | 9368 | #define><31) |
|
8826 | #define><16)) |
9369 | #define>0) |
8827 | 9370 | #define><0) |
|
8828 | #define>24)|(0x17<<16)) |
9371 | #define>10)><10)>11)><11)>0)><0)>0) |
8829 | 9372 | #define><0) |
|
8830 | #define><24)|(0x17<<16)) |
9373 | #define>11) |
8831 | 9374 | #define><11) |
|
8832 | #define>27)|(0x1<<24)|(0x17<<16)) |
9375 | #define>1) |
8833 | 9376 | #define><1) |
|
8834 | #define><27)|(0x1<<24)|(0x17<<16)) |
9377 | #define>9) |
8835 | 9378 | #define><9) |
|
8836 | #define>29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
9379 | #define>5) |
8837 | 9380 | #define><5) |
|
8838 | #define><29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
9381 | #define>4) |
8839 | 9382 | #define><4) |
|
8840 | #define>16)) |
9383 | #define>><>><>><>0) |
8841 | #define><16)) |
9384 | #define><0) |
8842 | #define>24)|(0x3A<<16)) |
9385 | #define>><>8) |
8843 | #define><24)|(0x3A<<16)) |
9386 | |
8844 | #define>27)|(0x0<<24)|(0x3A<<16)) |
9387 | #define><8) |
8845 | #define><27)|(0x0<<24)|(0x3A<<16)) |
9388 | |
8846 | #define>29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
9389 | #define>0) |
8847 | #define><29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
9390 | #define><0) |
8848 | #define>16)) |
9391 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>31) |
8849 | #define><16)) |
9392 | #define><31) |
8850 | #define>24)|(0x39<<16)) |
9393 | #define>><>><>><>27) |
8851 | #define><24)|(0x39<<16)) |
9394 | #define><27) |
8852 | #define>27)|(0x0<<24)|(0x39<<16)) |
9395 | #define>><>0) |
8853 | #define><27)|(0x0<<24)|(0x39<<16)) |
9396 | #define><0) |
8854 | #define>29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
9397 | #define>1) |
8855 | #define><29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
9398 | #define><1) |
8856 | #define>16)) |
9399 | #define>3) |
8857 | #define><16)) |
9400 | #define><3) |
8858 | #define>24)|(0x5<<16)) |
9401 | #define>16) |
8859 | #define><24)|(0x5<<16)) |
9402 | #define><16) |
8860 | #define>27)|(0x1<<24)|(0x5<<16)) |
9403 | #define>16) |
8861 | #define><27)|(0x1<<24)|(0x5<<16)) |
9404 | #define><16) |
8862 | #define>29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
9405 | #define>16) |
8863 | #define><29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
9406 | #define><16) |
8864 | #define>16)) |
9407 | #define>24) |
8865 | #define><16)) |
9408 | #define><24) |
8866 | #define>24)|(0x4<<16)) |
9409 | #define>24) |
8867 | #define><24)|(0x4<<16)) |
9410 | #define><24) |
8868 | #define>27)|(0x1<<24)|(0x4<<16)) |
9411 | #define>24) |
8869 | #define><27)|(0x1<<24)|(0x4<<16)) |
9412 | #define><24) |
8870 | #define>29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
9413 | #define>31) |
8871 | #define><29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
9414 | #define><31) |
8872 | #define>16)) |
9415 | #define>30) |
8873 | #define><16)) |
9416 | #define><30) |
8874 | #define>24)|(0x0<<16)) |
9417 | #define>10) |
8875 | #define><24)|(0x0<<16)) |
9418 | #define><10) |
8876 | #define>27)|(0x0<<24)|(0x0<<16)) |
9419 | #define>10) |
8877 | #define><27)|(0x0<<24)|(0x0<<16)) |
9420 | #define><10) |
8878 | #define>29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
9421 | #define>10) |
8879 | #define><29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
9422 | #define><10) |
8880 | #define>16)) |
9423 | #define>13) |
8881 | #define><16)) |
9424 | #define><13) |
8882 | #define>24)|(0xB<<16)) |
9425 | #define>13) |
8883 | #define><24)|(0xB<<16)) |
9426 | #define><13) |
8884 | #define>27)|(0x0<<24)|(0xB<<16)) |
9427 | #define>13) |
8885 | #define><27)|(0x0<<24)|(0xB<<16)) |
9428 | #define><13) |
8886 | #define>29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
9429 | #define>><>><>5) |
8887 | #define><29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
9430 | #define><5) |
8888 | #define>16)) |
9431 | #define>21) |
8889 | #define><16)) |
9432 | #define><21) |
8890 | #define>24)|(0x4<<16)) |
9433 | #define>22) |
8891 | #define><24)|(0x4<<16)) |
9434 | #define><22) |
8892 | #define>27)|(0x1<<24)|(0x4<<16)) |
9435 | #define>23) |
8893 | #define><27)|(0x1<<24)|(0x4<<16)) |
9436 | #define><23) |
8894 | #define>29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
9437 | #define>3) |
8895 | #define><29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
9438 | #define><3) |
8896 | #define>0) |
9439 | #define>4) |
8897 | #define><0) |
9440 | #define><4) |
8898 | #define>2)><2)>0) |
9441 | #define>7) |
8899 | #define><0) |
9442 | #define><7) |
8900 | #define>1) |
9443 | #define>16) |
8901 | #define><1) |
9444 | #define><16) |
8902 | #define>2) |
9445 | #define>11) |
8903 | #define><2) |
9446 | #define><11) |
8904 | #define>3) |
9447 | #define>0) |
8905 | #define><3) |
9448 | |
8906 | #define>4) |
9449 | #define><0) |
8907 | #define><4) |
9450 | |
8908 | #define>7)><7)>8) |
9451 | #define>1) |
8909 | #define><8) |
9452 | #define><1) |
8910 | #define>9) |
9453 | #define>2)><2)>3)><3)>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>0) |
8911 | #define><9) |
9454 | #define><0) |
8912 | #define>10)><10)>11)><11)>12)><12)>12) |
9455 | #define>4) |
8913 | #define><12) |
9456 | #define><4) |
8914 | #define>13) |
9457 | #define>><>><>><>><>><>><>><>><>><>><>><>0) |
8915 | #define><13) |
9458 | #define><0) |
8916 | #define>14) |
9459 | #define>9) |
8917 | #define><14) |
9460 | |
8918 | #define>14) |
9461 | /* |
8919 | #define><14) |
9462 | ><9) |
8920 | #define>18) |
9463 | |
8921 | #define><18) |
9464 | /* |
8922 | #define>20) |
9465 | >8) |
8923 | #define><20) |
9466 | #define><8) |
8924 | #define>21) |
9467 | #define>7) |
8925 | #define><21) |
9468 | #define><7) |
8926 | #define>23) |
9469 | #define>22)) |
8927 | #define><23) |
9470 | |
8928 | #define>24)><24)>24)|(len-2)) |
9471 | /* |
8929 | #define><24)|(len-2)) |
9472 | ><22)) |
8930 | #define>27)|(0x2<<24)|(len-2)) |
9473 | |
8931 | #define><27)|(0x2<<24)|(len-2)) |
9474 | /* |
8932 | #define>29)|(0x3<<27)|(0x2<<24)|(len-2)) |
9475 | >29)|(0x43<<22)) |
8933 | #define><29)|(0x3<<27)|(0x2<<24)|(len-2)) |
9476 | |
8934 | #define>20) |
9477 | /* |
8935 | #define><20) |
9478 | ><29)|(0x43<<22)) |
8936 | #define>20) |
9479 | |
8937 | #define><20) |
9480 | /* |
8938 | #define>22) |
9481 | >22)) |
8939 | #define><22) |
9482 | #define><22)) |
8940 | #define>23)|2) |
9483 | #define>29)|(0x40<<22)) |
8941 | #define><23)|2) |
9484 | #define><29)|(0x40<<22)) |
8942 | #define>29)|(0x14<<23)|2) |
9485 | #define>16)) |
8943 | #define><29)|(0x14<<23)|2) |
9486 | |
8944 | #define>11)><11)>15)><15)>16) |
9487 | #define><16)) |
8945 | #define><16) |
9488 | |
8946 | #define>16) |
9489 | #define>27)|(0x0<<16)) |
8947 | #define><16) |
9490 | |
8948 | #define>24) |
9491 | #define><27)|(0x0<<16)) |
8949 | #define><24) |
9492 | |
8950 | #define>24) |
9493 | #define>29)|(0x1<<27)|(0x0<<16)) |
8951 | #define><24) |
9494 | |
8952 | #define>24) |
9495 | #define><29)|(0x1<<27)|(0x0<<16)) |
8953 | #define><24) |
9496 | |
8954 | #define>24) |
9497 | #define>16)) |
8955 | #define><24) |
9498 | |
8956 | #define>20) |
9499 | #define><16)) |
8957 | #define><20) |
9500 | |
8958 | #define>20) |
9501 | #define>24)|(0x47<<16)) |
8959 | #define><20) |
9502 | |
8960 | #define>22)|5) |
9503 | #define><24)|(0x47<<16)) |
8961 | #define><22)|5) |
9504 | |
8962 | #define>29)|(0x71<<22)|5) |
9505 | #define>27)|(0x0<<24)|(0x47<<16)) |
8963 | #define><29)|(0x71<<22)|5) |
9506 | |
8964 | #define>22)|6) |
9507 | #define><27)|(0x0<<24)|(0x47<<16)) |
8965 | #define><22)|6) |
9508 | |
8966 | #define>29)|(0x53<<22)|6) |
9509 | #define>29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
8967 | #define><29)|(0x53<<22)|6) |
9510 | |
8968 | #define>22)|4) |
9511 | #define><29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
8969 | #define><22)|4) |
9512 | |
8970 | #define>29)|(0x43<<22)|4) |
9513 | #define>16)) |
8971 | #define><29)|(0x43<<22)|4) |
9514 | #define><16)) |
8972 | #define>22><22>29><29>16)|0x2) |
9515 | #define>24)|(0x46<<16)) |
8973 | 9516 | #define><24)|(0x46<<16)) |
|
8974 | #define><16)|0x2) |
9517 | #define>27)|(0x0<<24)|(0x46<<16)) |
8975 | 9518 | #define><27)|(0x0<<24)|(0x46<<16)) |
|
8976 | #define>16)|(0x3)) |
9519 | #define>29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
8977 | #define><16)|(0x3)) |
9520 | #define><29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
8978 | #define>24)|(0x80<<16)|(0x3)) |
9521 | #define>16)) |
8979 | #define><24)|(0x80<<16)|(0x3)) |
9522 | #define><16)) |
8980 | #define>29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
9523 | #define>24)|(0x45<<16)) |
8981 | #define><29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
9524 | #define><24)|(0x45<<16)) |
8982 | #define>16)|1) |
9525 | #define>27)|(0x0<<24)|(0x45<<16)) |
8983 | #define><16)|1) |
9526 | #define><27)|(0x0<<24)|(0x45<<16)) |
8984 | #define>24)|(0x8e<<16)|1) |
9527 | #define>29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
8985 | #define><24)|(0x8e<<16)|1) |
9528 | #define><29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
8986 | #define>29)|(0x1d<<24)|(0x8e<<16)|1) |
9529 | #define>16)) |
8987 | #define><29)|(0x1d<<24)|(0x8e<<16)|1) |
9530 | #define><16)) |
8988 | #define>16)|0x0) |
9531 | #define>24)|(0x44<<16)) |
8989 | #define><16)|0x0) |
9532 | #define><24)|(0x44<<16)) |
8990 | #define>24)|(0x85<<16)|0x0) |
9533 | #define>27)|(0x0<<24)|(0x44<<16)) |
8991 | #define><24)|(0x85<<16)|0x0) |
9534 | #define><27)|(0x0<<24)|(0x44<<16)) |
8992 | #define>29)|(0x1d<<24)|(0x85<<16)|0x0) |
9535 | #define>29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
8993 | #define><29)|(0x1d<<24)|(0x85<<16)|0x0) |
9536 | #define><29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
8994 | #define>24)|0x4) |
9537 | #define>16)) |
8995 | #define><24)|0x4) |
9538 | #define><16)) |
8996 | #define>29)|(0x1d<<24)|0x4) |
9539 | #define>24)|(0x43<<16)) |
8997 | #define><29)|(0x1d<<24)|0x4) |
9540 | #define><24)|(0x43<<16)) |
8998 | #define>16)) |
9541 | #define>27)|(0x0<<24)|(0x43<<16)) |
8999 | #define><16)) |
9542 | #define><27)|(0x0<<24)|(0x43<<16)) |
9000 | #define>24)|(0x83<<16)) |
9543 | #define>29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
9001 | #define><24)|(0x83<<16)) |
9544 | #define><29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
9002 | #define>29)|(0x1d<<24)|(0x83<<16)) |
9545 | #define>16)) |
9003 | #define><29)|(0x1d<<24)|(0x83<<16)) |
9546 | |
9004 | #define>16)|0x0) |
9547 | #define><16)) |
9005 | #define><16)|0x0) |
9548 | |
9006 | #define>24)|(0x1<<16)|0x0) |
9549 | #define>24)|(0x17<<16)) |
9007 | #define><24)|(0x1<<16)|0x0) |
9550 | |
9008 | #define>29)|(0x1d<<24)|(0x1<<16)|0x0) |
9551 | #define><24)|(0x17<<16)) |
9009 | #define><29)|(0x1d<<24)|(0x1<<16)|0x0) |
9552 | |
9010 | #define>16)|1) |
9553 | #define>27)|(0x1<<24)|(0x17<<16)) |
9011 | #define><16)|1) |
9554 | |
9012 | #define>24)|(0x81<<16)|1) |
9555 | #define><27)|(0x1<<24)|(0x17<<16)) |
9013 | #define><24)|(0x81<<16)|1) |
9556 | |
9014 | #define>29)|(0x1d<<24)|(0x81<<16)|1) |
9557 | #define>29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
9015 | #define><29)|(0x1d<<24)|(0x81<<16)|1) |
9558 | |
9016 | #define>19)) |
9559 | #define><29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
9017 | #define><19)) |
9560 | |
9018 | #define>24)|(0x10<<19)) |
9561 | #define>16)) |
9019 | #define><24)|(0x10<<19)) |
9562 | #define><16)) |
9020 | #define>29)|(0x1c<<24)|(0x10<<19)) |
9563 | #define>24)|(0x3A<<16)) |
9021 | #define><29)|(0x1c<<24)|(0x10<<19)) |
9564 | #define><24)|(0x3A<<16)) |
9022 | #define>0) |
9565 | #define>27)|(0x0<<24)|(0x3A<<16)) |
9023 | #define><0) |
9566 | #define><27)|(0x0<<24)|(0x3A<<16)) |
9024 | #define>16) |
9567 | #define>29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
9025 | #define><16) |
9568 | #define><29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
9026 | #define>0) |
9569 | #define>16)) |
9027 | #define><0) |
9570 | #define><16)) |
9028 | #define>16) |
9571 | #define>24)|(0x39<<16)) |
9029 | #define><16) |
9572 | #define><24)|(0x39<<16)) |
9030 | #define>16)|(0x1)) |
9573 | #define>27)|(0x0<<24)|(0x39<<16)) |
9031 | #define><16)|(0x1)) |
9574 | #define><27)|(0x0<<24)|(0x39<<16)) |
9032 | #define>24)|(0x81<<16)|(0x1)) |
9575 | #define>29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
9033 | #define><24)|(0x81<<16)|(0x1)) |
9576 | #define><29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
9034 | #define>29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
9577 | #define>16)) |
9035 | #define><29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
9578 | #define><16)) |
9036 | #define>16)) |
9579 | #define>24)|(0x5<<16)) |
9037 | #define><16)) |
9580 | #define><24)|(0x5<<16)) |
9038 | #define>24)|(0x7<<16)) |
9581 | #define>27)|(0x1<<24)|(0x5<<16)) |
9039 | #define><24)|(0x7<<16)) |
9582 | #define><27)|(0x1<<24)|(0x5<<16)) |
9040 | #define>29)|(0x1d<<24)|(0x7<<16)) |
9583 | #define>29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
9041 | #define><29)|(0x1d<<24)|(0x7<<16)) |
9584 | #define><29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
9042 | #define>0) |
9585 | #define>16)) |
9043 | #define><0) |
9586 | #define><16)) |
9044 | #define>0) |
9587 | #define>24)|(0x4<<16)) |
9045 | #define><0) |
9588 | #define><24)|(0x4<<16)) |
9046 | #define>1) |
9589 | #define>27)|(0x1<<24)|(0x4<<16)) |
9047 | #define><1) |
9590 | #define><27)|(0x1<<24)|(0x4<<16)) |
9048 | #define>19)) |
9591 | #define>29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
9049 | #define><19)) |
9592 | #define><29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
9050 | #define>24)|(0x10<<19)) |
9593 | #define>16)) |
9051 | #define><24)|(0x10<<19)) |
9594 | #define><16)) |
9052 | #define>29)|(0x1c<<24)|(0x10<<19)) |
9595 | #define>24)|(0x0<<16)) |
9053 | #define><29)|(0x1c<<24)|(0x10<<19)) |
9596 | #define><24)|(0x0<<16)) |
9054 | #define>24)) |
9597 | #define>27)|(0x0<<24)|(0x0<<16)) |
9055 | #define><24)) |
9598 | #define><27)|(0x0<<24)|(0x0<<16)) |
9056 | #define>29)|(0x7<<24)) |
9599 | #define>29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
9057 | #define><29)|(0x7<<24)) |
9600 | #define><29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
9058 | #define>><>><>0) |
9601 | #define>16)) |
9059 | 9602 | #define><16)) |
|
9060 | /* |
9603 | #define>24)|(0xB<<16)) |
9061 | ><0) |
9604 | #define><24)|(0xB<<16)) |
9062 | 9605 | #define>27)|(0x0<<24)|(0xB<<16)) |
|
9063 | /* |
9606 | #define><27)|(0x0<<24)|(0xB<<16)) |
9064 | >0) |
9607 | #define>29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
9065 | #define><0) |
9608 | #define><29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
9066 | #define>7)><7)>6)><6)>13) |
9609 | #define>16)) |
9067 | #define><13) |
9610 | #define><16)) |
9068 | #define>8) |
9611 | #define>24)|(0x4<<16)) |
9069 | #define><8) |
9612 | #define><24)|(0x4<<16)) |
9070 | #define>8) |
9613 | #define>27)|(0x1<<24)|(0x4<<16)) |
9071 | #define><8) |
9614 | #define><27)|(0x1<<24)|(0x4<<16)) |
9072 | #define>2) |
9615 | #define>29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
9073 | #define><2) |
9616 | #define><29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
9074 | #define>2) |
9617 | #define>0) |
9075 | #define><2) |
9618 | #define><0) |
9076 | #define>7) |
9619 | #define>2)><2)>0) |
9077 | #define><7) |
9620 | #define><0) |
9078 | #define>8) |
9621 | #define>1) |
9079 | #define><8) |
9622 | #define><1) |
9080 | #define>14) |
9623 | #define>2) |
9081 | #define><14) |
9624 | #define><2) |
9082 | #define>14) |
9625 | #define>3) |
9083 | #define><14) |
9626 | #define><3) |
9084 | #define>18) |
9627 | #define>4) |
9085 | #define><18) |
9628 | #define><4) |
9086 | #define>21) |
9629 | #define>7)><7)>8) |
9087 | #define><21) |
9630 | #define><8) |
9088 | #define>22) |
9631 | #define>9) |
9089 | #define><22) |
9632 | #define><9) |
9090 | #define>=>><>12) |
9633 | #define>10)><10)>11)><11)>12)><12)>12) |
9091 | #define><12) |
9634 | #define><12) |
9092 | #define>15) |
9635 | #define>13) |
9093 | #define><15) |
9636 | #define><13) |
9094 | #define>15) |
9637 | #define>14) |
9095 | #define><15) |
9638 | #define><14) |
9096 | #define>0) |
9639 | #define>14) |
9097 | #define><0) |
9640 | #define><14) |
9098 | #define>1) |
9641 | #define>16) |
9099 | #define><1) |
9642 | #define><16) |
9100 | #define>2) |
9643 | #define>18) |
9101 | #define><2) |
9644 | #define><18) |
9102 | #define>3) |
9645 | #define>20) |
9103 | #define><3) |
9646 | #define><20) |
9104 | #define>8) |
9647 | #define>21) |
9105 | #define><8) |
9648 | #define><21) |
9106 | #define>8) |
9649 | #define>23) |
9107 | #define><8) |
9650 | #define><23) |
9108 | #define>16) |
9651 | #define>24)><24)>24)|(len-2)) |
9109 | #define><16) |
9652 | #define><24)|(len-2)) |
9110 | #define>16) |
9653 | #define>27)|(0x2<<24)|(len-2)) |
9111 | #define><16) |
9654 | #define><27)|(0x2<<24)|(len-2)) |
9112 | #define>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>18) |
9655 | #define>29)|(0x3<<27)|(0x2<<24)|(len-2)) |
9113 | #define><18) |
9656 | #define><29)|(0x3<<27)|(0x2<<24)|(len-2)) |
9114 | #define>20) |
9657 | #define>20) |
9115 | #define><20) |
9658 | #define><20) |
9116 | #define>21) |
9659 | #define>20) |
9117 | #define><21) |
9660 | #define><20) |
9118 | #define>22) |
9661 | #define>22) |
9119 | #define><22) |
9662 | #define><22) |
9120 | #define>><>><>><>><>><>><>><>21) |
9663 | #define>23)|2) |
9121 | #define><21) |
9664 | #define><23)|2) |
9122 | #define>21) |
9665 | #define>29)|(0x14<<23)|2) |
9123 | #define><21) |
9666 | #define><29)|(0x14<<23)|2) |
9124 | #define>21) |
9667 | #define>11)><11)>15)><15)>16) |
9125 | #define><21) |
9668 | #define><16) |
9126 | #define>0) |
9669 | #define>16) |
9127 | #define><0) |
9670 | #define><16) |
9128 | #define>0) |
9671 | #define>24) |
9129 | #define><0) |
9672 | #define><24) |
9130 | #define>0) |
9673 | #define>24) |
9131 | #define><0) |
9674 | #define><24) |
9132 | #define>><>><>><>><>><>><>1) |
9675 | #define>24) |
9133 | #define><1) |
9676 | #define><24) |
9134 | #define>2) |
9677 | #define>24) |
9135 | #define><2) |
9678 | #define><24) |
9136 | #define>6) |
9679 | #define>20) |
9137 | #define><6) |
9680 | #define><20) |
9138 | #define>16) |
9681 | #define>20) |
9139 | #define><16) |
9682 | #define><20) |
9140 | #define>22) |
9683 | #define>22)|5) |
9141 | 9684 | #define><22)|5) |
|
9142 | #define><22) |
9685 | #define>29)|(0x71<<22)|5) |
9143 | 9686 | #define><29)|(0x71<<22)|5) |
|
9144 | #define>><>5) |
9687 | #define>22)|6) |
9145 | #define><5) |
9688 | #define><22)|6) |
9146 | #define>0) |
9689 | #define>29)|(0x53<<22)|6) |
9147 | 9690 | #define><29)|(0x53<<22)|6) |
|
9148 | #define><0) |
9691 | #define>22)|4) |
9149 | 9692 | #define><22)|4) |
|
9150 | #define>1) |
9693 | #define>29)|(0x43<<22)|4) |
9151 | #define><1) |
9694 | #define><29)|(0x43<<22)|4) |
9152 | #define>8) |
9695 | #define>22><22>29><29>16)|0x2) |
9153 | 9696 | ||
9154 | /*><8) |
9697 | #define><16)|0x2) |
9155 | 9698 | ||
9156 | /*>8) |
9699 | #define>16)|(0x3)) |
9157 | 9700 | #define><16)|(0x3)) |
|
9158 | #define><8) |
9701 | #define>24)|(0x80<<16)|(0x3)) |
9159 | 9702 | #define><24)|(0x80<<16)|(0x3)) |
|
9160 | #define>8) |
9703 | #define>29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
9161 | #define><8) |
9704 | #define><29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
9162 | #define>13) |
9705 | #define>16)|1) |
9163 | #define><13) |
9706 | #define><16)|1) |
9164 | #define>3) |
9707 | #define>24)|(0x8e<<16)|1) |
9165 | 9708 | #define><24)|(0x8e<<16)|1) |
|
9166 | #define><3) |
9709 | #define>29)|(0x1d<<24)|(0x8e<<16)|1) |
9167 | 9710 | #define><29)|(0x1d<<24)|(0x8e<<16)|1) |
|
9168 | #define>3) |
9711 | #define>16)|0x0) |
9169 | #define><3) |
9712 | #define><16)|0x0) |
9170 | #define>3) |
9713 | #define>24)|(0x85<<16)|0x0) |
9171 | #define><3) |
9714 | #define><24)|(0x85<<16)|0x0) |
9172 | #define>3) |
9715 | #define>29)|(0x1d<<24)|(0x85<<16)|0x0) |
9173 | #define><3) |
9716 | #define><29)|(0x1d<<24)|(0x85<<16)|0x0) |
9174 | #define>4) |
9717 | #define>24)|0x4) |
9175 | #define><4) |
9718 | #define><24)|0x4) |
9176 | #define>3) |
9719 | #define>29)|(0x1d<<24)|0x4) |
9177 | #define><3) |
9720 | #define><29)|(0x1d<<24)|0x4) |
9178 | #define>3) |
9721 | #define>16)) |
9179 | #define><3) |
9722 | #define><16)) |
9180 | #define>6) |
9723 | #define>24)|(0x83<<16)) |
9181 | #define><6) |
9724 | #define><24)|(0x83<<16)) |
9182 | #define>10) |
9725 | #define>29)|(0x1d<<24)|(0x83<<16)) |
9183 | #define><10) |
9726 | #define><29)|(0x1d<<24)|(0x83<<16)) |
9184 | #define>><>><>><>><>><>><>><>><>><>21)><21)>21) |
9727 | #define>16)|0x0) |
9185 | #define><21) |
9728 | #define><16)|0x0) |
9186 | #define>21) |
9729 | #define>24)|(0x1<<16)|0x0) |
9187 | #define><21) |
9730 | #define><24)|(0x1<<16)|0x0) |
9188 | #define>21) |
9731 | #define>29)|(0x1d<<24)|(0x1<<16)|0x0) |
9189 | #define><21) |
9732 | #define><29)|(0x1d<<24)|(0x1<<16)|0x0) |
9190 | #define>21) |
9733 | #define>16)|1) |
9191 | #define><21) |
9734 | #define><16)|1) |
9192 | #define>0) |
9735 | #define>24)|(0x81<<16)|1) |
9193 | 9736 | #define><24)|(0x81<<16)|1) |
|
9194 | #define><0) |
9737 | #define>29)|(0x1d<<24)|(0x81<<16)|1) |
9195 | 9738 | #define><29)|(0x1d<<24)|(0x81<<16)|1) |
|
9196 | #define>1) |
9739 | #define>19)) |
9197 | #define><1) |
9740 | #define><19)) |
9198 | #define>1) |
9741 | #define>24)|(0x10<<19)) |
9199 | #define><1) |
9742 | #define><24)|(0x10<<19)) |
9200 | #define>1) |
9743 | #define>29)|(0x1c<<24)|(0x10<<19)) |
9201 | #define><1) |
9744 | #define><29)|(0x1c<<24)|(0x10<<19)) |
9202 | #define>1) |
9745 | #define>0) |
9203 | #define><1) |
9746 | #define><0) |
9204 | #define>0) |
9747 | #define>16) |
9205 | 9748 | #define><16) |
|
9206 | #define><0) |
9749 | #define>0) |
9207 | 9750 | #define><0) |
|
9208 | #define>2) |
9751 | #define>16) |
9209 | #define><2) |
9752 | #define><16) |
9210 | #define>2) |
9753 | #define>16)|(0x1)) |
9211 | #define><2) |
9754 | #define><16)|(0x1)) |
9212 | #define>2) |
9755 | #define>24)|(0x81<<16)|(0x1)) |
9213 | #define><2) |
9756 | #define><24)|(0x81<<16)|(0x1)) |
9214 | #define>2) |
9757 | #define>29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
9215 | #define><2) |
9758 | #define><29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
9216 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
9759 | #define>16)) |
- | 9760 | #define><16)) |
|
- | 9761 | #define>24)|(0x7<<16)) |
|
- | 9762 | #define><24)|(0x7<<16)) |
|
- | 9763 | #define>29)|(0x1d<<24)|(0x7<<16)) |
|
- | 9764 | #define><29)|(0x1d<<24)|(0x7<<16)) |
|
- | 9765 | #define>0) |
|
- | 9766 | #define><0) |
|
- | 9767 | #define>0) |
|
- | 9768 | #define><0) |
|
- | 9769 | #define>1) |
|
- | 9770 | #define><1) |
|
- | 9771 | #define>19)) |
|
- | 9772 | #define><19)) |
|
- | 9773 | #define>24)|(0x10<<19)) |
|
- | 9774 | #define><24)|(0x10<<19)) |
|
- | 9775 | #define>29)|(0x1c<<24)|(0x10<<19)) |
|
- | 9776 | #define><29)|(0x1c<<24)|(0x10<<19)) |
|
- | 9777 | #define>24)) |
|
- | 9778 | #define><24)) |
|
- | 9779 | #define>29)|(0x7<<24)) |
|
- | 9780 | #define><29)|(0x7<<24)) |
|
- | 9781 | #define>><>><>0) |
|
- | 9782 | ||
- | 9783 | /* |
|
- | 9784 | ><0) |
|
- | 9785 | ||
- | 9786 | /* |
|
- | 9787 | >0) |
|
- | 9788 | #define><0) |
|
- | 9789 | #define>7)><7)>6)><6)>13) |
|
- | 9790 | #define><13) |
|
- | 9791 | #define>8) |
|
- | 9792 | #define><8) |
|
- | 9793 | #define>8) |
|
- | 9794 | #define><8) |
|
- | 9795 | #define>2) |
|
- | 9796 | #define><2) |
|
- | 9797 | #define>2) |
|
- | 9798 | #define><2) |
|
- | 9799 | #define>7) |
|
- | 9800 | #define><7) |
|
- | 9801 | #define>8) |
|
- | 9802 | #define><8) |
|
- | 9803 | #define>14) |
|
- | 9804 | #define><14) |
|
- | 9805 | #define>14) |
|
- | 9806 | #define><14) |
|
- | 9807 | #define>18) |
|
- | 9808 | #define><18) |
|
- | 9809 | #define>21) |
|
- | 9810 | #define><21) |
|
- | 9811 | #define>22) |
|
- | 9812 | #define><22) |
|
- | 9813 | #define>12) |
|
- | 9814 | #define><12) |
|
- | 9815 | #define>=>><>12) |
|
- | 9816 | #define><12) |
|
- | 9817 | #define>15) |
|
- | 9818 | #define><15) |
|
- | 9819 | #define>15) |
|
- | 9820 | #define><15) |
|
- | 9821 | #define>0) |
|
- | 9822 | #define><0) |
|
- | 9823 | #define>1) |
|
- | 9824 | #define><1) |
|
- | 9825 | #define>2) |
|
- | 9826 | #define><2) |
|
- | 9827 | #define>3) |
|
- | 9828 | #define><3) |
|
- | 9829 | #define>8) |
|
- | 9830 | #define><8) |
|
- | 9831 | #define>8) |
|
- | 9832 | #define><8) |
|
- | 9833 | #define>16) |
|
- | 9834 | #define><16) |
|
- | 9835 | #define>16) |
|
- | 9836 | #define><16) |
|
- | 9837 | #define>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>16)><16)>18) |
|
- | 9838 | #define><18) |
|
- | 9839 | #define>20) |
|
- | 9840 | #define><20) |
|
- | 9841 | #define>21) |
|
- | 9842 | #define><21) |
|
- | 9843 | #define>22) |
|
- | 9844 | #define><22) |
|
- | 9845 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>21) |
|
- | 9846 | #define><21) |
|
- | 9847 | #define>21) |
|
- | 9848 | #define><21) |
|
- | 9849 | #define>21) |
|
- | 9850 | #define><21) |
|
- | 9851 | #define>0) |
|
- | 9852 | #define><0) |
|
- | 9853 | #define>0) |
|
- | 9854 | #define><0) |
|
- | 9855 | #define>0) |
|
- | 9856 | #define><0) |
|
- | 9857 | #define>><>><>><>><>><>><>1) |
|
- | 9858 | #define><1) |
|
- | 9859 | #define>2) |
|
- | 9860 | #define><2) |
|
- | 9861 | #define>6) |
|
- | 9862 | #define><6) |
|
- | 9863 | #define>16) |
|
- | 9864 | #define><16) |
|
- | 9865 | #define>22) |
|
- | 9866 | ||
- | 9867 | #define><22) |
|
- | 9868 | ||
- | 9869 | #define>><>5) |
|
- | 9870 | #define><5) |
|
- | 9871 | #define>0) |
|
- | 9872 | ||
- | 9873 | #define><0) |
|
- | 9874 | ||
- | 9875 | #define>1) |
|
- | 9876 | #define><1) |
|
- | 9877 | #define>><>><>8) |
|
- | 9878 | ||
- | 9879 | #define><8) |
|
- | 9880 | ||
- | 9881 | #define>8) |
|
- | 9882 | ||
- | 9883 | #define><8) |
|
- | 9884 | ||
- | 9885 | #define>8) |
|
- | 9886 | #define><8) |
|
- | 9887 | #define>13) |
|
- | 9888 | #define><13) |
|
- | 9889 | #define>3) |
|
- | 9890 | ||
- | 9891 | #define><3) |
|
- | 9892 | ||
- | 9893 | #define>3) |
|
- | 9894 | #define><3) |
|
- | 9895 | #define>3) |
|
- | 9896 | #define><3) |
|
- | 9897 | #define>3) |
|
- | 9898 | #define><3) |
|
- | 9899 | #define>4) |
|
- | 9900 | #define><4) |
|
- | 9901 | #define>3) |
|
- | 9902 | #define><3) |
|
- | 9903 | #define>3) |
|
- | 9904 | #define><3) |
|
- | 9905 | #define>6) |
|
- | 9906 | #define><6) |
|
- | 9907 | #define>10) |
|
- | 9908 | #define><10) |
|
- | 9909 | #define>><>><>><>><>><>><>><>><>><>21)><21)>21) |
|
- | 9910 | #define><21) |
|
- | 9911 | #define>21) |
|
- | 9912 | #define><21) |
|
- | 9913 | #define>21) |
|
- | 9914 | #define><21) |
|
- | 9915 | #define>21) |
|
- | 9916 | #define><21) |
|
- | 9917 | #define>0) |
|
- | 9918 | ||
- | 9919 | #define><0) |
|
- | 9920 | ||
- | 9921 | #define>1) |
|
- | 9922 | #define><1) |
|
- | 9923 | #define>1) |
|
- | 9924 | #define><1) |
|
- | 9925 | #define>1) |
|
- | 9926 | #define><1) |
|
- | 9927 | #define>1) |
|
- | 9928 | #define><1) |
|
- | 9929 | #define>0) |
|
- | 9930 | ||
- | 9931 | #define><0) |
|
- | 9932 | ||
- | 9933 | #define>1) |
|
- | 9934 | #define><1) |
|
- | 9935 | #define>2) |
|
- | 9936 | #define><2) |
|
- | 9937 | #define>2) |
|
- | 9938 | #define><2) |
|
- | 9939 | #define>2) |
|
- | 9940 | #define><2) |
|
- | 9941 | #define>2) |
|
- | 9942 | #define><2) |
|
- | 9943 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |