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Line 24... Line 24...
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25
#ifndef _I915_REG_H_
25
#ifndef _I915_REG_H_
Line 26... Line 26...
26
#define _I915_REG_H_
26
#define _I915_REG_H_
-
 
27
 
27
 
28
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
28
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
-
 
29
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
29
#define _PLANE(plane, a, b) _PIPE(plane, a, b)
30
 
30
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
31
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Line -... Line 32...
-
 
32
#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
-
 
33
			       (pipe) == PIPE_B ? (b) : (c))
-
 
34
 
-
 
35
#define _MASKED_FIELD(mask, value) ({					   \
-
 
36
	if (__builtin_constant_p(mask))					   \
-
 
37
		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
-
 
38
	if (__builtin_constant_p(value))				   \
-
 
39
		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
-
 
40
	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
32
#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
41
		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
33
			       (pipe) == PIPE_B ? (b) : (c))
42
				 "Incorrect value for mask");		   \
-
 
43
	(mask) << 16 | (value); })
-
 
44
#define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
Line 34... Line 45...
34
 
45
#define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
Line 35... Line 46...
35
#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
46
 
36
#define _MASKED_BIT_DISABLE(a) ((a) << 16)
47
 
Line 72... Line 83...
72
#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
83
#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
73
#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
84
#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
74
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
85
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
75
#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
86
#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
76
#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
87
#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
-
 
88
#define GCDGMBUS 0xcc
77
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
89
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
Line 78... Line 90...
78
 
90
 
79
 
91
 
80
/* Graphics reset regs */
92
/* Graphics reset regs */
81
#define I965_GDRST 0xc0 /* PCI config register */
93
#define I915_GDRST 0xc0 /* PCI config register */
82
#define  GRDOM_FULL	(0<<2)
94
#define  GRDOM_FULL	(0<<2)
83
#define  GRDOM_RENDER	(1<<2)
95
#define  GRDOM_RENDER	(1<<2)
-
 
96
#define  GRDOM_MEDIA	(3<<2)
84
#define  GRDOM_MEDIA	(3<<2)
97
#define  GRDOM_MASK	(3<<2)
Line 85... Line 98...
85
#define  GRDOM_MASK	(3<<2)
98
#define  GRDOM_RESET_STATUS (1<<1)
86
#define  GRDOM_RESET_ENABLE (1<<0)
99
#define  GRDOM_RESET_ENABLE (1<<0)
87
 
100
 
Line 141... Line 154...
141
#define   ECOBITS_PPGTT_CACHE4B		(0<<8)
154
#define   ECOBITS_PPGTT_CACHE4B		(0<<8)
Line 142... Line 155...
142
 
155
 
143
#define GAB_CTL				0x24000
156
#define GAB_CTL				0x24000
Line -... Line 157...
-
 
157
#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
-
 
158
 
-
 
159
#define GEN7_BIOS_RESERVED		0x1082C0
-
 
160
#define GEN7_BIOS_RESERVED_1M		(0 << 5)
-
 
161
#define GEN7_BIOS_RESERVED_256K		(1 << 5)
-
 
162
#define GEN8_BIOS_RESERVED_SHIFT       7
-
 
163
#define GEN7_BIOS_RESERVED_MASK        0x1
-
 
164
#define GEN8_BIOS_RESERVED_MASK        0x3
144
#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
165
 
Line 145... Line 166...
145
 
166
 
146
/* VGA stuff */
167
/* VGA stuff */
Line 238... Line 259...
238
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
259
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
239
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
260
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
240
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
261
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
241
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
262
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
242
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
263
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
-
 
264
/* SKL ones */
-
 
265
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
-
 
266
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
-
 
267
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
-
 
268
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
-
 
269
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
-
 
270
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
-
 
271
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
-
 
272
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
-
 
273
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
243
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
274
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
244
#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
275
#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
245
#define   MI_SEMAPHORE_UPDATE	    (1<<21)
276
#define   MI_SEMAPHORE_UPDATE	    (1<<21)
246
#define   MI_SEMAPHORE_COMPARE	    (1<<20)
277
#define   MI_SEMAPHORE_COMPARE	    (1<<20)
247
#define   MI_SEMAPHORE_REGISTER	    (1<<18)
278
#define   MI_SEMAPHORE_REGISTER	    (1<<18)
Line 270... Line 301...
270
#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
301
#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
271
#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
302
#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
272
#define   MI_SEMAPHORE_POLL		(1<<15)
303
#define   MI_SEMAPHORE_POLL		(1<<15)
273
#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
304
#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
274
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
305
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
-
 
306
#define MI_STORE_DWORD_IMM_GEN8	MI_INSTR(0x20, 2)
275
#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
307
#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
276
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
308
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
277
#define   MI_STORE_DWORD_INDEX_SHIFT 2
309
#define   MI_STORE_DWORD_INDEX_SHIFT 2
278
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
310
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
279
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
311
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
280
 *   simply ignores the register load under certain conditions.
312
 *   simply ignores the register load under certain conditions.
281
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
313
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
282
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
314
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
283
 */
315
 */
284
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
316
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
-
 
317
#define   MI_LRI_FORCE_POSTED		(1<<12)
285
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
318
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
286
#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
319
#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
287
#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
320
#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
288
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
321
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
289
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
322
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
Line 302... Line 335...
302
#define   MI_BATCH_NON_SECURE_HSW 	(1<<13)
335
#define   MI_BATCH_NON_SECURE_HSW 	(1<<13)
303
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
336
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
304
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
337
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
305
#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
338
#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
Line -... Line 339...
-
 
339
 
-
 
340
#define MI_PREDICATE_SRC0	(0x2400)
Line 306... Line 341...
306
 
341
#define MI_PREDICATE_SRC1	(0x2408)
307
 
342
 
308
#define MI_PREDICATE_RESULT_2	(0x2214)
343
#define MI_PREDICATE_RESULT_2	(0x2214)
Line 358... Line 393...
358
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
393
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
359
#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
394
#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
360
#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
395
#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
361
#define   PIPE_CONTROL_CS_STALL				(1<<20)
396
#define   PIPE_CONTROL_CS_STALL				(1<<20)
362
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
397
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
-
 
398
#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
363
#define   PIPE_CONTROL_QW_WRITE	(1<<14)
399
#define   PIPE_CONTROL_QW_WRITE	(1<<14)
364
#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
400
#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
365
#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
401
#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
366
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
402
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
367
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
403
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
Line 499... Line 535...
499
 
535
 
500
/* See configdb bunit SB addr map */
536
/* See configdb bunit SB addr map */
Line 501... Line 537...
501
#define BUNIT_REG_BISOC				0x11
537
#define BUNIT_REG_BISOC				0x11
-
 
538
 
-
 
539
#define PUNIT_REG_DSPFREQ			0x36
-
 
540
#define   DSPFREQSTAT_SHIFT_CHV			24
-
 
541
#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
502
 
542
#define   DSPFREQGUAR_SHIFT_CHV			8
503
#define PUNIT_REG_DSPFREQ			0x36
543
#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
504
#define   DSPFREQSTAT_SHIFT			30
544
#define   DSPFREQSTAT_SHIFT			30
505
#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
545
#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
-
 
546
#define   DSPFREQGUAR_SHIFT			14
-
 
547
#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
-
 
548
#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
-
 
549
#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
-
 
550
#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
-
 
551
#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
-
 
552
#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
-
 
553
#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
-
 
554
#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
-
 
555
#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
-
 
556
#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
-
 
557
#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
Line 506... Line 558...
506
#define   DSPFREQGUAR_SHIFT			14
558
#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
507
#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
559
#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
508
 
560
 
509
/* See the PUNIT HAS v0.8 for the below bits */
561
/* See the PUNIT HAS v0.8 for the below bits */
Line 516... Line 568...
516
	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,
568
	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,
517
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,
569
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,
518
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
570
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
519
	PUNIT_POWER_WELL_DPIO_RX0		= 10,
571
	PUNIT_POWER_WELL_DPIO_RX0		= 10,
520
	PUNIT_POWER_WELL_DPIO_RX1		= 11,
572
	PUNIT_POWER_WELL_DPIO_RX1		= 11,
-
 
573
	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
-
 
574
	/* FIXME: guesswork below */
-
 
575
	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
-
 
576
	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
-
 
577
	PUNIT_POWER_WELL_DPIO_RX2		= 15,
Line 521... Line 578...
521
 
578
 
522
	PUNIT_POWER_WELL_NUM,
579
	PUNIT_POWER_WELL_NUM,
Line 523... Line 580...
523
};
580
};
Line 531... Line 588...
531
#define   PUNIT_PWRGT_PWR_GATE(power_well)	(3 << ((power_well) * 2))
588
#define   PUNIT_PWRGT_PWR_GATE(power_well)	(3 << ((power_well) * 2))
Line 532... Line 589...
532
 
589
 
533
#define PUNIT_REG_GPU_LFM			0xd3
590
#define PUNIT_REG_GPU_LFM			0xd3
534
#define PUNIT_REG_GPU_FREQ_REQ			0xd4
591
#define PUNIT_REG_GPU_FREQ_REQ			0xd4
-
 
592
#define PUNIT_REG_GPU_FREQ_STS			0xd8
535
#define PUNIT_REG_GPU_FREQ_STS			0xd8
593
#define   GPLLENABLE				(1<<4)
536
#define   GENFREQSTATUS				(1<<0)
594
#define   GENFREQSTATUS				(1<<0)
537
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
595
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
Line 538... Line 596...
538
#define PUNIT_REG_CZ_TIMESTAMP			0xce
596
#define PUNIT_REG_CZ_TIMESTAMP			0xce
Line 639... Line 697...
639
 * this fact isn't really relevant for the driver since AUX is
697
 * this fact isn't really relevant for the driver since AUX is
640
 * controlled from the display controller side. No DPIO registers
698
 * controlled from the display controller side. No DPIO registers
641
 * need to be accessed during AUX communication,
699
 * need to be accessed during AUX communication,
642
 *
700
 *
643
 * Generally the common lane corresponds to the pipe and
701
 * Generally the common lane corresponds to the pipe and
644
 * the spline (PCS/TX) correponds to the port.
702
 * the spline (PCS/TX) corresponds to the port.
645
 *
703
 *
646
 * For dual channel PHY (VLV/CHV):
704
 * For dual channel PHY (VLV/CHV):
647
 *
705
 *
648
 *  pipe A == CMN/PLL/REF CH0
706
 *  pipe A == CMN/PLL/REF CH0
649
 *
707
 *
Line 763... Line 821...
763
 
821
 
764
#define _VLV_PCS_DW0_CH0		0x8200
822
#define _VLV_PCS_DW0_CH0		0x8200
765
#define _VLV_PCS_DW0_CH1		0x8400
823
#define _VLV_PCS_DW0_CH1		0x8400
766
#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
824
#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
-
 
825
#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
-
 
826
#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
767
#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
827
#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
Line 768... Line 828...
768
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
828
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
769
 
829
 
770
#define _VLV_PCS01_DW0_CH0		0x200
830
#define _VLV_PCS01_DW0_CH0		0x200
Line 803... Line 863...
803
#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
863
#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
804
#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
864
#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Line 805... Line 865...
805
 
865
 
806
#define _VLV_PCS_DW9_CH0		0x8224
866
#define _VLV_PCS_DW9_CH0		0x8224
-
 
867
#define _VLV_PCS_DW9_CH1		0x8424
-
 
868
#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
-
 
869
#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
-
 
870
#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
-
 
871
#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
-
 
872
#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
807
#define _VLV_PCS_DW9_CH1		0x8424
873
#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
Line -... Line 874...
-
 
874
#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
-
 
875
 
-
 
876
#define _VLV_PCS01_DW9_CH0		0x224
-
 
877
#define _VLV_PCS23_DW9_CH0		0x424
-
 
878
#define _VLV_PCS01_DW9_CH1		0x2624
-
 
879
#define _VLV_PCS23_DW9_CH1		0x2824
-
 
880
#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
808
#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
881
#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
809
 
882
 
810
#define _CHV_PCS_DW10_CH0		0x8228
883
#define _CHV_PCS_DW10_CH0		0x8228
811
#define _CHV_PCS_DW10_CH1		0x8428
884
#define _CHV_PCS_DW10_CH1		0x8428
-
 
885
#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
-
 
886
#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
-
 
887
#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
-
 
888
#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
-
 
889
#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
-
 
890
#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
812
#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
891
#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
Line 813... Line 892...
813
#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
892
#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
814
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
893
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
815
 
894
 
Line 820... Line 899...
820
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
899
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
821
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
900
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
Line 822... Line 901...
822
 
901
 
823
#define _VLV_PCS_DW11_CH0		0x822c
902
#define _VLV_PCS_DW11_CH0		0x822c
-
 
903
#define _VLV_PCS_DW11_CH1		0x842c
-
 
904
#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
-
 
905
#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
824
#define _VLV_PCS_DW11_CH1		0x842c
906
#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
Line -... Line 907...
-
 
907
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
-
 
908
 
-
 
909
#define _VLV_PCS01_DW11_CH0		0x022c
-
 
910
#define _VLV_PCS23_DW11_CH0		0x042c
-
 
911
#define _VLV_PCS01_DW11_CH1		0x262c
-
 
912
#define _VLV_PCS23_DW11_CH1		0x282c
-
 
913
#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
825
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
914
#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
826
 
915
 
827
#define _VLV_PCS_DW12_CH0		0x8230
916
#define _VLV_PCS_DW12_CH0		0x8230
Line 828... Line 917...
828
#define _VLV_PCS_DW12_CH1		0x8430
917
#define _VLV_PCS_DW12_CH1		0x8430
Line 836... Line 925...
836
#define _VLV_PCS_DW23_CH1		0x845c
925
#define _VLV_PCS_DW23_CH1		0x845c
837
#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
926
#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Line 838... Line 927...
838
 
927
 
839
#define _VLV_TX_DW2_CH0			0x8288
928
#define _VLV_TX_DW2_CH0			0x8288
840
#define _VLV_TX_DW2_CH1			0x8488
929
#define _VLV_TX_DW2_CH1			0x8488
841
#define   DPIO_SWING_MARGIN_SHIFT	16
930
#define   DPIO_SWING_MARGIN000_SHIFT	16
842
#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
931
#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
843
#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
932
#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
Line 844... Line 933...
844
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
933
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
845
 
934
 
846
#define _VLV_TX_DW3_CH0			0x828c
935
#define _VLV_TX_DW3_CH0			0x828c
847
#define _VLV_TX_DW3_CH1			0x848c
936
#define _VLV_TX_DW3_CH1			0x848c
-
 
937
/* The following bit for CHV phy */
-
 
938
#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
848
/* The following bit for CHV phy */
939
#define   DPIO_SWING_MARGIN101_SHIFT	16
Line 849... Line 940...
849
#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
940
#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
850
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
941
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
851
 
942
 
852
#define _VLV_TX_DW4_CH0			0x8290
943
#define _VLV_TX_DW4_CH0			0x8290
-
 
944
#define _VLV_TX_DW4_CH1			0x8490
-
 
945
#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
853
#define _VLV_TX_DW4_CH1			0x8490
946
#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Line 854... Line 947...
854
#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
947
#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
855
#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
948
#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
856
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
949
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
Line 1001... Line 1094...
1001
 */
1094
 */
1002
#define PGTBL_CTL	0x02020
1095
#define PGTBL_CTL	0x02020
1003
#define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
1096
#define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
1004
#define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
1097
#define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
1005
#define PGTBL_ER	0x02024
1098
#define PGTBL_ER	0x02024
-
 
1099
#define PRB0_BASE (0x2030-0x30)
-
 
1100
#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
-
 
1101
#define PRB2_BASE (0x2050-0x30) /* gen3 */
-
 
1102
#define SRB0_BASE (0x2100-0x30) /* gen2 */
-
 
1103
#define SRB1_BASE (0x2110-0x30) /* gen2 */
-
 
1104
#define SRB2_BASE (0x2120-0x30) /* 830 */
-
 
1105
#define SRB3_BASE (0x2130-0x30) /* 830 */
1006
#define RENDER_RING_BASE	0x02000
1106
#define RENDER_RING_BASE	0x02000
1007
#define BSD_RING_BASE		0x04000
1107
#define BSD_RING_BASE		0x04000
1008
#define GEN6_BSD_RING_BASE	0x12000
1108
#define GEN6_BSD_RING_BASE	0x12000
1009
#define GEN8_BSD2_RING_BASE	0x1c000
1109
#define GEN8_BSD2_RING_BASE	0x1c000
1010
#define VEBOX_RING_BASE		0x1a000
1110
#define VEBOX_RING_BASE		0x1a000
Line 1027... Line 1127...
1027
#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
1127
#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
1028
#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
1128
#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
1029
#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
1129
#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
1030
#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
1130
#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
1031
#define GEN6_NOSYNC 0
1131
#define GEN6_NOSYNC 0
-
 
1132
#define RING_PSMI_CTL(base)	((base)+0x50)
1032
#define RING_MAX_IDLE(base)	((base)+0x54)
1133
#define RING_MAX_IDLE(base)	((base)+0x54)
1033
#define RING_HWS_PGA(base)	((base)+0x80)
1134
#define RING_HWS_PGA(base)	((base)+0x80)
1034
#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
1135
#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
Line 1035... Line 1136...
1035
 
1136
 
Line 1062... Line 1163...
1062
#define VEBOX_HWS_PGA_GEN7	(0x04380)
1163
#define VEBOX_HWS_PGA_GEN7	(0x04380)
1063
#define RING_ACTHD(base)	((base)+0x74)
1164
#define RING_ACTHD(base)	((base)+0x74)
1064
#define RING_ACTHD_UDW(base)	((base)+0x5c)
1165
#define RING_ACTHD_UDW(base)	((base)+0x5c)
1065
#define RING_NOPID(base)	((base)+0x94)
1166
#define RING_NOPID(base)	((base)+0x94)
1066
#define RING_IMR(base)		((base)+0xa8)
1167
#define RING_IMR(base)		((base)+0xa8)
-
 
1168
#define RING_HWSTAM(base)	((base)+0x98)
1067
#define RING_TIMESTAMP(base)	((base)+0x358)
1169
#define RING_TIMESTAMP(base)	((base)+0x358)
1068
#define   TAIL_ADDR		0x001FFFF8
1170
#define   TAIL_ADDR		0x001FFFF8
1069
#define   HEAD_WRAP_COUNT	0xFFE00000
1171
#define   HEAD_WRAP_COUNT	0xFFE00000
1070
#define   HEAD_WRAP_ONE		0x00200000
1172
#define   HEAD_WRAP_ONE		0x00200000
1071
#define   HEAD_ADDR		0x001FFFFC
1173
#define   HEAD_ADDR		0x001FFFFC
Line 1192... Line 1294...
1192
#define GEN7_GT_MODE	0x7008
1294
#define GEN7_GT_MODE	0x7008
1193
#define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
1295
#define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
1194
#define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
1296
#define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
1195
#define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
1297
#define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
1196
#define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
1298
#define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
1197
#define   GEN6_WIZ_HASHING_MASK				(GEN6_WIZ_HASHING(1, 1) << 16)
1299
#define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
1198
#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
1300
#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
Line 1199... Line 1301...
1199
 
1301
 
1200
#define GFX_MODE	0x02520
1302
#define GFX_MODE	0x02520
1201
#define GFX_MODE_GEN7	0x0229c
1303
#define GFX_MODE_GEN7	0x0229c
Line 1246... Line 1348...
1246
					be delivered when out of C3. */
1348
					be delivered when out of C3. */
1247
#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
1349
#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
1248
#define   INSTPM_TLB_INVALIDATE	(1<<9)
1350
#define   INSTPM_TLB_INVALIDATE	(1<<9)
1249
#define   INSTPM_SYNC_FLUSH	(1<<5)
1351
#define   INSTPM_SYNC_FLUSH	(1<<5)
1250
#define ACTHD	        0x020c8
1352
#define ACTHD	        0x020c8
-
 
1353
#define MEM_MODE	0x020cc
-
 
1354
#define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
-
 
1355
#define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
-
 
1356
#define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1251
#define FW_BLC		0x020d8
1357
#define FW_BLC		0x020d8
1252
#define FW_BLC2		0x020dc
1358
#define FW_BLC2		0x020dc
1253
#define FW_BLC_SELF	0x020e0 /* 915+ only */
1359
#define FW_BLC_SELF	0x020e0 /* 915+ only */
1254
#define   FW_BLC_SELF_EN_MASK      (1<<31)
1360
#define   FW_BLC_SELF_EN_MASK      (1<<31)
1255
#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
1361
#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
Line 1352... Line 1458...
1352
#define GEN6_BLITTER_ECOSKPD	0x221d0
1458
#define GEN6_BLITTER_ECOSKPD	0x221d0
1353
#define   GEN6_BLITTER_LOCK_SHIFT			16
1459
#define   GEN6_BLITTER_LOCK_SHIFT			16
1354
#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
1460
#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
Line 1355... Line 1461...
1355
 
1461
 
-
 
1462
#define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
1356
#define GEN6_RC_SLEEP_PSMI_CONTROL	0x2050
1463
#define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
1357
#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
1464
#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
Line 1358... Line 1465...
1358
#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
1465
#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
1359
 
1466
 
Line 1378... Line 1485...
1378
#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
1485
#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
1379
#define GT_BLT_USER_INTERRUPT			(1 << 22)
1486
#define GT_BLT_USER_INTERRUPT			(1 << 22)
1380
#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
1487
#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
1381
#define GT_BSD_USER_INTERRUPT			(1 << 12)
1488
#define GT_BSD_USER_INTERRUPT			(1 << 12)
1382
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1489
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
-
 
1490
#define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
1383
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
1491
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
1384
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
1492
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
1385
#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
1493
#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
1386
#define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
1494
#define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
1387
#define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
1495
#define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
Line 1517... Line 1625...
1517
#define   DPFC_HT_MODIFY	(1<<31)
1625
#define   DPFC_HT_MODIFY	(1<<31)
Line 1518... Line 1626...
1518
 
1626
 
1519
/* Framebuffer compression for Ironlake */
1627
/* Framebuffer compression for Ironlake */
1520
#define ILK_DPFC_CB_BASE	0x43200
1628
#define ILK_DPFC_CB_BASE	0x43200
-
 
1629
#define ILK_DPFC_CONTROL	0x43208
1521
#define ILK_DPFC_CONTROL	0x43208
1630
#define   FBC_CTL_FALSE_COLOR	(1<<10)
1522
/* The bit 28-8 is reserved */
1631
/* The bit 28-8 is reserved */
1523
#define   DPFC_RESERVED		(0x1FFFFF00)
1632
#define   DPFC_RESERVED		(0x1FFFFF00)
1524
#define ILK_DPFC_RECOMP_CTL	0x4320c
1633
#define ILK_DPFC_RECOMP_CTL	0x4320c
1525
#define ILK_DPFC_STATUS		0x43210
1634
#define ILK_DPFC_STATUS		0x43210
Line 1673... Line 1782...
1673
 
1782
 
1674
/* Additional CHV pll/phy registers */
1783
/* Additional CHV pll/phy registers */
1675
#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
1784
#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
1676
#define   DPLL_PORTD_READY_MASK		(0xf)
1785
#define   DPLL_PORTD_READY_MASK		(0xf)
1677
#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
1786
#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
1678
#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
-
 
1679
				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
-
 
1680
#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
-
 
1681
				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
1787
#define   PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1682
#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
1788
#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
Line 1683... Line 1789...
1683
#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
1789
#define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
1684
 
1790
 
1685
/*
1791
/*
1686
 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1792
 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
Line 1951... Line 2057...
1951
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
2057
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
1952
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
2058
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
1953
#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
2059
#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
1954
#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
2060
#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
1955
#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
2061
#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
-
 
2062
#define DCC2			0x10204
-
 
2063
#define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
Line 1956... Line 2064...
1956
 
2064
 
1957
/* Pineview MCH register contains DDR3 setting */
2065
/* Pineview MCH register contains DDR3 setting */
1958
#define CSHRDDR3CTL            0x101a8
2066
#define CSHRDDR3CTL            0x101a8
Line 2234... Line 2342...
2234
#define DDRMPLL1		0X12c20
2342
#define DDRMPLL1		0X12c20
2235
#define PEG_BAND_GAP_DATA	0x14d68
2343
#define PEG_BAND_GAP_DATA	0x14d68
Line 2236... Line 2344...
2236
 
2344
 
2237
#define GEN6_GT_THREAD_STATUS_REG 0x13805c
2345
#define GEN6_GT_THREAD_STATUS_REG 0x13805c
2238
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
-
 
Line 2239... Line 2346...
2239
#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
2346
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2240
 
2347
 
2241
#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2348
#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
Line 2395... Line 2502...
2395
#define _VBLANK_A	0x60010
2502
#define _VBLANK_A	0x60010
2396
#define _VSYNC_A	0x60014
2503
#define _VSYNC_A	0x60014
2397
#define _PIPEASRC	0x6001c
2504
#define _PIPEASRC	0x6001c
2398
#define _BCLRPAT_A	0x60020
2505
#define _BCLRPAT_A	0x60020
2399
#define _VSYNCSHIFT_A	0x60028
2506
#define _VSYNCSHIFT_A	0x60028
-
 
2507
#define _PIPE_MULT_A	0x6002c
Line 2400... Line 2508...
2400
 
2508
 
2401
/* Pipe B timing regs */
2509
/* Pipe B timing regs */
2402
#define _HTOTAL_B	0x61000
2510
#define _HTOTAL_B	0x61000
2403
#define _HBLANK_B	0x61004
2511
#define _HBLANK_B	0x61004
Line 2406... Line 2514...
2406
#define _VBLANK_B	0x61010
2514
#define _VBLANK_B	0x61010
2407
#define _VSYNC_B	0x61014
2515
#define _VSYNC_B	0x61014
2408
#define _PIPEBSRC	0x6101c
2516
#define _PIPEBSRC	0x6101c
2409
#define _BCLRPAT_B	0x61020
2517
#define _BCLRPAT_B	0x61020
2410
#define _VSYNCSHIFT_B	0x61028
2518
#define _VSYNCSHIFT_B	0x61028
-
 
2519
#define _PIPE_MULT_B	0x6102c
Line 2411... Line 2520...
2411
 
2520
 
2412
#define TRANSCODER_A_OFFSET 0x60000
2521
#define TRANSCODER_A_OFFSET 0x60000
2413
#define TRANSCODER_B_OFFSET 0x61000
2522
#define TRANSCODER_B_OFFSET 0x61000
2414
#define TRANSCODER_C_OFFSET 0x62000
2523
#define TRANSCODER_C_OFFSET 0x62000
Line 2426... Line 2535...
2426
#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2535
#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2427
#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2536
#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2428
#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2537
#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2429
#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2538
#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2430
#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
2539
#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
-
 
2540
#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
Line 2431... Line 2541...
2431
 
2541
 
2432
/* HSW+ eDP PSR registers */
2542
/* HSW+ eDP PSR registers */
2433
#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2543
#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2434
#define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
2544
#define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
Line 2455... Line 2565...
2455
#define   EDP_PSR_TP1_TIME_0us			(3<<4)
2565
#define   EDP_PSR_TP1_TIME_0us			(3<<4)
2456
#define   EDP_PSR_IDLE_FRAME_SHIFT		0
2566
#define   EDP_PSR_IDLE_FRAME_SHIFT		0
Line 2457... Line 2567...
2457
 
2567
 
2458
#define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
2568
#define EDP_PSR_AUX_CTL(dev)			(EDP_PSR_BASE(dev) + 0x10)
2459
#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
-
 
2460
#define   EDP_PSR_DPCD_COMMAND		0x80060000
2569
#define EDP_PSR_AUX_DATA1(dev)			(EDP_PSR_BASE(dev) + 0x14)
2461
#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
-
 
2462
#define   EDP_PSR_DPCD_NORMAL_OPERATION	(1<<24)
2570
#define EDP_PSR_AUX_DATA2(dev)			(EDP_PSR_BASE(dev) + 0x18)
2463
#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
2571
#define EDP_PSR_AUX_DATA3(dev)			(EDP_PSR_BASE(dev) + 0x1c)
2464
#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
2572
#define EDP_PSR_AUX_DATA4(dev)			(EDP_PSR_BASE(dev) + 0x20)
Line 2465... Line 2573...
2465
#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
2573
#define EDP_PSR_AUX_DATA5(dev)			(EDP_PSR_BASE(dev) + 0x24)
Line 3474... Line 3582...
3474
#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
3582
#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
3475
#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
3583
#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
3476
#define   DP_LINK_TRAIN_OFF		(3 << 28)
3584
#define   DP_LINK_TRAIN_OFF		(3 << 28)
3477
#define   DP_LINK_TRAIN_MASK		(3 << 28)
3585
#define   DP_LINK_TRAIN_MASK		(3 << 28)
3478
#define   DP_LINK_TRAIN_SHIFT		28
3586
#define   DP_LINK_TRAIN_SHIFT		28
-
 
3587
#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
-
 
3588
#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
Line 3479... Line 3589...
3479
 
3589
 
3480
/* CPT Link training mode */
3590
/* CPT Link training mode */
3481
#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
3591
#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
3482
#define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
3592
#define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
Line 3592... Line 3702...
3592
#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
3702
#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
3593
#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
3703
#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
3594
#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
3704
#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
3595
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
3705
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
3596
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
3706
#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
-
 
3707
#define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
Line 3597... Line 3708...
3597
 
3708
 
3598
/*
3709
/*
3599
 * Computing GMCH M and N values for the Display Port link
3710
 * Computing GMCH M and N values for the Display Port link
3600
 *
3711
 *
Line 3730... Line 3841...
3730
#define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
3841
#define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL<<10)
3731
#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
3842
#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
3732
#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
3843
#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
3733
#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
3844
#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
3734
#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
3845
#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
3735
#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
-
 
3736
#define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
3846
#define   PIPE_A_PSR_STATUS_VLV			(1UL<<6)
3737
#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
3847
#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
3738
#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
3848
#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
3739
#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
3849
#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
3740
#define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
3850
#define   PIPE_B_PSR_STATUS_VLV			(1UL<<3)
Line 3840... Line 3950...
3840
#define   DSPARB_BSTART_MASK	(0x7f)
3950
#define   DSPARB_BSTART_MASK	(0x7f)
3841
#define   DSPARB_BSTART_SHIFT	0
3951
#define   DSPARB_BSTART_SHIFT	0
3842
#define   DSPARB_BEND_SHIFT	9 /* on 855 */
3952
#define   DSPARB_BEND_SHIFT	9 /* on 855 */
3843
#define   DSPARB_AEND_SHIFT	0
3953
#define   DSPARB_AEND_SHIFT	0
Line -... Line 3954...
-
 
3954
 
3844
 
3955
/* pnv/gen4/g4x/vlv/chv */
3845
#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
3956
#define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
3846
#define   DSPFW_SR_SHIFT	23
3957
#define   DSPFW_SR_SHIFT	23
3847
#define   DSPFW_SR_MASK 	(0x1ff<<23)
3958
#define   DSPFW_SR_MASK 	(0x1ff<<23)
3848
#define   DSPFW_CURSORB_SHIFT	16
3959
#define   DSPFW_CURSORB_SHIFT	16
3849
#define   DSPFW_CURSORB_MASK	(0x3f<<16)
3960
#define   DSPFW_CURSORB_MASK	(0x3f<<16)
3850
#define   DSPFW_PLANEB_SHIFT	8
3961
#define   DSPFW_PLANEB_SHIFT	8
-
 
3962
#define   DSPFW_PLANEB_MASK	(0x7f<<8)
-
 
3963
#define   DSPFW_PLANEB_MASK_VLV		(0xff<<8) /* vlv/chv */
3851
#define   DSPFW_PLANEB_MASK	(0x7f<<8)
3964
#define   DSPFW_PLANEA_SHIFT		0
-
 
3965
#define   DSPFW_PLANEA_MASK		(0x7f<<0)
3852
#define   DSPFW_PLANEA_MASK	(0x7f)
3966
#define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
-
 
3967
#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
-
 
3968
#define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
-
 
3969
#define   DSPFW_FBC_SR_SHIFT		28
-
 
3970
#define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
-
 
3971
#define   DSPFW_FBC_HPLL_SR_SHIFT	24
3853
#define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
3972
#define   DSPFW_FBC_HPLL_SR_MASK	(0xf<<24) /* g4x */
-
 
3973
#define   DSPFW_SPRITEB_SHIFT		(16)
-
 
3974
#define   DSPFW_SPRITEB_MASK		(0x7f<<16) /* g4x */
3854
#define   DSPFW_CURSORA_MASK	0x00003f00
3975
#define   DSPFW_SPRITEB_MASK_VLV	(0xff<<16) /* vlv/chv */
-
 
3976
#define   DSPFW_CURSORA_SHIFT	8
3855
#define   DSPFW_CURSORA_SHIFT	8
3977
#define   DSPFW_CURSORA_MASK		(0x3f<<8)
-
 
3978
#define   DSPFW_PLANEC_SHIFT_OLD	0
-
 
3979
#define   DSPFW_PLANEC_MASK_OLD		(0x7f<<0) /* pre-gen4 sprite C */
-
 
3980
#define   DSPFW_SPRITEA_SHIFT		0
-
 
3981
#define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
3856
#define   DSPFW_PLANEC_MASK	(0x7f)
3982
#define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
3857
#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
3983
#define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
3858
#define   DSPFW_HPLL_SR_EN	(1<<31)
-
 
3859
#define   DSPFW_CURSOR_SR_SHIFT	24
3984
#define   DSPFW_HPLL_SR_EN	(1<<31)
-
 
3985
#define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
3860
#define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
3986
#define   DSPFW_CURSOR_SR_SHIFT	24
3861
#define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
3987
#define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
3862
#define   DSPFW_HPLL_CURSOR_SHIFT	16
3988
#define   DSPFW_HPLL_CURSOR_SHIFT	16
-
 
3989
#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
3863
#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
3990
#define   DSPFW_HPLL_SR_SHIFT		0
-
 
3991
#define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
-
 
3992
 
3864
#define   DSPFW_HPLL_SR_MASK		(0x1ff)
3993
/* vlv/chv */
-
 
3994
#define DSPFW4			(VLV_DISPLAY_BASE + 0x70070)
-
 
3995
#define   DSPFW_SPRITEB_WM1_SHIFT	16
-
 
3996
#define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
-
 
3997
#define   DSPFW_CURSORA_WM1_SHIFT	8
-
 
3998
#define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
-
 
3999
#define   DSPFW_SPRITEA_WM1_SHIFT	0
-
 
4000
#define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
-
 
4001
#define DSPFW5			(VLV_DISPLAY_BASE + 0x70074)
-
 
4002
#define   DSPFW_PLANEB_WM1_SHIFT	24
-
 
4003
#define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
-
 
4004
#define   DSPFW_PLANEA_WM1_SHIFT	16
-
 
4005
#define   DSPFW_PLANEA_WM1_MASK		(0xff<<16)
-
 
4006
#define   DSPFW_CURSORB_WM1_SHIFT	8
-
 
4007
#define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
-
 
4008
#define   DSPFW_CURSOR_SR_WM1_SHIFT	0
-
 
4009
#define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
-
 
4010
#define DSPFW6			(VLV_DISPLAY_BASE + 0x70078)
-
 
4011
#define   DSPFW_SR_WM1_SHIFT		0
3865
#define DSPFW4			(dev_priv->info.display_mmio_offset + 0x70070)
4012
#define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
-
 
4013
#define DSPFW7			(VLV_DISPLAY_BASE + 0x7007c)
-
 
4014
#define DSPFW7_CHV		(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
-
 
4015
#define   DSPFW_SPRITED_WM1_SHIFT	24
-
 
4016
#define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
-
 
4017
#define   DSPFW_SPRITED_SHIFT		16
-
 
4018
#define   DSPFW_SPRITED_MASK		(0xff<<16)
-
 
4019
#define   DSPFW_SPRITEC_WM1_SHIFT	8
-
 
4020
#define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
-
 
4021
#define   DSPFW_SPRITEC_SHIFT		0
-
 
4022
#define   DSPFW_SPRITEC_MASK		(0xff<<0)
-
 
4023
#define DSPFW8_CHV		(VLV_DISPLAY_BASE + 0x700b8)
-
 
4024
#define   DSPFW_SPRITEF_WM1_SHIFT	24
-
 
4025
#define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
-
 
4026
#define   DSPFW_SPRITEF_SHIFT		16
-
 
4027
#define   DSPFW_SPRITEF_MASK		(0xff<<16)
-
 
4028
#define   DSPFW_SPRITEE_WM1_SHIFT	8
-
 
4029
#define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
-
 
4030
#define   DSPFW_SPRITEE_SHIFT		0
-
 
4031
#define   DSPFW_SPRITEE_MASK		(0xff<<0)
-
 
4032
#define DSPFW9_CHV		(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
-
 
4033
#define   DSPFW_PLANEC_WM1_SHIFT	24
-
 
4034
#define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
-
 
4035
#define   DSPFW_PLANEC_SHIFT		16
-
 
4036
#define   DSPFW_PLANEC_MASK		(0xff<<16)
-
 
4037
#define   DSPFW_CURSORC_WM1_SHIFT	8
-
 
4038
#define   DSPFW_CURSORC_WM1_MASK	(0x3f<<16)
-
 
4039
#define   DSPFW_CURSORC_SHIFT		0
-
 
4040
#define   DSPFW_CURSORC_MASK		(0x3f<<0)
-
 
4041
 
-
 
4042
/* vlv/chv high order bits */
-
 
4043
#define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
-
 
4044
#define   DSPFW_SR_HI_SHIFT		24
-
 
4045
#define   DSPFW_SR_HI_MASK		(1<<24)
-
 
4046
#define   DSPFW_SPRITEF_HI_SHIFT	23
-
 
4047
#define   DSPFW_SPRITEF_HI_MASK		(1<<23)
-
 
4048
#define   DSPFW_SPRITEE_HI_SHIFT	22
-
 
4049
#define   DSPFW_SPRITEE_HI_MASK		(1<<22)
-
 
4050
#define   DSPFW_PLANEC_HI_SHIFT		21
-
 
4051
#define   DSPFW_PLANEC_HI_MASK		(1<<21)
-
 
4052
#define   DSPFW_SPRITED_HI_SHIFT	20
-
 
4053
#define   DSPFW_SPRITED_HI_MASK		(1<<20)
-
 
4054
#define   DSPFW_SPRITEC_HI_SHIFT	16
-
 
4055
#define   DSPFW_SPRITEC_HI_MASK		(1<<16)
-
 
4056
#define   DSPFW_PLANEB_HI_SHIFT		12
-
 
4057
#define   DSPFW_PLANEB_HI_MASK		(1<<12)
-
 
4058
#define   DSPFW_SPRITEB_HI_SHIFT	8
-
 
4059
#define   DSPFW_SPRITEB_HI_MASK		(1<<8)
-
 
4060
#define   DSPFW_SPRITEA_HI_SHIFT	4
-
 
4061
#define   DSPFW_SPRITEA_HI_MASK		(1<<4)
-
 
4062
#define   DSPFW_PLANEA_HI_SHIFT		0
-
 
4063
#define   DSPFW_PLANEA_HI_MASK		(1<<0)
-
 
4064
#define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70068)
-
 
4065
#define   DSPFW_SR_WM1_HI_SHIFT		24
-
 
4066
#define   DSPFW_SR_WM1_HI_MASK		(1<<24)
-
 
4067
#define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
-
 
4068
#define   DSPFW_SPRITEF_WM1_HI_MASK	(1<<23)
-
 
4069
#define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
-
 
4070
#define   DSPFW_SPRITEE_WM1_HI_MASK	(1<<22)
-
 
4071
#define   DSPFW_PLANEC_WM1_HI_SHIFT	21
-
 
4072
#define   DSPFW_PLANEC_WM1_HI_MASK	(1<<21)
-
 
4073
#define   DSPFW_SPRITED_WM1_HI_SHIFT	20
-
 
4074
#define   DSPFW_SPRITED_WM1_HI_MASK	(1<<20)
-
 
4075
#define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
-
 
4076
#define   DSPFW_SPRITEC_WM1_HI_MASK	(1<<16)
-
 
4077
#define   DSPFW_PLANEB_WM1_HI_SHIFT	12
-
 
4078
#define   DSPFW_PLANEB_WM1_HI_MASK	(1<<12)
-
 
4079
#define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
-
 
4080
#define   DSPFW_SPRITEB_WM1_HI_MASK	(1<<8)
-
 
4081
#define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
-
 
4082
#define   DSPFW_SPRITEA_WM1_HI_MASK	(1<<4)
-
 
4083
#define   DSPFW_PLANEA_WM1_HI_SHIFT	0
Line 3866... Line 4084...
3866
#define DSPFW7			(dev_priv->info.display_mmio_offset + 0x7007c)
4084
#define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
-
 
4085
 
3867
 
4086
/* drain latency register values*/
3868
/* drain latency register values*/
4087
#define DRAIN_LATENCY_PRECISION_16	16
3869
#define DRAIN_LATENCY_PRECISION_32	32
4088
#define DRAIN_LATENCY_PRECISION_32	32
3870
#define DRAIN_LATENCY_PRECISION_64	64
4089
#define DRAIN_LATENCY_PRECISION_64	64
3871
#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
-
 
3872
#define DDL_CURSORA_PRECISION_64	(1<<31)
-
 
3873
#define DDL_CURSORA_PRECISION_32	(0<<31)
-
 
3874
#define DDL_CURSORA_SHIFT		24
-
 
3875
#define DDL_SPRITEB_PRECISION_64	(1<<23)
-
 
3876
#define DDL_SPRITEB_PRECISION_32	(0<<23)
-
 
3877
#define DDL_SPRITEB_SHIFT		16
-
 
3878
#define DDL_SPRITEA_PRECISION_64	(1<<15)
-
 
3879
#define DDL_SPRITEA_PRECISION_32	(0<<15)
-
 
3880
#define DDL_SPRITEA_SHIFT		8
-
 
3881
#define DDL_PLANEA_PRECISION_64		(1<<7)
-
 
3882
#define DDL_PLANEA_PRECISION_32		(0<<7)
-
 
3883
#define DDL_PLANEA_SHIFT		0
-
 
3884
 
-
 
3885
#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
4090
#define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
3886
#define DDL_CURSORB_PRECISION_64	(1<<31)
4091
#define DDL_CURSOR_PRECISION_HIGH	(1<<31)
3887
#define DDL_CURSORB_PRECISION_32	(0<<31)
-
 
3888
#define DDL_CURSORB_SHIFT		24
-
 
3889
#define DDL_SPRITED_PRECISION_64	(1<<23)
-
 
3890
#define DDL_SPRITED_PRECISION_32	(0<<23)
4092
#define DDL_CURSOR_PRECISION_LOW	(0<<31)
3891
#define DDL_SPRITED_SHIFT		16
4093
#define DDL_CURSOR_SHIFT		24
3892
#define DDL_SPRITEC_PRECISION_64	(1<<15)
4094
#define DDL_SPRITE_PRECISION_HIGH(sprite)	(1<<(15+8*(sprite)))
3893
#define DDL_SPRITEC_PRECISION_32	(0<<15)
4095
#define DDL_SPRITE_PRECISION_LOW(sprite)	(0<<(15+8*(sprite)))
3894
#define DDL_SPRITEC_SHIFT		8
4096
#define DDL_SPRITE_SHIFT(sprite)	(8+8*(sprite))
3895
#define DDL_PLANEB_PRECISION_64		(1<<7)
4097
#define DDL_PLANE_PRECISION_HIGH	(1<<7)
3896
#define DDL_PLANEB_PRECISION_32		(0<<7)
-
 
3897
#define DDL_PLANEB_SHIFT		0
-
 
3898
 
-
 
3899
#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)
-
 
3900
#define DDL_CURSORC_PRECISION_64	(1<<31)
-
 
3901
#define DDL_CURSORC_PRECISION_32	(0<<31)
-
 
3902
#define DDL_CURSORC_SHIFT		24
-
 
3903
#define DDL_SPRITEF_PRECISION_64	(1<<23)
-
 
3904
#define DDL_SPRITEF_PRECISION_32	(0<<23)
-
 
3905
#define DDL_SPRITEF_SHIFT		16
-
 
3906
#define DDL_SPRITEE_PRECISION_64	(1<<15)
-
 
3907
#define DDL_SPRITEE_PRECISION_32	(0<<15)
-
 
3908
#define DDL_SPRITEE_SHIFT		8
-
 
3909
#define DDL_PLANEC_PRECISION_64		(1<<7)
4098
#define DDL_PLANE_PRECISION_LOW		(0<<7)
Line 3910... Line 4099...
3910
#define DDL_PLANEC_PRECISION_32		(0<<7)
4099
#define DDL_PLANE_SHIFT			0
3911
#define DDL_PLANEC_SHIFT		0
4100
#define DRAIN_LATENCY_MASK		0x7f
3912
 
4101
 
3913
/* FIFO watermark sizes etc */
4102
/* FIFO watermark sizes etc */
Line 3941... Line 4130...
3941
#define VALLEYVIEW_CURSOR_MAX_WM 64
4130
#define VALLEYVIEW_CURSOR_MAX_WM 64
3942
#define I965_CURSOR_FIFO	64
4131
#define I965_CURSOR_FIFO	64
3943
#define I965_CURSOR_MAX_WM	32
4132
#define I965_CURSOR_MAX_WM	32
3944
#define I965_CURSOR_DFT_WM	8
4133
#define I965_CURSOR_DFT_WM	8
Line -... Line 4134...
-
 
4134
 
-
 
4135
/* Watermark register definitions for SKL */
-
 
4136
#define CUR_WM_A_0		0x70140
-
 
4137
#define CUR_WM_B_0		0x71140
-
 
4138
#define PLANE_WM_1_A_0		0x70240
-
 
4139
#define PLANE_WM_1_B_0		0x71240
-
 
4140
#define PLANE_WM_2_A_0		0x70340
-
 
4141
#define PLANE_WM_2_B_0		0x71340
-
 
4142
#define PLANE_WM_TRANS_1_A_0	0x70268
-
 
4143
#define PLANE_WM_TRANS_1_B_0	0x71268
-
 
4144
#define PLANE_WM_TRANS_2_A_0	0x70368
-
 
4145
#define PLANE_WM_TRANS_2_B_0	0x71368
-
 
4146
#define CUR_WM_TRANS_A_0	0x70168
-
 
4147
#define CUR_WM_TRANS_B_0	0x71168
-
 
4148
#define   PLANE_WM_EN		(1 << 31)
-
 
4149
#define   PLANE_WM_LINES_SHIFT	14
-
 
4150
#define   PLANE_WM_LINES_MASK	0x1f
-
 
4151
#define   PLANE_WM_BLOCKS_MASK	0x3ff
-
 
4152
 
-
 
4153
#define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
-
 
4154
#define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
-
 
4155
#define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
-
 
4156
 
-
 
4157
#define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
-
 
4158
#define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
-
 
4159
#define _PLANE_WM_BASE(pipe, plane)	\
-
 
4160
			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-
 
4161
#define PLANE_WM(pipe, plane, level)	\
-
 
4162
			(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-
 
4163
#define _PLANE_WM_TRANS_1(pipe)	\
-
 
4164
			_PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
-
 
4165
#define _PLANE_WM_TRANS_2(pipe)	\
-
 
4166
			_PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
-
 
4167
#define PLANE_WM_TRANS(pipe, plane)	\
-
 
4168
		_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
3945
 
4169
 
3946
/* define the Watermark register on Ironlake */
4170
/* define the Watermark register on Ironlake */
3947
#define WM0_PIPEA_ILK		0x45100
4171
#define WM0_PIPEA_ILK		0x45100
3948
#define  WM0_PIPE_PLANE_MASK	(0xffff<<16)
4172
#define  WM0_PIPE_PLANE_MASK	(0xffff<<16)
3949
#define  WM0_PIPE_PLANE_SHIFT	16
4173
#define  WM0_PIPE_PLANE_SHIFT	16
Line 4024... Line 4248...
4024
/* Cursor A & B regs */
4248
/* Cursor A & B regs */
4025
#define _CURACNTR		0x70080
4249
#define _CURACNTR		0x70080
4026
/* Old style CUR*CNTR flags (desktop 8xx) */
4250
/* Old style CUR*CNTR flags (desktop 8xx) */
4027
#define   CURSOR_ENABLE		0x80000000
4251
#define   CURSOR_ENABLE		0x80000000
4028
#define   CURSOR_GAMMA_ENABLE	0x40000000
4252
#define   CURSOR_GAMMA_ENABLE	0x40000000
4029
#define   CURSOR_STRIDE_MASK	0x30000000
4253
#define   CURSOR_STRIDE_SHIFT	28
-
 
4254
#define   CURSOR_STRIDE(x)	((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4030
#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
4255
#define   CURSOR_PIPE_CSC_ENABLE (1<<24)
4031
#define   CURSOR_FORMAT_SHIFT	24
4256
#define   CURSOR_FORMAT_SHIFT	24
4032
#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
4257
#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
4033
#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
4258
#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
4034
#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
4259
#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
Line 4046... Line 4271...
4046
#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4271
#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4047
#define   MCURSOR_PIPE_SELECT	(1 << 28)
4272
#define   MCURSOR_PIPE_SELECT	(1 << 28)
4048
#define   MCURSOR_PIPE_A	0x00
4273
#define   MCURSOR_PIPE_A	0x00
4049
#define   MCURSOR_PIPE_B	(1 << 28)
4274
#define   MCURSOR_PIPE_B	(1 << 28)
4050
#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
4275
#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-
 
4276
#define   CURSOR_ROTATE_180	(1<<15)
4051
#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
4277
#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
4052
#define _CURABASE		0x70084
4278
#define _CURABASE		0x70084
4053
#define _CURAPOS		0x70088
4279
#define _CURAPOS		0x70088
4054
#define   CURSOR_POS_MASK       0x007FF
4280
#define   CURSOR_POS_MASK       0x007FF
4055
#define   CURSOR_POS_SIGN       0x8000
4281
#define   CURSOR_POS_SIGN       0x8000
Line 4109... Line 4335...
4109
#define   DISPPLANE_SRC_KEY_DISABLE		0
4335
#define   DISPPLANE_SRC_KEY_DISABLE		0
4110
#define   DISPPLANE_LINE_DOUBLE			(1<<20)
4336
#define   DISPPLANE_LINE_DOUBLE			(1<<20)
4111
#define   DISPPLANE_NO_LINE_DOUBLE		0
4337
#define   DISPPLANE_NO_LINE_DOUBLE		0
4112
#define   DISPPLANE_STEREO_POLARITY_FIRST	0
4338
#define   DISPPLANE_STEREO_POLARITY_FIRST	0
4113
#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
4339
#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
-
 
4340
#define   DISPPLANE_ALPHA_PREMULTIPLY		(1<<16) /* CHV pipe B */
-
 
4341
#define   DISPPLANE_ROTATE_180			(1<<15)
4114
#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
4342
#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
4115
#define   DISPPLANE_TILED			(1<<10)
4343
#define   DISPPLANE_TILED			(1<<10)
-
 
4344
#define   DISPPLANE_MIRROR			(1<<8) /* CHV pipe B */
4116
#define _DSPAADDR				0x70184
4345
#define _DSPAADDR				0x70184
4117
#define _DSPASTRIDE				0x70188
4346
#define _DSPASTRIDE				0x70188
4118
#define _DSPAPOS				0x7018C /* reserved */
4347
#define _DSPAPOS				0x7018C /* reserved */
4119
#define _DSPASIZE				0x70190
4348
#define _DSPASIZE				0x70190
4120
#define _DSPASURF				0x7019C /* 965+ only */
4349
#define _DSPASURF				0x7019C /* 965+ only */
Line 4131... Line 4360...
4131
#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4360
#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4132
#define DSPLINOFF(plane) DSPADDR(plane)
4361
#define DSPLINOFF(plane) DSPADDR(plane)
4133
#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4362
#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4134
#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
4363
#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
Line -... Line 4364...
-
 
4364
 
-
 
4365
/* CHV pipe B blender and primary plane */
-
 
4366
#define _CHV_BLEND_A		0x60a00
-
 
4367
#define   CHV_BLEND_LEGACY		(0<<30)
-
 
4368
#define   CHV_BLEND_ANDROID		(1<<30)
-
 
4369
#define   CHV_BLEND_MPO			(2<<30)
-
 
4370
#define   CHV_BLEND_MASK		(3<<30)
-
 
4371
#define _CHV_CANVAS_A		0x60a04
-
 
4372
#define _PRIMPOS_A		0x60a08
-
 
4373
#define _PRIMSIZE_A		0x60a0c
-
 
4374
#define _PRIMCNSTALPHA_A	0x60a10
-
 
4375
#define   PRIM_CONST_ALPHA_ENABLE	(1<<31)
-
 
4376
 
-
 
4377
#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
-
 
4378
#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
-
 
4379
#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
-
 
4380
#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
-
 
4381
#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4135
 
4382
 
4136
/* Display/Sprite base address macros */
4383
/* Display/Sprite base address macros */
4137
#define DISP_BASEADDR_MASK	(0xfffff000)
4384
#define DISP_BASEADDR_MASK	(0xfffff000)
4138
#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
4385
#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
Line 4193... Line 4440...
4193
#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
4440
#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
4194
#define   DVS_YUV_ORDER_YUYV	(0<<16)
4441
#define   DVS_YUV_ORDER_YUYV	(0<<16)
4195
#define   DVS_YUV_ORDER_UYVY	(1<<16)
4442
#define   DVS_YUV_ORDER_UYVY	(1<<16)
4196
#define   DVS_YUV_ORDER_YVYU	(2<<16)
4443
#define   DVS_YUV_ORDER_YVYU	(2<<16)
4197
#define   DVS_YUV_ORDER_VYUY	(3<<16)
4444
#define   DVS_YUV_ORDER_VYUY	(3<<16)
-
 
4445
#define   DVS_ROTATE_180	(1<<15)
4198
#define   DVS_DEST_KEY		(1<<2)
4446
#define   DVS_DEST_KEY		(1<<2)
4199
#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
4447
#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
4200
#define   DVS_TILED		(1<<10)
4448
#define   DVS_TILED		(1<<10)
4201
#define _DVSALINOFF		0x72184
4449
#define _DVSALINOFF		0x72184
4202
#define _DVSASTRIDE		0x72188
4450
#define _DVSASTRIDE		0x72188
Line 4263... Line 4511...
4263
#define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
4511
#define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
4264
#define   SPRITE_YUV_ORDER_YUYV		(0<<16)
4512
#define   SPRITE_YUV_ORDER_YUYV		(0<<16)
4265
#define   SPRITE_YUV_ORDER_UYVY		(1<<16)
4513
#define   SPRITE_YUV_ORDER_UYVY		(1<<16)
4266
#define   SPRITE_YUV_ORDER_YVYU		(2<<16)
4514
#define   SPRITE_YUV_ORDER_YVYU		(2<<16)
4267
#define   SPRITE_YUV_ORDER_VYUY		(3<<16)
4515
#define   SPRITE_YUV_ORDER_VYUY		(3<<16)
-
 
4516
#define   SPRITE_ROTATE_180		(1<<15)
4268
#define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
4517
#define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
4269
#define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
4518
#define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
4270
#define   SPRITE_TILED			(1<<10)
4519
#define   SPRITE_TILED			(1<<10)
4271
#define   SPRITE_DEST_KEY		(1<<2)
4520
#define   SPRITE_DEST_KEY		(1<<2)
4272
#define _SPRA_LINOFF		0x70284
4521
#define _SPRA_LINOFF		0x70284
Line 4330... Line 4579...
4330
#define   SP_FORMAT_BGRA8888		(7<<26)
4579
#define   SP_FORMAT_BGRA8888		(7<<26)
4331
#define   SP_FORMAT_RGBX1010102		(8<<26)
4580
#define   SP_FORMAT_RGBX1010102		(8<<26)
4332
#define   SP_FORMAT_RGBA1010102		(9<<26)
4581
#define   SP_FORMAT_RGBA1010102		(9<<26)
4333
#define   SP_FORMAT_RGBX8888		(0xe<<26)
4582
#define   SP_FORMAT_RGBX8888		(0xe<<26)
4334
#define   SP_FORMAT_RGBA8888		(0xf<<26)
4583
#define   SP_FORMAT_RGBA8888		(0xf<<26)
-
 
4584
#define   SP_ALPHA_PREMULTIPLY		(1<<23) /* CHV pipe B */
4335
#define   SP_SOURCE_KEY			(1<<22)
4585
#define   SP_SOURCE_KEY			(1<<22)
4336
#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
4586
#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
4337
#define   SP_YUV_ORDER_YUYV		(0<<16)
4587
#define   SP_YUV_ORDER_YUYV		(0<<16)
4338
#define   SP_YUV_ORDER_UYVY		(1<<16)
4588
#define   SP_YUV_ORDER_UYVY		(1<<16)
4339
#define   SP_YUV_ORDER_YVYU		(2<<16)
4589
#define   SP_YUV_ORDER_YVYU		(2<<16)
4340
#define   SP_YUV_ORDER_VYUY		(3<<16)
4590
#define   SP_YUV_ORDER_VYUY		(3<<16)
-
 
4591
#define   SP_ROTATE_180			(1<<15)
4341
#define   SP_TILED			(1<<10)
4592
#define   SP_TILED			(1<<10)
-
 
4593
#define   SP_MIRROR			(1<<8) /* CHV pipe B */
4342
#define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
4594
#define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
4343
#define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
4595
#define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
4344
#define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
4596
#define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
4345
#define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
4597
#define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
4346
#define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
4598
#define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
4347
#define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
4599
#define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
4348
#define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
4600
#define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
4349
#define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
4601
#define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
4350
#define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
4602
#define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
4351
#define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
4603
#define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
-
 
4604
#define   SP_CONST_ALPHA_ENABLE		(1<<31)
4352
#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
4605
#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
Line 4353... Line 4606...
4353
 
4606
 
4354
#define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
4607
#define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
4355
#define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
4608
#define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
Line 4375... Line 4628...
4375
#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4628
#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4376
#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4629
#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4377
#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4630
#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4378
#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4631
#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
Line -... Line 4632...
-
 
4632
 
-
 
4633
/*
-
 
4634
 * CHV pipe B sprite CSC
-
 
4635
 *
-
 
4636
 * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
-
 
4637
 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
-
 
4638
 * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
-
 
4639
 */
-
 
4640
#define SPCSCYGOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
-
 
4641
#define SPCSCCBOFF(sprite)	(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
-
 
4642
#define SPCSCCROFF(sprite)	(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
-
 
4643
#define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
-
 
4644
#define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
-
 
4645
 
-
 
4646
#define SPCSCC01(sprite)	(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
-
 
4647
#define SPCSCC23(sprite)	(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
-
 
4648
#define SPCSCC45(sprite)	(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
-
 
4649
#define SPCSCC67(sprite)	(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
-
 
4650
#define SPCSCC8(sprite)		(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
-
 
4651
#define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
-
 
4652
#define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
-
 
4653
 
-
 
4654
#define SPCSCYGICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
-
 
4655
#define SPCSCCBICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
-
 
4656
#define SPCSCCRICLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
-
 
4657
#define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
-
 
4658
#define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
-
 
4659
 
-
 
4660
#define SPCSCYGOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
-
 
4661
#define SPCSCCBOCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
-
 
4662
#define SPCSCCROCLAMP(sprite)	(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
-
 
4663
#define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
-
 
4664
#define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
-
 
4665
 
-
 
4666
/* Skylake plane registers */
-
 
4667
 
-
 
4668
#define _PLANE_CTL_1_A				0x70180
-
 
4669
#define _PLANE_CTL_2_A				0x70280
-
 
4670
#define _PLANE_CTL_3_A				0x70380
-
 
4671
#define   PLANE_CTL_ENABLE			(1 << 31)
-
 
4672
#define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)
-
 
4673
#define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
-
 
4674
#define   PLANE_CTL_FORMAT_YUV422		(  0 << 24)
-
 
4675
#define   PLANE_CTL_FORMAT_NV12			(  1 << 24)
-
 
4676
#define   PLANE_CTL_FORMAT_XRGB_2101010		(  2 << 24)
-
 
4677
#define   PLANE_CTL_FORMAT_XRGB_8888		(  4 << 24)
-
 
4678
#define   PLANE_CTL_FORMAT_XRGB_16161616F	(  6 << 24)
-
 
4679
#define   PLANE_CTL_FORMAT_AYUV			(  8 << 24)
-
 
4680
#define   PLANE_CTL_FORMAT_INDEXED		( 12 << 24)
-
 
4681
#define   PLANE_CTL_FORMAT_RGB_565		( 14 << 24)
-
 
4682
#define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23)
-
 
4683
#define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
-
 
4684
#define   PLANE_CTL_KEY_ENABLE_SOURCE		(  1 << 21)
-
 
4685
#define   PLANE_CTL_KEY_ENABLE_DESTINATION	(  2 << 21)
-
 
4686
#define   PLANE_CTL_ORDER_BGRX			(0 << 20)
-
 
4687
#define   PLANE_CTL_ORDER_RGBX			(1 << 20)
-
 
4688
#define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
-
 
4689
#define   PLANE_CTL_YUV422_YUYV			(  0 << 16)
-
 
4690
#define   PLANE_CTL_YUV422_UYVY			(  1 << 16)
-
 
4691
#define   PLANE_CTL_YUV422_YVYU			(  2 << 16)
-
 
4692
#define   PLANE_CTL_YUV422_VYUY			(  3 << 16)
-
 
4693
#define   PLANE_CTL_DECOMPRESSION_ENABLE	(1 << 15)
-
 
4694
#define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
-
 
4695
#define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13)
-
 
4696
#define   PLANE_CTL_TILED_MASK			(0x7 << 10)
-
 
4697
#define   PLANE_CTL_TILED_LINEAR		(  0 << 10)
-
 
4698
#define   PLANE_CTL_TILED_X			(  1 << 10)
-
 
4699
#define   PLANE_CTL_TILED_Y			(  4 << 10)
-
 
4700
#define   PLANE_CTL_TILED_YF			(  5 << 10)
-
 
4701
#define   PLANE_CTL_ALPHA_MASK			(0x3 << 4)
-
 
4702
#define   PLANE_CTL_ALPHA_DISABLE		(  0 << 4)
-
 
4703
#define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(  2 << 4)
-
 
4704
#define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(  3 << 4)
-
 
4705
#define   PLANE_CTL_ROTATE_MASK			0x3
-
 
4706
#define   PLANE_CTL_ROTATE_0			0x0
-
 
4707
#define   PLANE_CTL_ROTATE_180			0x2
-
 
4708
#define _PLANE_STRIDE_1_A			0x70188
-
 
4709
#define _PLANE_STRIDE_2_A			0x70288
-
 
4710
#define _PLANE_STRIDE_3_A			0x70388
-
 
4711
#define _PLANE_POS_1_A				0x7018c
-
 
4712
#define _PLANE_POS_2_A				0x7028c
-
 
4713
#define _PLANE_POS_3_A				0x7038c
-
 
4714
#define _PLANE_SIZE_1_A				0x70190
-
 
4715
#define _PLANE_SIZE_2_A				0x70290
-
 
4716
#define _PLANE_SIZE_3_A				0x70390
-
 
4717
#define _PLANE_SURF_1_A				0x7019c
-
 
4718
#define _PLANE_SURF_2_A				0x7029c
-
 
4719
#define _PLANE_SURF_3_A				0x7039c
-
 
4720
#define _PLANE_OFFSET_1_A			0x701a4
-
 
4721
#define _PLANE_OFFSET_2_A			0x702a4
-
 
4722
#define _PLANE_OFFSET_3_A			0x703a4
-
 
4723
#define _PLANE_KEYVAL_1_A			0x70194
-
 
4724
#define _PLANE_KEYVAL_2_A			0x70294
-
 
4725
#define _PLANE_KEYMSK_1_A			0x70198
-
 
4726
#define _PLANE_KEYMSK_2_A			0x70298
-
 
4727
#define _PLANE_KEYMAX_1_A			0x701a0
-
 
4728
#define _PLANE_KEYMAX_2_A			0x702a0
-
 
4729
#define _PLANE_BUF_CFG_1_A			0x7027c
-
 
4730
#define _PLANE_BUF_CFG_2_A			0x7037c
-
 
4731
 
-
 
4732
#define _PLANE_CTL_1_B				0x71180
-
 
4733
#define _PLANE_CTL_2_B				0x71280
-
 
4734
#define _PLANE_CTL_3_B				0x71380
-
 
4735
#define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
-
 
4736
#define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-
 
4737
#define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
-
 
4738
#define PLANE_CTL(pipe, plane)	\
-
 
4739
	_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
-
 
4740
 
-
 
4741
#define _PLANE_STRIDE_1_B			0x71188
-
 
4742
#define _PLANE_STRIDE_2_B			0x71288
-
 
4743
#define _PLANE_STRIDE_3_B			0x71388
-
 
4744
#define _PLANE_STRIDE_1(pipe)	\
-
 
4745
	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
-
 
4746
#define _PLANE_STRIDE_2(pipe)	\
-
 
4747
	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-
 
4748
#define _PLANE_STRIDE_3(pipe)	\
-
 
4749
	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
-
 
4750
#define PLANE_STRIDE(pipe, plane)	\
-
 
4751
	_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-
 
4752
 
-
 
4753
#define _PLANE_POS_1_B				0x7118c
-
 
4754
#define _PLANE_POS_2_B				0x7128c
-
 
4755
#define _PLANE_POS_3_B				0x7138c
-
 
4756
#define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
-
 
4757
#define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-
 
4758
#define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
-
 
4759
#define PLANE_POS(pipe, plane)	\
-
 
4760
	_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
-
 
4761
 
-
 
4762
#define _PLANE_SIZE_1_B				0x71190
-
 
4763
#define _PLANE_SIZE_2_B				0x71290
-
 
4764
#define _PLANE_SIZE_3_B				0x71390
-
 
4765
#define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
-
 
4766
#define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-
 
4767
#define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
-
 
4768
#define PLANE_SIZE(pipe, plane)	\
-
 
4769
	_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
-
 
4770
 
-
 
4771
#define _PLANE_SURF_1_B				0x7119c
-
 
4772
#define _PLANE_SURF_2_B				0x7129c
-
 
4773
#define _PLANE_SURF_3_B				0x7139c
-
 
4774
#define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
-
 
4775
#define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-
 
4776
#define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
-
 
4777
#define PLANE_SURF(pipe, plane)	\
-
 
4778
	_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-
 
4779
 
-
 
4780
#define _PLANE_OFFSET_1_B			0x711a4
-
 
4781
#define _PLANE_OFFSET_2_B			0x712a4
-
 
4782
#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
-
 
4783
#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
-
 
4784
#define PLANE_OFFSET(pipe, plane)	\
-
 
4785
	_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-
 
4786
 
-
 
4787
#define _PLANE_KEYVAL_1_B			0x71194
-
 
4788
#define _PLANE_KEYVAL_2_B			0x71294
-
 
4789
#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
-
 
4790
#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
-
 
4791
#define PLANE_KEYVAL(pipe, plane)	\
-
 
4792
	_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-
 
4793
 
-
 
4794
#define _PLANE_KEYMSK_1_B			0x71198
-
 
4795
#define _PLANE_KEYMSK_2_B			0x71298
-
 
4796
#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
-
 
4797
#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
-
 
4798
#define PLANE_KEYMSK(pipe, plane)	\
-
 
4799
	_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-
 
4800
 
-
 
4801
#define _PLANE_KEYMAX_1_B			0x711a0
-
 
4802
#define _PLANE_KEYMAX_2_B			0x712a0
-
 
4803
#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
-
 
4804
#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
-
 
4805
#define PLANE_KEYMAX(pipe, plane)	\
-
 
4806
	_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-
 
4807
 
-
 
4808
#define _PLANE_BUF_CFG_1_B			0x7127c
-
 
4809
#define _PLANE_BUF_CFG_2_B			0x7137c
-
 
4810
#define _PLANE_BUF_CFG_1(pipe)	\
-
 
4811
	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-
 
4812
#define _PLANE_BUF_CFG_2(pipe)	\
-
 
4813
	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-
 
4814
#define PLANE_BUF_CFG(pipe, plane)	\
-
 
4815
	_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-
 
4816
 
-
 
4817
/* SKL new cursor registers */
-
 
4818
#define _CUR_BUF_CFG_A				0x7017c
-
 
4819
#define _CUR_BUF_CFG_B				0x7117c
-
 
4820
#define CUR_BUF_CFG(pipe)	_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
4379
 
4821
 
4380
/* VBIOS regs */
4822
/* VBIOS regs */
4381
#define VGACNTRL		0x71400
4823
#define VGACNTRL		0x71400
4382
# define VGA_DISP_DISABLE			(1 << 31)
4824
# define VGA_DISP_DISABLE			(1 << 31)
4383
# define VGA_2X_MODE				(1 << 30)
4825
# define VGA_2X_MODE				(1 << 30)
Line 4490... Line 4932...
4490
#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4932
#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4491
#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4933
#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4492
#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4934
#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4493
#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4935
#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Line -... Line 4936...
-
 
4936
 
-
 
4937
#define _PSA_CTL		0x68180
-
 
4938
#define _PSB_CTL		0x68980
-
 
4939
#define PS_ENABLE		(1<<31)
-
 
4940
#define _PSA_WIN_SZ		0x68174
-
 
4941
#define _PSB_WIN_SZ		0x68974
-
 
4942
#define _PSA_WIN_POS		0x68170
-
 
4943
#define _PSB_WIN_POS		0x68970
-
 
4944
 
-
 
4945
#define PS_CTL(pipe)		_PIPE(pipe, _PSA_CTL, _PSB_CTL)
-
 
4946
#define PS_WIN_SZ(pipe)		_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
-
 
4947
#define PS_WIN_POS(pipe)	_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
4494
 
4948
 
4495
/* legacy palette */
4949
/* legacy palette */
4496
#define _LGC_PALETTE_A           0x4a000
4950
#define _LGC_PALETTE_A           0x4a000
4497
#define _LGC_PALETTE_B           0x4a800
4951
#define _LGC_PALETTE_B           0x4a800
Line 4611... Line 5065...
4611
#define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
5065
#define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
4612
#define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
5066
#define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
4613
#define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
5067
#define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
4614
#define  GEN8_PIPE_VSYNC		(1 << 1)
5068
#define  GEN8_PIPE_VSYNC		(1 << 1)
4615
#define  GEN8_PIPE_VBLANK		(1 << 0)
5069
#define  GEN8_PIPE_VBLANK		(1 << 0)
-
 
5070
#define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
-
 
5071
#define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
-
 
5072
#define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
-
 
5073
#define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
-
 
5074
#define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
-
 
5075
#define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
-
 
5076
#define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
-
 
5077
#define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + p))
4616
#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5078
#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4617
	(GEN8_PIPE_CURSOR_FAULT | \
5079
	(GEN8_PIPE_CURSOR_FAULT | \
4618
	 GEN8_PIPE_SPRITE_FAULT | \
5080
	 GEN8_PIPE_SPRITE_FAULT | \
4619
	 GEN8_PIPE_PRIMARY_FAULT)
5081
	 GEN8_PIPE_PRIMARY_FAULT)
-
 
5082
#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
-
 
5083
	(GEN9_PIPE_CURSOR_FAULT | \
-
 
5084
	 GEN9_PIPE_PLANE3_FAULT | \
-
 
5085
	 GEN9_PIPE_PLANE2_FAULT | \
-
 
5086
	 GEN9_PIPE_PLANE1_FAULT)
Line 4620... Line 5087...
4620
 
5087
 
4621
#define GEN8_DE_PORT_ISR 0x44440
5088
#define GEN8_DE_PORT_ISR 0x44440
4622
#define GEN8_DE_PORT_IMR 0x44444
5089
#define GEN8_DE_PORT_IMR 0x44444
4623
#define GEN8_DE_PORT_IIR 0x44448
5090
#define GEN8_DE_PORT_IIR 0x44448
4624
#define GEN8_DE_PORT_IER 0x4444c
5091
#define GEN8_DE_PORT_IER 0x4444c
-
 
5092
#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
-
 
5093
#define  GEN9_AUX_CHANNEL_D		(1 << 27)
-
 
5094
#define  GEN9_AUX_CHANNEL_C		(1 << 26)
4625
#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
5095
#define  GEN9_AUX_CHANNEL_B		(1 << 25)
Line 4626... Line 5096...
4626
#define  GEN8_AUX_CHANNEL_A		(1 << 0)
5096
#define  GEN8_AUX_CHANNEL_A		(1 << 0)
4627
 
5097
 
4628
#define GEN8_DE_MISC_ISR 0x44460
5098
#define GEN8_DE_MISC_ISR 0x44460
Line 4704... Line 5174...
4704
#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
5174
#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
Line 4705... Line 5175...
4705
 
5175
 
4706
/* GEN8 chicken */
5176
/* GEN8 chicken */
4707
#define HDC_CHICKEN0				0x7300
5177
#define HDC_CHICKEN0				0x7300
-
 
5178
#define  HDC_FORCE_NON_COHERENT			(1<<4)
-
 
5179
#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
Line 4708... Line 5180...
4708
#define  HDC_FORCE_NON_COHERENT			(1<<4)
5180
#define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
4709
 
5181
 
4710
/* WaCatErrorRejectionIssue */
5182
/* WaCatErrorRejectionIssue */
Line 5244... Line 5716...
5244
 
5716
 
5245
/* vlv has 2 sets of panel control regs. */
5717
/* vlv has 2 sets of panel control regs. */
5246
#define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
5718
#define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
5247
#define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
5719
#define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
5248
#define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
-
 
5249
#define  PANEL_PORT_SELECT_DPB_VLV	(1 << 30)
5720
#define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
5250
#define  PANEL_PORT_SELECT_DPC_VLV	(2 << 30)
5721
#define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
5251
#define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
5722
#define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
Line 5252... Line 5723...
5252
#define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
5723
#define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
5253
 
5724
 
Line 5405... Line 5876...
5405
#define  VLV_GTLC_PW_STATUS			0x130094
5876
#define  VLV_GTLC_PW_STATUS			0x130094
5406
#define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
5877
#define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
5407
#define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
5878
#define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
5408
#define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
5879
#define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
5409
#define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
5880
#define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
5410
#define VLV_GTLC_SURVIVABILITY_REG              0x130098
-
 
5411
#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
5881
#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
-
 
5882
#define  FORCEWAKE_MEDIA_GEN9			0xa270
-
 
5883
#define  FORCEWAKE_RENDER_GEN9			0xa278
-
 
5884
#define  FORCEWAKE_BLITTER_GEN9			0xa188
-
 
5885
#define  FORCEWAKE_ACK_MEDIA_GEN9		0x0D88
-
 
5886
#define  FORCEWAKE_ACK_RENDER_GEN9		0x0D84
-
 
5887
#define  FORCEWAKE_ACK_BLITTER_GEN9		0x130044
5412
#define   FORCEWAKE_KERNEL			0x1
5888
#define   FORCEWAKE_KERNEL			0x1
5413
#define   FORCEWAKE_USER			0x2
5889
#define   FORCEWAKE_USER			0x2
5414
#define  FORCEWAKE_MT_ACK			0x130040
5890
#define  FORCEWAKE_MT_ACK			0x130040
5415
#define  ECOBUS					0xa180
5891
#define  ECOBUS					0xa180
5416
#define    FORCEWAKE_MT_ENABLE			(1<<5)
5892
#define    FORCEWAKE_MT_ENABLE			(1<<5)
Line 5543... Line 6019...
5543
#define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
6019
#define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
5544
#define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_THRESHOLD | \
6020
#define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_THRESHOLD | \
5545
						 GEN6_PM_RP_DOWN_THRESHOLD | \
6021
						 GEN6_PM_RP_DOWN_THRESHOLD | \
5546
						 GEN6_PM_RP_DOWN_TIMEOUT)
6022
						 GEN6_PM_RP_DOWN_TIMEOUT)
Line 5547... Line -...
5547
 
-
 
5548
#define CHV_CZ_CLOCK_FREQ_MODE_200			200
-
 
5549
#define CHV_CZ_CLOCK_FREQ_MODE_267			267
-
 
5550
#define CHV_CZ_CLOCK_FREQ_MODE_320			320
-
 
5551
#define CHV_CZ_CLOCK_FREQ_MODE_333			333
-
 
5552
#define CHV_CZ_CLOCK_FREQ_MODE_400			400
-
 
5553
 
6023
 
5554
#define GEN7_GT_SCRATCH_BASE			0x4F100
6024
#define GEN7_GT_SCRATCH_BASE			0x4F100
Line 5555... Line 6025...
5555
#define GEN7_GT_SCRATCH_REG_NUM			8
6025
#define GEN7_GT_SCRATCH_REG_NUM			8
5556
 
6026
 
Line 5584... Line 6054...
5584
#define   GEN6_PCODE_READ_D_COMP		0x10
6054
#define   GEN6_PCODE_READ_D_COMP		0x10
5585
#define   GEN6_PCODE_WRITE_D_COMP		0x11
6055
#define   GEN6_PCODE_WRITE_D_COMP		0x11
5586
#define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
6056
#define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
5587
#define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
6057
#define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
5588
#define   DISPLAY_IPS_CONTROL			0x19
6058
#define   DISPLAY_IPS_CONTROL			0x19
-
 
6059
#define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
5589
#define GEN6_PCODE_DATA				0x138128
6060
#define GEN6_PCODE_DATA				0x138128
5590
#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
6061
#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
5591
#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
6062
#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
-
 
6063
#define GEN6_PCODE_DATA1			0x13812C
-
 
6064
 
-
 
6065
#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
-
 
6066
#define   GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
-
 
6067
#define   GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
-
 
6068
#define   GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
-
 
6069
#define   GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
Line 5592... Line 6070...
5592
 
6070
 
5593
#define GEN6_GT_CORE_STATUS		0x138060
6071
#define GEN6_GT_CORE_STATUS		0x138060
5594
#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
6072
#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
5595
#define   GEN6_RCn_MASK			7
6073
#define   GEN6_RCn_MASK			7
Line 5624... Line 6102...
5624
#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
6102
#define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
5625
#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
6103
#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
5626
#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
6104
#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
5627
#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
6105
#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
Line -... Line 6106...
-
 
6106
 
-
 
6107
#define GEN9_HALF_SLICE_CHICKEN5	0xe188
-
 
6108
#define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
5628
 
6109
 
5629
#define GEN8_ROW_CHICKEN		0xe4f0
6110
#define GEN8_ROW_CHICKEN		0xe4f0
5630
#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
6111
#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
Line 5631... Line 6112...
5631
#define   STALL_DOP_GATING_DISABLE		(1<<5)
6112
#define   STALL_DOP_GATING_DISABLE		(1<<5)
Line 5639... Line 6120...
5639
 
6120
 
5640
#define HALF_SLICE_CHICKEN3		0xe184
6121
#define HALF_SLICE_CHICKEN3		0xe184
5641
#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
6122
#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
Line -... Line 6123...
-
 
6123
#define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
5642
#define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
6124
 
5643
 
6125
/* Audio */
5644
#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
6126
#define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
5645
#define INTEL_AUDIO_DEVCL		0x808629FB
6127
#define INTEL_AUDIO_DEVCL		0x808629FB
Line 5646... Line 6128...
5646
#define INTEL_AUDIO_DEVBLC		0x80862801
6128
#define INTEL_AUDIO_DEVBLC		0x80862801
5647
#define INTEL_AUDIO_DEVCTG		0x80862802
6129
#define INTEL_AUDIO_DEVCTG		0x80862802
5648
 
6130
 
5649
#define G4X_AUD_CNTL_ST			0x620B4
6131
#define G4X_AUD_CNTL_ST			0x620B4
5650
#define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
6132
#define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
5651
#define G4X_ELDV_DEVCTG			(1 << 14)
6133
#define G4X_ELDV_DEVCTG			(1 << 14)
Line 5652... Line 6134...
5652
#define G4X_ELD_ADDR			(0xf << 5)
6134
#define   G4X_ELD_ADDR_MASK		(0xf << 5)
5653
#define G4X_ELD_ACK			(1 << 4)
6135
#define G4X_ELD_ACK			(1 << 4)
5654
#define G4X_HDMIW_HDMIEDID		0x6210C
6136
#define G4X_HDMIW_HDMIEDID		0x6210C
5655
 
6137
 
5656
#define IBX_HDMIW_HDMIEDID_A		0xE2050
6138
#define _IBX_HDMIW_HDMIEDID_A		0xE2050
5657
#define IBX_HDMIW_HDMIEDID_B		0xE2150
6139
#define _IBX_HDMIW_HDMIEDID_B		0xE2150
5658
#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6140
#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5659
					IBX_HDMIW_HDMIEDID_A, \
6141
					_IBX_HDMIW_HDMIEDID_A, \
5660
					IBX_HDMIW_HDMIEDID_B)
6142
					_IBX_HDMIW_HDMIEDID_B)
5661
#define IBX_AUD_CNTL_ST_A		0xE20B4
6143
#define _IBX_AUD_CNTL_ST_A		0xE20B4
5662
#define IBX_AUD_CNTL_ST_B		0xE21B4
6144
#define _IBX_AUD_CNTL_ST_B		0xE21B4
5663
#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6145
#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5664
					IBX_AUD_CNTL_ST_A, \
6146
					_IBX_AUD_CNTL_ST_A, \
5665
					IBX_AUD_CNTL_ST_B)
6147
					_IBX_AUD_CNTL_ST_B)
5666
#define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
6148
#define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
5667
#define IBX_ELD_ADDRESS			(0x1f << 5)
6149
#define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
Line 5668... Line 6150...
5668
#define IBX_ELD_ACK			(1 << 4)
6150
#define IBX_ELD_ACK			(1 << 4)
5669
#define IBX_AUD_CNTL_ST2		0xE20C0
6151
#define IBX_AUD_CNTL_ST2		0xE20C0
5670
#define IBX_ELD_VALIDB			(1 << 0)
6152
#define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
5671
#define IBX_CP_READYB			(1 << 1)
6153
#define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
5672
 
6154
 
5673
#define CPT_HDMIW_HDMIEDID_A		0xE5050
6155
#define _CPT_HDMIW_HDMIEDID_A		0xE5050
5674
#define CPT_HDMIW_HDMIEDID_B		0xE5150
6156
#define _CPT_HDMIW_HDMIEDID_B		0xE5150
5675
#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6157
#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5676
					CPT_HDMIW_HDMIEDID_A, \
6158
					_CPT_HDMIW_HDMIEDID_A, \
5677
					CPT_HDMIW_HDMIEDID_B)
6159
					_CPT_HDMIW_HDMIEDID_B)
5678
#define CPT_AUD_CNTL_ST_A		0xE50B4
6160
#define _CPT_AUD_CNTL_ST_A		0xE50B4
Line 5679... Line 6161...
5679
#define CPT_AUD_CNTL_ST_B		0xE51B4
6161
#define _CPT_AUD_CNTL_ST_B		0xE51B4
5680
#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6162
#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5681
					CPT_AUD_CNTL_ST_A, \
6163
					_CPT_AUD_CNTL_ST_A, \
5682
					CPT_AUD_CNTL_ST_B)
6164
					_CPT_AUD_CNTL_ST_B)
5683
#define CPT_AUD_CNTRL_ST2		0xE50C0
6165
#define CPT_AUD_CNTRL_ST2		0xE50C0
5684
 
6166
 
5685
#define VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
6167
#define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
5686
#define VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
6168
#define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
5687
#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6169
#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5688
					VLV_HDMIW_HDMIEDID_A, \
6170
					_VLV_HDMIW_HDMIEDID_A, \
5689
					VLV_HDMIW_HDMIEDID_B)
6171
					_VLV_HDMIW_HDMIEDID_B)
Line 5690... Line 6172...
5690
#define VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
6172
#define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
5691
#define VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
6173
#define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
5692
#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6174
#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5693
					VLV_AUD_CNTL_ST_A, \
6175
					_VLV_AUD_CNTL_ST_A, \
5694
					VLV_AUD_CNTL_ST_B)
6176
					_VLV_AUD_CNTL_ST_B)
Line 5695... Line 6177...
5695
#define VLV_AUD_CNTL_ST2		(VLV_DISPLAY_BASE + 0x620C0)
6177
#define VLV_AUD_CNTL_ST2		(VLV_DISPLAY_BASE + 0x620C0)
5696
 
6178
 
5697
/* These are the 4 32-bit write offset registers for each stream
6179
/* These are the 4 32-bit write offset registers for each stream
5698
 * output buffer.  It determines the offset from the
6180
 * output buffer.  It determines the offset from the
5699
 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6181
 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5700
 */
6182
 */
5701
#define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
6183
#define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
5702
 
6184
 
5703
#define IBX_AUD_CONFIG_A			0xe2000
6185
#define _IBX_AUD_CONFIG_A		0xe2000
5704
#define IBX_AUD_CONFIG_B			0xe2100
6186
#define _IBX_AUD_CONFIG_B		0xe2100
5705
#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
6187
#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5706
					IBX_AUD_CONFIG_A, \
6188
					_IBX_AUD_CONFIG_A, \
5707
					IBX_AUD_CONFIG_B)
6189
					_IBX_AUD_CONFIG_B)
5708
#define CPT_AUD_CONFIG_A			0xe5000
6190
#define _CPT_AUD_CONFIG_A		0xe5000
5709
#define CPT_AUD_CONFIG_B			0xe5100
6191
#define _CPT_AUD_CONFIG_B		0xe5100
Line 5710... Line 6192...
5710
#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
6192
#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5711
					CPT_AUD_CONFIG_A, \
6193
					_CPT_AUD_CONFIG_A, \
5712
					CPT_AUD_CONFIG_B)
6194
					_CPT_AUD_CONFIG_B)
5713
#define VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
6195
#define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
5714
#define VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
6196
#define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
5715
#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
6197
#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5716
					VLV_AUD_CONFIG_A, \
6198
					_VLV_AUD_CONFIG_A, \
5717
					VLV_AUD_CONFIG_B)
6199
					_VLV_AUD_CONFIG_B)
5718
 
6200
 
5719
#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
6201
#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
5720
#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
6202
#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
Line 5735... Line 6217...
5735
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
6217
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
5736
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
6218
#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
5737
#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
6219
#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
Line 5738... Line 6220...
5738
 
6220
 
5739
/* HSW Audio */
6221
/* HSW Audio */
5740
#define   HSW_AUD_CONFIG_A		0x65000 /* Audio Configuration Transcoder A */
6222
#define _HSW_AUD_CONFIG_A		0x65000
5741
#define   HSW_AUD_CONFIG_B		0x65100 /* Audio Configuration Transcoder B */
6223
#define _HSW_AUD_CONFIG_B		0x65100
5742
#define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
6224
#define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
5743
					HSW_AUD_CONFIG_A, \
6225
					_HSW_AUD_CONFIG_A, \
Line 5744... Line 6226...
5744
					HSW_AUD_CONFIG_B)
6226
					_HSW_AUD_CONFIG_B)
5745
 
6227
 
5746
#define   HSW_AUD_MISC_CTRL_A		0x65010 /* Audio Misc Control Convert 1 */
6228
#define _HSW_AUD_MISC_CTRL_A		0x65010
5747
#define   HSW_AUD_MISC_CTRL_B		0x65110 /* Audio Misc Control Convert 2 */
6229
#define _HSW_AUD_MISC_CTRL_B		0x65110
5748
#define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
6230
#define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
Line 5749... Line 6231...
5749
					HSW_AUD_MISC_CTRL_A, \
6231
					_HSW_AUD_MISC_CTRL_A, \
5750
					HSW_AUD_MISC_CTRL_B)
6232
					_HSW_AUD_MISC_CTRL_B)
5751
 
6233
 
5752
#define   HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4 /* Audio DIP and ELD Control State Transcoder A */
6234
#define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
5753
#define   HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4 /* Audio DIP and ELD Control State Transcoder B */
6235
#define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
Line 5754... Line 6236...
5754
#define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
6236
#define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5755
					HSW_AUD_DIP_ELD_CTRL_ST_A, \
6237
					_HSW_AUD_DIP_ELD_CTRL_ST_A, \
5756
					HSW_AUD_DIP_ELD_CTRL_ST_B)
6238
					_HSW_AUD_DIP_ELD_CTRL_ST_B)
5757
 
6239
 
5758
/* Audio Digital Converter */
6240
/* Audio Digital Converter */
5759
#define   HSW_AUD_DIG_CNVT_1		0x65080 /* Audio Converter 1 */
6241
#define _HSW_AUD_DIG_CNVT_1		0x65080
5760
#define   HSW_AUD_DIG_CNVT_2		0x65180 /* Audio Converter 1 */
6242
#define _HSW_AUD_DIG_CNVT_2		0x65180
Line 5761... Line 6243...
5761
#define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
6243
#define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5762
					HSW_AUD_DIG_CNVT_1, \
6244
					_HSW_AUD_DIG_CNVT_1, \
5763
					HSW_AUD_DIG_CNVT_2)
6245
					_HSW_AUD_DIG_CNVT_2)
5764
#define   DIP_PORT_SEL_MASK		0x3
6246
#define   DIP_PORT_SEL_MASK		0x3
5765
 
6247
 
Line 5766... Line -...
5766
#define   HSW_AUD_EDID_DATA_A		0x65050
-
 
5767
#define   HSW_AUD_EDID_DATA_B		0x65150
-
 
5768
#define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
6248
#define _HSW_AUD_EDID_DATA_A		0x65050
5769
					HSW_AUD_EDID_DATA_A, \
6249
#define _HSW_AUD_EDID_DATA_B		0x65150
5770
					HSW_AUD_EDID_DATA_B)
6250
#define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5771
 
6251
					_HSW_AUD_EDID_DATA_A, \
5772
#define   HSW_AUD_PIPE_CONV_CFG		0x6507c /* Audio pipe and converter configs */
-
 
5773
#define   HSW_AUD_PIN_ELD_CP_VLD	0x650c0 /* Audio ELD and CP Ready Status */
6252
					_HSW_AUD_EDID_DATA_B)
5774
#define   AUDIO_INACTIVE_C		(1<<11)
-
 
5775
#define   AUDIO_INACTIVE_B		(1<<7)
6253
 
5776
#define   AUDIO_INACTIVE_A		(1<<3)
-
 
5777
#define   AUDIO_OUTPUT_ENABLE_A		(1<<2)
-
 
5778
#define   AUDIO_OUTPUT_ENABLE_B		(1<<6)
-
 
5779
#define   AUDIO_OUTPUT_ENABLE_C		(1<<10)
-
 
Line 5780... Line 6254...
5780
#define   AUDIO_ELD_VALID_A		(1<<0)
6254
#define HSW_AUD_PIPE_CONV_CFG		0x6507c
5781
#define   AUDIO_ELD_VALID_B		(1<<4)
6255
#define HSW_AUD_PIN_ELD_CP_VLD		0x650c0
5782
#define   AUDIO_ELD_VALID_C		(1<<8)
6256
#define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
5783
#define   AUDIO_CP_READY_A		(1<<1)
6257
#define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
Line 5864... Line 6338...
5864
/* DDI Buffer Control */
6338
/* DDI Buffer Control */
5865
#define DDI_BUF_CTL_A				0x64000
6339
#define DDI_BUF_CTL_A				0x64000
5866
#define DDI_BUF_CTL_B				0x64100
6340
#define DDI_BUF_CTL_B				0x64100
5867
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
6341
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5868
#define  DDI_BUF_CTL_ENABLE				(1<<31)
6342
#define  DDI_BUF_CTL_ENABLE				(1<<31)
5869
#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
-
 
5870
#define  DDI_BUF_EMP_400MV_3_5DB_HSW	(1<<24)   /* Sel1 */
-
 
5871
#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
-
 
5872
#define  DDI_BUF_EMP_400MV_9_5DB_HSW	(3<<24)   /* Sel3 */
-
 
5873
#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
6343
#define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
5874
#define  DDI_BUF_EMP_600MV_3_5DB_HSW	(5<<24)   /* Sel5 */
-
 
5875
#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
-
 
5876
#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
-
 
5877
#define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
-
 
5878
#define  DDI_BUF_EMP_MASK				(0xf<<24)
6344
#define  DDI_BUF_EMP_MASK				(0xf<<24)
5879
#define  DDI_BUF_PORT_REVERSAL			(1<<16)
6345
#define  DDI_BUF_PORT_REVERSAL			(1<<16)
5880
#define  DDI_BUF_IS_IDLE				(1<<7)
6346
#define  DDI_BUF_IS_IDLE				(1<<7)
5881
#define  DDI_A_4_LANES				(1<<4)
6347
#define  DDI_A_4_LANES				(1<<4)
5882
#define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
6348
#define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
Line 6006... Line 6472...
6006
#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
6472
#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
6007
#define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
6473
#define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
6008
#define  LCPLL_CD_SOURCE_FCLK		(1<<21)
6474
#define  LCPLL_CD_SOURCE_FCLK		(1<<21)
6009
#define  LCPLL_CD_SOURCE_FCLK_DONE	(1<<19)
6475
#define  LCPLL_CD_SOURCE_FCLK_DONE	(1<<19)
Line -... Line 6476...
-
 
6476
 
-
 
6477
/*
-
 
6478
 * SKL Clocks
-
 
6479
 */
-
 
6480
 
-
 
6481
/* CDCLK_CTL */
-
 
6482
#define CDCLK_CTL			0x46000
-
 
6483
#define  CDCLK_FREQ_SEL_MASK		(3<<26)
-
 
6484
#define  CDCLK_FREQ_450_432		(0<<26)
-
 
6485
#define  CDCLK_FREQ_540			(1<<26)
-
 
6486
#define  CDCLK_FREQ_337_308		(2<<26)
-
 
6487
#define  CDCLK_FREQ_675_617		(3<<26)
-
 
6488
#define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
-
 
6489
 
-
 
6490
/* LCPLL_CTL */
-
 
6491
#define LCPLL1_CTL		0x46010
-
 
6492
#define LCPLL2_CTL		0x46014
-
 
6493
#define  LCPLL_PLL_ENABLE	(1<<31)
-
 
6494
 
-
 
6495
/* DPLL control1 */
-
 
6496
#define DPLL_CTRL1		0x6C058
-
 
6497
#define  DPLL_CTRL1_HDMI_MODE(id)		(1<<((id)*6+5))
-
 
6498
#define  DPLL_CTRL1_SSC(id)			(1<<((id)*6+4))
-
 
6499
#define  DPLL_CRTL1_LINK_RATE_MASK(id)		(7<<((id)*6+1))
-
 
6500
#define  DPLL_CRTL1_LINK_RATE_SHIFT(id)		((id)*6+1)
-
 
6501
#define  DPLL_CRTL1_LINK_RATE(linkrate, id)	((linkrate)<<((id)*6+1))
-
 
6502
#define  DPLL_CTRL1_OVERRIDE(id)		(1<<((id)*6))
-
 
6503
#define  DPLL_CRTL1_LINK_RATE_2700		0
-
 
6504
#define  DPLL_CRTL1_LINK_RATE_1350		1
-
 
6505
#define  DPLL_CRTL1_LINK_RATE_810		2
-
 
6506
#define  DPLL_CRTL1_LINK_RATE_1620		3
-
 
6507
#define  DPLL_CRTL1_LINK_RATE_1080		4
-
 
6508
#define  DPLL_CRTL1_LINK_RATE_2160		5
-
 
6509
 
-
 
6510
/* DPLL control2 */
-
 
6511
#define DPLL_CTRL2				0x6C05C
-
 
6512
#define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1<<(port+15))
-
 
6513
#define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3<<((port)*3+1))
-
 
6514
#define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port)*3+1)
-
 
6515
#define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	(clk<<((port)*3+1))
-
 
6516
#define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1<<((port)*3))
-
 
6517
 
-
 
6518
/* DPLL Status */
-
 
6519
#define DPLL_STATUS	0x6C060
-
 
6520
#define  DPLL_LOCK(id) (1<<((id)*8))
-
 
6521
 
-
 
6522
/* DPLL cfg */
-
 
6523
#define DPLL1_CFGCR1	0x6C040
-
 
6524
#define DPLL2_CFGCR1	0x6C048
-
 
6525
#define DPLL3_CFGCR1	0x6C050
-
 
6526
#define  DPLL_CFGCR1_FREQ_ENABLE	(1<<31)
-
 
6527
#define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff<<9)
-
 
6528
#define  DPLL_CFGCR1_DCO_FRACTION(x)	(x<<9)
-
 
6529
#define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
-
 
6530
 
-
 
6531
#define DPLL1_CFGCR2	0x6C044
-
 
6532
#define DPLL2_CFGCR2	0x6C04C
-
 
6533
#define DPLL3_CFGCR2	0x6C054
-
 
6534
#define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff<<8)
-
 
6535
#define  DPLL_CFGCR2_QDIV_RATIO(x)	(x<<8)
-
 
6536
#define  DPLL_CFGCR2_QDIV_MODE(x)	(x<<7)
-
 
6537
#define  DPLL_CFGCR2_KDIV_MASK		(3<<5)
-
 
6538
#define  DPLL_CFGCR2_KDIV(x)		(x<<5)
-
 
6539
#define  DPLL_CFGCR2_KDIV_5 (0<<5)
-
 
6540
#define  DPLL_CFGCR2_KDIV_2 (1<<5)
-
 
6541
#define  DPLL_CFGCR2_KDIV_3 (2<<5)
-
 
6542
#define  DPLL_CFGCR2_KDIV_1 (3<<5)
-
 
6543
#define  DPLL_CFGCR2_PDIV_MASK		(7<<2)
-
 
6544
#define  DPLL_CFGCR2_PDIV(x)		(x<<2)
-
 
6545
#define  DPLL_CFGCR2_PDIV_1 (0<<2)
-
 
6546
#define  DPLL_CFGCR2_PDIV_2 (1<<2)
-
 
6547
#define  DPLL_CFGCR2_PDIV_3 (2<<2)
-
 
6548
#define  DPLL_CFGCR2_PDIV_7 (4<<2)
-
 
6549
#define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
-
 
6550
 
-
 
6551
#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
-
 
6552
#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
6010
 
6553
 
6011
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
6554
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
6012
 * since on HSW we can't write to it using I915_WRITE. */
6555
 * since on HSW we can't write to it using I915_WRITE. */
6013
#define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
6556
#define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
6014
#define D_COMP_BDW			0x138144
6557
#define D_COMP_BDW			0x138144