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Line 25... | Line 25... | ||
25 | #ifndef _I915_REG_H_ |
25 | #ifndef _I915_REG_H_ |
26 | #define _I915_REG_H_ |
26 | #define _I915_REG_H_ |
Line 27... | Line 27... | ||
27 | 27 | ||
Line -... | Line 28... | ||
- | 28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
|
- | 29 | ||
- | 30 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
|
- | 31 | ||
- | 32 | #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
|
28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
33 | #define _MASKED_BIT_DISABLE(a) ((a) << 16) |
29 | 34 | ||
30 | /* |
35 | /* |
31 | * The Bridge device's PCI config space has information about the |
36 | * The Bridge device's PCI config space has information about the |
32 | * fb aperture size and the amount of pre-reserved memory. |
37 | * fb aperture size and the amount of pre-reserved memory. |
Line 75... | Line 80... | ||
75 | #define I965_GDRST 0xc0 /* PCI config register */ |
80 | #define I965_GDRST 0xc0 /* PCI config register */ |
76 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
81 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
77 | #define GRDOM_FULL (0<<2) |
82 | #define GRDOM_FULL (0<<2) |
78 | #define GRDOM_RENDER (1<<2) |
83 | #define GRDOM_RENDER (1<<2) |
79 | #define GRDOM_MEDIA (3<<2) |
84 | #define GRDOM_MEDIA (3<<2) |
- | 85 | #define GRDOM_RESET_ENABLE (1<<0) |
|
Line 80... | Line 86... | ||
80 | 86 | ||
81 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
87 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
82 | #define GEN6_MBC_SNPCR_SHIFT 21 |
88 | #define GEN6_MBC_SNPCR_SHIFT 21 |
83 | #define GEN6_MBC_SNPCR_MASK (3<<21) |
89 | #define GEN6_MBC_SNPCR_MASK (3<<21) |
84 | #define GEN6_MBC_SNPCR_MAX (0<<21) |
90 | #define GEN6_MBC_SNPCR_MAX (0<<21) |
85 | #define GEN6_MBC_SNPCR_MED (1<<21) |
91 | #define GEN6_MBC_SNPCR_MED (1<<21) |
86 | #define GEN6_MBC_SNPCR_LOW (2<<21) |
92 | #define GEN6_MBC_SNPCR_LOW (2<<21) |
Line -... | Line 93... | ||
- | 93 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
|
- | 94 | ||
- | 95 | #define GEN6_MBCTL 0x0907c |
|
- | 96 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
|
- | 97 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
|
- | 98 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) |
|
- | 99 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) |
|
87 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
100 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) |
88 | 101 | ||
89 | #define GEN6_GDRST 0x941c |
102 | #define GEN6_GDRST 0x941c |
90 | #define GEN6_GRDOM_FULL (1 << 0) |
103 | #define GEN6_GRDOM_FULL (1 << 0) |
91 | #define GEN6_GRDOM_RENDER (1 << 1) |
104 | #define GEN6_GRDOM_RENDER (1 << 1) |
Line -... | Line 105... | ||
- | 105 | #define GEN6_GRDOM_MEDIA (1 << 2) |
|
- | 106 | #define GEN6_GRDOM_BLT (1 << 3) |
|
- | 107 | ||
- | 108 | /* PPGTT stuff */ |
|
- | 109 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) |
|
- | 110 | ||
- | 111 | #define GEN6_PDE_VALID (1 << 0) |
|
- | 112 | #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */ |
|
- | 113 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ |
|
- | 114 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
|
- | 115 | ||
- | 116 | #define GEN6_PTE_VALID (1 << 0) |
|
- | 117 | #define GEN6_PTE_UNCACHED (1 << 1) |
|
- | 118 | #define HSW_PTE_UNCACHED (0) |
|
- | 119 | #define GEN6_PTE_CACHE_LLC (2 << 1) |
|
- | 120 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) |
|
- | 121 | #define GEN6_PTE_CACHE_BITS (3 << 1) |
|
- | 122 | #define GEN6_PTE_GFDT (1 << 3) |
|
- | 123 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
|
- | 124 | ||
- | 125 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
|
- | 126 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) |
|
- | 127 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) |
|
- | 128 | #define PP_DIR_DCLV_2G 0xffffffff |
|
- | 129 | ||
- | 130 | #define GAM_ECOCHK 0x4090 |
|
- | 131 | #define ECOCHK_SNB_BIT (1<<10) |
|
- | 132 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
|
- | 133 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
|
- | 134 | ||
- | 135 | #define GAC_ECO_BITS 0x14090 |
|
- | 136 | #define ECOBITS_PPGTT_CACHE64B (3<<8) |
|
- | 137 | #define ECOBITS_PPGTT_CACHE4B (0<<8) |
|
- | 138 | ||
92 | #define GEN6_GRDOM_MEDIA (1 << 2) |
139 | #define GAB_CTL 0x24000 |
Line 93... | Line 140... | ||
93 | #define GEN6_GRDOM_BLT (1 << 3) |
140 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
94 | 141 | ||
Line 162... | Line 209... | ||
162 | #define MI_OVERLAY_OFF (0x2<<21) |
209 | #define MI_OVERLAY_OFF (0x2<<21) |
163 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
210 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
164 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
211 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
165 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
212 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
166 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
213 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
- | 214 | /* IVB has funny definitions for which plane to flip. */ |
|
- | 215 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) |
|
- | 216 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) |
|
- | 217 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) |
|
- | 218 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
|
- | 219 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
|
- | 220 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
|
- | 221 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
|
- | 222 | #define MI_ARB_ENABLE (1<<0) |
|
- | 223 | #define MI_ARB_DISABLE (0<<0) |
|
- | 224 | ||
167 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
225 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
168 | #define MI_MM_SPACE_GTT (1<<8) |
226 | #define MI_MM_SPACE_GTT (1<<8) |
169 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
227 | #define MI_MM_SPACE_PHYSICAL (0<<8) |
170 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
228 | #define MI_SAVE_EXT_STATE_EN (1<<3) |
171 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
229 | #define MI_RESTORE_EXT_STATE_EN (1<<2) |
Line 187... | Line 245... | ||
187 | #define MI_INVALIDATE_BSD (1<<7) |
245 | #define MI_INVALIDATE_BSD (1<<7) |
188 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
246 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
189 | #define MI_BATCH_NON_SECURE (1) |
247 | #define MI_BATCH_NON_SECURE (1) |
190 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
248 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
191 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
249 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
- | 250 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
|
192 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
251 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
193 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
252 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
194 | #define MI_SEMAPHORE_UPDATE (1<<21) |
253 | #define MI_SEMAPHORE_UPDATE (1<<21) |
195 | #define MI_SEMAPHORE_COMPARE (1<<20) |
254 | #define MI_SEMAPHORE_COMPARE (1<<20) |
196 | #define MI_SEMAPHORE_REGISTER (1<<18) |
255 | #define MI_SEMAPHORE_REGISTER (1<<18) |
Line 242... | Line 301... | ||
242 | #define ASYNC_FLIP (1<<22) |
301 | #define ASYNC_FLIP (1<<22) |
243 | #define DISPLAY_PLANE_A (0<<20) |
302 | #define DISPLAY_PLANE_A (0<<20) |
244 | #define DISPLAY_PLANE_B (1<<20) |
303 | #define DISPLAY_PLANE_B (1<<20) |
245 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
304 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
246 | #define PIPE_CONTROL_CS_STALL (1<<20) |
305 | #define PIPE_CONTROL_CS_STALL (1<<20) |
- | 306 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
|
247 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
307 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
248 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
308 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
249 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) |
309 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) |
250 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
310 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
251 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
311 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
Line 266... | Line 326... | ||
266 | #define DEBUG_RESET_I830 0x6070 |
326 | #define DEBUG_RESET_I830 0x6070 |
267 | #define DEBUG_RESET_FULL (1<<7) |
327 | #define DEBUG_RESET_FULL (1<<7) |
268 | #define DEBUG_RESET_RENDER (1<<8) |
328 | #define DEBUG_RESET_RENDER (1<<8) |
269 | #define DEBUG_RESET_DISPLAY (1<<9) |
329 | #define DEBUG_RESET_DISPLAY (1<<9) |
Line -... | Line 330... | ||
- | 330 | ||
- | 331 | /* |
|
- | 332 | * DPIO - a special bus for various display related registers to hide behind: |
|
- | 333 | * 0x800c: m1, m2, n, p1, p2, k dividers |
|
- | 334 | * 0x8014: REF and SFR select |
|
- | 335 | * 0x8014: N divider, VCO select |
|
- | 336 | * 0x801c/3c: core clock bits |
|
- | 337 | * 0x8048/68: low pass filter coefficients |
|
- | 338 | * 0x8100: fast clock controls |
|
- | 339 | */ |
|
- | 340 | #define DPIO_PKT 0x2100 |
|
- | 341 | #define DPIO_RID (0<<24) |
|
- | 342 | #define DPIO_OP_WRITE (1<<16) |
|
- | 343 | #define DPIO_OP_READ (0<<16) |
|
- | 344 | #define DPIO_PORTID (0x12<<8) |
|
- | 345 | #define DPIO_BYTE (0xf<<4) |
|
- | 346 | #define DPIO_BUSY (1<<0) /* status only */ |
|
- | 347 | #define DPIO_DATA 0x2104 |
|
- | 348 | #define DPIO_REG 0x2108 |
|
- | 349 | #define DPIO_CTL 0x2110 |
|
- | 350 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
|
- | 351 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ |
|
- | 352 | #define DPIO_SFR_BYPASS (1<<1) |
|
- | 353 | #define DPIO_RESET (1<<0) |
|
- | 354 | ||
- | 355 | #define _DPIO_DIV_A 0x800c |
|
- | 356 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
|
- | 357 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
|
- | 358 | #define DPIO_P1_SHIFT (21) /* 3 bits */ |
|
- | 359 | #define DPIO_P2_SHIFT (16) /* 5 bits */ |
|
- | 360 | #define DPIO_N_SHIFT (12) /* 4 bits */ |
|
- | 361 | #define DPIO_ENABLE_CALIBRATION (1<<11) |
|
- | 362 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
|
- | 363 | #define DPIO_M2DIV_MASK 0xff |
|
- | 364 | #define _DPIO_DIV_B 0x802c |
|
- | 365 | #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) |
|
- | 366 | ||
- | 367 | #define _DPIO_REFSFR_A 0x8014 |
|
- | 368 | #define DPIO_REFSEL_OVERRIDE 27 |
|
- | 369 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
|
- | 370 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
|
- | 371 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
|
- | 372 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
|
- | 373 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
|
- | 374 | #define _DPIO_REFSFR_B 0x8034 |
|
- | 375 | #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) |
|
- | 376 | ||
- | 377 | #define _DPIO_CORE_CLK_A 0x801c |
|
- | 378 | #define _DPIO_CORE_CLK_B 0x803c |
|
- | 379 | #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) |
|
- | 380 | ||
- | 381 | #define _DPIO_LFP_COEFF_A 0x8048 |
|
- | 382 | #define _DPIO_LFP_COEFF_B 0x8068 |
|
- | 383 | #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) |
|
- | 384 | ||
Line 270... | Line 385... | ||
270 | 385 | #define DPIO_FASTCLK_DISABLE 0x8100 |
|
271 | 386 | ||
272 | /* |
387 | /* |
273 | * Fence registers |
388 | * Fence registers |
Line 293... | Line 408... | ||
293 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
408 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
Line 294... | Line 409... | ||
294 | 409 | ||
295 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
410 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
Line -... | Line 411... | ||
- | 411 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
|
- | 412 | ||
- | 413 | /* control register for cpu gtt access */ |
|
- | 414 | #define TILECTL 0x101000 |
|
- | 415 | #define TILECTL_SWZCTL (1 << 0) |
|
- | 416 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
|
296 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
417 | #define TILECTL_BACKSNOOP_DIS (1 << 3) |
297 | 418 | ||
298 | /* |
419 | /* |
299 | * Instruction and interrupt control regs |
420 | * Instruction and interrupt control regs |
300 | */ |
421 | */ |
Line 316... | Line 437... | ||
316 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
437 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
317 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
438 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
318 | #define RING_MAX_IDLE(base) ((base)+0x54) |
439 | #define RING_MAX_IDLE(base) ((base)+0x54) |
319 | #define RING_HWS_PGA(base) ((base)+0x80) |
440 | #define RING_HWS_PGA(base) ((base)+0x80) |
320 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
441 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
- | 442 | #define ARB_MODE 0x04030 |
|
- | 443 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
|
- | 444 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
|
321 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
445 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
- | 446 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
|
- | 447 | #define DONE_REG 0x40b0 |
|
322 | #define BSD_HWS_PGA_GEN7 (0x04180) |
448 | #define BSD_HWS_PGA_GEN7 (0x04180) |
323 | #define BLT_HWS_PGA_GEN7 (0x04280) |
449 | #define BLT_HWS_PGA_GEN7 (0x04280) |
324 | #define RING_ACTHD(base) ((base)+0x74) |
450 | #define RING_ACTHD(base) ((base)+0x74) |
325 | #define RING_NOPID(base) ((base)+0x94) |
451 | #define RING_NOPID(base) ((base)+0x94) |
326 | #define RING_IMR(base) ((base)+0xa8) |
452 | #define RING_IMR(base) ((base)+0xa8) |
- | 453 | #define RING_TIMESTAMP(base) ((base)+0x358) |
|
327 | #define TAIL_ADDR 0x001FFFF8 |
454 | #define TAIL_ADDR 0x001FFFF8 |
328 | #define HEAD_WRAP_COUNT 0xFFE00000 |
455 | #define HEAD_WRAP_COUNT 0xFFE00000 |
329 | #define HEAD_WRAP_ONE 0x00200000 |
456 | #define HEAD_WRAP_ONE 0x00200000 |
330 | #define HEAD_ADDR 0x001FFFFC |
457 | #define HEAD_ADDR 0x001FFFFC |
331 | #define RING_NR_PAGES 0x001FF000 |
458 | #define RING_NR_PAGES 0x001FF000 |
Line 350... | Line 477... | ||
350 | #define PRB1_CTL 0x0204c /* 915+ only */ |
477 | #define PRB1_CTL 0x0204c /* 915+ only */ |
351 | #endif |
478 | #endif |
352 | #define IPEIR_I965 0x02064 |
479 | #define IPEIR_I965 0x02064 |
353 | #define IPEHR_I965 0x02068 |
480 | #define IPEHR_I965 0x02068 |
354 | #define INSTDONE_I965 0x0206c |
481 | #define INSTDONE_I965 0x0206c |
- | 482 | #define GEN7_INSTDONE_1 0x0206c |
|
- | 483 | #define GEN7_SC_INSTDONE 0x07100 |
|
- | 484 | #define GEN7_SAMPLER_INSTDONE 0x0e160 |
|
- | 485 | #define GEN7_ROW_INSTDONE 0x0e164 |
|
- | 486 | #define I915_NUM_INSTDONE_REG 4 |
|
- | 487 | #define RING_IPEIR(base) ((base)+0x64) |
|
- | 488 | #define RING_IPEHR(base) ((base)+0x68) |
|
- | 489 | #define RING_INSTDONE(base) ((base)+0x6c) |
|
- | 490 | #define RING_INSTPS(base) ((base)+0x70) |
|
- | 491 | #define RING_DMA_FADD(base) ((base)+0x78) |
|
- | 492 | #define RING_INSTPM(base) ((base)+0xc0) |
|
355 | #define INSTPS 0x02070 /* 965+ only */ |
493 | #define INSTPS 0x02070 /* 965+ only */ |
356 | #define INSTDONE1 0x0207c /* 965+ only */ |
494 | #define INSTDONE1 0x0207c /* 965+ only */ |
357 | #define ACTHD_I965 0x02074 |
495 | #define ACTHD_I965 0x02074 |
358 | #define HWS_PGA 0x02080 |
496 | #define HWS_PGA 0x02080 |
359 | #define HWS_ADDRESS_MASK 0xfffff000 |
497 | #define HWS_ADDRESS_MASK 0xfffff000 |
Line 363... | Line 501... | ||
363 | #define IPEIR 0x02088 |
501 | #define IPEIR 0x02088 |
364 | #define IPEHR 0x0208c |
502 | #define IPEHR 0x0208c |
365 | #define INSTDONE 0x02090 |
503 | #define INSTDONE 0x02090 |
366 | #define NOPID 0x02094 |
504 | #define NOPID 0x02094 |
367 | #define HWSTAM 0x02098 |
505 | #define HWSTAM 0x02098 |
368 | #define VCS_INSTDONE 0x1206C |
- | |
369 | #define VCS_IPEIR 0x12064 |
- | |
370 | #define VCS_IPEHR 0x12068 |
- | |
371 | #define VCS_ACTHD 0x12074 |
506 | #define DMA_FADD_I8XX 0x020d0 |
372 | #define BCS_INSTDONE 0x2206C |
- | |
373 | #define BCS_IPEIR 0x22064 |
- | |
374 | #define BCS_IPEHR 0x22068 |
- | |
375 | #define BCS_ACTHD 0x22074 |
- | |
Line 376... | Line 507... | ||
376 | 507 | ||
- | 508 | #define ERROR_GEN6 0x040a0 |
|
- | 509 | #define GEN7_ERR_INT 0x44040 |
|
Line 377... | Line 510... | ||
377 | #define ERROR_GEN6 0x040a0 |
510 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
378 | 511 | ||
379 | /* GM45+ chicken bits -- debug workaround bits that may be required |
512 | /* GM45+ chicken bits -- debug workaround bits that may be required |
380 | * for various sorts of correct behavior. The top 16 bits of each are |
513 | * for various sorts of correct behavior. The top 16 bits of each are |
Line 386... | Line 519... | ||
386 | * Required on all Ironlake steppings according to the B-Spec, but the |
519 | * Required on all Ironlake steppings according to the B-Spec, but the |
387 | * particular danger of not doing so is not specified. |
520 | * particular danger of not doing so is not specified. |
388 | */ |
521 | */ |
389 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
522 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
390 | #define _3D_CHICKEN3 0x02090 |
523 | #define _3D_CHICKEN3 0x02090 |
- | 524 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
|
Line 391... | Line 525... | ||
391 | 525 | ||
392 | #define MI_MODE 0x0209c |
526 | #define MI_MODE 0x0209c |
393 | # define VS_TIMER_DISPATCH (1 << 6) |
527 | # define VS_TIMER_DISPATCH (1 << 6) |
- | 528 | # define MI_FLUSH_ENABLE (1 << 12) |
|
- | 529 | ||
- | 530 | #define GEN6_GT_MODE 0x20d0 |
|
Line 394... | Line 531... | ||
394 | # define MI_FLUSH_ENABLE (1 << 11) |
531 | #define GEN6_GT_MODE_HI (1 << 9) |
395 | 532 | ||
- | 533 | #define GFX_MODE 0x02520 |
|
396 | #define GFX_MODE 0x02520 |
534 | #define GFX_MODE_GEN7 0x0229c |
397 | #define GFX_MODE_GEN7 0x0229c |
535 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
398 | #define GFX_RUN_LIST_ENABLE (1<<15) |
536 | #define GFX_RUN_LIST_ENABLE (1<<15) |
399 | #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) |
537 | #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) |
400 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
538 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
401 | #define GFX_REPLAY_MODE (1<<11) |
539 | #define GFX_REPLAY_MODE (1<<11) |
Line 402... | Line -... | ||
402 | #define GFX_PSMI_GRANULARITY (1<<10) |
- | |
403 | #define GFX_PPGTT_ENABLE (1<<9) |
540 | #define GFX_PSMI_GRANULARITY (1<<10) |
Line 404... | Line 541... | ||
404 | 541 | #define GFX_PPGTT_ENABLE (1<<9) |
|
405 | #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) |
542 | |
406 | #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) |
543 | #define VLV_DISPLAY_BASE 0x180000 |
407 | 544 | ||
408 | #define SCPD0 0x0209c /* 915+ only */ |
545 | #define SCPD0 0x0209c /* 915+ only */ |
- | 546 | #define IER 0x020a0 |
|
- | 547 | #define IIR 0x020a4 |
|
- | 548 | #define IMR 0x020a8 |
|
- | 549 | #define ISR 0x020ac |
|
- | 550 | #define VLV_IIR_RW 0x182084 |
|
409 | #define IER 0x020a0 |
551 | #define VLV_IER 0x1820a0 |
410 | #define IIR 0x020a4 |
552 | #define VLV_IIR 0x1820a4 |
411 | #define IMR 0x020a8 |
553 | #define VLV_IMR 0x1820a8 |
412 | #define ISR 0x020ac |
554 | #define VLV_ISR 0x1820ac |
413 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
555 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
Line 453... | Line 595... | ||
453 | #define MM_BURST_LENGTH 0x00700000 |
595 | #define MM_BURST_LENGTH 0x00700000 |
454 | #define MM_FIFO_WATERMARK 0x0001F000 |
596 | #define MM_FIFO_WATERMARK 0x0001F000 |
455 | #define LM_BURST_LENGTH 0x00000700 |
597 | #define LM_BURST_LENGTH 0x00000700 |
456 | #define LM_FIFO_WATERMARK 0x0000001F |
598 | #define LM_FIFO_WATERMARK 0x0000001F |
457 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
599 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
458 | #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ |
- | |
Line 459... | Line 600... | ||
459 | 600 | ||
460 | /* Make render/texture TLB fetches lower priorty than associated data |
601 | /* Make render/texture TLB fetches lower priorty than associated data |
461 | * fetches. This is not turned on by default |
602 | * fetches. This is not turned on by default |
462 | */ |
603 | */ |
Line 518... | Line 659... | ||
518 | /* Set display plane priority */ |
659 | /* Set display plane priority */ |
519 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
660 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
520 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
661 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
Line 521... | Line 662... | ||
521 | 662 | ||
522 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
- | |
523 | #define CM0_MASK_SHIFT 16 |
663 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
524 | #define CM0_IZ_OPT_DISABLE (1<<6) |
664 | #define CM0_IZ_OPT_DISABLE (1<<6) |
- | 665 | #define CM0_ZR_OPT_DISABLE (1<<5) |
|
525 | #define CM0_ZR_OPT_DISABLE (1<<5) |
666 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
526 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
667 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
527 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
668 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
528 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
669 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
529 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
670 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
530 | #define BB_ADDR 0x02140 /* 8 bytes */ |
671 | #define BB_ADDR 0x02140 /* 8 bytes */ |
531 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
672 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
532 | #define ECOSKPD 0x021d0 |
673 | #define ECOSKPD 0x021d0 |
533 | #define ECO_GATING_CX_ONLY (1<<3) |
674 | #define ECO_GATING_CX_ONLY (1<<3) |
Line -... | Line 675... | ||
- | 675 | #define ECO_FLIP_DONE (1<<0) |
|
- | 676 | ||
- | 677 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
|
534 | #define ECO_FLIP_DONE (1<<0) |
678 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
- | 679 | ||
- | 680 | /* GEN6 interrupt control |
|
535 | 681 | * Note that the per-ring interrupt bits do alias with the global interrupt bits |
|
536 | /* GEN6 interrupt control */ |
682 | * in GTIMR. */ |
537 | #define GEN6_RENDER_HWSTAM 0x2098 |
683 | #define GEN6_RENDER_HWSTAM 0x2098 |
538 | #define GEN6_RENDER_IMR 0x20a8 |
684 | #define GEN6_RENDER_IMR 0x20a8 |
539 | #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
685 | #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
Line 556... | Line 702... | ||
556 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
702 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
557 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
703 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
558 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
704 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
Line 559... | Line 705... | ||
559 | 705 | ||
560 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
706 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
561 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) |
707 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
562 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) |
708 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) |
563 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 |
709 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) |
Line 564... | Line 710... | ||
564 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) |
710 | #define GEN6_BSD_GO_INDICATOR (1 << 4) |
565 | 711 | ||
566 | #define GEN6_BSD_HWSTAM 0x12098 |
712 | #define GEN6_BSD_HWSTAM 0x12098 |
Line 567... | Line 713... | ||
567 | #define GEN6_BSD_IMR 0x120a8 |
713 | #define GEN6_BSD_IMR 0x120a8 |
Line -... | Line 714... | ||
- | 714 | #define GEN6_BSD_USER_INTERRUPT (1 << 12) |
|
- | 715 | ||
- | 716 | #define GEN6_BSD_RNCID 0x12198 |
|
- | 717 | ||
- | 718 | #define GEN7_FF_THREAD_MODE 0x20a0 |
|
- | 719 | #define GEN7_FF_SCHED_MASK 0x0077070 |
|
- | 720 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
|
- | 721 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) |
|
- | 722 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) |
|
- | 723 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ |
|
- | 724 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
|
- | 725 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) |
|
- | 726 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ |
|
- | 727 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) |
|
- | 728 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) |
|
568 | #define GEN6_BSD_USER_INTERRUPT (1 << 12) |
729 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) |
569 | 730 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ |
|
570 | #define GEN6_BSD_RNCID 0x12198 |
731 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) |
Line 571... | Line 732... | ||
571 | 732 | ||
Line 695... | Line 856... | ||
695 | #define GMBUS_PORT_SSC 1 |
856 | #define GMBUS_PORT_SSC 1 |
696 | #define GMBUS_PORT_VGADDC 2 |
857 | #define GMBUS_PORT_VGADDC 2 |
697 | #define GMBUS_PORT_PANEL 3 |
858 | #define GMBUS_PORT_PANEL 3 |
698 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
859 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
699 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
860 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
700 | /* 6 reserved */ |
861 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
701 | #define GMBUS_PORT_DPD 7 /* HDMID */ |
862 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
702 | #define GMBUS_NUM_PORTS 8 |
863 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
703 | #define GMBUS1 0x5104 /* command/status */ |
864 | #define GMBUS1 0x5104 /* command/status */ |
704 | #define GMBUS_SW_CLR_INT (1<<31) |
865 | #define GMBUS_SW_CLR_INT (1<<31) |
705 | #define GMBUS_SW_RDY (1<<30) |
866 | #define GMBUS_SW_RDY (1<<30) |
706 | #define GMBUS_ENT (1<<29) /* enable timeout */ |
867 | #define GMBUS_ENT (1<<29) /* enable timeout */ |
707 | #define GMBUS_CYCLE_NONE (0<<25) |
868 | #define GMBUS_CYCLE_NONE (0<<25) |
Line 749... | Line 910... | ||
749 | #define _DPLL_A 0x06014 |
910 | #define _DPLL_A 0x06014 |
750 | #define _DPLL_B 0x06018 |
911 | #define _DPLL_B 0x06018 |
751 | #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) |
912 | #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) |
752 | #define DPLL_VCO_ENABLE (1 << 31) |
913 | #define DPLL_VCO_ENABLE (1 << 31) |
753 | #define DPLL_DVO_HIGH_SPEED (1 << 30) |
914 | #define DPLL_DVO_HIGH_SPEED (1 << 30) |
- | 915 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
|
754 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
916 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
- | 917 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
|
755 | #define DPLL_VGA_MODE_DIS (1 << 28) |
918 | #define DPLL_VGA_MODE_DIS (1 << 28) |
756 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
919 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
757 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
920 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
758 | #define DPLL_MODE_MASK (3 << 26) |
921 | #define DPLL_MODE_MASK (3 << 26) |
759 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
922 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
Line 761... | Line 924... | ||
761 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
924 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
762 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
925 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
763 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
926 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
764 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
927 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
765 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
928 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
- | 929 | #define DPLL_LOCK_VLV (1<<15) |
|
- | 930 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
|
Line 766... | Line 931... | ||
766 | 931 | ||
767 | #define SRX_INDEX 0x3c4 |
932 | #define SRX_INDEX 0x3c4 |
768 | #define SRX_DATA 0x3c5 |
933 | #define SRX_DATA 0x3c5 |
769 | #define SR01 1 |
934 | #define SR01 1 |
Line 856... | Line 1021... | ||
856 | */ |
1021 | */ |
857 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
1022 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
858 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
1023 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
859 | #define _DPLL_B_MD 0x06020 /* 965+ only */ |
1024 | #define _DPLL_B_MD 0x06020 /* 965+ only */ |
860 | #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) |
1025 | #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) |
- | 1026 | ||
861 | #define _FPA0 0x06040 |
1027 | #define _FPA0 0x06040 |
862 | #define _FPA1 0x06044 |
1028 | #define _FPA1 0x06044 |
863 | #define _FPB0 0x06048 |
1029 | #define _FPB0 0x06048 |
864 | #define _FPB1 0x0604c |
1030 | #define _FPB1 0x0604c |
865 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) |
1031 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) |
Line 996... | Line 1162... | ||
996 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
1162 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
997 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
1163 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
998 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
1164 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
999 | #define DEUC 0x6214 /* CRL only */ |
1165 | #define DEUC 0x6214 /* CRL only */ |
Line -... | Line 1166... | ||
- | 1166 | ||
- | 1167 | #define FW_BLC_SELF_VLV 0x6500 |
|
- | 1168 | #define FW_CSPWRDWNEN (1<<15) |
|
1000 | 1169 | ||
1001 | /* |
1170 | /* |
1002 | * Palette regs |
1171 | * Palette regs |
Line 1003... | Line 1172... | ||
1003 | */ |
1172 | */ |
Line 1035... | Line 1204... | ||
1035 | 1204 | ||
1036 | /** 965 MCH register controlling DRAM channel configuration */ |
1205 | /** 965 MCH register controlling DRAM channel configuration */ |
1037 | #define C0DRB3 0x10206 |
1206 | #define C0DRB3 0x10206 |
Line -... | Line 1207... | ||
- | 1207 | #define C1DRB3 0x10606 |
|
- | 1208 | ||
- | 1209 | /** snb MCH registers for reading the DRAM channel configuration */ |
|
- | 1210 | #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) |
|
- | 1211 | #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) |
|
- | 1212 | #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) |
|
- | 1213 | #define MAD_DIMM_ECC_MASK (0x3 << 24) |
|
- | 1214 | #define MAD_DIMM_ECC_OFF (0x0 << 24) |
|
- | 1215 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) |
|
- | 1216 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) |
|
- | 1217 | #define MAD_DIMM_ECC_ON (0x3 << 24) |
|
- | 1218 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) |
|
- | 1219 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) |
|
- | 1220 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ |
|
- | 1221 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ |
|
- | 1222 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) |
|
- | 1223 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) |
|
- | 1224 | #define MAD_DIMM_A_SELECT (0x1 << 16) |
|
- | 1225 | /* DIMM sizes are in multiples of 256mb. */ |
|
- | 1226 | #define MAD_DIMM_B_SIZE_SHIFT 8 |
|
- | 1227 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) |
|
- | 1228 | #define MAD_DIMM_A_SIZE_SHIFT 0 |
|
- | 1229 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) |
|
1038 | #define C1DRB3 0x10606 |
1230 | |
1039 | 1231 | ||
1040 | /* Clocking configuration register */ |
1232 | /* Clocking configuration register */ |
1041 | #define CLKCFG 0x10c00 |
1233 | #define CLKCFG 0x10c00 |
1042 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
1234 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
Line 1278... | Line 1470... | ||
1278 | #define LCFUSE_HIV_MASK 0x000000ff |
1470 | #define LCFUSE_HIV_MASK 0x000000ff |
1279 | #define CSIPLL0 0x12c10 |
1471 | #define CSIPLL0 0x12c10 |
1280 | #define DDRMPLL1 0X12c20 |
1472 | #define DDRMPLL1 0X12c20 |
1281 | #define PEG_BAND_GAP_DATA 0x14d68 |
1473 | #define PEG_BAND_GAP_DATA 0x14d68 |
Line -... | Line 1474... | ||
- | 1474 | ||
- | 1475 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
|
- | 1476 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
|
- | 1477 | #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) |
|
1282 | 1478 | ||
1283 | #define GEN6_GT_PERF_STATUS 0x145948 |
1479 | #define GEN6_GT_PERF_STATUS 0x145948 |
1284 | #define GEN6_RP_STATE_LIMITS 0x145994 |
1480 | #define GEN6_RP_STATE_LIMITS 0x145994 |
Line 1285... | Line 1481... | ||
1285 | #define GEN6_RP_STATE_CAP 0x145998 |
1481 | #define GEN6_RP_STATE_CAP 0x145998 |
1286 | 1482 | ||
1287 | /* |
1483 | /* |
1288 | * Logical Context regs |
1484 | * Logical Context regs |
1289 | */ |
1485 | */ |
- | 1486 | #define CCID 0x2180 |
|
- | 1487 | #define CCID_EN (1<<0) |
|
- | 1488 | #define CXT_SIZE 0x21a0 |
|
- | 1489 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) |
|
- | 1490 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) |
|
- | 1491 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) |
|
- | 1492 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) |
|
- | 1493 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) |
|
- | 1494 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \ |
|
- | 1495 | GEN6_CXT_RING_SIZE(cxt_reg) + \ |
|
- | 1496 | GEN6_CXT_RENDER_SIZE(cxt_reg) + \ |
|
- | 1497 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
|
- | 1498 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) |
|
- | 1499 | #define GEN7_CXT_SIZE 0x21a8 |
|
- | 1500 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
|
- | 1501 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) |
|
- | 1502 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
|
- | 1503 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) |
|
- | 1504 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) |
|
- | 1505 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) |
|
- | 1506 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \ |
|
- | 1507 | GEN7_CXT_RING_SIZE(ctx_reg) + \ |
|
- | 1508 | GEN7_CXT_RENDER_SIZE(ctx_reg) + \ |
|
- | 1509 | GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
|
- | 1510 | GEN7_CXT_GT1_SIZE(ctx_reg) + \ |
|
- | 1511 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
|
- | 1512 | #define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f) |
|
- | 1513 | #define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7) |
|
- | 1514 | #define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff) |
|
- | 1515 | #define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \ |
|
- | 1516 | HSW_CXT_RING_SIZE(ctx_reg) + \ |
|
- | 1517 | HSW_CXT_RENDER_SIZE(ctx_reg) + \ |
|
- | 1518 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
|
1290 | #define CCID 0x2180 |
1519 | |
1291 | #define CCID_EN (1<<0) |
1520 | |
1292 | /* |
1521 | /* |
Line 1293... | Line 1522... | ||
1293 | * Overlay regs |
1522 | * Overlay regs |
Line 1314... | Line 1543... | ||
1314 | #define _VTOTAL_A 0x6000c |
1543 | #define _VTOTAL_A 0x6000c |
1315 | #define _VBLANK_A 0x60010 |
1544 | #define _VBLANK_A 0x60010 |
1316 | #define _VSYNC_A 0x60014 |
1545 | #define _VSYNC_A 0x60014 |
1317 | #define _PIPEASRC 0x6001c |
1546 | #define _PIPEASRC 0x6001c |
1318 | #define _BCLRPAT_A 0x60020 |
1547 | #define _BCLRPAT_A 0x60020 |
- | 1548 | #define _VSYNCSHIFT_A 0x60028 |
|
Line 1319... | Line 1549... | ||
1319 | 1549 | ||
1320 | /* Pipe B timing regs */ |
1550 | /* Pipe B timing regs */ |
1321 | #define _HTOTAL_B 0x61000 |
1551 | #define _HTOTAL_B 0x61000 |
1322 | #define _HBLANK_B 0x61004 |
1552 | #define _HBLANK_B 0x61004 |
1323 | #define _HSYNC_B 0x61008 |
1553 | #define _HSYNC_B 0x61008 |
1324 | #define _VTOTAL_B 0x6100c |
1554 | #define _VTOTAL_B 0x6100c |
1325 | #define _VBLANK_B 0x61010 |
1555 | #define _VBLANK_B 0x61010 |
1326 | #define _VSYNC_B 0x61014 |
1556 | #define _VSYNC_B 0x61014 |
1327 | #define _PIPEBSRC 0x6101c |
1557 | #define _PIPEBSRC 0x6101c |
- | 1558 | #define _BCLRPAT_B 0x61020 |
|
- | 1559 | #define _VSYNCSHIFT_B 0x61028 |
|
Line 1328... | Line 1560... | ||
1328 | #define _BCLRPAT_B 0x61020 |
1560 | |
1329 | 1561 | ||
1330 | #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) |
1562 | #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) |
1331 | #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) |
1563 | #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) |
1332 | #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) |
1564 | #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) |
1333 | #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) |
1565 | #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) |
1334 | #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) |
1566 | #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) |
- | 1567 | #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) |
|
Line 1335... | Line 1568... | ||
1335 | #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) |
1568 | #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
1336 | #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
1569 | #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
- | 1570 | ||
- | 1571 | /* VGA port control */ |
|
- | 1572 | #define ADPA 0x61100 |
|
1337 | 1573 | #define PCH_ADPA 0xe1100 |
|
1338 | /* VGA port control */ |
1574 | #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
1339 | #define ADPA 0x61100 |
1575 | |
1340 | #define ADPA_DAC_ENABLE (1<<31) |
1576 | #define ADPA_DAC_ENABLE (1<<31) |
1341 | #define ADPA_DAC_DISABLE 0 |
1577 | #define ADPA_DAC_DISABLE 0 |
1342 | #define ADPA_PIPE_SELECT_MASK (1<<30) |
1578 | #define ADPA_PIPE_SELECT_MASK (1<<30) |
- | 1579 | #define ADPA_PIPE_A_SELECT 0 |
|
- | 1580 | #define ADPA_PIPE_B_SELECT (1<<30) |
|
- | 1581 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
|
- | 1582 | /* CPT uses bits 29:30 for pch transcoder select */ |
|
- | 1583 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
|
- | 1584 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
|
- | 1585 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
|
- | 1586 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
|
- | 1587 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
|
- | 1588 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
|
- | 1589 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
|
- | 1590 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
|
- | 1591 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
|
- | 1592 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
|
- | 1593 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
|
- | 1594 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
|
- | 1595 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
|
- | 1596 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
|
- | 1597 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
|
- | 1598 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
|
1343 | #define ADPA_PIPE_A_SELECT 0 |
1599 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
1344 | #define ADPA_PIPE_B_SELECT (1<<30) |
1600 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
1345 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
1601 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
1346 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
1602 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
1347 | #define ADPA_SETS_HVPOLARITY 0 |
1603 | #define ADPA_SETS_HVPOLARITY 0 |
Line 1387... | Line 1643... | ||
1387 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
1643 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
1388 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
1644 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
1389 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
1645 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
Line 1390... | Line 1646... | ||
1390 | 1646 | ||
- | 1647 | #define PORT_HOTPLUG_STAT 0x61114 |
|
- | 1648 | /* HDMI/DP bits are gen4+ */ |
|
- | 1649 | #define DPB_HOTPLUG_LIVE_STATUS (1 << 29) |
|
- | 1650 | #define DPC_HOTPLUG_LIVE_STATUS (1 << 28) |
|
1391 | #define PORT_HOTPLUG_STAT 0x61114 |
1651 | #define DPD_HOTPLUG_LIVE_STATUS (1 << 27) |
1392 | #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) |
1652 | #define DPD_HOTPLUG_INT_STATUS (3 << 21) |
1393 | #define DPB_HOTPLUG_INT_STATUS (1 << 29) |
1653 | #define DPC_HOTPLUG_INT_STATUS (3 << 19) |
- | 1654 | #define DPB_HOTPLUG_INT_STATUS (3 << 17) |
|
- | 1655 | /* HDMI bits are shared with the DP bits */ |
|
- | 1656 | #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29) |
|
- | 1657 | #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28) |
|
1394 | #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) |
1658 | #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27) |
1395 | #define DPC_HOTPLUG_INT_STATUS (1 << 28) |
1659 | #define HDMID_HOTPLUG_INT_STATUS (3 << 21) |
1396 | #define HDMID_HOTPLUG_INT_STATUS (1 << 27) |
1660 | #define HDMIC_HOTPLUG_INT_STATUS (3 << 19) |
- | 1661 | #define HDMIB_HOTPLUG_INT_STATUS (3 << 17) |
|
1397 | #define DPD_HOTPLUG_INT_STATUS (1 << 27) |
1662 | /* CRT/TV common between gen3+ */ |
1398 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
1663 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
1399 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
1664 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
1400 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
1665 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
1401 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
1666 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
1402 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
1667 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
- | 1668 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
|
- | 1669 | /* SDVO is different across gen3/4 */ |
|
- | 1670 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
|
- | 1671 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
|
- | 1672 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
|
1403 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
1673 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
1404 | #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) |
1674 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
Line 1405... | Line 1675... | ||
1405 | #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) |
1675 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
1406 | 1676 | ||
1407 | /* SDVO port control */ |
1677 | /* SDVO port control */ |
1408 | #define SDVOB 0x61140 |
1678 | #define SDVOB 0x61140 |
Line 1525... | Line 1795... | ||
1525 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
1795 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
1526 | #define LVDS_B0B3_POWER_UP (3 << 2) |
1796 | #define LVDS_B0B3_POWER_UP (3 << 2) |
Line 1527... | Line 1797... | ||
1527 | 1797 | ||
1528 | /* Video Data Island Packet control */ |
1798 | /* Video Data Island Packet control */ |
- | 1799 | #define VIDEO_DIP_DATA 0x61178 |
|
- | 1800 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC |
|
- | 1801 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
|
- | 1802 | * of the infoframe structure specified by CEA-861. */ |
|
1529 | #define VIDEO_DIP_DATA 0x61178 |
1803 | #define VIDEO_DIP_DATA_SIZE 32 |
- | 1804 | #define VIDEO_DIP_CTL 0x61170 |
|
1530 | #define VIDEO_DIP_CTL 0x61170 |
1805 | /* Pre HSW: */ |
1531 | #define VIDEO_DIP_ENABLE (1 << 31) |
1806 | #define VIDEO_DIP_ENABLE (1 << 31) |
1532 | #define VIDEO_DIP_PORT_B (1 << 29) |
1807 | #define VIDEO_DIP_PORT_B (1 << 29) |
- | 1808 | #define VIDEO_DIP_PORT_C (2 << 29) |
|
- | 1809 | #define VIDEO_DIP_PORT_D (3 << 29) |
|
- | 1810 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
|
1533 | #define VIDEO_DIP_PORT_C (2 << 29) |
1811 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
1534 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
1812 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
- | 1813 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
|
1535 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
1814 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
1536 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
1815 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
1537 | #define VIDEO_DIP_SELECT_AVI (0 << 19) |
1816 | #define VIDEO_DIP_SELECT_AVI (0 << 19) |
1538 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
1817 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
1539 | #define VIDEO_DIP_SELECT_SPD (3 << 19) |
1818 | #define VIDEO_DIP_SELECT_SPD (3 << 19) |
1540 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
1819 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
1541 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
1820 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
1542 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
1821 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
- | 1822 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
|
- | 1823 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
|
- | 1824 | /* HSW and later: */ |
|
- | 1825 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
|
- | 1826 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
|
- | 1827 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
|
- | 1828 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
|
- | 1829 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
|
Line 1543... | Line 1830... | ||
1543 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
1830 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
1544 | 1831 | ||
1545 | /* Panel power sequencing */ |
1832 | /* Panel power sequencing */ |
1546 | #define PP_STATUS 0x61200 |
1833 | #define PP_STATUS 0x61200 |
Line 1609... | Line 1896... | ||
1609 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
1896 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
Line 1610... | Line 1897... | ||
1610 | 1897 | ||
Line 1611... | Line 1898... | ||
1611 | #define PFIT_AUTO_RATIOS 0x61238 |
1898 | #define PFIT_AUTO_RATIOS 0x61238 |
1612 | - | ||
1613 | /* Backlight control */ |
- | |
1614 | #define BLC_PWM_CTL 0x61254 |
1899 | |
- | 1900 | /* Backlight control */ |
|
1615 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
1901 | #define BLC_PWM_CTL2 0x61250 /* 965+ only */ |
- | 1902 | #define BLM_PWM_ENABLE (1 << 31) |
|
- | 1903 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
|
- | 1904 | #define BLM_PIPE_SELECT (1 << 29) |
|
- | 1905 | #define BLM_PIPE_SELECT_IVB (3 << 29) |
|
- | 1906 | #define BLM_PIPE_A (0 << 29) |
|
- | 1907 | #define BLM_PIPE_B (1 << 29) |
|
- | 1908 | #define BLM_PIPE_C (2 << 29) /* ivb + */ |
|
- | 1909 | #define BLM_PIPE(pipe) ((pipe) << 29) |
|
- | 1910 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
|
- | 1911 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) |
|
- | 1912 | #define BLM_PHASE_IN_ENABLE (1 << 25) |
|
- | 1913 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) |
|
- | 1914 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) |
|
- | 1915 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) |
|
- | 1916 | #define BLM_PHASE_IN_COUNT_SHIFT (8) |
|
- | 1917 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
|
- | 1918 | #define BLM_PHASE_IN_INCR_SHIFT (0) |
|
1616 | #define BLC_PWM_CTL2 0x61250 /* 965+ only */ |
1919 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) |
1617 | #define BLM_COMBINATION_MODE (1 << 30) |
1920 | #define BLC_PWM_CTL 0x61254 |
1618 | /* |
1921 | /* |
1619 | * This is the most significant 15 bits of the number of backlight cycles in a |
1922 | * This is the most significant 15 bits of the number of backlight cycles in a |
1620 | * complete cycle of the modulated backlight control. |
1923 | * complete cycle of the modulated backlight control. |
1621 | * |
1924 | * |
- | 1925 | * The actual value is this field multiplied by two. |
|
1622 | * The actual value is this field multiplied by two. |
1926 | */ |
1623 | */ |
1927 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
1624 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
1928 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
1625 | #define BLM_LEGACY_MODE (1 << 16) |
1929 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ |
1626 | /* |
1930 | /* |
1627 | * This is the number of cycles out of the backlight modulation cycle for which |
1931 | * This is the number of cycles out of the backlight modulation cycle for which |
1628 | * the backlight is on. |
1932 | * the backlight is on. |
1629 | * |
1933 | * |
1630 | * This field must be no greater than the number of cycles in the complete |
1934 | * This field must be no greater than the number of cycles in the complete |
1631 | * backlight modulation cycle. |
1935 | * backlight modulation cycle. |
1632 | */ |
1936 | */ |
- | 1937 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
|
- | 1938 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
|
Line 1633... | Line 1939... | ||
1633 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
1939 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
Line -... | Line 1940... | ||
- | 1940 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
|
- | 1941 | ||
- | 1942 | #define BLC_HIST_CTL 0x61260 |
|
- | 1943 | ||
- | 1944 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
|
- | 1945 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
|
- | 1946 | #define BLC_PWM_CPU_CTL2 0x48250 |
|
- | 1947 | #define BLC_PWM_CPU_CTL 0x48254 |
|
- | 1948 | ||
- | 1949 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
|
- | 1950 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ |
|
- | 1951 | #define BLC_PWM_PCH_CTL1 0xc8250 |
|
- | 1952 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
|
1634 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
1953 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
1635 | 1954 | #define BLM_PCH_POLARITY (1 << 29) |
|
1636 | #define BLC_HIST_CTL 0x61260 |
1955 | #define BLC_PWM_PCH_CTL2 0xc8254 |
1637 | 1956 | ||
1638 | /* TV port control */ |
1957 | /* TV port control */ |
Line 2305... | Line 2624... | ||
2305 | 2624 | ||
Line 2306... | Line 2625... | ||
2306 | /* Display & cursor control */ |
2625 | /* Display & cursor control */ |
2307 | 2626 | ||
2308 | /* Pipe A */ |
2627 | /* Pipe A */ |
- | 2628 | #define _PIPEADSL 0x70000 |
|
2309 | #define _PIPEADSL 0x70000 |
2629 | #define DSL_LINEMASK_GEN2 0x00000fff |
2310 | #define DSL_LINEMASK 0x00000fff |
2630 | #define DSL_LINEMASK_GEN3 0x00001fff |
2311 | #define _PIPEACONF 0x70008 |
2631 | #define _PIPEACONF 0x70008 |
2312 | #define PIPECONF_ENABLE (1<<31) |
2632 | #define PIPECONF_ENABLE (1<<31) |
2313 | #define PIPECONF_DISABLE 0 |
2633 | #define PIPECONF_DISABLE 0 |
- | 2634 | #define PIPECONF_DOUBLE_WIDE (1<<30) |
|
2314 | #define PIPECONF_DOUBLE_WIDE (1<<30) |
2635 | #define I965_PIPECONF_ACTIVE (1<<30) |
2315 | #define I965_PIPECONF_ACTIVE (1<<30) |
2636 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
2316 | #define PIPECONF_SINGLE_WIDE 0 |
2637 | #define PIPECONF_SINGLE_WIDE 0 |
2317 | #define PIPECONF_PIPE_UNLOCKED 0 |
2638 | #define PIPECONF_PIPE_UNLOCKED 0 |
2318 | #define PIPECONF_PIPE_LOCKED (1<<25) |
2639 | #define PIPECONF_PIPE_LOCKED (1<<25) |
2319 | #define PIPECONF_PALETTE 0 |
2640 | #define PIPECONF_PALETTE 0 |
- | 2641 | #define PIPECONF_GAMMA (1<<24) |
|
- | 2642 | #define PIPECONF_FORCE_BORDER (1<<25) |
|
- | 2643 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
|
2320 | #define PIPECONF_GAMMA (1<<24) |
2644 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
- | 2645 | * fitting must be disabled on pre-ilk for interlaced. */ |
|
- | 2646 | #define PIPECONF_PROGRESSIVE (0 << 21) |
|
2321 | #define PIPECONF_FORCE_BORDER (1<<25) |
2647 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ |
2322 | #define PIPECONF_PROGRESSIVE (0 << 21) |
2648 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ |
- | 2649 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
|
- | 2650 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ |
|
- | 2651 | /* Ironlake and later have a complete new set of values for interlaced. PFIT |
|
- | 2652 | * means panel fitter required, PF means progressive fetch, DBL means power |
|
2323 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
2653 | * saving pixel doubling. */ |
- | 2654 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) |
|
- | 2655 | #define PIPECONF_INTERLACED_ILK (3 << 21) |
|
2324 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) |
2656 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
2325 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
2657 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
2326 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
2658 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
2327 | #define PIPECONF_BPP_MASK (0x000000e0) |
2659 | #define PIPECONF_BPP_MASK (0x000000e0) |
2328 | #define PIPECONF_BPP_8 (0<<5) |
2660 | #define PIPECONF_BPP_8 (0<<5) |
Line 2335... | Line 2667... | ||
2335 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) |
2667 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) |
2336 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) |
2668 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) |
2337 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
2669 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
2338 | #define _PIPEASTAT 0x70024 |
2670 | #define _PIPEASTAT 0x70024 |
2339 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
2671 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
- | 2672 | #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) |
|
2340 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
2673 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
2341 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
2674 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
2342 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
2675 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
- | 2676 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
|
2343 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
2677 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
2344 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
2678 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
2345 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
2679 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
2346 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
2680 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
- | 2681 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) |
|
2347 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
2682 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
2348 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
2683 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
2349 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
2684 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
2350 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
2685 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
2351 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
2686 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
2352 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
2687 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
- | 2688 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
|
2353 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
2689 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
- | 2690 | #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
|
- | 2691 | #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
|
2354 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
2692 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
2355 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
2693 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
2356 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
2694 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
- | 2695 | #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) |
|
2357 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
2696 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
2358 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
2697 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
2359 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
2698 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
2360 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) |
2699 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) |
2361 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
2700 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
Line 2376... | Line 2715... | ||
2376 | #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
2715 | #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
2377 | #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
2716 | #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
2378 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
2717 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
2379 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
2718 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
Line -... | Line 2719... | ||
- | 2719 | ||
- | 2720 | #define VLV_DPFLIPSTAT 0x70028 |
|
- | 2721 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
|
- | 2722 | #define PIPEB_HLINE_INT_EN (1<<28) |
|
- | 2723 | #define PIPEB_VBLANK_INT_EN (1<<27) |
|
- | 2724 | #define SPRITED_FLIPDONE_INT_EN (1<<26) |
|
- | 2725 | #define SPRITEC_FLIPDONE_INT_EN (1<<25) |
|
- | 2726 | #define PLANEB_FLIPDONE_INT_EN (1<<24) |
|
- | 2727 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
|
- | 2728 | #define PIPEA_HLINE_INT_EN (1<<20) |
|
- | 2729 | #define PIPEA_VBLANK_INT_EN (1<<19) |
|
- | 2730 | #define SPRITEB_FLIPDONE_INT_EN (1<<18) |
|
- | 2731 | #define SPRITEA_FLIPDONE_INT_EN (1<<17) |
|
- | 2732 | #define PLANEA_FLIPDONE_INT_EN (1<<16) |
|
- | 2733 | ||
- | 2734 | #define DPINVGTT 0x7002c /* VLV only */ |
|
- | 2735 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) |
|
- | 2736 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) |
|
- | 2737 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) |
|
- | 2738 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) |
|
- | 2739 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) |
|
- | 2740 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) |
|
- | 2741 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) |
|
- | 2742 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) |
|
- | 2743 | #define DPINVGTT_EN_MASK 0xff0000 |
|
- | 2744 | #define CURSORB_INVALID_GTT_STATUS (1<<7) |
|
- | 2745 | #define CURSORA_INVALID_GTT_STATUS (1<<6) |
|
- | 2746 | #define SPRITED_INVALID_GTT_STATUS (1<<5) |
|
- | 2747 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) |
|
- | 2748 | #define PLANEB_INVALID_GTT_STATUS (1<<3) |
|
- | 2749 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) |
|
- | 2750 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) |
|
- | 2751 | #define PLANEA_INVALID_GTT_STATUS (1<<0) |
|
- | 2752 | #define DPINVGTT_STATUS_MASK 0xff |
|
2380 | 2753 | ||
2381 | #define DSPARB 0x70030 |
2754 | #define DSPARB 0x70030 |
2382 | #define DSPARB_CSTART_MASK (0x7f << 7) |
2755 | #define DSPARB_CSTART_MASK (0x7f << 7) |
2383 | #define DSPARB_CSTART_SHIFT 7 |
2756 | #define DSPARB_CSTART_SHIFT 7 |
2384 | #define DSPARB_BSTART_MASK (0x7f) |
2757 | #define DSPARB_BSTART_MASK (0x7f) |
Line 2405... | Line 2778... | ||
2405 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
2778 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
2406 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
2779 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
2407 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
2780 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
2408 | #define DSPFW_HPLL_SR_MASK (0x1ff) |
2781 | #define DSPFW_HPLL_SR_MASK (0x1ff) |
Line -... | Line 2782... | ||
- | 2782 | ||
- | 2783 | /* drain latency register values*/ |
|
- | 2784 | #define DRAIN_LATENCY_PRECISION_32 32 |
|
- | 2785 | #define DRAIN_LATENCY_PRECISION_16 16 |
|
- | 2786 | #define VLV_DDL1 0x70050 |
|
- | 2787 | #define DDL_CURSORA_PRECISION_32 (1<<31) |
|
- | 2788 | #define DDL_CURSORA_PRECISION_16 (0<<31) |
|
- | 2789 | #define DDL_CURSORA_SHIFT 24 |
|
- | 2790 | #define DDL_PLANEA_PRECISION_32 (1<<7) |
|
- | 2791 | #define DDL_PLANEA_PRECISION_16 (0<<7) |
|
- | 2792 | #define VLV_DDL2 0x70054 |
|
- | 2793 | #define DDL_CURSORB_PRECISION_32 (1<<31) |
|
- | 2794 | #define DDL_CURSORB_PRECISION_16 (0<<31) |
|
- | 2795 | #define DDL_CURSORB_SHIFT 24 |
|
- | 2796 | #define DDL_PLANEB_PRECISION_32 (1<<7) |
|
- | 2797 | #define DDL_PLANEB_PRECISION_16 (0<<7) |
|
2409 | 2798 | ||
2410 | /* FIFO watermark sizes etc */ |
2799 | /* FIFO watermark sizes etc */ |
2411 | #define G4X_FIFO_LINE_SIZE 64 |
2800 | #define G4X_FIFO_LINE_SIZE 64 |
2412 | #define I915_FIFO_LINE_SIZE 64 |
2801 | #define I915_FIFO_LINE_SIZE 64 |
Line -... | Line 2802... | ||
- | 2802 | #define I830_FIFO_LINE_SIZE 32 |
|
2413 | #define I830_FIFO_LINE_SIZE 32 |
2803 | |
2414 | 2804 | #define VALLEYVIEW_FIFO_SIZE 255 |
|
2415 | #define G4X_FIFO_SIZE 127 |
2805 | #define G4X_FIFO_SIZE 127 |
2416 | #define I965_FIFO_SIZE 512 |
2806 | #define I965_FIFO_SIZE 512 |
2417 | #define I945_FIFO_SIZE 127 |
2807 | #define I945_FIFO_SIZE 127 |
2418 | #define I915_FIFO_SIZE 95 |
2808 | #define I915_FIFO_SIZE 95 |
Line -... | Line 2809... | ||
- | 2809 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
|
2419 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
2810 | #define I830_FIFO_SIZE 95 |
2420 | #define I830_FIFO_SIZE 95 |
2811 | |
Line 2421... | Line 2812... | ||
2421 | 2812 | #define VALLEYVIEW_MAX_WM 0xff |
|
2422 | #define G4X_MAX_WM 0x3f |
2813 | #define G4X_MAX_WM 0x3f |
Line 2431... | Line 2822... | ||
2431 | #define PINEVIEW_CURSOR_FIFO 64 |
2822 | #define PINEVIEW_CURSOR_FIFO 64 |
2432 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
2823 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
2433 | #define PINEVIEW_CURSOR_DFT_WM 0 |
2824 | #define PINEVIEW_CURSOR_DFT_WM 0 |
2434 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
2825 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
Line -... | Line 2826... | ||
- | 2826 | ||
2435 | 2827 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
|
2436 | #define I965_CURSOR_FIFO 64 |
2828 | #define I965_CURSOR_FIFO 64 |
2437 | #define I965_CURSOR_MAX_WM 32 |
2829 | #define I965_CURSOR_MAX_WM 32 |
Line 2438... | Line 2830... | ||
2438 | #define I965_CURSOR_DFT_WM 8 |
2830 | #define I965_CURSOR_DFT_WM 8 |
Line 2638... | Line 3030... | ||
2638 | #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) |
3030 | #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) |
2639 | #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) |
3031 | #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) |
2640 | #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) |
3032 | #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) |
2641 | #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) |
3033 | #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) |
2642 | #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) |
3034 | #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) |
- | 3035 | #define DSPLINOFF(plane) DSPADDR(plane) |
|
- | 3036 | ||
- | 3037 | /* Display/Sprite base address macros */ |
|
- | 3038 | #define DISP_BASEADDR_MASK (0xfffff000) |
|
- | 3039 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
|
- | 3040 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
|
- | 3041 | #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ |
|
- | 3042 | (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) |
|
Line 2643... | Line 3043... | ||
2643 | 3043 | ||
2644 | /* VBIOS flags */ |
3044 | /* VBIOS flags */ |
2645 | #define SWF00 0x71410 |
3045 | #define SWF00 0x71410 |
2646 | #define SWF01 0x71414 |
3046 | #define SWF01 0x71414 |
Line 2687... | Line 3087... | ||
2687 | #define DVS_FORMAT_YUV422 (0<<25) |
3087 | #define DVS_FORMAT_YUV422 (0<<25) |
2688 | #define DVS_FORMAT_RGBX101010 (1<<25) |
3088 | #define DVS_FORMAT_RGBX101010 (1<<25) |
2689 | #define DVS_FORMAT_RGBX888 (2<<25) |
3089 | #define DVS_FORMAT_RGBX888 (2<<25) |
2690 | #define DVS_FORMAT_RGBX161616 (3<<25) |
3090 | #define DVS_FORMAT_RGBX161616 (3<<25) |
2691 | #define DVS_SOURCE_KEY (1<<22) |
3091 | #define DVS_SOURCE_KEY (1<<22) |
2692 | #define DVS_RGB_ORDER_RGBX (1<<20) |
3092 | #define DVS_RGB_ORDER_XBGR (1<<20) |
2693 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
3093 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
2694 | #define DVS_YUV_ORDER_YUYV (0<<16) |
3094 | #define DVS_YUV_ORDER_YUYV (0<<16) |
2695 | #define DVS_YUV_ORDER_UYVY (1<<16) |
3095 | #define DVS_YUV_ORDER_UYVY (1<<16) |
2696 | #define DVS_YUV_ORDER_YVYU (2<<16) |
3096 | #define DVS_YUV_ORDER_YVYU (2<<16) |
2697 | #define DVS_YUV_ORDER_VYUY (3<<16) |
3097 | #define DVS_YUV_ORDER_VYUY (3<<16) |
Line 2971... | Line 3371... | ||
2971 | #define DE_ERR_DEBUG_IVB (1<<30) |
3371 | #define DE_ERR_DEBUG_IVB (1<<30) |
2972 | #define DE_GSE_IVB (1<<29) |
3372 | #define DE_GSE_IVB (1<<29) |
2973 | #define DE_PCH_EVENT_IVB (1<<28) |
3373 | #define DE_PCH_EVENT_IVB (1<<28) |
2974 | #define DE_DP_A_HOTPLUG_IVB (1<<27) |
3374 | #define DE_DP_A_HOTPLUG_IVB (1<<27) |
2975 | #define DE_AUX_CHANNEL_A_IVB (1<<26) |
3375 | #define DE_AUX_CHANNEL_A_IVB (1<<26) |
- | 3376 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
|
- | 3377 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) |
|
- | 3378 | #define DE_PIPEC_VBLANK_IVB (1<<10) |
|
2976 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
3379 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
2977 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
- | |
2978 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
3380 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
2979 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
- | |
2980 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
3381 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
- | 3382 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
|
- | 3383 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) |
|
2981 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
3384 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
Line -... | Line 3385... | ||
- | 3385 | ||
- | 3386 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
|
- | 3387 | #define MASTER_INTERRUPT_ENABLE (1<<31) |
|
2982 | 3388 | ||
2983 | #define DEISR 0x44000 |
3389 | #define DEISR 0x44000 |
2984 | #define DEIMR 0x44004 |
3390 | #define DEIMR 0x44004 |
2985 | #define DEIIR 0x44008 |
3391 | #define DEIIR 0x44008 |
Line 2986... | Line 3392... | ||
2986 | #define DEIER 0x4400c |
3392 | #define DEIER 0x4400c |
- | 3393 | ||
- | 3394 | /* GT interrupt. |
|
- | 3395 | * Note that for gen6+ the ring-specific interrupt bits do alias with the |
|
- | 3396 | * corresponding bits in the per-ring interrupt control registers. */ |
|
- | 3397 | #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
|
- | 3398 | #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) |
|
- | 3399 | #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) |
|
- | 3400 | #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) |
|
- | 3401 | #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) |
|
2987 | 3402 | #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ |
|
- | 3403 | #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) |
|
2988 | /* GT interrupt */ |
3404 | #define GT_PIPE_NOTIFY (1 << 4) |
2989 | #define GT_PIPE_NOTIFY (1 << 4) |
3405 | #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) |
2990 | #define GT_SYNC_STATUS (1 << 2) |
- | |
2991 | #define GT_USER_INTERRUPT (1 << 0) |
- | |
2992 | #define GT_BSD_USER_INTERRUPT (1 << 5) |
- | |
Line 2993... | Line 3406... | ||
2993 | #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) |
3406 | #define GT_SYNC_STATUS (1 << 2) |
2994 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
3407 | #define GT_USER_INTERRUPT (1 << 0) |
2995 | 3408 | ||
2996 | #define GTISR 0x44010 |
3409 | #define GTISR 0x44010 |
Line 3026... | Line 3439... | ||
3026 | 3439 | ||
3027 | #define DISP_ARB_CTL 0x45000 |
3440 | #define DISP_ARB_CTL 0x45000 |
3028 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
3441 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
Line -... | Line 3442... | ||
- | 3442 | #define DISP_FBC_WM_DIS (1<<15) |
|
- | 3443 | ||
- | 3444 | /* GEN7 chicken */ |
|
- | 3445 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
|
- | 3446 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
|
- | 3447 | ||
- | 3448 | #define GEN7_L3CNTLREG1 0xB01C |
|
- | 3449 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C |
|
- | 3450 | ||
- | 3451 | #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 |
|
- | 3452 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
|
- | 3453 | ||
- | 3454 | /* WaCatErrorRejectionIssue */ |
|
- | 3455 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
|
3029 | #define DISP_FBC_WM_DIS (1<<15) |
3456 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
Line 3030... | Line 3457... | ||
3030 | 3457 | ||
3031 | /* PCH */ |
3458 | /* PCH */ |
3032 | 3459 | ||
3033 | /* south display engine interrupt */ |
3460 | /* south display engine interrupt: IBX */ |
3034 | #define SDE_AUDIO_POWER_D (1 << 27) |
3461 | #define SDE_AUDIO_POWER_D (1 << 27) |
3035 | #define SDE_AUDIO_POWER_C (1 << 26) |
3462 | #define SDE_AUDIO_POWER_C (1 << 26) |
Line 3064... | Line 3491... | ||
3064 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) |
3491 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) |
3065 | #define SDE_TRANSA_CRC_DONE (1 << 2) |
3492 | #define SDE_TRANSA_CRC_DONE (1 << 2) |
3066 | #define SDE_TRANSA_CRC_ERR (1 << 1) |
3493 | #define SDE_TRANSA_CRC_ERR (1 << 1) |
3067 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) |
3494 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) |
3068 | #define SDE_TRANS_MASK (0x3f) |
3495 | #define SDE_TRANS_MASK (0x3f) |
- | 3496 | ||
- | 3497 | /* south display engine interrupt: CPT/PPT */ |
|
- | 3498 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) |
|
- | 3499 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) |
|
- | 3500 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) |
|
- | 3501 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 |
|
- | 3502 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
|
3069 | /* CPT */ |
3503 | #define SDE_AUXD_CPT (1 << 27) |
- | 3504 | #define SDE_AUXC_CPT (1 << 26) |
|
- | 3505 | #define SDE_AUXB_CPT (1 << 25) |
|
3070 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
3506 | #define SDE_AUX_MASK_CPT (7 << 25) |
3071 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
3507 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
3072 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
3508 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
3073 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
3509 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
- | 3510 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
|
3074 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
3511 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
3075 | SDE_PORTD_HOTPLUG_CPT | \ |
3512 | SDE_PORTD_HOTPLUG_CPT | \ |
3076 | SDE_PORTC_HOTPLUG_CPT | \ |
3513 | SDE_PORTC_HOTPLUG_CPT | \ |
3077 | SDE_PORTB_HOTPLUG_CPT) |
3514 | SDE_PORTB_HOTPLUG_CPT) |
- | 3515 | #define SDE_GMBUS_CPT (1 << 17) |
|
- | 3516 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
|
- | 3517 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
|
- | 3518 | #define SDE_FDI_RXC_CPT (1 << 8) |
|
- | 3519 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
|
- | 3520 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
|
- | 3521 | #define SDE_FDI_RXB_CPT (1 << 4) |
|
- | 3522 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
|
- | 3523 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
|
- | 3524 | #define SDE_FDI_RXA_CPT (1 << 0) |
|
- | 3525 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ |
|
- | 3526 | SDE_AUDIO_CP_REQ_B_CPT | \ |
|
- | 3527 | SDE_AUDIO_CP_REQ_A_CPT) |
|
- | 3528 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ |
|
- | 3529 | SDE_AUDIO_CP_CHG_B_CPT | \ |
|
- | 3530 | SDE_AUDIO_CP_CHG_A_CPT) |
|
- | 3531 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ |
|
- | 3532 | SDE_FDI_RXB_CPT | \ |
|
- | 3533 | SDE_FDI_RXA_CPT) |
|
Line 3078... | Line 3534... | ||
3078 | 3534 | ||
3079 | #define SDEISR 0xc4000 |
3535 | #define SDEISR 0xc4000 |
3080 | #define SDEIMR 0xc4004 |
3536 | #define SDEIMR 0xc4004 |
3081 | #define SDEIIR 0xc4008 |
3537 | #define SDEIIR 0xc4008 |
Line 3125... | Line 3581... | ||
3125 | #define PCH_GMBUS4 0xc5110 |
3581 | #define PCH_GMBUS4 0xc5110 |
3126 | #define PCH_GMBUS5 0xc5120 |
3582 | #define PCH_GMBUS5 0xc5120 |
Line 3127... | Line 3583... | ||
3127 | 3583 | ||
3128 | #define _PCH_DPLL_A 0xc6014 |
3584 | #define _PCH_DPLL_A 0xc6014 |
3129 | #define _PCH_DPLL_B 0xc6018 |
3585 | #define _PCH_DPLL_B 0xc6018 |
Line 3130... | Line 3586... | ||
3130 | #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
3586 | #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
3131 | 3587 | ||
3132 | #define _PCH_FPA0 0xc6040 |
3588 | #define _PCH_FPA0 0xc6040 |
3133 | #define FP_CB_TUNE (0x3<<22) |
3589 | #define FP_CB_TUNE (0x3<<22) |
3134 | #define _PCH_FPA1 0xc6044 |
3590 | #define _PCH_FPA1 0xc6044 |
3135 | #define _PCH_FPB0 0xc6048 |
3591 | #define _PCH_FPB0 0xc6048 |
3136 | #define _PCH_FPB1 0xc604c |
3592 | #define _PCH_FPB1 0xc604c |
Line 3137... | Line 3593... | ||
3137 | #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) |
3593 | #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
Line 3138... | Line 3594... | ||
3138 | #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1) |
3594 | #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) |
3139 | 3595 | ||
Line 3203... | Line 3659... | ||
3203 | #define TRANS_VBLANK_END_SHIFT 16 |
3659 | #define TRANS_VBLANK_END_SHIFT 16 |
3204 | #define TRANS_VBLANK_START_SHIFT 0 |
3660 | #define TRANS_VBLANK_START_SHIFT 0 |
3205 | #define _TRANS_VSYNC_A 0xe0014 |
3661 | #define _TRANS_VSYNC_A 0xe0014 |
3206 | #define TRANS_VSYNC_END_SHIFT 16 |
3662 | #define TRANS_VSYNC_END_SHIFT 16 |
3207 | #define TRANS_VSYNC_START_SHIFT 0 |
3663 | #define TRANS_VSYNC_START_SHIFT 0 |
- | 3664 | #define _TRANS_VSYNCSHIFT_A 0xe0028 |
|
Line 3208... | Line 3665... | ||
3208 | 3665 | ||
3209 | #define _TRANSA_DATA_M1 0xe0030 |
3666 | #define _TRANSA_DATA_M1 0xe0030 |
3210 | #define _TRANSA_DATA_N1 0xe0034 |
3667 | #define _TRANSA_DATA_N1 0xe0034 |
3211 | #define _TRANSA_DATA_M2 0xe0038 |
3668 | #define _TRANSA_DATA_M2 0xe0038 |
Line 3227... | Line 3684... | ||
3227 | 3684 | ||
3228 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
3685 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
3229 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
3686 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
Line -... | Line 3687... | ||
- | 3687 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
|
- | 3688 | ||
- | 3689 | #define VLV_VIDEO_DIP_CTL_A 0x60220 |
|
- | 3690 | #define VLV_VIDEO_DIP_DATA_A 0x60208 |
|
- | 3691 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 |
|
- | 3692 | ||
- | 3693 | #define VLV_VIDEO_DIP_CTL_B 0x61170 |
|
- | 3694 | #define VLV_VIDEO_DIP_DATA_B 0x61174 |
|
- | 3695 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 |
|
- | 3696 | ||
- | 3697 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
|
- | 3698 | _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) |
|
- | 3699 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
|
- | 3700 | _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) |
|
- | 3701 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
|
- | 3702 | _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) |
|
- | 3703 | ||
- | 3704 | /* Haswell DIP controls */ |
|
- | 3705 | #define HSW_VIDEO_DIP_CTL_A 0x60200 |
|
- | 3706 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
|
- | 3707 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
|
- | 3708 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
|
- | 3709 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
|
- | 3710 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
|
- | 3711 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
|
- | 3712 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
|
- | 3713 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
|
- | 3714 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
|
- | 3715 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
|
- | 3716 | #define HSW_VIDEO_DIP_GCP_A 0x60210 |
|
- | 3717 | ||
- | 3718 | #define HSW_VIDEO_DIP_CTL_B 0x61200 |
|
- | 3719 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
|
- | 3720 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
|
- | 3721 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
|
- | 3722 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
|
- | 3723 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
|
- | 3724 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
|
- | 3725 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
|
- | 3726 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
|
- | 3727 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
|
- | 3728 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
|
- | 3729 | #define HSW_VIDEO_DIP_GCP_B 0x61210 |
|
- | 3730 | ||
- | 3731 | #define HSW_TVIDEO_DIP_CTL(pipe) \ |
|
- | 3732 | _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) |
|
- | 3733 | #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ |
|
- | 3734 | _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) |
|
- | 3735 | #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ |
|
- | 3736 | _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) |
|
- | 3737 | #define HSW_TVIDEO_DIP_GCP(pipe) \ |
|
3230 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
3738 | _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) |
3231 | 3739 | ||
3232 | #define _TRANS_HTOTAL_B 0xe1000 |
3740 | #define _TRANS_HTOTAL_B 0xe1000 |
3233 | #define _TRANS_HBLANK_B 0xe1004 |
3741 | #define _TRANS_HBLANK_B 0xe1004 |
3234 | #define _TRANS_HSYNC_B 0xe1008 |
3742 | #define _TRANS_HSYNC_B 0xe1008 |
3235 | #define _TRANS_VTOTAL_B 0xe100c |
3743 | #define _TRANS_VTOTAL_B 0xe100c |
- | 3744 | #define _TRANS_VBLANK_B 0xe1010 |
|
Line 3236... | Line 3745... | ||
3236 | #define _TRANS_VBLANK_B 0xe1010 |
3745 | #define _TRANS_VSYNC_B 0xe1014 |
3237 | #define _TRANS_VSYNC_B 0xe1014 |
3746 | #define _TRANS_VSYNCSHIFT_B 0xe1028 |
3238 | 3747 | ||
3239 | #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) |
3748 | #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) |
3240 | #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) |
3749 | #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) |
3241 | #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) |
3750 | #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) |
- | 3751 | #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) |
|
- | 3752 | #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) |
|
Line 3242... | Line 3753... | ||
3242 | #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) |
3753 | #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) |
3243 | #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) |
3754 | #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ |
3244 | #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) |
3755 | _TRANS_VSYNCSHIFT_B) |
3245 | 3756 | ||
Line 3273... | Line 3784... | ||
3273 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) |
3784 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) |
3274 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) |
3785 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) |
3275 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) |
3786 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) |
3276 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
3787 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
3277 | #define TRANS_DP_VIDEO_AUDIO (0<<26) |
3788 | #define TRANS_DP_VIDEO_AUDIO (0<<26) |
- | 3789 | #define TRANS_INTERLACE_MASK (7<<21) |
|
3278 | #define TRANS_PROGRESSIVE (0<<21) |
3790 | #define TRANS_PROGRESSIVE (0<<21) |
- | 3791 | #define TRANS_INTERLACED (3<<21) |
|
- | 3792 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
|
3279 | #define TRANS_8BPC (0<<5) |
3793 | #define TRANS_8BPC (0<<5) |
3280 | #define TRANS_10BPC (1<<5) |
3794 | #define TRANS_10BPC (1<<5) |
3281 | #define TRANS_6BPC (2<<5) |
3795 | #define TRANS_6BPC (2<<5) |
3282 | #define TRANS_12BPC (3<<5) |
3796 | #define TRANS_12BPC (3<<5) |
Line 3381... | Line 3895... | ||
3381 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
3895 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
3382 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
3896 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
3383 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
3897 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
3384 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
3898 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
3385 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
3899 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
- | 3900 | /* LPT */ |
|
- | 3901 | #define FDI_PORT_WIDTH_2X_LPT (1<<19) |
|
- | 3902 | #define FDI_PORT_WIDTH_1X_LPT (0<<19) |
|
Line 3386... | Line 3903... | ||
3386 | 3903 | ||
3387 | #define _FDI_RXA_MISC 0xf0010 |
3904 | #define _FDI_RXA_MISC 0xf0010 |
3388 | #define _FDI_RXB_MISC 0xf1010 |
3905 | #define _FDI_RXB_MISC 0xf1010 |
3389 | #define _FDI_RXA_TUSIZE1 0xf0030 |
3906 | #define _FDI_RXA_TUSIZE1 0xf0030 |
3390 | #define _FDI_RXA_TUSIZE2 0xf0038 |
3907 | #define _FDI_RXA_TUSIZE2 0xf0038 |
3391 | #define _FDI_RXB_TUSIZE1 0xf1030 |
3908 | #define _FDI_RXB_TUSIZE1 0xf1030 |
- | 3909 | #define _FDI_RXB_TUSIZE2 0xf1038 |
|
- | 3910 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) |
|
- | 3911 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) |
|
3392 | #define _FDI_RXB_TUSIZE2 0xf1038 |
3912 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) |
3393 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
3913 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
3394 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
3914 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
Line 3395... | Line 3915... | ||
3395 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) |
3915 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) |
Line 3415... | Line 3935... | ||
3415 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) |
3935 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) |
Line 3416... | Line 3936... | ||
3416 | 3936 | ||
3417 | #define FDI_PLL_CTL_1 0xfe000 |
3937 | #define FDI_PLL_CTL_1 0xfe000 |
Line 3418... | Line -... | ||
3418 | #define FDI_PLL_CTL_2 0xfe004 |
- | |
3419 | - | ||
3420 | /* CRT */ |
- | |
3421 | #define PCH_ADPA 0xe1100 |
- | |
3422 | #define ADPA_TRANS_SELECT_MASK (1<<30) |
- | |
3423 | #define ADPA_TRANS_A_SELECT 0 |
- | |
3424 | #define ADPA_TRANS_B_SELECT (1<<30) |
- | |
3425 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
- | |
3426 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
- | |
3427 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
- | |
3428 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
- | |
3429 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
- | |
3430 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
- | |
3431 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
- | |
3432 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
- | |
3433 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
- | |
3434 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
- | |
3435 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
- | |
3436 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
- | |
3437 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
- | |
3438 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
- | |
3439 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
- | |
3440 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
- | |
3441 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
- | |
3442 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
- | |
3443 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
3938 | #define FDI_PLL_CTL_2 0xfe004 |
3444 | 3939 | ||
3445 | /* or SDVOB */ |
3940 | /* or SDVOB */ |
3446 | #define HDMIB 0xe1140 |
3941 | #define HDMIB 0xe1140 |
3447 | #define PORT_ENABLE (1 << 31) |
3942 | #define PORT_ENABLE (1 << 31) |
Line 3471... | Line 3966... | ||
3471 | #define HDMID 0xe1160 |
3966 | #define HDMID 0xe1160 |
Line 3472... | Line 3967... | ||
3472 | 3967 | ||
3473 | #define PCH_LVDS 0xe1180 |
3968 | #define PCH_LVDS 0xe1180 |
Line -... | Line 3969... | ||
- | 3969 | #define LVDS_DETECTED (1 << 1) |
|
3474 | #define LVDS_DETECTED (1 << 1) |
3970 | |
3475 | 3971 | /* vlv has 2 sets of panel control regs. */ |
|
3476 | #define BLC_PWM_CPU_CTL2 0x48250 |
3972 | #define PIPEA_PP_STATUS 0x61200 |
3477 | #define PWM_ENABLE (1 << 31) |
3973 | #define PIPEA_PP_CONTROL 0x61204 |
3478 | #define PWM_PIPE_A (0 << 29) |
3974 | #define PIPEA_PP_ON_DELAYS 0x61208 |
3479 | #define PWM_PIPE_B (1 << 29) |
3975 | #define PIPEA_PP_OFF_DELAYS 0x6120c |
3480 | #define BLC_PWM_CPU_CTL 0x48254 |
3976 | #define PIPEA_PP_DIVISOR 0x61210 |
3481 | 3977 | ||
3482 | #define BLC_PWM_PCH_CTL1 0xc8250 |
3978 | #define PIPEB_PP_STATUS 0x61300 |
3483 | #define PWM_PCH_ENABLE (1 << 31) |
- | |
3484 | #define PWM_POLARITY_ACTIVE_LOW (1 << 29) |
3979 | #define PIPEB_PP_CONTROL 0x61304 |
3485 | #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) |
- | |
3486 | #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) |
- | |
3487 | #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) |
3980 | #define PIPEB_PP_ON_DELAYS 0x61308 |
Line 3488... | Line 3981... | ||
3488 | 3981 | #define PIPEB_PP_OFF_DELAYS 0x6130c |
|
3489 | #define BLC_PWM_PCH_CTL2 0xc8254 |
3982 | #define PIPEB_PP_DIVISOR 0x61310 |
3490 | 3983 | ||
3491 | #define PCH_PP_STATUS 0xc7200 |
3984 | #define PCH_PP_STATUS 0xc7200 |
Line 3549... | Line 4042... | ||
3549 | #define PORT_TRANS_A_SEL_CPT 0 |
4042 | #define PORT_TRANS_A_SEL_CPT 0 |
3550 | #define PORT_TRANS_B_SEL_CPT (1<<29) |
4043 | #define PORT_TRANS_B_SEL_CPT (1<<29) |
3551 | #define PORT_TRANS_C_SEL_CPT (2<<29) |
4044 | #define PORT_TRANS_C_SEL_CPT (2<<29) |
3552 | #define PORT_TRANS_SEL_MASK (3<<29) |
4045 | #define PORT_TRANS_SEL_MASK (3<<29) |
3553 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
4046 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
- | 4047 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
|
- | 4048 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) |
|
Line 3554... | Line 4049... | ||
3554 | 4049 | ||
3555 | #define TRANS_DP_CTL_A 0xe0300 |
4050 | #define TRANS_DP_CTL_A 0xe0300 |
3556 | #define TRANS_DP_CTL_B 0xe1300 |
4051 | #define TRANS_DP_CTL_B 0xe1300 |
3557 | #define TRANS_DP_CTL_C 0xe2300 |
4052 | #define TRANS_DP_CTL_C 0xe2300 |
Line 3606... | Line 4101... | ||
3606 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) |
4101 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) |
Line 3607... | Line 4102... | ||
3607 | 4102 | ||
Line 3608... | Line 4103... | ||
3608 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
4103 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
- | 4104 | ||
- | 4105 | #define FORCEWAKE 0xA18C |
|
- | 4106 | #define FORCEWAKE_VLV 0x1300b0 |
|
3609 | 4107 | #define FORCEWAKE_ACK_VLV 0x1300b4 |
|
3610 | #define FORCEWAKE 0xA18C |
4108 | #define FORCEWAKE_ACK_HSW 0x130044 |
3611 | #define FORCEWAKE_ACK 0x130090 |
4109 | #define FORCEWAKE_ACK 0x130090 |
3612 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
4110 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
3613 | #define FORCEWAKE_MT_ACK 0x130040 |
4111 | #define FORCEWAKE_MT_ACK 0x130040 |
Line -... | Line 4112... | ||
- | 4112 | #define ECOBUS 0xa180 |
|
- | 4113 | #define FORCEWAKE_MT_ENABLE (1<<5) |
|
- | 4114 | ||
- | 4115 | #define GTFIFODBG 0x120000 |
|
- | 4116 | #define GT_FIFO_CPU_ERROR_MASK 7 |
|
- | 4117 | #define GT_FIFO_OVFERR (1<<2) |
|
3614 | #define ECOBUS 0xa180 |
4118 | #define GT_FIFO_IAWRERR (1<<1) |
3615 | #define FORCEWAKE_MT_ENABLE (1<<5) |
4119 | #define GT_FIFO_IARDERR (1<<0) |
Line -... | Line 4120... | ||
- | 4120 | ||
- | 4121 | #define GT_FIFO_FREE_ENTRIES 0x120008 |
|
- | 4122 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
|
- | 4123 | ||
3616 | 4124 | #define GEN6_UCGCTL1 0x9400 |
|
- | 4125 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
|
- | 4126 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
|
- | 4127 | ||
3617 | #define GT_FIFO_FREE_ENTRIES 0x120008 |
4128 | #define GEN6_UCGCTL2 0x9404 |
3618 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
4129 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
Line -... | Line 4130... | ||
- | 4130 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
|
- | 4131 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
|
- | 4132 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
|
3619 | 4133 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
|
3620 | #define GEN6_UCGCTL2 0x9404 |
4134 | |
3621 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
4135 | #define GEN7_UCGCTL4 0x940c |
3622 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
4136 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
3623 | 4137 | ||
Line 3650... | Line 4164... | ||
3650 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
4164 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
3651 | #define GEN6_RP_ENABLE (1<<7) |
4165 | #define GEN6_RP_ENABLE (1<<7) |
3652 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
4166 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
3653 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
4167 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) |
3654 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
4168 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) |
- | 4169 | #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) |
|
3655 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
4170 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
3656 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
4171 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
3657 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 |
4172 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 |
3658 | #define GEN6_RP_CUR_UP_EI 0xA050 |
4173 | #define GEN6_RP_CUR_UP_EI 0xA050 |
3659 | #define GEN6_CURICONT_MASK 0xffffff |
4174 | #define GEN6_CURICONT_MASK 0xffffff |
Line 3693... | Line 4208... | ||
3693 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
4208 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) |
3694 | #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
4209 | #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
3695 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
4210 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
3696 | GEN6_PM_RP_DOWN_TIMEOUT) |
4211 | GEN6_PM_RP_DOWN_TIMEOUT) |
Line -... | Line 4212... | ||
- | 4212 | ||
- | 4213 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
|
- | 4214 | #define GEN6_GT_GFX_RC6 0x138108 |
|
- | 4215 | #define GEN6_GT_GFX_RC6p 0x13810C |
|
- | 4216 | #define GEN6_GT_GFX_RC6pp 0x138110 |
|
3697 | 4217 | ||
3698 | #define GEN6_PCODE_MAILBOX 0x138124 |
4218 | #define GEN6_PCODE_MAILBOX 0x138124 |
3699 | #define GEN6_PCODE_READY (1<<31) |
4219 | #define GEN6_PCODE_READY (1<<31) |
3700 | #define GEN6_READ_OC_PARAMS 0xc |
4220 | #define GEN6_READ_OC_PARAMS 0xc |
3701 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
4221 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
Line 3709... | Line 4229... | ||
3709 | #define GEN6_RC0 0 |
4229 | #define GEN6_RC0 0 |
3710 | #define GEN6_RC3 2 |
4230 | #define GEN6_RC3 2 |
3711 | #define GEN6_RC6 3 |
4231 | #define GEN6_RC6 3 |
3712 | #define GEN6_RC7 4 |
4232 | #define GEN6_RC7 4 |
Line -... | Line 4233... | ||
- | 4233 | ||
- | 4234 | #define GEN7_MISCCPCTL (0x9424) |
|
- | 4235 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
|
- | 4236 | ||
- | 4237 | /* IVYBRIDGE DPF */ |
|
- | 4238 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ |
|
- | 4239 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
|
- | 4240 | #define GEN7_PARITY_ERROR_VALID (1<<13) |
|
- | 4241 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) |
|
- | 4242 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) |
|
- | 4243 | #define GEN7_PARITY_ERROR_ROW(reg) \ |
|
- | 4244 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
|
- | 4245 | #define GEN7_PARITY_ERROR_BANK(reg) \ |
|
- | 4246 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
|
- | 4247 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
|
- | 4248 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
|
- | 4249 | #define GEN7_L3CDERRST1_ENABLE (1<<7) |
|
- | 4250 | ||
- | 4251 | #define GEN7_L3LOG_BASE 0xB070 |
|
- | 4252 | #define GEN7_L3LOG_SIZE 0x80 |
|
3713 | 4253 | ||
3714 | #define G4X_AUD_VID_DID 0x62020 |
4254 | #define G4X_AUD_VID_DID 0x62020 |
3715 | #define INTEL_AUDIO_DEVCL 0x808629FB |
4255 | #define INTEL_AUDIO_DEVCL 0x808629FB |
3716 | #define INTEL_AUDIO_DEVBLC 0x80862801 |
4256 | #define INTEL_AUDIO_DEVBLC 0x80862801 |
Line 3722... | Line 4262... | ||
3722 | #define G4X_ELD_ADDR (0xf << 5) |
4262 | #define G4X_ELD_ADDR (0xf << 5) |
3723 | #define G4X_ELD_ACK (1 << 4) |
4263 | #define G4X_ELD_ACK (1 << 4) |
3724 | #define G4X_HDMIW_HDMIEDID 0x6210C |
4264 | #define G4X_HDMIW_HDMIEDID 0x6210C |
Line 3725... | Line 4265... | ||
3725 | 4265 | ||
- | 4266 | #define IBX_HDMIW_HDMIEDID_A 0xE2050 |
|
- | 4267 | #define IBX_HDMIW_HDMIEDID_B 0xE2150 |
|
- | 4268 | #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
|
- | 4269 | IBX_HDMIW_HDMIEDID_A, \ |
|
3726 | #define IBX_HDMIW_HDMIEDID_A 0xE2050 |
4270 | IBX_HDMIW_HDMIEDID_B) |
- | 4271 | #define IBX_AUD_CNTL_ST_A 0xE20B4 |
|
- | 4272 | #define IBX_AUD_CNTL_ST_B 0xE21B4 |
|
- | 4273 | #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
|
- | 4274 | IBX_AUD_CNTL_ST_A, \ |
|
3727 | #define IBX_AUD_CNTL_ST_A 0xE20B4 |
4275 | IBX_AUD_CNTL_ST_B) |
3728 | #define IBX_ELD_BUFFER_SIZE (0x1f << 10) |
4276 | #define IBX_ELD_BUFFER_SIZE (0x1f << 10) |
3729 | #define IBX_ELD_ADDRESS (0x1f << 5) |
4277 | #define IBX_ELD_ADDRESS (0x1f << 5) |
3730 | #define IBX_ELD_ACK (1 << 4) |
4278 | #define IBX_ELD_ACK (1 << 4) |
3731 | #define IBX_AUD_CNTL_ST2 0xE20C0 |
4279 | #define IBX_AUD_CNTL_ST2 0xE20C0 |
3732 | #define IBX_ELD_VALIDB (1 << 0) |
4280 | #define IBX_ELD_VALIDB (1 << 0) |
Line 3733... | Line 4281... | ||
3733 | #define IBX_CP_READYB (1 << 1) |
4281 | #define IBX_CP_READYB (1 << 1) |
- | 4282 | ||
- | 4283 | #define CPT_HDMIW_HDMIEDID_A 0xE5050 |
|
- | 4284 | #define CPT_HDMIW_HDMIEDID_B 0xE5150 |
|
- | 4285 | #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
|
3734 | 4286 | CPT_HDMIW_HDMIEDID_A, \ |
|
- | 4287 | CPT_HDMIW_HDMIEDID_B) |
|
- | 4288 | #define CPT_AUD_CNTL_ST_A 0xE50B4 |
|
- | 4289 | #define CPT_AUD_CNTL_ST_B 0xE51B4 |
|
- | 4290 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
|
3735 | #define CPT_HDMIW_HDMIEDID_A 0xE5050 |
4291 | CPT_AUD_CNTL_ST_A, \ |
Line 3736... | Line 4292... | ||
3736 | #define CPT_AUD_CNTL_ST_A 0xE50B4 |
4292 | CPT_AUD_CNTL_ST_B) |
3737 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
4293 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
3738 | 4294 | ||
3739 | /* These are the 4 32-bit write offset registers for each stream |
4295 | /* These are the 4 32-bit write offset registers for each stream |
3740 | * output buffer. It determines the offset from the |
4296 | * output buffer. It determines the offset from the |
Line -... | Line 4297... | ||
- | 4297 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
|
- | 4298 | */ |
|
- | 4299 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) |
|
- | 4300 | ||
- | 4301 | #define IBX_AUD_CONFIG_A 0xe2000 |
|
- | 4302 | #define IBX_AUD_CONFIG_B 0xe2100 |
|
- | 4303 | #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ |
|
- | 4304 | IBX_AUD_CONFIG_A, \ |
|
- | 4305 | IBX_AUD_CONFIG_B) |
|
- | 4306 | #define CPT_AUD_CONFIG_A 0xe5000 |
|
- | 4307 | #define CPT_AUD_CONFIG_B 0xe5100 |
|
- | 4308 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
|
- | 4309 | CPT_AUD_CONFIG_A, \ |
|
- | 4310 | CPT_AUD_CONFIG_B) |
|
- | 4311 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
|
- | 4312 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
|
- | 4313 | #define AUD_CONFIG_UPPER_N_SHIFT 20 |
|
- | 4314 | #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
|
- | 4315 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
|
- | 4316 | #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
|
- | 4317 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
|
- | 4318 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) |
|
- | 4319 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
|
- | 4320 | ||
- | 4321 | /* HSW Audio */ |
|
- | 4322 | #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
|
- | 4323 | #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ |
|
- | 4324 | #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ |
|
- | 4325 | HSW_AUD_CONFIG_A, \ |
|
- | 4326 | HSW_AUD_CONFIG_B) |
|
- | 4327 | ||
- | 4328 | #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ |
|
- | 4329 | #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ |
|
- | 4330 | #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ |
|
- | 4331 | HSW_AUD_MISC_CTRL_A, \ |
|
- | 4332 | HSW_AUD_MISC_CTRL_B) |
|
- | 4333 | ||
- | 4334 | #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ |
|
- | 4335 | #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ |
|
- | 4336 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ |
|
- | 4337 | HSW_AUD_DIP_ELD_CTRL_ST_A, \ |
|
- | 4338 | HSW_AUD_DIP_ELD_CTRL_ST_B) |
|
- | 4339 | ||
- | 4340 | /* Audio Digital Converter */ |
|
- | 4341 | #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ |
|
- | 4342 | #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ |
|
- | 4343 | #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ |
|
- | 4344 | HSW_AUD_DIG_CNVT_1, \ |
|
- | 4345 | HSW_AUD_DIG_CNVT_2) |
|
- | 4346 | #define DIP_PORT_SEL_MASK 0x3 |
|
- | 4347 | ||
- | 4348 | #define HSW_AUD_EDID_DATA_A 0x65050 |
|
- | 4349 | #define HSW_AUD_EDID_DATA_B 0x65150 |
|
- | 4350 | #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ |
|
- | 4351 | HSW_AUD_EDID_DATA_A, \ |
|
- | 4352 | HSW_AUD_EDID_DATA_B) |
|
- | 4353 | ||
- | 4354 | #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ |
|
- | 4355 | #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ |
|
- | 4356 | #define AUDIO_INACTIVE_C (1<<11) |
|
- | 4357 | #define AUDIO_INACTIVE_B (1<<7) |
|
- | 4358 | #define AUDIO_INACTIVE_A (1<<3) |
|
- | 4359 | #define AUDIO_OUTPUT_ENABLE_A (1<<2) |
|
- | 4360 | #define AUDIO_OUTPUT_ENABLE_B (1<<6) |
|
- | 4361 | #define AUDIO_OUTPUT_ENABLE_C (1<<10) |
|
- | 4362 | #define AUDIO_ELD_VALID_A (1<<0) |
|
- | 4363 | #define AUDIO_ELD_VALID_B (1<<4) |
|
- | 4364 | #define AUDIO_ELD_VALID_C (1<<8) |
|
- | 4365 | #define AUDIO_CP_READY_A (1<<1) |
|
- | 4366 | #define AUDIO_CP_READY_B (1<<5) |
|
- | 4367 | #define AUDIO_CP_READY_C (1<<9) |
|
- | 4368 | ||
- | 4369 | /* HSW Power Wells */ |
|
- | 4370 | #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ |
|
- | 4371 | #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ |
|
- | 4372 | #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ |
|
- | 4373 | #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ |
|
- | 4374 | #define HSW_PWR_WELL_ENABLE (1<<31) |
|
- | 4375 | #define HSW_PWR_WELL_STATE (1<<30) |
|
- | 4376 | #define HSW_PWR_WELL_CTL5 0x45410 |
|
- | 4377 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
|
- | 4378 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
|
- | 4379 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
|
- | 4380 | #define HSW_PWR_WELL_CTL6 0x45414 |
|
- | 4381 | ||
- | 4382 | /* Per-pipe DDI Function Control */ |
|
- | 4383 | #define PIPE_DDI_FUNC_CTL_A 0x60400 |
|
- | 4384 | #define PIPE_DDI_FUNC_CTL_B 0x61400 |
|
- | 4385 | #define PIPE_DDI_FUNC_CTL_C 0x62400 |
|
- | 4386 | #define PIPE_DDI_FUNC_CTL_EDP 0x6F400 |
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- | 4387 | #define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \ |
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- | 4388 | PIPE_DDI_FUNC_CTL_B) |
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- | 4389 | #define PIPE_DDI_FUNC_ENABLE (1<<31) |
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- | 4390 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
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- | 4391 | #define PIPE_DDI_PORT_MASK (7<<28) |
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- | 4392 | #define PIPE_DDI_SELECT_PORT(x) ((x)<<28) |
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- | 4393 | #define PIPE_DDI_MODE_SELECT_MASK (7<<24) |
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- | 4394 | #define PIPE_DDI_MODE_SELECT_HDMI (0<<24) |
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- | 4395 | #define PIPE_DDI_MODE_SELECT_DVI (1<<24) |
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- | 4396 | #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) |
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- | 4397 | #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) |
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- | 4398 | #define PIPE_DDI_MODE_SELECT_FDI (4<<24) |
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- | 4399 | #define PIPE_DDI_BPC_MASK (7<<20) |
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- | 4400 | #define PIPE_DDI_BPC_8 (0<<20) |
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- | 4401 | #define PIPE_DDI_BPC_10 (1<<20) |
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- | 4402 | #define PIPE_DDI_BPC_6 (2<<20) |
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- | 4403 | #define PIPE_DDI_BPC_12 (3<<20) |
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- | 4404 | #define PIPE_DDI_PVSYNC (1<<17) |
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- | 4405 | #define PIPE_DDI_PHSYNC (1<<16) |
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- | 4406 | #define PIPE_DDI_BFI_ENABLE (1<<4) |
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- | 4407 | #define PIPE_DDI_PORT_WIDTH_X1 (0<<1) |
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- | 4408 | #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) |
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- | 4409 | #define PIPE_DDI_PORT_WIDTH_X4 (3<<1) |
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- | 4410 | ||
- | 4411 | /* DisplayPort Transport Control */ |
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- | 4412 | #define DP_TP_CTL_A 0x64040 |
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- | 4413 | #define DP_TP_CTL_B 0x64140 |
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- | 4414 | #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
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- | 4415 | #define DP_TP_CTL_ENABLE (1<<31) |
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- | 4416 | #define DP_TP_CTL_MODE_SST (0<<27) |
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- | 4417 | #define DP_TP_CTL_MODE_MST (1<<27) |
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- | 4418 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
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- | 4419 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
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- | 4420 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
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- | 4421 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) |
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- | 4422 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) |
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- | 4423 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
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- | 4424 | ||
- | 4425 | /* DisplayPort Transport Status */ |
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- | 4426 | #define DP_TP_STATUS_A 0x64044 |
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- | 4427 | #define DP_TP_STATUS_B 0x64144 |
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- | 4428 | #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
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- | 4429 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
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- | 4430 | ||
- | 4431 | /* DDI Buffer Control */ |
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- | 4432 | #define DDI_BUF_CTL_A 0x64000 |
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- | 4433 | #define DDI_BUF_CTL_B 0x64100 |
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- | 4434 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
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- | 4435 | #define DDI_BUF_CTL_ENABLE (1<<31) |
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- | 4436 | #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
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- | 4437 | #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
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- | 4438 | #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
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- | 4439 | #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
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- | 4440 | #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
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- | 4441 | #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
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- | 4442 | #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
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- | 4443 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
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- | 4444 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
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- | 4445 | #define DDI_BUF_EMP_MASK (0xf<<24) |
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- | 4446 | #define DDI_BUF_IS_IDLE (1<<7) |
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- | 4447 | #define DDI_PORT_WIDTH_X1 (0<<1) |
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- | 4448 | #define DDI_PORT_WIDTH_X2 (1<<1) |
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- | 4449 | #define DDI_PORT_WIDTH_X4 (3<<1) |
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- | 4450 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
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- | 4451 | ||
- | 4452 | /* DDI Buffer Translations */ |
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- | 4453 | #define DDI_BUF_TRANS_A 0x64E00 |
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- | 4454 | #define DDI_BUF_TRANS_B 0x64E60 |
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- | 4455 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
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- | 4456 | ||
- | 4457 | /* Sideband Interface (SBI) is programmed indirectly, via |
|
- | 4458 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
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- | 4459 | * which contains the payload */ |
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- | 4460 | #define SBI_ADDR 0xC6000 |
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- | 4461 | #define SBI_DATA 0xC6004 |
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- | 4462 | #define SBI_CTL_STAT 0xC6008 |
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- | 4463 | #define SBI_CTL_OP_CRRD (0x6<<8) |
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- | 4464 | #define SBI_CTL_OP_CRWR (0x7<<8) |
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- | 4465 | #define SBI_RESPONSE_FAIL (0x1<<1) |
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- | 4466 | #define SBI_RESPONSE_SUCCESS (0x0<<1) |
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- | 4467 | #define SBI_BUSY (0x1<<0) |
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- | 4468 | #define SBI_READY (0x0<<0) |
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- | 4469 | ||
- | 4470 | /* SBI offsets */ |
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- | 4471 | #define SBI_SSCDIVINTPHASE6 0x0600 |
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- | 4472 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
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- | 4473 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) |
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- | 4474 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) |
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- | 4475 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) |
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- | 4476 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
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- | 4477 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
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- | 4478 | #define SBI_SSCCTL 0x020c |
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- | 4479 | #define SBI_SSCCTL6 0x060C |
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- | 4480 | #define SBI_SSCCTL_DISABLE (1<<0) |
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- | 4481 | #define SBI_SSCAUXDIV6 0x0610 |
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- | 4482 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) |
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- | 4483 | #define SBI_DBUFF0 0x2a00 |
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- | 4484 | ||
- | 4485 | /* LPT PIXCLK_GATE */ |
|
- | 4486 | #define PIXCLK_GATE 0xC6020 |
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- | 4487 | #define PIXCLK_GATE_UNGATE (1<<0) |
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- | 4488 | #define PIXCLK_GATE_GATE (0<<0) |
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- | 4489 | ||
- | 4490 | /* SPLL */ |
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- | 4491 | #define SPLL_CTL 0x46020 |
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- | 4492 | #define SPLL_PLL_ENABLE (1<<31) |
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- | 4493 | #define SPLL_PLL_SCC (1<<28) |
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- | 4494 | #define SPLL_PLL_NON_SCC (2<<28) |
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- | 4495 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
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- | 4496 | #define SPLL_PLL_FREQ_1350MHz (1<<26) |
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- | 4497 | ||
- | 4498 | /* WRPLL */ |
|
- | 4499 | #define WRPLL_CTL1 0x46040 |
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- | 4500 | #define WRPLL_CTL2 0x46060 |
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- | 4501 | #define WRPLL_PLL_ENABLE (1<<31) |
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- | 4502 | #define WRPLL_PLL_SELECT_SSC (0x01<<28) |
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- | 4503 | #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) |
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- | 4504 | #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) |
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- | 4505 | /* WRPLL divider programming */ |
|
- | 4506 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
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- | 4507 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) |
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- | 4508 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
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- | 4509 | ||
- | 4510 | /* Port clock selection */ |
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- | 4511 | #define PORT_CLK_SEL_A 0x46100 |
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- | 4512 | #define PORT_CLK_SEL_B 0x46104 |
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- | 4513 | #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
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- | 4514 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
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- | 4515 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) |
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- | 4516 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) |
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- | 4517 | #define PORT_CLK_SEL_SPLL (3<<29) |
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- | 4518 | #define PORT_CLK_SEL_WRPLL1 (4<<29) |
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- | 4519 | #define PORT_CLK_SEL_WRPLL2 (5<<29) |
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- | 4520 | ||
- | 4521 | /* Pipe clock selection */ |
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- | 4522 | #define PIPE_CLK_SEL_A 0x46140 |
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- | 4523 | #define PIPE_CLK_SEL_B 0x46144 |
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- | 4524 | #define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B) |
|
- | 4525 | /* For each pipe, we need to select the corresponding port clock */ |
|
- | 4526 | #define PIPE_CLK_SEL_DISABLED (0x0<<29) |
|
- | 4527 | #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) |
|
- | 4528 | ||
- | 4529 | /* LCPLL Control */ |
|
- | 4530 | #define LCPLL_CTL 0x130040 |
|
- | 4531 | #define LCPLL_PLL_DISABLE (1<<31) |
|
- | 4532 | #define LCPLL_PLL_LOCK (1<<30) |
|
- | 4533 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
|
- | 4534 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
|
- | 4535 | ||
- | 4536 | /* Pipe WM_LINETIME - watermark line time */ |
|
- | 4537 | #define PIPE_WM_LINETIME_A 0x45270 |
|
- | 4538 | #define PIPE_WM_LINETIME_B 0x45274 |
|
- | 4539 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ |
|
- | 4540 | PIPE_WM_LINETIME_B) |
|
- | 4541 | #define PIPE_WM_LINETIME_MASK (0x1ff) |
|
- | 4542 | #define PIPE_WM_LINETIME_TIME(x) ((x)) |
|
- | 4543 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
|
- | 4544 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
|
- | 4545 | ||
- | 4546 | /* SFUSE_STRAP */ |
|
- | 4547 | #define SFUSE_STRAP 0xc2014 |
|
- | 4548 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
|
- | 4549 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) |
|
- | 4550 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) |
|
- | 4551 | ||
- | 4552 | #define WM_DBG 0x45280 |
|
3741 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
4553 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) |