WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_irq.c

 	pipestat &= ~mask;
 	I915_WRITE(reg, pipestat);
 		POSTING_READ(reg);
+}
 #if 0
 /**
  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
  */
 static void i915_enable_asle_pipestat(struct drm_device *dev)
 		if (INTEL_INFO(dev)->gen >= 4)
 		i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
-}
 #endif
 /**
  * i915_pipe_enabled - check if a pipe is enabled
 	 /* if there were no outputs to poll, poll was disabled,
 	  * therefore make sure it's enabled when disabling HPD on
 	  * some connectors */
 	if (hpd_disabled) {
 		drm_kms_helper_poll_enable(dev);
-//       mod_timer(&dev_priv->hotplug_reenable_timer,
+		mod_timer(&dev_priv->hotplug_reenable_timer,
-//             jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
+			  GetTimerTicks() + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
+	}
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 	wake_up_all(&ring->irq_queue);
-}
+}
 #if 0
 static void gen6_pm_rps_work(struct work_struct *work)
+{
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 		 * On VLV, when we enter RC6 we may not be at the minimum
 		 * voltage level, so arm a timer to check.  It should only
 		 * fire when there's activity or once after we've entered
 		 * RC6, and then won't be re-armed until the next RPS interrupt.
 		 */
-		mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
+//		mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
-				 msecs_to_jiffies(100));
+//				 msecs_to_jiffies(100));
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 	ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
-	mutex_unlock(&dev_priv->dev->struct_mutex);
-	parity_event[0] = I915_L3_PARITY_UEVENT "=1";
-	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
-	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
-	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
-	parity_event[4] = NULL;
-	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
-			   KOBJ_CHANGE, parity_event);
+	mutex_unlock(&dev_priv->dev->struct_mutex);
-	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
-		  row, bank, subbank);
-	kfree(parity_event[3]);
+	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
-	kfree(parity_event[2]);
+		  row, bank, subbank);
 	kfree(parity_event[1]);
+}
 	spin_unlock(&dev_priv->irq_lock);
 	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
-}
 #endif
 static void ilk_gt_irq_handler(struct drm_device *dev,
 			       struct drm_i915_private *dev_priv,
 			       u32 gt_iir)
 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 		      GT_BSD_CS_ERROR_INTERRUPT |
 		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
 		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
-//       i915_handle_error(dev, false);
+		i915_handle_error(dev, false);
 	}
-//	if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
+	if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
-//		ivybridge_handle_parity_error(dev);
+		ivybridge_parity_error_irq_handler(dev);
+}
 		if (!(hpd[i] & hotplug_trigger) ||
 		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
 			continue;
 		dev_priv->hpd_event_bits |= (1 << i);
-//        if (!time_in_range(GetTimerTicks(), dev_priv->hpd_stats[i].hpd_last_jiffies,
+		if (!time_in_range(GetTimerTicks(), dev_priv->hpd_stats[i].hpd_last_jiffies,
-//                  dev_priv->hpd_stats[i].hpd_last_jiffies
+                  dev_priv->hpd_stats[i].hpd_last_jiffies
-//                  + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
+                  + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
-//            dev_priv->hpd_stats[i].hpd_last_jiffies = GetTimerTicks;
+			dev_priv->hpd_stats[i].hpd_last_jiffies = GetTimerTicks();
+           dev_priv->hpd_stats[i].hpd_cnt = 0;
-//           dev_priv->hpd_stats[i].hpd_cnt = 0;
+			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
-//       } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
+       } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
+           dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
-//           dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
+			dev_priv->hpd_event_bits &= ~(1 << i);
-//           DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
+           DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
-//           ret = true;
+			storm_detected = true;
-//       } else {
+		} else {
+			dev_priv->hpd_stats[i].hpd_cnt++;
+			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
-			dev_priv->hpd_stats[i].hpd_cnt++;
+				      dev_priv->hpd_stats[i].hpd_cnt);
 //       }
+	}
 	if (storm_detected)
 		dev_priv->display.hpd_irq_setup(dev);
+	spin_unlock(&dev_priv->irq_lock);
+	/*
+	 * Our hotplug handler can grab modeset locks (by calling down into the
+	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
+	 * queue for otherwise the flush_work in the pageflip code will
-	spin_unlock(&dev_priv->irq_lock);
+	 * deadlock.
 	 */
 	schedule_work(&dev_priv->hotplug_work);
+}
 		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
 			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
 		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
 			DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
-//           i915_handle_error(dev_priv->dev, false);
+			i915_handle_error(dev_priv->dev, false);
+		}
+	}
+}
+		}
 		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 			gmbus_irq_handler(dev);
-//        if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+		if (pm_iir)
-//            gen6_queue_rps_work(dev_priv, pm_iir);
+			gen6_rps_irq_handler(dev_priv, pm_iir);
 		I915_WRITE(GTIIR, gt_iir);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (de_iir & DE_AUX_CHANNEL_A)
-		dp_aux_irq_handler(dev);
 		dp_aux_irq_handler(dev);
 #if 0
+	if (de_iir & DE_GSE)
-	if (de_iir & DE_GSE)
+		intel_opregion_asle_intr(dev);
 		intel_opregion_asle_intr(dev);
 #if 0
 	if (de_iir & DE_PIPEA_VBLANK)
+		drm_handle_vblank(dev, 0);
 		drm_handle_vblank(dev, 0);
 	if (de_iir & DE_PIPEB_VBLANK)
-	if (de_iir & DE_PIPEB_VBLANK)
 		drm_handle_vblank(dev, 1);
 #endif
 	if (de_iir & DE_POISON)
 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
-//	if (de_iir & DE_ERR_INT_IVB)
+	if (de_iir & DE_ERR_INT_IVB)
-//		ivb_err_int_handler(dev);
+		ivb_err_int_handler(dev);
 	if (de_iir & DE_AUX_CHANNEL_A_IVB)
 	 */
 	if (reset_completed)
 		wake_up_all(&dev_priv->gpu_error.reset_queue);
+}
 #if 0
 /**
  * i915_error_work_func - do process context error handling work
  * @work: work struct
+ *
 	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
 	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
 	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
 	int ret;
-	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 	/*
 	 * Note that there's only one work item which does gpu resets, so we
 	 * need not worry about concurrent gpu resets potentially incrementing
 	 * error->reset_counter twice. We only need to take care of another
 	 * the reset in-progress bit is only ever set by code outside of this
 	 * work we don't need to worry about any other races.
 	 */
 	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 		DRM_DEBUG_DRIVER("resetting chip\n");
-		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
-				   reset_event);
 		/*
 		 * All state reset _must_ be completed before we update the
 		 * reset counter, for otherwise waiters might miss the reset
 		 * pending state and not properly drop locks, resulting in
 		 * deadlocks with the reset work.
 		 */
-		ret = i915_reset(dev);
+//       ret = i915_reset(dev);
-		intel_display_handle_reset(dev);
+//       intel_display_handle_reset(dev);
 		if (ret == 0) {
 			 * Since unlock operations are a one-sided barrier only,
 			 * we need to insert a barrier here to order any seqno
 			 * updates before
 			 * the counter increment.
 			 */
-			smp_mb__before_atomic_inc();
 			atomic_inc(&dev_priv->gpu_error.reset_counter);
-			kobject_uevent_env(&dev->primary->kdev.kobj,
 					   KOBJ_CHANGE, reset_done_event);
 		} else {
 			atomic_set(&error->reset_counter, I915_WEDGED);
+	}
  */
 void i915_handle_error(struct drm_device *dev, bool wedged)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	i915_capture_error_state(dev);
+//   i915_capture_error_state(dev);
 	i915_report_and_clear_eir(dev);
 	if (wedged) {
 	 * code will deadlock.
 	 */
 	schedule_work(&dev_priv->gpu_error.work);
+}
 #if 0
 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
+{
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 //               if (waitqueue_active(&ring->irq_queue)) {
 					/* Issue a wake-up to catch stuck h/w. */
 //                   DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
 //                         ring->name);
 //                   wake_up_all(&ring->irq_queue);
-//                   ring->hangcheck.score += HUNG;
 //               } else
 					busy = false;
 			} else {
 				/* We always increment the hangcheck score
 				 * if the ring is busy and still processing
 		 * have been cleared after the pipestat interrupt was received.
 		 * It doesn't set the bit in iir again, but it still produces
 		 * interrupts (for non-MSI).
 		 */
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-//       if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-//           i915_handle_error(dev, false);
+			i915_handle_error(dev, false);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 	I915_WRITE(IMR, dev_priv->irq_mask);
 	I915_WRITE(IER, enable_mask);
 	POSTING_READ(IER);
-//	intel_opregion_enable_asle(dev);
+	i915_enable_asle_pipestat(dev);
 		 * have been cleared after the pipestat interrupt was received.
 		 * It doesn't set the bit in iir again, but it still produces
 		 * interrupts (for non-MSI).
 		 */
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-//       if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-//           i915_handle_error(dev, false);
+			i915_handle_error(dev, false);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 				blc_event = true;
 		}
-//		if (blc_event || (iir & I915_ASLE_INTERRUPT))
+		if (blc_event || (iir & I915_ASLE_INTERRUPT))
-//			intel_opregion_asle_intr(dev);
+			intel_opregion_asle_intr(dev);
 		/* With MSI, interrupts are only generated when iir
 	POSTING_READ(IER);
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	POSTING_READ(PORT_HOTPLUG_EN);
-//	intel_opregion_enable_asle(dev);
+	i915_enable_asle_pipestat(dev);
 		 * have been cleared after the pipestat interrupt was received.
 		 * It doesn't set the bit in iir again, but it still produces
 		 * interrupts (for non-MSI).
 		 */
 		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-//       if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-//           i915_handle_error(dev, false);
+			i915_handle_error(dev, false);
 		for_each_pipe(pipe) {
 			int reg = PIPESTAT(pipe);
 			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 				blc_event = true;
+		}
-//		if (blc_event || (iir & I915_ASLE_INTERRUPT))
+		if (blc_event || (iir & I915_ASLE_INTERRUPT))
-//			intel_opregion_asle_intr(dev);
+			intel_opregion_asle_intr(dev);
 		I915_WRITE(PIPESTAT(pipe),
 			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
 	I915_WRITE(IIR, I915_READ(IIR));
+}
+static void i915_reenable_hotplug_timer_func(unsigned long data)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
+	struct drm_device *dev = dev_priv->dev;
+	struct drm_mode_config *mode_config = &dev->mode_config;
+	unsigned long irqflags;
+	int i;
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
+		struct drm_connector *connector;
+		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
+			continue;
+		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
+		list_for_each_entry(connector, &mode_config->connector_list, head) {
+			struct intel_connector *intel_connector = to_intel_connector(connector);
+			if (intel_connector->encoder->hpd_pin == i) {
+				if (connector->polled != intel_connector->polled)
+					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
+							 drm_get_connector_name(connector));
+				connector->polled = intel_connector->polled;
+				if (!connector->polled)
+					connector->polled = DRM_CONNECTOR_POLL_HPD;
+			}
+		}
+	}
+	if (dev_priv->display.hpd_irq_setup)
+		dev_priv->display.hpd_irq_setup(dev);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
 void intel_irq_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
+	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
+	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
 	setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_irq.c – Rev 4104 → 4126