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24 | #ifndef _I915_GUC_REG_H_ |
24 | #ifndef _I915_GUC_REG_H_ |
25 | #define _I915_GUC_REG_H_ |
25 | #define _I915_GUC_REG_H_ |
Line 26... | Line 26... | ||
26 | 26 | ||
Line 27... | Line 27... | ||
27 | /* Definitions of GuC H/W registers, bits, etc */ |
27 | /* Definitions of GuC H/W registers, bits, etc */ |
28 | 28 | ||
29 | #define GUC_STATUS 0xc000 |
29 | #define GUC_STATUS _MMIO(0xc000) |
30 | #define GS_BOOTROM_SHIFT 1 |
30 | #define GS_BOOTROM_SHIFT 1 |
31 | #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT) |
31 | #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT) |
32 | #define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT) |
32 | #define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT) |
Line 37... | Line 37... | ||
37 | #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT) |
37 | #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT) |
38 | #define GS_MIA_SHIFT 16 |
38 | #define GS_MIA_SHIFT 16 |
39 | #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT) |
39 | #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT) |
40 | #define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT) |
40 | #define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT) |
Line 41... | Line 41... | ||
41 | 41 | ||
Line 42... | Line 42... | ||
42 | #define SOFT_SCRATCH(n) (0xc180 + ((n) * 4)) |
42 | #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) |
- | 43 | ||
43 | 44 | #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) |
|
44 | #define UOS_RSA_SCRATCH(i) (0xc200 + (i) * 4) |
45 | #define UOS_RSA_SCRATCH_MAX_COUNT 64 |
45 | #define DMA_ADDR_0_LOW 0xc300 |
46 | #define DMA_ADDR_0_LOW _MMIO(0xc300) |
46 | #define DMA_ADDR_0_HIGH 0xc304 |
47 | #define DMA_ADDR_0_HIGH _MMIO(0xc304) |
47 | #define DMA_ADDR_1_LOW 0xc308 |
48 | #define DMA_ADDR_1_LOW _MMIO(0xc308) |
48 | #define DMA_ADDR_1_HIGH 0xc30c |
49 | #define DMA_ADDR_1_HIGH _MMIO(0xc30c) |
49 | #define DMA_ADDRESS_SPACE_WOPCM (7 << 16) |
50 | #define DMA_ADDRESS_SPACE_WOPCM (7 << 16) |
50 | #define DMA_ADDRESS_SPACE_GTT (8 << 16) |
51 | #define DMA_ADDRESS_SPACE_GTT (8 << 16) |
51 | #define DMA_COPY_SIZE 0xc310 |
52 | #define DMA_COPY_SIZE _MMIO(0xc310) |
52 | #define DMA_CTRL 0xc314 |
53 | #define DMA_CTRL _MMIO(0xc314) |
53 | #define UOS_MOVE (1<<4) |
54 | #define UOS_MOVE (1<<4) |
54 | #define START_DMA (1<<0) |
55 | #define START_DMA (1<<0) |
55 | #define DMA_GUC_WOPCM_OFFSET 0xc340 |
56 | #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) |
Line 56... | Line 57... | ||
56 | #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ |
57 | #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ |
57 | #define GUC_MAX_IDLE_COUNT 0xC3E4 |
58 | #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) |
Line 58... | Line 59... | ||
58 | 59 | ||
59 | #define GUC_WOPCM_SIZE 0xc050 |
60 | #define GUC_WOPCM_SIZE _MMIO(0xc050) |
Line 60... | Line 61... | ||
60 | #define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */ |
61 | #define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */ |
61 | 62 | ||
62 | /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */ |
63 | /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */ |
63 | #define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE) |
64 | #define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE) |
Line 64... | Line 65... | ||
64 | 65 | ||
65 | #define GEN8_GT_PM_CONFIG 0x138140 |
66 | #define GEN8_GT_PM_CONFIG _MMIO(0x138140) |
Line 66... | Line 67... | ||
66 | #define GEN9LP_GT_PM_CONFIG 0x138140 |
67 | #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) |
Line 67... | Line 68... | ||
67 | #define GEN9_GT_PM_CONFIG 0x13816c |
68 | #define GEN9_GT_PM_CONFIG _MMIO(0x13816c) |
68 | #define GT_DOORBELL_ENABLE (1<<0) |
69 | #define GT_DOORBELL_ENABLE (1<<0) |
69 | 70 | ||
70 | #define GEN8_GTCR 0x4274 |
71 | #define GEN8_GTCR _MMIO(0x4274) |
71 | #define GEN8_GTCR_INVALIDATE (1<<0) |
72 | #define GEN8_GTCR_INVALIDATE (1<<0) |
72 | 73 | ||
Line 87... | Line 88... | ||
87 | GUC_ENABLE_MIA_CACHING | \ |
88 | GUC_ENABLE_MIA_CACHING | \ |
88 | GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \ |
89 | GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \ |
89 | GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \ |
90 | GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \ |
90 | GUC_ENABLE_MIA_CLOCK_GATING) |
91 | GUC_ENABLE_MIA_CLOCK_GATING) |
Line 91... | Line 92... | ||
91 | 92 | ||
92 | #define HOST2GUC_INTERRUPT 0xc4c8 |
93 | #define HOST2GUC_INTERRUPT _MMIO(0xc4c8) |
Line 93... | Line 94... | ||
93 | #define HOST2GUC_TRIGGER (1<<0) |
94 | #define HOST2GUC_TRIGGER (1<<0) |
94 | 95 | ||
Line 95... | Line 96... | ||
95 | #define DRBMISC1 0x1984 |
96 | #define DRBMISC1 0x1984 |
96 | #define DOORBELL_ENABLE (1<<0) |
97 | #define DOORBELL_ENABLE (1<<0) |
97 | 98 | ||
Line 98... | Line 99... | ||
98 | #define GEN8_DRBREGL(x) (0x1000 + (x) * 8) |
99 | #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8) |
Line 99... | Line 100... | ||
99 | #define GEN8_DRB_VALID (1<<0) |
100 | #define GEN8_DRB_VALID (1<<0) |
100 | #define GEN8_DRBREGU(x) (GEN8_DRBREGL(x) + 4) |
101 | #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) |
101 | 102 | ||
102 | #define DE_GUCRMR 0x44054 |
103 | #define DE_GUCRMR _MMIO(0x44054) |
Line 103... | Line 104... | ||
103 | 104 |