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Rev 6937 Rev 7144
Line 25... Line 25...
25
 *    Keith Packard 
25
 *    Keith Packard 
26
 *    Mika Kuoppala 
26
 *    Mika Kuoppala 
27
 *
27
 *
28
 */
28
 */
Line -... Line 29...
-
 
29
 
29
 
30
#define UTS_RELEASE " 4.6.7 "
Line 30... Line -...
30
#include "i915_drv.h"
-
 
31
 
-
 
32
#if 0
31
#include "i915_drv.h"
33
 
32
 
34
static const char *ring_str(int ring)
33
static const char *ring_str(int ring)
35
{
34
{
36
	switch (ring) {
35
	switch (ring) {
Line 364... Line 363...
364
		}
363
		}
365
	}
364
	}
366
	err_printf(m, "Reset count: %u\n", error->reset_count);
365
	err_printf(m, "Reset count: %u\n", error->reset_count);
367
	err_printf(m, "Suspend count: %u\n", error->suspend_count);
366
	err_printf(m, "Suspend count: %u\n", error->suspend_count);
368
	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
367
	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
-
 
368
	err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
-
 
369
	err_printf(m, "PCI Subsystem: %04x:%04x\n",
-
 
370
		   dev->pdev->subsystem_vendor,
-
 
371
		   dev->pdev->subsystem_device);
369
	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
372
	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
Line 370... Line 373...
370
 
373
 
371
	if (HAS_CSR(dev)) {
374
	if (HAS_CSR(dev)) {
Line 509... Line 512...
509
				   obj->pages[0][elt+2],
512
				   obj->pages[0][elt+2],
510
				   obj->pages[0][elt+3]);
513
				   obj->pages[0][elt+3]);
511
		}
514
		}
512
	}
515
	}
Line 513... Line 516...
513
 
516
 
514
	if (error->overlay)
517
//	if (error->overlay)
Line 515... Line 518...
515
		intel_overlay_print_error_state(m, error->overlay);
518
//		intel_overlay_print_error_state(m, error->overlay);
516
 
519
 
Line 517... Line 520...
517
	if (error->display)
520
	if (error->display)
Line 731... Line 734...
731
			     int count, struct list_head *head)
734
			     int count, struct list_head *head)
732
{
735
{
733
	struct i915_vma *vma;
736
	struct i915_vma *vma;
734
	int i = 0;
737
	int i = 0;
Line 735... Line 738...
735
 
738
 
736
	list_for_each_entry(vma, head, mm_list) {
739
	list_for_each_entry(vma, head, vm_link) {
737
		capture_bo(err++, vma);
740
		capture_bo(err++, vma);
738
		if (++i == count)
741
		if (++i == count)
739
			break;
742
			break;
Line 754... Line 757...
754
		struct i915_vma *vma;
757
		struct i915_vma *vma;
Line 755... Line 758...
755
 
758
 
756
		if (err == last)
759
		if (err == last)
Line 757... Line 760...
757
			break;
760
			break;
758
 
761
 
759
		list_for_each_entry(vma, &obj->vma_list, vma_link)
762
		list_for_each_entry(vma, &obj->vma_list, obj_link)
760
			if (vma->vm == vm && vma->pin_count > 0)
763
			if (vma->vm == vm && vma->pin_count > 0)
Line 761... Line 764...
761
				capture_bo(err++, vma);
764
				capture_bo(err++, vma);
Line 1027... Line 1030...
1027
			if (HAS_BROKEN_CS_TLB(dev_priv->dev))
1030
			if (HAS_BROKEN_CS_TLB(dev_priv->dev))
1028
				error->ring[i].wa_batchbuffer =
1031
				error->ring[i].wa_batchbuffer =
1029
					i915_error_ggtt_object_create(dev_priv,
1032
					i915_error_ggtt_object_create(dev_priv,
1030
							     ring->scratch.obj);
1033
							     ring->scratch.obj);
Line 1031... Line -...
1031
 
-
 
1032
			if (request->pid) {
-
 
1033
				struct task_struct *task;
-
 
1034
 
-
 
1035
				rcu_read_lock();
-
 
1036
				task = pid_task(request->pid, PIDTYPE_PID);
-
 
1037
				if (task) {
-
 
1038
					strcpy(error->ring[i].comm, task->comm);
-
 
1039
					error->ring[i].pid = task->pid;
-
 
1040
				}
-
 
1041
				rcu_read_unlock();
-
 
1042
			}
1034
 
Line 1043... Line 1035...
1043
		}
1035
		}
1044
 
1036
 
1045
		if (i915.enable_execlists) {
1037
		if (i915.enable_execlists) {
Line 1049... Line 1041...
1049
			 * executed).
1041
			 * executed).
1050
			 */
1042
			 */
1051
			if (request)
1043
			if (request)
1052
				rbuf = request->ctx->engine[ring->id].ringbuf;
1044
				rbuf = request->ctx->engine[ring->id].ringbuf;
1053
			else
1045
			else
1054
				rbuf = ring->default_context->engine[ring->id].ringbuf;
1046
				rbuf = dev_priv->kernel_context->engine[ring->id].ringbuf;
1055
		} else
1047
		} else
1056
			rbuf = ring->buffer;
1048
			rbuf = ring->buffer;
Line 1057... Line 1049...
1057
 
1049
 
1058
		error->ring[i].cpu_ring_head = rbuf->head;
1050
		error->ring[i].cpu_ring_head = rbuf->head;
Line 1122... Line 1114...
1122
	struct drm_i915_gem_object *obj;
1114
	struct drm_i915_gem_object *obj;
1123
	struct i915_vma *vma;
1115
	struct i915_vma *vma;
1124
	int i;
1116
	int i;
Line 1125... Line 1117...
1125
 
1117
 
1126
	i = 0;
1118
	i = 0;
1127
	list_for_each_entry(vma, &vm->active_list, mm_list)
1119
	list_for_each_entry(vma, &vm->active_list, vm_link)
1128
		i++;
1120
		i++;
Line 1129... Line 1121...
1129
	error->active_bo_count[ndx] = i;
1121
	error->active_bo_count[ndx] = i;
1130
 
1122
 
1131
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1123
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1132
		list_for_each_entry(vma, &obj->vma_list, vma_link)
1124
		list_for_each_entry(vma, &obj->vma_list, obj_link)
1133
			if (vma->vm == vm && vma->pin_count > 0)
1125
			if (vma->vm == vm && vma->pin_count > 0)
1134
				i++;
1126
				i++;
Line 1336... Line 1328...
1336
	i915_capture_reg_state(dev_priv, error);
1328
	i915_capture_reg_state(dev_priv, error);
1337
	i915_gem_capture_buffers(dev_priv, error);
1329
	i915_gem_capture_buffers(dev_priv, error);
1338
	i915_gem_record_fences(dev, error);
1330
	i915_gem_record_fences(dev, error);
1339
	i915_gem_record_rings(dev, error);
1331
	i915_gem_record_rings(dev, error);
Line 1340... Line 1332...
1340
 
1332
 
Line 1341... Line 1333...
1341
	do_gettimeofday(&error->time);
1333
//	do_gettimeofday(&error->time);
1342
 
1334
 
Line 1343... Line 1335...
1343
	error->overlay = intel_overlay_capture_error_state(dev);
1335
//	error->overlay = intel_overlay_capture_error_state(dev);
1344
	error->display = intel_display_capture_error_state(dev);
1336
	error->display = intel_display_capture_error_state(dev);
Line 1398... Line 1390...
1398
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1390
	spin_unlock_irq(&dev_priv->gpu_error.lock);
Line 1399... Line 1391...
1399
 
1391
 
1400
	if (error)
1392
	if (error)
1401
		kref_put(&error->ref, i915_error_state_free);
1393
		kref_put(&error->ref, i915_error_state_free);
1402
}
-
 
Line 1403... Line 1394...
1403
#endif
1394
}
1404
 
1395
 
1405
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1396
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1406
{
1397
{