WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_tiling.c


/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt 
 *
 */
 
#include 
#include 
#include 
#include 
#include "i915_drv.h"
 
/** @file i915_gem_tiling.c
 *
 * Support for managing tiling state of buffer objects.
 *
 * The idea behind tiling is to increase cache hit rates by rearranging
 * pixel data so that a group of pixel accesses are in the same cacheline.
 * Performance improvement from doing this on the back/depth buffer are on
 * the order of 30%.
 *
 * Intel architectures make this somewhat more complicated, though, by
 * adjustments made to addressing of data when the memory is in interleaved
 * mode (matched pairs of DIMMS) to improve memory bandwidth.
 * For interleaved memory, the CPU sends every sequential 64 bytes
 * to an alternate memory channel so it can get the bandwidth from both.
 *
 * The GPU also rearranges its accesses for increased bandwidth to interleaved
 * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 * it does it a little differently, since one walks addresses not just in the
 * X direction but also Y.  So, along with alternating channels when bit
 * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 * are common to both the 915 and 965-class hardware.
 *
 * The CPU also sometimes XORs in higher bits as well, to improve
 * bandwidth doing strided access like we do so frequently in graphics.  This
 * is called "Channel XOR Randomization" in the MCH documentation.  The result
 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 * decode.
 *
 * All of this bit 6 XORing has an effect on our memory management,
 * as we need to make sure that the 3d driver can correctly address object
 * contents.
 *
 * If we don't have interleaved memory, all tiling is safe and no swizzling is
 * required.
 *
 * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 * 17 is not just a page offset, so as we page an objet out and back in,
 * individual pages in it will have different bit 17 addresses, resulting in
 * each 64 bytes being swapped with its neighbor!
 *
 * Otherwise, if interleaved, we have to tell the 3d driver what the address
 * swizzling it needs to do is, since it's writing with the CPU to the pages
 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 * to match what the GPU expects.
 */
 
/**
 * Detects bit 6 swizzling of address lookup between IGD access and CPU
 * access through main memory.
 */
void
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
	if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
		/*
		 * On BDW+, swizzling is not used. We leave the CPU memory
		 * controller in charge of optimizing memory accesses without
		 * the extra address manipulation GPU side.
		 *
		 * VLV and CHV don't have GPU swizzling.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (INTEL_INFO(dev)->gen >= 6) {
		if (dev_priv->preserve_bios_swizzle) {
			if (I915_READ(DISP_ARB_CTL) &
			    DISP_TILE_SURFACE_SWIZZLING) {
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else {
				swizzle_x = I915_BIT_6_SWIZZLE_NONE;
				swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			}
		} else {
		uint32_t dimm_c0, dimm_c1;
		dimm_c0 = I915_READ(MAD_DIMM_C0);
		dimm_c1 = I915_READ(MAD_DIMM_C1);
		dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
		dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
			/* Enable swizzling when the channels are populated
			 * with identically sized dimms. We don't need to check
			 * the 3rd channel because no cpu with gpu attached
			 * ships in that configuration. Also, swizzling only
			 * makes sense for 2 channels anyway. */
		if (dimm_c0 == dimm_c1) {
			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
			swizzle_y = I915_BIT_6_SWIZZLE_9;
		} else {
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		}
		}
	} else if (IS_GEN5(dev)) {
		/* On Ironlake whatever DRAM config, GPU always do
		 * same swizzling setup.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_9_10;
		swizzle_y = I915_BIT_6_SWIZZLE_9;
	} else if (IS_GEN2(dev)) {
		/* As far as we know, the 865 doesn't have these bit 6
		 * swizzling issues.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
		uint32_t dcc;
 
		/* On 9xx chipsets, channel interleave by the CPU is
		 * determined by DCC.  For single-channel, neither the CPU
		 * nor the GPU do swizzling.  For dual channel interleaved,
		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
		 * 9 for Y tiled.  The CPU's interleave is independent, and
		 * can be based on either bit 11 (haven't seen this yet) or
		 * bit 17 (common).
		 */
		dcc = I915_READ(DCC);
		switch (dcc & DCC_ADDRESSING_MODE_MASK) {
		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			break;
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
			if (dcc & DCC_CHANNEL_XOR_DISABLE) {
				/* This is the base swizzling by the GPU for
				 * tiled buffers.
				 */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
				/* Bit 11 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
				swizzle_y = I915_BIT_6_SWIZZLE_9_11;
			} else {
				/* Bit 17 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
			}
			break;
		}
 
		/* check for L-shaped memory aka modified enhanced addressing */
		if (IS_GEN4(dev)) {
			uint32_t ddc2 = I915_READ(DCC2);
 
			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
		}
 
		if (dcc == 0xffffffff) {
			DRM_ERROR("Couldn't read from MCHBAR.  "
				  "Disabling tiling.\n");
			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
		}
	} else {
		/* The 965, G33, and newer, have a very flexible memory
		 * configuration.  It will enable dual-channel mode
		 * (interleaving) on as much memory as it can, and the GPU
		 * will additionally sometimes enable different bit 6
		 * swizzling for tiled objects from the CPU.
		 *
		 * Here's what I found on the G965:
		 *    slot fill         memory size  swizzling
		 * 0A   0B   1A   1B    1-ch   2-ch
		 * 512  0    0    0     512    0     O
		 * 512  0    512  0     16     1008  X
		 * 512  0    0    512   16     1008  X
		 * 0    512  0    512   16     1008  X
		 * 1024 1024 1024 0     2048   1024  O
		 *
		 * We could probably detect this based on either the DRB
		 * matching, which was the case for the swizzling required in
		 * the table above, or from the 1-ch value being less than
		 * the minimum size of a rank.
		 */
		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		} else {
			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
			swizzle_y = I915_BIT_6_SWIZZLE_9;
		}
	}
 
	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
}
 
/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;
 
	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;
 
	if (IS_GEN2(dev) ||
	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
		tile_width = 128;
	else
		tile_width = 512;
 
	/* check maximum stride & object size */
	/* i965+ stores the end address of the gtt mapping in the fence
		 * reg, so dont bother to check the size */
	if (INTEL_INFO(dev)->gen >= 7) {
		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
			return false;
	} else if (INTEL_INFO(dev)->gen >= 4) {
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else {
		if (stride > 8192)
			return false;
 
		if (IS_GEN3(dev)) {
			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
				return false;
		} else {
			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
				return false;
		}
	}
 
	if (stride < tile_width)
		return false;
 
	/* 965+ just needs multiples of tile width */
	if (INTEL_INFO(dev)->gen >= 4) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}
 
	/* Pre-965 needs power of two tile widths */
	if (stride & (stride - 1))
		return false;
 
	return true;
}
 
/* Is the current GTT allocation valid for the change in tiling? */
static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
{
	u32 size;
 
	if (tiling_mode == I915_TILING_NONE)
		return true;
 
	if (INTEL_INFO(obj->base.dev)->gen >= 4)
		return true;
 
	if (INTEL_INFO(obj->base.dev)->gen == 3) {
		if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
			return false;
	} else {
		if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
			return false;
	}
 
	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
	if (i915_gem_obj_ggtt_size(obj) != size)
		return false;
 
	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
		return false;
 
	return true;
}
 
/**
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_set_tiling *args = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int ret = 0;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;
 
	if (!i915_tiling_ok(dev,
			    args->stride, obj->base.size, args->tiling_mode)) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EINVAL;
	}
 
	if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EBUSY;
	}
 
	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		args->stride = 0;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 
		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 
		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
			args->stride = 0;
		}
	}
 
	mutex_lock(&dev->struct_mutex);
	if (args->tiling_mode != obj->tiling_mode ||
	    args->stride != obj->stride) {
		/* We need to rebind the object if its current allocation
		 * no longer meets the alignment restrictions for its new
		 * tiling mode. Otherwise we can just leave it alone, but
		 * need to ensure that any fence register is updated before
		 * the next fenced (either through the GTT or by the BLT unit
		 * on older GPUs) access.
		 *
		 * After updating the tiling parameters, we then flag whether
		 * we need to update an associated fence register. Note this
		 * has to also include the unfenced register the GPU uses
		 * whilst executing a fenced command for an untiled object.
		 */
 
		if (obj->map_and_fenceable &&
 
 
 
		    !i915_gem_object_fence_ok(obj, args->tiling_mode))
 
 
 
 
 
 
 
 
			ret = i915_gem_object_ggtt_unbind(obj);
 
 
		if (ret == 0) {
			if (obj->pages &&
			    obj->madv == I915_MADV_WILLNEED &&
			    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
				if (args->tiling_mode == I915_TILING_NONE)
					i915_gem_object_unpin_pages(obj);
				if (obj->tiling_mode == I915_TILING_NONE)
					i915_gem_object_pin_pages(obj);
		}
 
			obj->fence_dirty =
				obj->last_fenced_seqno ||
				obj->fence_reg != I915_FENCE_REG_NONE;
 
			obj->tiling_mode = args->tiling_mode;
			obj->stride = args->stride;
 
			/* Force the fence to be reacquired for GTT access */
			i915_gem_release_mmap(obj);
		}
	}
	/* we have to maintain this existing ABI... */
	args->stride = obj->stride;
	args->tiling_mode = obj->tiling_mode;
 
	/* Try to preallocate memory required to save swizzling on put-pages */
	if (i915_gem_object_needs_bit17_swizzle(obj)) {
		if (obj->bit_17 == NULL) {
			obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
					      sizeof(long), GFP_KERNEL);
		}
	} else {
		kfree(obj->bit_17);
		obj->bit_17 = NULL;
	}
 
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);
 
	return ret;
}
 
/**
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_get_tiling *args = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
 
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;
 
	mutex_lock(&dev->struct_mutex);
 
	args->tiling_mode = obj->tiling_mode;
	switch (obj->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	default:
		DRM_ERROR("unknown tiling mode\n");
	}
 
	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	args->phys_swizzle_mode = args->swizzle_mode;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);
 
	return 0;
}
 
#if 0
/**
 * Swap every 64 bytes of this page around, to account for it having a new
 * bit 17 of its physical address and therefore being interpreted differently
 * by the GPU.
 */
static void
i915_gem_swizzle_page(struct page *page)
{
	char temp[64];
	char *vaddr;
	int i;
 
	vaddr = kmap(page);
 
	for (i = 0; i < PAGE_SIZE; i += 128) {
		memcpy(temp, &vaddr[i], 64);
		memcpy(&vaddr[i], &vaddr[i + 64], 64);
		memcpy(&vaddr[i + 64], temp, 64);
	}
 
	kunmap(page);
}
 
void
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
{
	struct sg_page_iter sg_iter;
	int i;
 
	if (obj->bit_17 == NULL)
		return;
 
	i = 0;
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
		struct page *page = sg_page_iter_page(&sg_iter);
		char new_bit_17 = page_to_phys(page) >> 17;
		if ((new_bit_17 & 0x1) !=
		    (test_bit(i, obj->bit_17) != 0)) {
			i915_gem_swizzle_page(page);
			set_page_dirty(page);
		}
		i++;
	}
}
 
void
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
{
	struct sg_page_iter sg_iter;
	int page_count = obj->base.size >> PAGE_SHIFT;
	int i;
 
	if (obj->bit_17 == NULL) {
		obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
					   sizeof(long), GFP_KERNEL);
		if (obj->bit_17 == NULL) {
			DRM_ERROR("Failed to allocate memory for bit 17 "
				  "record\n");
			return;
		}
	}
 
	i = 0;
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
		if (page_to_phys(sg_page_iter_page(&sg_iter)) & (1 << 17))
			__set_bit(i, obj->bit_17);
		else
			__clear_bit(i, obj->bit_17);
		i++;
	}
}
#endif

Rev 5060	Rev 5354
1	/*	1	/*
2	* Copyright © 2008 Intel Corporation	2	* Copyright © 2008 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	*	25	*
26	*/	26	*/
27		27
28	#include	28	#include
29	#include	29	#include
30	#include	30	#include
31	#include	31	#include
32	#include "i915_drv.h"	32	#include "i915_drv.h"
33		33
34	/** @file i915_gem_tiling.c	34	/** @file i915_gem_tiling.c
35	*	35	*
36	* Support for managing tiling state of buffer objects.	36	* Support for managing tiling state of buffer objects.
37	*	37	*
38	* The idea behind tiling is to increase cache hit rates by rearranging	38	* The idea behind tiling is to increase cache hit rates by rearranging
39	* pixel data so that a group of pixel accesses are in the same cacheline.	39	* pixel data so that a group of pixel accesses are in the same cacheline.
40	* Performance improvement from doing this on the back/depth buffer are on	40	* Performance improvement from doing this on the back/depth buffer are on
41	* the order of 30%.	41	* the order of 30%.
42	*	42	*
43	* Intel architectures make this somewhat more complicated, though, by	43	* Intel architectures make this somewhat more complicated, though, by
44	* adjustments made to addressing of data when the memory is in interleaved	44	* adjustments made to addressing of data when the memory is in interleaved
45	* mode (matched pairs of DIMMS) to improve memory bandwidth.	45	* mode (matched pairs of DIMMS) to improve memory bandwidth.
46	* For interleaved memory, the CPU sends every sequential 64 bytes	46	* For interleaved memory, the CPU sends every sequential 64 bytes
47	* to an alternate memory channel so it can get the bandwidth from both.	47	* to an alternate memory channel so it can get the bandwidth from both.
48	*	48	*
49	* The GPU also rearranges its accesses for increased bandwidth to interleaved	49	* The GPU also rearranges its accesses for increased bandwidth to interleaved
50	* memory, and it matches what the CPU does for non-tiled. However, when tiled	50	* memory, and it matches what the CPU does for non-tiled. However, when tiled
51	* it does it a little differently, since one walks addresses not just in the	51	* it does it a little differently, since one walks addresses not just in the
52	* X direction but also Y. So, along with alternating channels when bit	52	* X direction but also Y. So, along with alternating channels when bit
53	* 6 of the address flips, it also alternates when other bits flip -- Bits 9	53	* 6 of the address flips, it also alternates when other bits flip -- Bits 9
54	* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)	54	* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
55	* are common to both the 915 and 965-class hardware.	55	* are common to both the 915 and 965-class hardware.
56	*	56	*
57	* The CPU also sometimes XORs in higher bits as well, to improve	57	* The CPU also sometimes XORs in higher bits as well, to improve
58	* bandwidth doing strided access like we do so frequently in graphics. This	58	* bandwidth doing strided access like we do so frequently in graphics. This
59	* is called "Channel XOR Randomization" in the MCH documentation. The result	59	* is called "Channel XOR Randomization" in the MCH documentation. The result
60	* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address	60	* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
61	* decode.	61	* decode.
62	*	62	*
63	* All of this bit 6 XORing has an effect on our memory management,	63	* All of this bit 6 XORing has an effect on our memory management,
64	* as we need to make sure that the 3d driver can correctly address object	64	* as we need to make sure that the 3d driver can correctly address object
65	* contents.	65	* contents.
66	*	66	*
67	* If we don't have interleaved memory, all tiling is safe and no swizzling is	67	* If we don't have interleaved memory, all tiling is safe and no swizzling is
68	* required.	68	* required.
69	*	69	*
70	* When bit 17 is XORed in, we simply refuse to tile at all. Bit	70	* When bit 17 is XORed in, we simply refuse to tile at all. Bit
71	* 17 is not just a page offset, so as we page an objet out and back in,	71	* 17 is not just a page offset, so as we page an objet out and back in,
72	* individual pages in it will have different bit 17 addresses, resulting in	72	* individual pages in it will have different bit 17 addresses, resulting in
73	* each 64 bytes being swapped with its neighbor!	73	* each 64 bytes being swapped with its neighbor!
74	*	74	*
75	* Otherwise, if interleaved, we have to tell the 3d driver what the address	75	* Otherwise, if interleaved, we have to tell the 3d driver what the address
76	* swizzling it needs to do is, since it's writing with the CPU to the pages	76	* swizzling it needs to do is, since it's writing with the CPU to the pages
77	* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the	77	* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
78	* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling	78	* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
79	* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order	79	* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
80	* to match what the GPU expects.	80	* to match what the GPU expects.
81	*/	81	*/
82		82
83	/**	83	/**
84	* Detects bit 6 swizzling of address lookup between IGD access and CPU	84	* Detects bit 6 swizzling of address lookup between IGD access and CPU
85	* access through main memory.	85	* access through main memory.
86	*/	86	*/
87	void	87	void
88	i915_gem_detect_bit_6_swizzle(struct drm_device *dev)	88	i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
89	{	89	{
90	struct drm_i915_private *dev_priv = dev->dev_private;	90	struct drm_i915_private *dev_priv = dev->dev_private;
91	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;	91	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
92	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;	92	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
93		93
-		94	if (INTEL_INFO(dev)->gen >= 8 \|\| IS_VALLEYVIEW(dev)) {
-		95	/*
-		96	* On BDW+, swizzling is not used. We leave the CPU memory
-		97	* controller in charge of optimizing memory accesses without
-		98	* the extra address manipulation GPU side.
-		99	*
-		100	* VLV and CHV don't have GPU swizzling.
94	if (IS_VALLEYVIEW(dev)) {	101	*/
95	swizzle_x = I915_BIT_6_SWIZZLE_NONE;	102	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
96	swizzle_y = I915_BIT_6_SWIZZLE_NONE;	103	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
97	} else if (INTEL_INFO(dev)->gen >= 6) {	104	} else if (INTEL_INFO(dev)->gen >= 6) {
-		105	if (dev_priv->preserve_bios_swizzle) {
-		106	if (I915_READ(DISP_ARB_CTL) &
-		107	DISP_TILE_SURFACE_SWIZZLING) {
-		108	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
-		109	swizzle_y = I915_BIT_6_SWIZZLE_9;
-		110	} else {
-		111	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
-		112	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-		113	}
-		114	} else {
98	uint32_t dimm_c0, dimm_c1;	115	uint32_t dimm_c0, dimm_c1;
99	dimm_c0 = I915_READ(MAD_DIMM_C0);	116	dimm_c0 = I915_READ(MAD_DIMM_C0);
100	dimm_c1 = I915_READ(MAD_DIMM_C1);	117	dimm_c1 = I915_READ(MAD_DIMM_C1);
101	dimm_c0 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;	118	dimm_c0 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;
102	dimm_c1 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;	119	dimm_c1 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;
103	/* Enable swizzling when the channels are populated with	120	/* Enable swizzling when the channels are populated
104	* identically sized dimms. We don't need to check the 3rd	121	* with identically sized dimms. We don't need to check
105	* channel because no cpu with gpu attached ships in that	122	* the 3rd channel because no cpu with gpu attached
106	* configuration. Also, swizzling only makes sense for 2	123	* ships in that configuration. Also, swizzling only
107	* channels anyway. */	124	* makes sense for 2 channels anyway. */
108	if (dimm_c0 == dimm_c1) {	125	if (dimm_c0 == dimm_c1) {
109	swizzle_x = I915_BIT_6_SWIZZLE_9_10;	126	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
110	swizzle_y = I915_BIT_6_SWIZZLE_9;	127	swizzle_y = I915_BIT_6_SWIZZLE_9;
111	} else {	128	} else {
112	swizzle_x = I915_BIT_6_SWIZZLE_NONE;	129	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
113	swizzle_y = I915_BIT_6_SWIZZLE_NONE;	130	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
114	}	131	}
-		132	}
115	} else if (IS_GEN5(dev)) {	133	} else if (IS_GEN5(dev)) {
116	/* On Ironlake whatever DRAM config, GPU always do	134	/* On Ironlake whatever DRAM config, GPU always do
117	* same swizzling setup.	135	* same swizzling setup.
118	*/	136	*/
119	swizzle_x = I915_BIT_6_SWIZZLE_9_10;	137	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
120	swizzle_y = I915_BIT_6_SWIZZLE_9;	138	swizzle_y = I915_BIT_6_SWIZZLE_9;
121	} else if (IS_GEN2(dev)) {	139	} else if (IS_GEN2(dev)) {
122	/* As far as we know, the 865 doesn't have these bit 6	140	/* As far as we know, the 865 doesn't have these bit 6
123	* swizzling issues.	141	* swizzling issues.
124	*/	142	*/
125	swizzle_x = I915_BIT_6_SWIZZLE_NONE;	143	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
126	swizzle_y = I915_BIT_6_SWIZZLE_NONE;	144	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
127	} else if (IS_MOBILE(dev) \|\| (IS_GEN3(dev) && !IS_G33(dev))) {	145	} else if (IS_MOBILE(dev) \|\| (IS_GEN3(dev) && !IS_G33(dev))) {
128	uint32_t dcc;	146	uint32_t dcc;
129		147
130	/* On 9xx chipsets, channel interleave by the CPU is	148	/* On 9xx chipsets, channel interleave by the CPU is
131	* determined by DCC. For single-channel, neither the CPU	149	* determined by DCC. For single-channel, neither the CPU
132	* nor the GPU do swizzling. For dual channel interleaved,	150	* nor the GPU do swizzling. For dual channel interleaved,
133	* the GPU's interleave is bit 9 and 10 for X tiled, and bit	151	* the GPU's interleave is bit 9 and 10 for X tiled, and bit
134	* 9 for Y tiled. The CPU's interleave is independent, and	152	* 9 for Y tiled. The CPU's interleave is independent, and
135	* can be based on either bit 11 (haven't seen this yet) or	153	* can be based on either bit 11 (haven't seen this yet) or
136	* bit 17 (common).	154	* bit 17 (common).
137	*/	155	*/
138	dcc = I915_READ(DCC);	156	dcc = I915_READ(DCC);
139	switch (dcc & DCC_ADDRESSING_MODE_MASK) {	157	switch (dcc & DCC_ADDRESSING_MODE_MASK) {
140	case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:	158	case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
141	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:	159	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
142	swizzle_x = I915_BIT_6_SWIZZLE_NONE;	160	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
143	swizzle_y = I915_BIT_6_SWIZZLE_NONE;	161	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
144	break;	162	break;
145	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:	163	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
146	if (dcc & DCC_CHANNEL_XOR_DISABLE) {	164	if (dcc & DCC_CHANNEL_XOR_DISABLE) {
147	/* This is the base swizzling by the GPU for	165	/* This is the base swizzling by the GPU for
148	* tiled buffers.	166	* tiled buffers.
149	*/	167	*/
150	swizzle_x = I915_BIT_6_SWIZZLE_9_10;	168	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
151	swizzle_y = I915_BIT_6_SWIZZLE_9;	169	swizzle_y = I915_BIT_6_SWIZZLE_9;
152	} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {	170	} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
153	/* Bit 11 swizzling by the CPU in addition. */	171	/* Bit 11 swizzling by the CPU in addition. */
154	swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;	172	swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
155	swizzle_y = I915_BIT_6_SWIZZLE_9_11;	173	swizzle_y = I915_BIT_6_SWIZZLE_9_11;
156	} else {	174	} else {
157	/* Bit 17 swizzling by the CPU in addition. */	175	/* Bit 17 swizzling by the CPU in addition. */
158	swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;	176	swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
159	swizzle_y = I915_BIT_6_SWIZZLE_9_17;	177	swizzle_y = I915_BIT_6_SWIZZLE_9_17;
160	}	178	}
161	break;	179	break;
162	}	180	}
-		181
-		182	/* check for L-shaped memory aka modified enhanced addressing */
-		183	if (IS_GEN4(dev)) {
-		184	uint32_t ddc2 = I915_READ(DCC2);
-		185
-		186	if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
-		187	dev_priv->quirks \|= QUIRK_PIN_SWIZZLED_PAGES;
-		188	}
-		189
163	if (dcc == 0xffffffff) {	190	if (dcc == 0xffffffff) {
164	DRM_ERROR("Couldn't read from MCHBAR. "	191	DRM_ERROR("Couldn't read from MCHBAR. "
165	"Disabling tiling.\n");	192	"Disabling tiling.\n");
166	swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;	193	swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
167	swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;	194	swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
168	}	195	}
169	} else {	196	} else {
170	/* The 965, G33, and newer, have a very flexible memory	197	/* The 965, G33, and newer, have a very flexible memory
171	* configuration. It will enable dual-channel mode	198	* configuration. It will enable dual-channel mode
172	* (interleaving) on as much memory as it can, and the GPU	199	* (interleaving) on as much memory as it can, and the GPU
173	* will additionally sometimes enable different bit 6	200	* will additionally sometimes enable different bit 6
174	* swizzling for tiled objects from the CPU.	201	* swizzling for tiled objects from the CPU.
175	*	202	*
176	* Here's what I found on the G965:	203	* Here's what I found on the G965:
177	* slot fill memory size swizzling	204	* slot fill memory size swizzling
178	* 0A 0B 1A 1B 1-ch 2-ch	205	* 0A 0B 1A 1B 1-ch 2-ch
179	* 512 0 0 0 512 0 O	206	* 512 0 0 0 512 0 O
180	* 512 0 512 0 16 1008 X	207	* 512 0 512 0 16 1008 X
181	* 512 0 0 512 16 1008 X	208	* 512 0 0 512 16 1008 X
182	* 0 512 0 512 16 1008 X	209	* 0 512 0 512 16 1008 X
183	* 1024 1024 1024 0 2048 1024 O	210	* 1024 1024 1024 0 2048 1024 O
184	*	211	*
185	* We could probably detect this based on either the DRB	212	* We could probably detect this based on either the DRB
186	* matching, which was the case for the swizzling required in	213	* matching, which was the case for the swizzling required in
187	* the table above, or from the 1-ch value being less than	214	* the table above, or from the 1-ch value being less than
188	* the minimum size of a rank.	215	* the minimum size of a rank.
189	*/	216	*/
190	if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {	217	if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
191	swizzle_x = I915_BIT_6_SWIZZLE_NONE;	218	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
192	swizzle_y = I915_BIT_6_SWIZZLE_NONE;	219	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
193	} else {	220	} else {
194	swizzle_x = I915_BIT_6_SWIZZLE_9_10;	221	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
195	swizzle_y = I915_BIT_6_SWIZZLE_9;	222	swizzle_y = I915_BIT_6_SWIZZLE_9;
196	}	223	}
197	}	224	}
198		225
199	dev_priv->mm.bit_6_swizzle_x = swizzle_x;	226	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
200	dev_priv->mm.bit_6_swizzle_y = swizzle_y;	227	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
201	}	228	}
202		229
203	/* Check pitch constriants for all chips & tiling formats */	230	/* Check pitch constriants for all chips & tiling formats */
204	static bool	231	static bool
205	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)	232	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
206	{	233	{
207	int tile_width;	234	int tile_width;
208		235
209	/* Linear is always fine */	236	/* Linear is always fine */
210	if (tiling_mode == I915_TILING_NONE)	237	if (tiling_mode == I915_TILING_NONE)
211	return true;	238	return true;
212		239
213	if (IS_GEN2(dev) \|\|	240	if (IS_GEN2(dev) \|\|
214	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))	241	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
215	tile_width = 128;	242	tile_width = 128;
216	else	243	else
217	tile_width = 512;	244	tile_width = 512;
218		245
219	/* check maximum stride & object size */	246	/* check maximum stride & object size */
220	/* i965+ stores the end address of the gtt mapping in the fence	247	/* i965+ stores the end address of the gtt mapping in the fence
221	* reg, so dont bother to check the size */	248	* reg, so dont bother to check the size */
222	if (INTEL_INFO(dev)->gen >= 7) {	249	if (INTEL_INFO(dev)->gen >= 7) {
223	if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)	250	if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
224	return false;	251	return false;
225	} else if (INTEL_INFO(dev)->gen >= 4) {	252	} else if (INTEL_INFO(dev)->gen >= 4) {
226	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)	253	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
227	return false;	254	return false;
228	} else {	255	} else {
229	if (stride > 8192)	256	if (stride > 8192)
230	return false;	257	return false;
231		258
232	if (IS_GEN3(dev)) {	259	if (IS_GEN3(dev)) {
233	if (size > I830_FENCE_MAX_SIZE_VAL << 20)	260	if (size > I830_FENCE_MAX_SIZE_VAL << 20)
234	return false;	261	return false;
235	} else {	262	} else {
236	if (size > I830_FENCE_MAX_SIZE_VAL << 19)	263	if (size > I830_FENCE_MAX_SIZE_VAL << 19)
237	return false;	264	return false;
238	}	265	}
239	}	266	}
240		267
241	if (stride < tile_width)	268	if (stride < tile_width)
242	return false;	269	return false;
243		270
244	/* 965+ just needs multiples of tile width */	271	/* 965+ just needs multiples of tile width */
245	if (INTEL_INFO(dev)->gen >= 4) {	272	if (INTEL_INFO(dev)->gen >= 4) {
246	if (stride & (tile_width - 1))	273	if (stride & (tile_width - 1))
247	return false;	274	return false;
248	return true;	275	return true;
249	}	276	}
250		277
251	/* Pre-965 needs power of two tile widths */	278	/* Pre-965 needs power of two tile widths */
252	if (stride & (stride - 1))	279	if (stride & (stride - 1))
253	return false;	280	return false;
254		281
255	return true;	282	return true;
256	}	283	}
257		284
258	/* Is the current GTT allocation valid for the change in tiling? */	285	/* Is the current GTT allocation valid for the change in tiling? */
259	static bool	286	static bool
260	i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)	287	i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
261	{	288	{
262	u32 size;	289	u32 size;
263		290
264	if (tiling_mode == I915_TILING_NONE)	291	if (tiling_mode == I915_TILING_NONE)
265	return true;	292	return true;
266		293
267	if (INTEL_INFO(obj->base.dev)->gen >= 4)	294	if (INTEL_INFO(obj->base.dev)->gen >= 4)
268	return true;	295	return true;
269		296
270	if (INTEL_INFO(obj->base.dev)->gen == 3) {	297	if (INTEL_INFO(obj->base.dev)->gen == 3) {
271	if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)	298	if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
272	return false;	299	return false;
273	} else {	300	} else {
274	if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)	301	if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
275	return false;	302	return false;
276	}	303	}
277		304
278	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);	305	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
279	if (i915_gem_obj_ggtt_size(obj) != size)	306	if (i915_gem_obj_ggtt_size(obj) != size)
280	return false;	307	return false;
281		308
282	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))	309	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
283	return false;	310	return false;
284		311
285	return true;	312	return true;
286	}	313	}
287		314
288	/**	315	/**
289	* Sets the tiling mode of an object, returning the required swizzling of	316	* Sets the tiling mode of an object, returning the required swizzling of
290	* bit 6 of addresses in the object.	317	* bit 6 of addresses in the object.
291	*/	318	*/
292	int	319	int
293	i915_gem_set_tiling(struct drm_device dev, void data,	320	i915_gem_set_tiling(struct drm_device dev, void data,
294	struct drm_file *file)	321	struct drm_file *file)
295	{	322	{
296	struct drm_i915_gem_set_tiling *args = data;	323	struct drm_i915_gem_set_tiling *args = data;
297	struct drm_i915_private *dev_priv = dev->dev_private;	324	struct drm_i915_private *dev_priv = dev->dev_private;
298	struct drm_i915_gem_object *obj;	325	struct drm_i915_gem_object *obj;
299	int ret = 0;	326	int ret = 0;
300		327
301	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));	328	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
302	if (&obj->base == NULL)	329	if (&obj->base == NULL)
303	return -ENOENT;	330	return -ENOENT;
304		331
305	if (!i915_tiling_ok(dev,	332	if (!i915_tiling_ok(dev,
306	args->stride, obj->base.size, args->tiling_mode)) {	333	args->stride, obj->base.size, args->tiling_mode)) {
307	drm_gem_object_unreference_unlocked(&obj->base);	334	drm_gem_object_unreference_unlocked(&obj->base);
308	return -EINVAL;	335	return -EINVAL;
309	}	336	}
310		337
311	if (i915_gem_obj_is_pinned(obj) \|\| obj->framebuffer_references) {	338	if (i915_gem_obj_is_pinned(obj) \|\| obj->framebuffer_references) {
312	drm_gem_object_unreference_unlocked(&obj->base);	339	drm_gem_object_unreference_unlocked(&obj->base);
313	return -EBUSY;	340	return -EBUSY;
314	}	341	}
315		342
316	if (args->tiling_mode == I915_TILING_NONE) {	343	if (args->tiling_mode == I915_TILING_NONE) {
317	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;	344	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
318	args->stride = 0;	345	args->stride = 0;
319	} else {	346	} else {
320	if (args->tiling_mode == I915_TILING_X)	347	if (args->tiling_mode == I915_TILING_X)
321	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;	348	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
322	else	349	else
323	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;	350	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
324		351
325	/* Hide bit 17 swizzling from the user. This prevents old Mesa	352	/* Hide bit 17 swizzling from the user. This prevents old Mesa
326	* from aborting the application on sw fallbacks to bit 17,	353	* from aborting the application on sw fallbacks to bit 17,
327	* and we use the pread/pwrite bit17 paths to swizzle for it.	354	* and we use the pread/pwrite bit17 paths to swizzle for it.
328	* If there was a user that was relying on the swizzle	355	* If there was a user that was relying on the swizzle
329	* information for drm_intel_bo_map()ed reads/writes this would	356	* information for drm_intel_bo_map()ed reads/writes this would
330	* break it, but we don't have any of those.	357	* break it, but we don't have any of those.
331	*/	358	*/
332	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)	359	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
333	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;	360	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
334	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)	361	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
335	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;	362	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
336		363
337	/* If we can't handle the swizzling, make it untiled. */	364	/* If we can't handle the swizzling, make it untiled. */
338	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {	365	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
339	args->tiling_mode = I915_TILING_NONE;	366	args->tiling_mode = I915_TILING_NONE;
340	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;	367	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
341	args->stride = 0;	368	args->stride = 0;
342	}	369	}
343	}	370	}
344		371
345	mutex_lock(&dev->struct_mutex);	372	mutex_lock(&dev->struct_mutex);
346	if (args->tiling_mode != obj->tiling_mode \|\|	373	if (args->tiling_mode != obj->tiling_mode \|\|
347	args->stride != obj->stride) {	374	args->stride != obj->stride) {
348	/* We need to rebind the object if its current allocation	375	/* We need to rebind the object if its current allocation
349	* no longer meets the alignment restrictions for its new	376	* no longer meets the alignment restrictions for its new
350	* tiling mode. Otherwise we can just leave it alone, but	377	* tiling mode. Otherwise we can just leave it alone, but
351	* need to ensure that any fence register is updated before	378	* need to ensure that any fence register is updated before
352	* the next fenced (either through the GTT or by the BLT unit	379	* the next fenced (either through the GTT or by the BLT unit
353	* on older GPUs) access.	380	* on older GPUs) access.
354	*	381	*
355	* After updating the tiling parameters, we then flag whether	382	* After updating the tiling parameters, we then flag whether
356	* we need to update an associated fence register. Note this	383	* we need to update an associated fence register. Note this
357	* has to also include the unfenced register the GPU uses	384	* has to also include the unfenced register the GPU uses
358	* whilst executing a fenced command for an untiled object.	385	* whilst executing a fenced command for an untiled object.
359	*/	386	*/
360		-
361	obj->map_and_fenceable =	387	if (obj->map_and_fenceable &&
362	!i915_gem_obj_ggtt_bound(obj) \|\|	-
363	(i915_gem_obj_ggtt_offset(obj) +	-
364	obj->base.size <= dev_priv->gtt.mappable_end &&	-
365	i915_gem_object_fence_ok(obj, args->tiling_mode));	388	!i915_gem_object_fence_ok(obj, args->tiling_mode))
366		-
367	/* Rebind if we need a change of alignment */	-
368	if (!obj->map_and_fenceable) {	-
369	u32 unfenced_align =	-
370	i915_gem_get_gtt_alignment(dev, obj->base.size,	-
371	args->tiling_mode,	-
372	false);	-
373	if (i915_gem_obj_ggtt_offset(obj) & (unfenced_align - 1))	-
374	ret = i915_gem_object_ggtt_unbind(obj);	389	ret = i915_gem_object_ggtt_unbind(obj);
375	}	-
376		390
-		391	if (ret == 0) {
-		392	if (obj->pages &&
-		393	obj->madv == I915_MADV_WILLNEED &&
-		394	dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
-		395	if (args->tiling_mode == I915_TILING_NONE)
-		396	i915_gem_object_unpin_pages(obj);
-		397	if (obj->tiling_mode == I915_TILING_NONE)
-		398	i915_gem_object_pin_pages(obj);
-		399	}
377	if (ret == 0) {	400
378	obj->fence_dirty =	401	obj->fence_dirty =
379	obj->fenced_gpu_access \|\|	402	obj->last_fenced_seqno \|\|
380	obj->fence_reg != I915_FENCE_REG_NONE;	403	obj->fence_reg != I915_FENCE_REG_NONE;
381		404
382	obj->tiling_mode = args->tiling_mode;	405	obj->tiling_mode = args->tiling_mode;
383	obj->stride = args->stride;	406	obj->stride = args->stride;
384		407
385	/* Force the fence to be reacquired for GTT access */	408	/* Force the fence to be reacquired for GTT access */
386	i915_gem_release_mmap(obj);	409	i915_gem_release_mmap(obj);
387	}	410	}
388	}	411	}
389	/* we have to maintain this existing ABI... */	412	/* we have to maintain this existing ABI... */
390	args->stride = obj->stride;	413	args->stride = obj->stride;
391	args->tiling_mode = obj->tiling_mode;	414	args->tiling_mode = obj->tiling_mode;
392		415
393	/* Try to preallocate memory required to save swizzling on put-pages */	416	/* Try to preallocate memory required to save swizzling on put-pages */
394	if (i915_gem_object_needs_bit17_swizzle(obj)) {	417	if (i915_gem_object_needs_bit17_swizzle(obj)) {
395	if (obj->bit_17 == NULL) {	418	if (obj->bit_17 == NULL) {
396	obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),	419	obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
397	sizeof(long), GFP_KERNEL);	420	sizeof(long), GFP_KERNEL);
398	}	421	}
399	} else {	422	} else {
400	kfree(obj->bit_17);	423	kfree(obj->bit_17);
401	obj->bit_17 = NULL;	424	obj->bit_17 = NULL;
402	}	425	}
403		426
404	drm_gem_object_unreference(&obj->base);	427	drm_gem_object_unreference(&obj->base);
405	mutex_unlock(&dev->struct_mutex);	428	mutex_unlock(&dev->struct_mutex);
406		429
407	return ret;	430	return ret;
408	}	431	}
409		432
410	/**	433	/**
411	* Returns the current tiling mode and required bit 6 swizzling for the object.	434	* Returns the current tiling mode and required bit 6 swizzling for the object.
412	*/	435	*/
413	int	436	int
414	i915_gem_get_tiling(struct drm_device dev, void data,	437	i915_gem_get_tiling(struct drm_device dev, void data,
415	struct drm_file *file)	438	struct drm_file *file)
416	{	439	{
417	struct drm_i915_gem_get_tiling *args = data;	440	struct drm_i915_gem_get_tiling *args = data;
418	struct drm_i915_private *dev_priv = dev->dev_private;	441	struct drm_i915_private *dev_priv = dev->dev_private;
419	struct drm_i915_gem_object *obj;	442	struct drm_i915_gem_object *obj;
420		443
421	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));	444	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
422	if (&obj->base == NULL)	445	if (&obj->base == NULL)
423	return -ENOENT;	446	return -ENOENT;
424		447
425	mutex_lock(&dev->struct_mutex);	448	mutex_lock(&dev->struct_mutex);
426		449
427	args->tiling_mode = obj->tiling_mode;	450	args->tiling_mode = obj->tiling_mode;
428	switch (obj->tiling_mode) {	451	switch (obj->tiling_mode) {
429	case I915_TILING_X:	452	case I915_TILING_X:
430	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;	453	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
431	break;	454	break;
432	case I915_TILING_Y:	455	case I915_TILING_Y:
433	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;	456	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
434	break;	457	break;
435	case I915_TILING_NONE:	458	case I915_TILING_NONE:
436	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;	459	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
437	break;	460	break;
438	default:	461	default:
439	DRM_ERROR("unknown tiling mode\n");	462	DRM_ERROR("unknown tiling mode\n");
440	}	463	}
441		464
442	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */	465	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
-		466	args->phys_swizzle_mode = args->swizzle_mode;
443	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)	467	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
444	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;	468	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
445	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)	469	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
446	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;	470	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
447		471
448	drm_gem_object_unreference(&obj->base);	472	drm_gem_object_unreference(&obj->base);
449	mutex_unlock(&dev->struct_mutex);	473	mutex_unlock(&dev->struct_mutex);
450		474
451	return 0;	475	return 0;
452	}	476	}
453		477
454	#if 0	478	#if 0
455	/**	479	/**
456	* Swap every 64 bytes of this page around, to account for it having a new	480	* Swap every 64 bytes of this page around, to account for it having a new
457	* bit 17 of its physical address and therefore being interpreted differently	481	* bit 17 of its physical address and therefore being interpreted differently
458	* by the GPU.	482	* by the GPU.
459	*/	483	*/
460	static void	484	static void
461	i915_gem_swizzle_page(struct page *page)	485	i915_gem_swizzle_page(struct page *page)
462	{	486	{
463	char temp[64];	487	char temp[64];

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(root)/drivers/video/drm/i915/i915_gem_tiling.c – Rev 5060 → 5354