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| Rev 5060 | Rev 5354 | ||
|---|---|---|---|
| Line 89... | Line 89... | ||
| 89 | { |
89 | { |
| 90 | struct drm_i915_private *dev_priv = dev->dev_private; |
90 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 91 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
91 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 92 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
92 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| Line 93... | Line 93... | ||
| 93 | 93 | ||
| - | 94 | if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { |
|
| - | 95 | /* |
|
| - | 96 | * On BDW+, swizzling is not used. We leave the CPU memory |
|
| - | 97 | * controller in charge of optimizing memory accesses without |
|
| - | 98 | * the extra address manipulation GPU side. |
|
| - | 99 | * |
|
| - | 100 | * VLV and CHV don't have GPU swizzling. |
|
| 94 | if (IS_VALLEYVIEW(dev)) { |
101 | */ |
| 95 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
102 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 96 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
103 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| - | 104 | } else if (INTEL_INFO(dev)->gen >= 6) { |
|
| - | 105 | if (dev_priv->preserve_bios_swizzle) { |
|
| - | 106 | if (I915_READ(DISP_ARB_CTL) & |
|
| - | 107 | DISP_TILE_SURFACE_SWIZZLING) { |
|
| - | 108 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
|
| - | 109 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
|
| - | 110 | } else { |
|
| - | 111 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
|
| - | 112 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
|
| - | 113 | } |
|
| 97 | } else if (INTEL_INFO(dev)->gen >= 6) { |
114 | } else { |
| 98 | uint32_t dimm_c0, dimm_c1; |
115 | uint32_t dimm_c0, dimm_c1; |
| 99 | dimm_c0 = I915_READ(MAD_DIMM_C0); |
116 | dimm_c0 = I915_READ(MAD_DIMM_C0); |
| 100 | dimm_c1 = I915_READ(MAD_DIMM_C1); |
117 | dimm_c1 = I915_READ(MAD_DIMM_C1); |
| 101 | dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
118 | dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
| 102 | dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
119 | dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
| 103 | /* Enable swizzling when the channels are populated with |
120 | /* Enable swizzling when the channels are populated |
| 104 | * identically sized dimms. We don't need to check the 3rd |
121 | * with identically sized dimms. We don't need to check |
| 105 | * channel because no cpu with gpu attached ships in that |
122 | * the 3rd channel because no cpu with gpu attached |
| 106 | * configuration. Also, swizzling only makes sense for 2 |
123 | * ships in that configuration. Also, swizzling only |
| 107 | * channels anyway. */ |
124 | * makes sense for 2 channels anyway. */ |
| 108 | if (dimm_c0 == dimm_c1) { |
125 | if (dimm_c0 == dimm_c1) { |
| 109 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
126 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 110 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
127 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
| 111 | } else { |
128 | } else { |
| 112 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
129 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 113 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
130 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| - | 131 | } |
|
| 114 | } |
132 | } |
| 115 | } else if (IS_GEN5(dev)) { |
133 | } else if (IS_GEN5(dev)) { |
| 116 | /* On Ironlake whatever DRAM config, GPU always do |
134 | /* On Ironlake whatever DRAM config, GPU always do |
| 117 | * same swizzling setup. |
135 | * same swizzling setup. |
| 118 | */ |
136 | */ |
| Line 158... | Line 176... | ||
| 158 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
176 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
| 159 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; |
177 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; |
| 160 | } |
178 | } |
| 161 | break; |
179 | break; |
| 162 | } |
180 | } |
| - | 181 | ||
| - | 182 | /* check for L-shaped memory aka modified enhanced addressing */ |
|
| - | 183 | if (IS_GEN4(dev)) { |
|
| - | 184 | uint32_t ddc2 = I915_READ(DCC2); |
|
| - | 185 | ||
| - | 186 | if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) |
|
| - | 187 | dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES; |
|
| - | 188 | } |
|
| - | 189 | ||
| 163 | if (dcc == 0xffffffff) { |
190 | if (dcc == 0xffffffff) { |
| 164 | DRM_ERROR("Couldn't read from MCHBAR. " |
191 | DRM_ERROR("Couldn't read from MCHBAR. " |
| 165 | "Disabling tiling.\n"); |
192 | "Disabling tiling.\n"); |
| 166 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
193 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 167 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
194 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| Line 355... | Line 382... | ||
| 355 | * After updating the tiling parameters, we then flag whether |
382 | * After updating the tiling parameters, we then flag whether |
| 356 | * we need to update an associated fence register. Note this |
383 | * we need to update an associated fence register. Note this |
| 357 | * has to also include the unfenced register the GPU uses |
384 | * has to also include the unfenced register the GPU uses |
| 358 | * whilst executing a fenced command for an untiled object. |
385 | * whilst executing a fenced command for an untiled object. |
| 359 | */ |
386 | */ |
| 360 | - | ||
| 361 | obj->map_and_fenceable = |
387 | if (obj->map_and_fenceable && |
| 362 | !i915_gem_obj_ggtt_bound(obj) || |
- | |
| 363 | (i915_gem_obj_ggtt_offset(obj) + |
- | |
| 364 | obj->base.size <= dev_priv->gtt.mappable_end && |
- | |
| 365 | i915_gem_object_fence_ok(obj, args->tiling_mode)); |
388 | !i915_gem_object_fence_ok(obj, args->tiling_mode)) |
| 366 | - | ||
| 367 | /* Rebind if we need a change of alignment */ |
- | |
| 368 | if (!obj->map_and_fenceable) { |
- | |
| 369 | u32 unfenced_align = |
- | |
| 370 | i915_gem_get_gtt_alignment(dev, obj->base.size, |
- | |
| 371 | args->tiling_mode, |
- | |
| 372 | false); |
- | |
| 373 | if (i915_gem_obj_ggtt_offset(obj) & (unfenced_align - 1)) |
- | |
| 374 | ret = i915_gem_object_ggtt_unbind(obj); |
389 | ret = i915_gem_object_ggtt_unbind(obj); |
| 375 | } |
- | |
| Line 376... | Line 390... | ||
| 376 | 390 | ||
| - | 391 | if (ret == 0) { |
|
| - | 392 | if (obj->pages && |
|
| - | 393 | obj->madv == I915_MADV_WILLNEED && |
|
| - | 394 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
|
| - | 395 | if (args->tiling_mode == I915_TILING_NONE) |
|
| - | 396 | i915_gem_object_unpin_pages(obj); |
|
| - | 397 | if (obj->tiling_mode == I915_TILING_NONE) |
|
| - | 398 | i915_gem_object_pin_pages(obj); |
|
| - | 399 | } |
|
| 377 | if (ret == 0) { |
400 | |
| 378 | obj->fence_dirty = |
401 | obj->fence_dirty = |
| 379 | obj->fenced_gpu_access || |
402 | obj->last_fenced_seqno || |
| Line 380... | Line 403... | ||
| 380 | obj->fence_reg != I915_FENCE_REG_NONE; |
403 | obj->fence_reg != I915_FENCE_REG_NONE; |
| 381 | 404 | ||
| Line 438... | Line 461... | ||
| 438 | default: |
461 | default: |
| 439 | DRM_ERROR("unknown tiling mode\n"); |
462 | DRM_ERROR("unknown tiling mode\n"); |
| 440 | } |
463 | } |
| Line 441... | Line 464... | ||
| 441 | 464 | ||
| - | 465 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
|
| 442 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
466 | args->phys_swizzle_mode = args->swizzle_mode; |
| 443 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
467 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 444 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
468 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 445 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
469 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |