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Rev 4104 Rev 4246
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 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
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 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
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 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
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 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
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 * to match what the GPU expects.
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 * to match what the GPU expects.
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 */
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 */
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#define I915_TILING_NONE   0
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#define I915_TILING_X       1
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#define I915_TILING_Y       2
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#define I915_BIT_6_SWIZZLE_NONE     0
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#define I915_BIT_6_SWIZZLE_9        1
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#define I915_BIT_6_SWIZZLE_9_10     2
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#define I915_BIT_6_SWIZZLE_9_11     3
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#define I915_BIT_6_SWIZZLE_9_10_11  4
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/* Not seen by userland */
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#define I915_BIT_6_SWIZZLE_UNKNOWN  5
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/* Seen by userland. */
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#define I915_BIT_6_SWIZZLE_9_17     6
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#define I915_BIT_6_SWIZZLE_9_10_17  7
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/**
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/**
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 * Detects bit 6 swizzling of address lookup between IGD access and CPU
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 * Detects bit 6 swizzling of address lookup between IGD access and CPU
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 * access through main memory.
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 * access through main memory.
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 */
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 */
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	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
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	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
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	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
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	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
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}
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}
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#if 0
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/* Check pitch constriants for all chips & tiling formats */
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/* Check pitch constriants for all chips & tiling formats */
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static bool
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static bool
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i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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	mutex_unlock(&dev->struct_mutex);
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	mutex_unlock(&dev->struct_mutex);
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	return 0;
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	return 0;
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}
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}
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#if 0
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/**
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/**
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 * Swap every 64 bytes of this page around, to account for it having a new
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 * Swap every 64 bytes of this page around, to account for it having a new
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 * bit 17 of its physical address and therefore being interpreted differently
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 * bit 17 of its physical address and therefore being interpreted differently