Rev 4104 | Rev 4560 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 4104 | Rev 4246 | ||
---|---|---|---|
Line 78... | Line 78... | ||
78 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling |
78 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling |
79 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order |
79 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order |
80 | * to match what the GPU expects. |
80 | * to match what the GPU expects. |
81 | */ |
81 | */ |
Line 82... | Line -... | ||
82 | - | ||
83 | #define I915_TILING_NONE 0 |
- | |
84 | #define I915_TILING_X 1 |
- | |
85 | #define I915_TILING_Y 2 |
- | |
86 | - | ||
87 | #define I915_BIT_6_SWIZZLE_NONE 0 |
- | |
88 | #define I915_BIT_6_SWIZZLE_9 1 |
- | |
89 | #define I915_BIT_6_SWIZZLE_9_10 2 |
- | |
90 | #define I915_BIT_6_SWIZZLE_9_11 3 |
- | |
91 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
- | |
92 | /* Not seen by userland */ |
- | |
93 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
- | |
94 | /* Seen by userland. */ |
- | |
95 | #define I915_BIT_6_SWIZZLE_9_17 6 |
- | |
96 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
- | |
97 | - | ||
98 | - | ||
99 | - | ||
100 | 82 | ||
101 | /** |
83 | /** |
102 | * Detects bit 6 swizzling of address lookup between IGD access and CPU |
84 | * Detects bit 6 swizzling of address lookup between IGD access and CPU |
103 | * access through main memory. |
85 | * access through main memory. |
104 | */ |
86 | */ |
Line 216... | Line 198... | ||
216 | 198 | ||
217 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; |
199 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; |
218 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; |
200 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; |
Line 219... | Line -... | ||
219 | } |
- | |
220 | 201 | } |
|
221 | #if 0 |
202 | |
222 | /* Check pitch constriants for all chips & tiling formats */ |
203 | /* Check pitch constriants for all chips & tiling formats */ |
223 | static bool |
204 | static bool |
224 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
205 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
Line 468... | Line 449... | ||
468 | mutex_unlock(&dev->struct_mutex); |
449 | mutex_unlock(&dev->struct_mutex); |
Line 469... | Line 450... | ||
469 | 450 | ||
470 | return 0; |
451 | return 0; |
Line -... | Line 452... | ||
- | 452 | } |
|
471 | } |
453 | |
472 | 454 | #if 0 |
|
473 | /** |
455 | /** |
474 | * Swap every 64 bytes of this page around, to account for it having a new |
456 | * Swap every 64 bytes of this page around, to account for it having a new |
475 | * bit 17 of its physical address and therefore being interpreted differently |
457 | * bit 17 of its physical address and therefore being interpreted differently |