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Line 23... | Line 23... | ||
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | * |
25 | * |
26 | */ |
26 | */ |
Line 27... | Line 27... | ||
27 | 27 | ||
28 | #include "linux/string.h" |
28 | #include |
29 | #include "linux/bitops.h" |
29 | #include |
30 | #include "drmP.h" |
- | |
31 | #include "drm.h" |
30 | #include |
32 | #include "i915_drm.h" |
31 | #include |
Line 33... | Line 32... | ||
33 | #include "i915_drv.h" |
32 | #include "i915_drv.h" |
34 | 33 | ||
35 | /** @file i915_gem_tiling.c |
34 | /** @file i915_gem_tiling.c |
Line 108... | Line 107... | ||
108 | { |
107 | { |
109 | drm_i915_private_t *dev_priv = dev->dev_private; |
108 | drm_i915_private_t *dev_priv = dev->dev_private; |
110 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
109 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
111 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
110 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
Line 112... | Line 111... | ||
112 | 111 | ||
113 | if (INTEL_INFO(dev)->gen >= 6) { |
112 | if (IS_VALLEYVIEW(dev)) { |
114 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
113 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
- | 114 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
|
- | 115 | } else if (INTEL_INFO(dev)->gen >= 6) { |
|
- | 116 | uint32_t dimm_c0, dimm_c1; |
|
- | 117 | dimm_c0 = I915_READ(MAD_DIMM_C0); |
|
- | 118 | dimm_c1 = I915_READ(MAD_DIMM_C1); |
|
- | 119 | dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
|
- | 120 | dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; |
|
- | 121 | /* Enable swizzling when the channels are populated with |
|
- | 122 | * identically sized dimms. We don't need to check the 3rd |
|
- | 123 | * channel because no cpu with gpu attached ships in that |
|
- | 124 | * configuration. Also, swizzling only makes sense for 2 |
|
- | 125 | * channels anyway. */ |
|
- | 126 | if (dimm_c0 == dimm_c1) { |
|
- | 127 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
|
- | 128 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
|
- | 129 | } else { |
|
- | 130 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
|
- | 131 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
|
115 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
132 | } |
116 | } else if (IS_GEN5(dev)) { |
133 | } else if (IS_GEN5(dev)) { |
117 | /* On Ironlake whatever DRAM config, GPU always do |
134 | /* On Ironlake whatever DRAM config, GPU always do |
118 | * same swizzling setup. |
135 | * same swizzling setup. |
119 | */ |
136 | */ |
Line 123... | Line 140... | ||
123 | /* As far as we know, the 865 doesn't have these bit 6 |
140 | /* As far as we know, the 865 doesn't have these bit 6 |
124 | * swizzling issues. |
141 | * swizzling issues. |
125 | */ |
142 | */ |
126 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
143 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
127 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
144 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
128 | } else if (IS_MOBILE(dev)) { |
145 | } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { |
129 | uint32_t dcc; |
146 | uint32_t dcc; |
Line 130... | Line 147... | ||
130 | 147 | ||
131 | /* On mobile 9xx chipsets, channel interleave by the CPU is |
148 | /* On 9xx chipsets, channel interleave by the CPU is |
132 | * determined by DCC. For single-channel, neither the CPU |
149 | * determined by DCC. For single-channel, neither the CPU |
133 | * nor the GPU do swizzling. For dual channel interleaved, |
150 | * nor the GPU do swizzling. For dual channel interleaved, |
134 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit |
151 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit |
135 | * 9 for Y tiled. The CPU's interleave is independent, and |
152 | * 9 for Y tiled. The CPU's interleave is independent, and |
Line 356... | Line 373... | ||
356 | if (args->tiling_mode != obj->tiling_mode || |
373 | if (args->tiling_mode != obj->tiling_mode || |
357 | args->stride != obj->stride) { |
374 | args->stride != obj->stride) { |
358 | /* We need to rebind the object if its current allocation |
375 | /* We need to rebind the object if its current allocation |
359 | * no longer meets the alignment restrictions for its new |
376 | * no longer meets the alignment restrictions for its new |
360 | * tiling mode. Otherwise we can just leave it alone, but |
377 | * tiling mode. Otherwise we can just leave it alone, but |
361 | * need to ensure that any fence register is cleared. |
378 | * need to ensure that any fence register is updated before |
- | 379 | * the next fenced (either through the GTT or by the BLT unit |
|
- | 380 | * on older GPUs) access. |
|
- | 381 | * |
|
- | 382 | * After updating the tiling parameters, we then flag whether |
|
- | 383 | * we need to update an associated fence register. Note this |
|
- | 384 | * has to also include the unfenced register the GPU uses |
|
- | 385 | * whilst executing a fenced command for an untiled object. |
|
362 | */ |
386 | */ |
363 | i915_gem_release_mmap(obj); |
- | |
Line 364... | Line 387... | ||
364 | 387 | ||
365 | obj->map_and_fenceable = |
388 | obj->map_and_fenceable = |
366 | obj->gtt_space == NULL || |
389 | obj->gtt_space == NULL || |
367 | (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && |
390 | (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && |
Line 376... | Line 399... | ||
376 | if (obj->gtt_offset & (unfenced_alignment - 1)) |
399 | if (obj->gtt_offset & (unfenced_alignment - 1)) |
377 | ret = i915_gem_object_unbind(obj); |
400 | ret = i915_gem_object_unbind(obj); |
378 | } |
401 | } |
Line 379... | Line 402... | ||
379 | 402 | ||
380 | if (ret == 0) { |
403 | if (ret == 0) { |
- | 404 | obj->fence_dirty = |
|
- | 405 | obj->fenced_gpu_access || |
|
- | 406 | obj->fence_reg != I915_FENCE_REG_NONE; |
|
381 | obj->tiling_changed = true; |
407 | |
382 | obj->tiling_mode = args->tiling_mode; |
408 | obj->tiling_mode = args->tiling_mode; |
- | 409 | obj->stride = args->stride; |
|
- | 410 | ||
- | 411 | /* Force the fence to be reacquired for GTT access */ |
|
383 | obj->stride = args->stride; |
412 | i915_gem_release_mmap(obj); |
384 | } |
413 | } |
385 | } |
414 | } |
386 | /* we have to maintain this existing ABI... */ |
415 | /* we have to maintain this existing ABI... */ |
387 | args->stride = obj->stride; |
416 | args->stride = obj->stride; |
Line 460... | Line 489... | ||
460 | } |
489 | } |
Line 461... | Line 490... | ||
461 | 490 | ||
462 | void |
491 | void |
463 | i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) |
492 | i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) |
- | 493 | { |
|
464 | { |
494 | struct scatterlist *sg; |
465 | int page_count = obj->base.size >> PAGE_SHIFT; |
495 | int page_count = obj->base.size >> PAGE_SHIFT; |
Line 466... | Line 496... | ||
466 | int i; |
496 | int i; |
467 | 497 | ||
Line 468... | Line 498... | ||
468 | if (obj->bit_17 == NULL) |
498 | if (obj->bit_17 == NULL) |
- | 499 | return; |
|
469 | return; |
500 | |
470 | 501 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
|
471 | for (i = 0; i < page_count; i++) { |
502 | struct page *page = sg_page(sg); |
472 | char new_bit_17 = page_to_phys(obj->pages[i]) >> 17; |
503 | char new_bit_17 = page_to_phys(page) >> 17; |
473 | if ((new_bit_17 & 0x1) != |
504 | if ((new_bit_17 & 0x1) != |
474 | (test_bit(i, obj->bit_17) != 0)) { |
505 | (test_bit(i, obj->bit_17) != 0)) { |
475 | i915_gem_swizzle_page(obj->pages[i]); |
506 | i915_gem_swizzle_page(page); |
476 | set_page_dirty(obj->pages[i]); |
507 | set_page_dirty(page); |
Line 477... | Line 508... | ||
477 | } |
508 | } |
478 | } |
509 | } |
479 | } |
510 | } |
- | 511 | ||
480 | 512 | void |
|
481 | void |
513 | i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) |
Line 482... | Line 514... | ||
482 | i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) |
514 | { |
483 | { |
515 | struct scatterlist *sg; |
Line 492... | Line 524... | ||
492 | "record\n"); |
524 | "record\n"); |
493 | return; |
525 | return; |
494 | } |
526 | } |
495 | } |
527 | } |
Line 496... | Line 528... | ||
496 | 528 | ||
- | 529 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
|
497 | for (i = 0; i < page_count; i++) { |
530 | struct page *page = sg_page(sg); |
498 | if (page_to_phys(obj->pages[i]) & (1 << 17)) |
531 | if (page_to_phys(page) & (1 << 17)) |
499 | __set_bit(i, obj->bit_17); |
532 | __set_bit(i, obj->bit_17); |
500 | else |
533 | else |
501 | __clear_bit(i, obj->bit_17); |
534 | __clear_bit(i, obj->bit_17); |
502 | } |
535 | } |