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Rev 5354 Rev 6084
Line 71... Line 71...
71
free_gem:
71
free_gem:
72
	drm_gem_object_unreference(&so->obj->base);
72
	drm_gem_object_unreference(&so->obj->base);
73
	return ret;
73
	return ret;
74
}
74
}
Line -... Line 75...
-
 
75
 
-
 
76
/*
-
 
77
 * Macro to add commands to auxiliary batch.
-
 
78
 * This macro only checks for page overflow before inserting the commands,
-
 
79
 * this is sufficient as the null state generator makes the final batch
-
 
80
 * with two passes to build command and state separately. At this point
-
 
81
 * the size of both are known and it compacts them by relocating the state
-
 
82
 * right after the commands taking care of aligment so we should sufficient
-
 
83
 * space below them for adding new commands.
-
 
84
 */
-
 
85
#define OUT_BATCH(batch, i, val)				\
-
 
86
	do {							\
-
 
87
		if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) {	\
-
 
88
			ret = -ENOSPC;				\
-
 
89
			goto err_out;				\
-
 
90
		}						\
-
 
91
		(batch)[(i)++] = (val);				\
-
 
92
	} while(0)
75
 
93
 
76
static int render_state_setup(struct render_state *so)
94
static int render_state_setup(struct render_state *so)
77
{
95
{
78
	const struct intel_renderstate_rodata *rodata = so->rodata;
96
	const struct intel_renderstate_rodata *rodata = so->rodata;
79
	unsigned int i = 0, reloc_index = 0;
97
	unsigned int i = 0, reloc_index = 0;
Line 94... Line 112...
94
		if (i * 4  == rodata->reloc[reloc_index]) {
112
		if (i * 4  == rodata->reloc[reloc_index]) {
95
			u64 r = s + so->ggtt_offset;
113
			u64 r = s + so->ggtt_offset;
96
			s = lower_32_bits(r);
114
			s = lower_32_bits(r);
97
			if (so->gen >= 8) {
115
			if (so->gen >= 8) {
98
				if (i + 1 >= rodata->batch_items ||
116
				if (i + 1 >= rodata->batch_items ||
99
				    rodata->batch[i + 1] != 0)
117
				    rodata->batch[i + 1] != 0) {
100
					return -EINVAL;
118
					ret = -EINVAL;
-
 
119
					goto err_out;
-
 
120
				}
Line 101... Line 121...
101
 
121
 
102
				d[i++] = s;
122
				d[i++] = s;
103
				s = upper_32_bits(r);
123
				s = upper_32_bits(r);
Line 104... Line 124...
104
			}
124
			}
105
 
125
 
Line 106... Line 126...
106
			reloc_index++;
126
			reloc_index++;
107
		}
127
		}
-
 
128
 
-
 
129
		d[i++] = s;
-
 
130
	}
-
 
131
 
-
 
132
	while (i % CACHELINE_DWORDS)
-
 
133
		OUT_BATCH(d, i, MI_NOOP);
-
 
134
 
-
 
135
	so->aux_batch_offset = i * sizeof(u32);
-
 
136
 
-
 
137
	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
-
 
138
	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
-
 
139
 
-
 
140
	/*
-
 
141
	 * Since we are sending length, we need to strictly conform to
-
 
142
	 * all requirements. For Gen2 this must be a multiple of 8.
108
 
143
	 */
Line 109... Line 144...
109
		d[i++] = s;
144
	so->aux_batch_size = ALIGN(so->aux_batch_size, 8);
110
	}
145
 
111
	kunmap(page);
146
	kunmap(page);
Line 118... Line 153...
118
		DRM_ERROR("only %d relocs resolved\n", reloc_index);
153
		DRM_ERROR("only %d relocs resolved\n", reloc_index);
119
		return -EINVAL;
154
		return -EINVAL;
120
	}
155
	}
Line 121... Line 156...
121
 
156
 
-
 
157
	return 0;
-
 
158
 
-
 
159
err_out:
-
 
160
	kunmap(page);
122
	return 0;
161
	return ret;
Line -... Line 162...
-
 
162
}
-
 
163
 
123
}
164
#undef OUT_BATCH
124
 
165
 
125
void i915_gem_render_state_fini(struct render_state *so)
166
void i915_gem_render_state_fini(struct render_state *so)
126
{
167
{
127
	i915_gem_object_ggtt_unpin(so->obj);
168
	i915_gem_object_ggtt_unpin(so->obj);
Line 150... Line 191...
150
	}
191
	}
Line 151... Line 192...
151
 
192
 
152
		return 0;
193
	return 0;
Line 153... Line 194...
153
}
194
}
154
 
195
 
155
int i915_gem_render_state_init(struct intel_engine_cs *ring)
196
int i915_gem_render_state_init(struct drm_i915_gem_request *req)
156
{
197
{
Line 157... Line 198...
157
	struct render_state so;
198
	struct render_state so;
158
	int ret;
199
	int ret;
159
 
200
 
Line 160... Line 201...
160
	ret = i915_gem_render_state_prepare(ring, &so);
201
	ret = i915_gem_render_state_prepare(req->ring, &so);
161
	if (ret)
202
	if (ret)
Line 162... Line 203...
162
		return ret;
203
		return ret;
163
 
-
 
164
	if (so.rodata == NULL)
204
 
165
		return 0;
205
	if (so.rodata == NULL)
166
 
206
		return 0;
167
	ret = ring->dispatch_execbuffer(ring,
207
 
Line -... Line 208...
-
 
208
	ret = req->ring->dispatch_execbuffer(req, so.ggtt_offset,
-
 
209
					     so.rodata->batch_items * 4,
-
 
210
					     I915_DISPATCH_SECURE);
-
 
211
	if (ret)
-
 
212
		goto out;
-
 
213
 
-
 
214
	if (so.aux_batch_size > 8) {
-
 
215
		ret = req->ring->dispatch_execbuffer(req,
-
 
216
						     (so.ggtt_offset +
-
 
217
						      so.aux_batch_offset),
168
					so.ggtt_offset,
218
						     so.aux_batch_size,
Line 169... Line -...
169
					so.rodata->batch_items * 4,
-
 
170
					I915_DISPATCH_SECURE);
-
 
171
	if (ret)
219
						     I915_DISPATCH_SECURE);
172
		goto out;
220
		if (ret)
173
 
221
			goto out;
174
	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
222
	}