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 */
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 */
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#ifndef __I915_GEM_GTT_H__
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#ifndef __I915_GEM_GTT_H__
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#define __I915_GEM_GTT_H__
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#define __I915_GEM_GTT_H__
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struct drm_i915_file_private;
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typedef uint32_t gen6_gtt_pte_t;
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typedef uint32_t gen6_gtt_pte_t;
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typedef uint64_t gen8_gtt_pte_t;
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typedef uint64_t gen8_gtt_pte_t;
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struct i915_vma {
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struct i915_vma {
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	struct drm_mm_node node;
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	struct drm_mm_node node;
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	struct drm_i915_gem_object *obj;
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	struct drm_i915_gem_object *obj;
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	struct i915_address_space *vm;
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	struct i915_address_space *vm;
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	/** Flags and address space this VMA is bound to */
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#define GLOBAL_BIND	(1<<0)
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#define LOCAL_BIND	(1<<1)
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#define PTE_READ_ONLY	(1<<2)
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	unsigned int bound : 4;
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	/** This object's place on the active/inactive lists */
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	/** This object's place on the active/inactive lists */
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	struct list_head mm_list;
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	struct list_head mm_list;
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	/** Unmap an object from an address space. This usually consists of
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	/** Unmap an object from an address space. This usually consists of
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	 * setting the valid PTE entries to a reserved scratch page. */
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	 * setting the valid PTE entries to a reserved scratch page. */
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	void (*unbind_vma)(struct i915_vma *vma);
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	void (*unbind_vma)(struct i915_vma *vma);
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	/* Map an object into an address space with the given cache flags. */
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#define GLOBAL_BIND (1<<0)
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#define PTE_READ_ONLY (1<<1)
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	/* Map an object into an address space with the given cache flags. */
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	void (*bind_vma)(struct i915_vma *vma,
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	void (*bind_vma)(struct i915_vma *vma,
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			 enum i915_cache_level cache_level,
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			 enum i915_cache_level cache_level,
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			 u32 flags);
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			 u32 flags);
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	union {
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	union {
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		dma_addr_t *pt_dma_addr;
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		dma_addr_t *pt_dma_addr;
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		dma_addr_t *gen8_pt_dma_addr[4];
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		dma_addr_t *gen8_pt_dma_addr[4];
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	};
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	};
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	struct intel_context *ctx;
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	struct drm_i915_file_private *file_priv;
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	int (*enable)(struct i915_hw_ppgtt *ppgtt);
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	int (*enable)(struct i915_hw_ppgtt *ppgtt);
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	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
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			 struct intel_engine_cs *ring,
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	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
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			 bool synchronous);
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			 struct intel_engine_cs *ring);
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//   void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
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//   void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
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};
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};
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int i915_gem_gtt_init(struct drm_device *dev);
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int i915_gem_gtt_init(struct drm_device *dev);
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void i915_gem_init_global_gtt(struct drm_device *dev);
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void i915_gem_init_global_gtt(struct drm_device *dev);
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void i915_global_gtt_cleanup(struct drm_device *dev);
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int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
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int i915_ppgtt_init_hw(struct drm_device *dev);
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void i915_ppgtt_release(struct kref *kref);
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struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
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					struct drm_i915_file_private *fpriv);
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static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
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void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
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{
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	if (ppgtt)
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		kref_get(&ppgtt->ref);
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}
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static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
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			       unsigned long mappable_end, unsigned long end);
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{
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	if (ppgtt)
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bool intel_enable_ppgtt(struct drm_device *dev, bool full);
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		kref_put(&ppgtt->ref, i915_ppgtt_release);