WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_gtt.c

 #include
 #include
 #include
+#include "i915_drv.h"
-#include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "i915_trace.h"
+#include "intel_drv.h"
+/**
+ * DOC: Global GTT views
+ *
+ * Background and previous state
+ *
+ * Historically objects could exists (be bound) in global GTT space only as
+ * singular instances with a view representing all of the object's backing pages
+ * in a linear fashion. This view will be called a normal view.
+ *
+ * To support multiple views of the same object, where the number of mapped
+ * pages is not equal to the backing store, or where the layout of the pages
+ * is not linear, concept of a GGTT view was added.
+ *
+ * One example of an alternative view is a stereo display driven by a single
+ * image. In this case we would have a framebuffer looking like this
+ * (2x2 pages):
+ *
+ *    12
+ *    34
+ *
+ * Above would represent a normal GGTT view as normally mapped for GPU or CPU
+ * rendering. In contrast, fed to the display engine would be an alternative
+ * view which could look something like this:
+ *
+ *   1212
+ *   3434
+ *
+ * In this example both the size and layout of pages in the alternative view is
-#include "intel_drv.h"
+ * different from the normal view.
+ *
+ * Implementation and usage
+ *
+ * GGTT views are implemented using VMAs and are distinguished via enum
+ * i915_ggtt_view_type and struct i915_ggtt_view.
+ *
+ * A new flavour of core GEM functions which work with GGTT bound objects were
+ * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
+ * renaming  in large amounts of code. They take the struct i915_ggtt_view
+ * parameter encapsulating all metadata required to implement a view.
+ *
+ * As a helper for callers which are only interested in the normal view,
+ * globally const i915_ggtt_view_normal singleton instance exists. All old core
+ * GEM API functions, the ones not taking the view parameter, are operating on,
+ * or with the normal GGTT view.
+ *
+ * Code wanting to add or use a new GGTT view needs to:
+ *
+ * 1. Add a new enum with a suitable name.
+ * 2. Extend the metadata in the i915_ggtt_view structure if required.
+ * 3. Add support to i915_get_vma_pages().
+ *
+ * New views are required to build a scatter-gather table from within the
+ * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
+ * exists for the lifetime of an VMA.
+ *
+ * Core API is designed to have copy semantics which means that passed in
+ * struct i915_ggtt_view does not need to be persistent (left around after
+ * calling the core API functions).
+ *
+ */
-#include
+static int
+i915_get_ggtt_vma_pages(struct i915_vma *vma);
+const struct i915_ggtt_view i915_ggtt_view_normal;
 const struct i915_ggtt_view i915_ggtt_view_rotated = {
-static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
+        .type = I915_GGTT_VIEW_ROTATED
-static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
+};
 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+{
+	bool has_aliasing_ppgtt;
-	bool has_aliasing_ppgtt;
+	bool has_full_ppgtt;
-	bool has_full_ppgtt;
 	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
-	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
+	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
-	if (IS_GEN8(dev))
+	if (intel_vgpu_active(dev))
 	    dev->pdev->revision < 0xb) {
 		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 		return 0;
+	}
+	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
+		return 2;
 	else
-	return has_aliasing_ppgtt ? 1 : 0;
+		return has_aliasing_ppgtt ? 1 : 0;
-}
+}
-static void ppgtt_bind_vma(struct i915_vma *vma,
+static int ppgtt_bind_vma(struct i915_vma *vma,
+			  enum i915_cache_level cache_level,
+			  u32 unused)
+{
-			   enum i915_cache_level cache_level,
+	u32 pte_flags = 0;
+	/* Currently applicable only to VLV */
+	if (vma->obj->gt_ro)
+		pte_flags |= PTE_READ_ONLY;
+	vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
+				cache_level, pte_flags);
+	return 0;
+}
+static void ppgtt_unbind_vma(struct i915_vma *vma)
+{
+	vma->vm->clear_range(vma->vm,
+			     vma->node.start,
+			     vma->obj->base.size,
-			   u32 flags);
+			     true);
 static void ppgtt_unbind_vma(struct i915_vma *vma);
-static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
+static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
-					     enum i915_cache_level level,
+				  enum i915_cache_level level,
-					     bool valid)
+				  bool valid)
+{
-	gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+	gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 	pte |= addr;
+	}
 	return pte;
 }
-static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
-					     dma_addr_t addr,
+static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
-					     enum i915_cache_level level)
+				  const enum i915_cache_level level)
+{
-	gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
+	gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 	pde |= addr;
 	if (level != I915_CACHE_NONE)
 		pde |= PPAT_CACHED_PDE_INDEX;
 	else
 		pde |= PPAT_UNCACHED_INDEX;
+	return pde;
+}
-	return pde;
+#define gen8_pdpe_encode gen8_pde_encode
 #define gen8_pml4e_encode gen8_pde_encode
-static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
+static gen6_pte_t snb_pte_encode(dma_addr_t addr,
-				     enum i915_cache_level level,
+				 enum i915_cache_level level,
-				     bool valid, u32 unused)
+				 bool valid, u32 unused)
+{
-	gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 		break;
 	case I915_CACHE_NONE:
 		pte |= GEN6_PTE_UNCACHED;
 		break;
 	default:
-		WARN_ON(1);
+		MISSING_CASE(level);
+	}
 	return pte;
 }
-static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
+static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
-				     enum i915_cache_level level,
+				 enum i915_cache_level level,
-				     bool valid, u32 unused)
+				 bool valid, u32 unused)
+{
-	gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 		break;
 	case I915_CACHE_NONE:
-			pte |= GEN6_PTE_UNCACHED;
+		pte |= GEN6_PTE_UNCACHED;
 		break;
 	default:
-		WARN_ON(1);
+		MISSING_CASE(level);
+	}
 	return pte;
 }
-static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
+static gen6_pte_t byt_pte_encode(dma_addr_t addr,
-				     enum i915_cache_level level,
+				 enum i915_cache_level level,
-				     bool valid, u32 flags)
+				 bool valid, u32 flags)
+{
-	gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 	return pte;
 }
-static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
+static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
-				     enum i915_cache_level level,
+				 enum i915_cache_level level,
-				     bool valid, u32 unused)
+				 bool valid, u32 unused)
+{
-	gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= HSW_PTE_ADDR_ENCODE(addr);
 	if (level != I915_CACHE_NONE)
 		pte |= HSW_WB_LLC_AGE3;
 	return pte;
+}
-static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
+static gen6_pte_t iris_pte_encode(dma_addr_t addr,
-				      enum i915_cache_level level,
+				  enum i915_cache_level level,
-				      bool valid, u32 unused)
+				  bool valid, u32 unused)
+{
+	}
 	return pte;
+}
+static int __setup_page_dma(struct drm_device *dev,
+			    struct i915_page_dma *p, gfp_t flags)
+{
+	struct device *device = &dev->pdev->dev;
+	p->page = alloc_page(flags);
+	if (!p->page)
+		return -ENOMEM;
+	p->daddr = page_to_phys(p->page);
+	return 0;
+}
+static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
+{
+	return __setup_page_dma(dev, p, GFP_KERNEL);
+}
+static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
+{
+	if (WARN_ON(!p->page))
+		return;
+	__free_page(p->page);
+	memset(p, 0, sizeof(*p));
+}
+static void *kmap_page_dma(struct i915_page_dma *p)
+{
+	return kmap_atomic(p->page);
+}
+/* We use the flushing unmap only with ppgtt structures:
+ * page directories, page tables and scratch pages.
+ */
+static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+{
+	/* There are only few exceptions for gen >=6. chv and bxt.
+	 * And we are not sure about the latter so play safe for now.
+	 */
+	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+		drm_clflush_virt_range(vaddr, PAGE_SIZE);
+	kunmap_atomic(vaddr);
+}
+#define kmap_px(px) kmap_page_dma(px_base(px))
+#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
+#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
+#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
+#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
+#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
+static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
+			  const uint64_t val)
+{
+	int i;
+	uint64_t * const vaddr = kmap_page_dma(p);
+	for (i = 0; i < 512; i++)
+		vaddr[i] = val;
+	kunmap_page_dma(dev, vaddr);
+}
+static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
+			     const uint32_t val32)
+{
+	uint64_t v = val32;
+	v = v << 32 | val32;
+	fill_page_dma(dev, p, v);
+}
+static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
+{
+	struct i915_page_scratch *sp;
+	int ret;
+	sp = kzalloc(sizeof(*sp), GFP_KERNEL);
+	if (sp == NULL)
+		return ERR_PTR(-ENOMEM);
+	ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
+	if (ret) {
+		kfree(sp);
+		return ERR_PTR(ret);
+	}
+//   set_pages_uc(px_page(sp), 1);
+	return sp;
+}
+static void free_scratch_page(struct drm_device *dev,
+			      struct i915_page_scratch *sp)
+{
+//   set_pages_wb(px_page(sp), 1);
+	cleanup_px(dev, sp);
+	kfree(sp);
+}
+static struct i915_page_table *alloc_pt(struct drm_device *dev)
+{
+	struct i915_page_table *pt;
+	const size_t count = INTEL_INFO(dev)->gen >= 8 ?
+		GEN8_PTES : GEN6_PTES;
+	int ret = -ENOMEM;
+	pt = kzalloc(sizeof(*pt), GFP_KERNEL);
+	if (!pt)
+		return ERR_PTR(-ENOMEM);
+	pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
+				GFP_KERNEL);
+	if (!pt->used_ptes)
+		goto fail_bitmap;
+	ret = setup_px(dev, pt);
+	if (ret)
+		goto fail_page_m;
+	return pt;
+fail_page_m:
+	kfree(pt->used_ptes);
+fail_bitmap:
+	kfree(pt);
+	return ERR_PTR(ret);
+}
+static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
+{
+	cleanup_px(dev, pt);
+	kfree(pt->used_ptes);
+	kfree(pt);
+}
+static void gen8_initialize_pt(struct i915_address_space *vm,
+			       struct i915_page_table *pt)
+{
+	gen8_pte_t scratch_pte;
+	scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
+				      I915_CACHE_LLC, true);
+	fill_px(vm->dev, pt, scratch_pte);
+}
+static void gen6_initialize_pt(struct i915_address_space *vm,
+			       struct i915_page_table *pt)
+{
+	gen6_pte_t scratch_pte;
+	WARN_ON(px_dma(vm->scratch_page) == 0);
+	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
+				     I915_CACHE_LLC, true, 0);
+	fill32_px(vm->dev, pt, scratch_pte);
+}
+static struct i915_page_directory *alloc_pd(struct drm_device *dev)
+{
+	struct i915_page_directory *pd;
+	int ret = -ENOMEM;
+	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return ERR_PTR(-ENOMEM);
+	pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
+				sizeof(*pd->used_pdes), GFP_KERNEL);
+	if (!pd->used_pdes)
+		goto fail_bitmap;
+	ret = setup_px(dev, pd);
+	if (ret)
+		goto fail_page_m;
+	return pd;
+fail_page_m:
+	kfree(pd->used_pdes);
+fail_bitmap:
+	kfree(pd);
+	return ERR_PTR(ret);
+}
+static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
+{
+	if (px_page(pd)) {
+		cleanup_px(dev, pd);
+		kfree(pd->used_pdes);
+		kfree(pd);
+	}
+}
+static void gen8_initialize_pd(struct i915_address_space *vm,
+			       struct i915_page_directory *pd)
+{
+	gen8_pde_t scratch_pde;
+	scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
+	fill_px(vm->dev, pd, scratch_pde);
+}
+static int __pdp_init(struct drm_device *dev,
+		      struct i915_page_directory_pointer *pdp)
+{
+	size_t pdpes = I915_PDPES_PER_PDP(dev);
+	pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
+				  sizeof(unsigned long),
+				  GFP_KERNEL);
+	if (!pdp->used_pdpes)
+		return -ENOMEM;
+	pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
+				      GFP_KERNEL);
+	if (!pdp->page_directory) {
+		kfree(pdp->used_pdpes);
+		/* the PDP might be the statically allocated top level. Keep it
+		 * as clean as possible */
+		pdp->used_pdpes = NULL;
+		return -ENOMEM;
+	}
+	return 0;
+}
+static void __pdp_fini(struct i915_page_directory_pointer *pdp)
+{
+	kfree(pdp->used_pdpes);
+	kfree(pdp->page_directory);
+	pdp->page_directory = NULL;
+}
+static struct
+i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
+{
+	struct i915_page_directory_pointer *pdp;
+	int ret = -ENOMEM;
+	WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
+	pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
+	if (!pdp)
+		return ERR_PTR(-ENOMEM);
+	ret = __pdp_init(dev, pdp);
+	if (ret)
+		goto fail_bitmap;
+	ret = setup_px(dev, pdp);
+	if (ret)
+		goto fail_page_m;
+	return pdp;
+fail_page_m:
+	__pdp_fini(pdp);
+fail_bitmap:
+	kfree(pdp);
+	return ERR_PTR(ret);
+}
+static void free_pdp(struct drm_device *dev,
+		     struct i915_page_directory_pointer *pdp)
+{
+	__pdp_fini(pdp);
+	if (USES_FULL_48BIT_PPGTT(dev)) {
+		cleanup_px(dev, pdp);
+		kfree(pdp);
+	}
+}
+static void gen8_initialize_pdp(struct i915_address_space *vm,
+				struct i915_page_directory_pointer *pdp)
+{
+	gen8_ppgtt_pdpe_t scratch_pdpe;
+	scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
+	fill_px(vm->dev, pdp, scratch_pdpe);
+}
+static void gen8_initialize_pml4(struct i915_address_space *vm,
+				 struct i915_pml4 *pml4)
+{
+	gen8_ppgtt_pml4e_t scratch_pml4e;
+	scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
+					  I915_CACHE_LLC);
+	fill_px(vm->dev, pml4, scratch_pml4e);
+}
+static void
+gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
+			  struct i915_page_directory_pointer *pdp,
+			  struct i915_page_directory *pd,
+			  int index)
+{
+	gen8_ppgtt_pdpe_t *page_directorypo;
+	if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
+		return;
+	page_directorypo = kmap_px(pdp);
+	page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
+	kunmap_px(ppgtt, page_directorypo);
+}
+static void
+gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
+				  struct i915_pml4 *pml4,
+				  struct i915_page_directory_pointer *pdp,
+				  int index)
+{
+	gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
+	WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
+	pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
+	kunmap_px(ppgtt, pagemap);
+}
+/* Broadwell Page Directory Pointer Descriptors */
-/* Broadwell Page Directory Pointer Descriptors */
+static int gen8_write_pdp(struct drm_i915_gem_request *req,
-static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
+			  unsigned entry,
+			  dma_addr_t addr)
 			   uint64_t val)
 	struct intel_engine_cs *ring = req->ring;
 	int ret;
 	BUG_ON(entry >= 4);
-	ret = intel_ring_begin(ring, 6);
+	ret = intel_ring_begin(req, 6);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
-	intel_ring_emit(ring, (u32)(val >> 32));
+	intel_ring_emit(ring, upper_32_bits(addr));
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
-	intel_ring_emit(ring, (u32)(val));
+	intel_ring_emit(ring, lower_32_bits(addr));
 	intel_ring_advance(ring);
 	return 0;
 }
-static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  struct intel_engine_cs *ring)
 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
-	int i, ret;
+				 struct drm_i915_gem_request *req)
+{
-	/* bit of a hack to find the actual last used pd */
+	int i, ret;
 	int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
+	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
+		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
+		ret = gen8_write_pdp(req, i, pd_daddr);
+		if (ret)
+			return ret;
+	}
-	for (i = used_pd - 1; i >= 0; i--) {
+	return 0;
 		dma_addr_t addr = ppgtt->pd_dma_addr[i];
-		ret = gen8_write_pdp(ring, i, addr);
-			if (ret)
+static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			return ret;
+			      struct drm_i915_gem_request *req)
+{
+	return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
-	return 0;
+}
-}
+static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
-static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
+				       struct i915_page_directory_pointer *pdp,
-				   uint64_t start,
+				       uint64_t start,
-				   uint64_t length,
+				       uint64_t length,
-				   bool use_scratch)
+				       gen8_pte_t scratch_pte)
+{
+	struct i915_hw_ppgtt *ppgtt =
-	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	gen8_pte_t *pt_vaddr;
+	unsigned pdpe = gen8_pdpe_index(start);
+	unsigned pde = gen8_pde_index(start);
+	unsigned pte = gen8_pte_index(start);
+	unsigned num_entries = length >> PAGE_SHIFT;
+	unsigned last_pte, i;
+	if (WARN_ON(!pdp))
+		return;
+	while (num_entries) {
+		struct i915_page_directory *pd;
+		struct i915_page_table *pt;
 		container_of(vm, struct i915_hw_ppgtt, base);
-	gen8_gtt_pte_t *pt_vaddr, scratch_pte;
+		if (WARN_ON(!pdp->page_directory[pdpe]))
-	unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
+			break;
-	unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
-	unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
+		pd = pdp->page_directory[pdpe];
 	unsigned num_entries = length >> PAGE_SHIFT;
-	unsigned last_pte, i;
+		if (WARN_ON(!pd->page_table[pde]))
 			break;
-    scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
-                      I915_CACHE_LLC, use_scratch);
-	while (num_entries) {
+		pt = pd->page_table[pde];
-		struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
+		if (WARN_ON(!px_page(pt)))
+			break;
 		last_pte = pte + num_entries;
-		if (last_pte > GEN8_PTES_PER_PAGE)
+		last_pte = pte + num_entries;
-			last_pte = GEN8_PTES_PER_PAGE;
+		if (last_pte > GEN8_PTES)
 			last_pte = GEN8_PTES;
-		pt_vaddr = kmap_atomic(page_table);
-		for (i = pte; i < last_pte; i++) {
+		pt_vaddr = kmap_px(pt);
-			pt_vaddr[i] = scratch_pte;
+		for (i = pte; i < last_pte; i++) {
-			num_entries--;
+			pt_vaddr[i] = scratch_pte;
 			num_entries--;
+		}
-		if (!HAS_LLC(ppgtt->base.dev))
-			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
-		kunmap_atomic(pt_vaddr);
-		pte = 0;
+		kunmap_px(ppgtt, pt);
+		pte = 0;
-		if (++pde == GEN8_PDES_PER_PAGE) {
+		if (++pde == I915_PDES) {
+			if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
+				break;
+			pde = 0;
-			pdpe++;
+		}
-			pde = 0;
+	}
+}
-		}
+static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
+				   uint64_t start,
+				   uint64_t length,
+				   bool use_scratch)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
+						 I915_CACHE_LLC, use_scratch);
+	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
+		gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
+					   scratch_pte);
+	} else {
+		uint64_t templ4, pml4e;
+		struct i915_page_directory_pointer *pdp;
+		gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
+			gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
-	}
+						   scratch_pte);
+		}
-}
+	}
+}
 static void
-static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
+gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
-				      struct sg_table *pages,
+			      struct i915_page_directory_pointer *pdp,
-				      uint64_t start,
+			      struct sg_page_iter *sg_iter,
-				      enum i915_cache_level cache_level, u32 unused)
-{
-	struct i915_hw_ppgtt *ppgtt =
+			      uint64_t start,
-		container_of(vm, struct i915_hw_ppgtt, base);
+			      enum i915_cache_level cache_level)
-	gen8_gtt_pte_t *pt_vaddr;
+{
+	struct i915_hw_ppgtt *ppgtt =
-	unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
+		container_of(vm, struct i915_hw_ppgtt, base);
-	unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
+	gen8_pte_t *pt_vaddr;
-	unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
+	unsigned pdpe = gen8_pdpe_index(start);
-	struct sg_page_iter sg_iter;
+	unsigned pde = gen8_pde_index(start);
 	unsigned pte = gen8_pte_index(start);
 	pt_vaddr = NULL;
+	pt_vaddr = NULL;
-	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
+	while (__sg_page_iter_next(sg_iter)) {
+		if (pt_vaddr == NULL) {
+			struct i915_page_directory *pd = pdp->page_directory[pdpe];
+			struct i915_page_table *pt = pd->page_table[pde];
+			pt_vaddr = kmap_px(pt);
+		}
+		pt_vaddr[pte] =
+			gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
+					cache_level, true);
+		if (++pte == GEN8_PTES) {
+			kunmap_px(ppgtt, pt_vaddr);
+			pt_vaddr = NULL;
+			if (++pde == I915_PDES) {
+				if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
+					break;
+				pde = 0;
+			}
+			pte = 0;
-		if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
+		}
-			break;
+	}
+	if (pt_vaddr)
+		kunmap_px(ppgtt, pt_vaddr);
+}
+static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 				      struct sg_table *pages,
-		if (pt_vaddr == NULL)
+				      uint64_t start,
-			pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
+				      enum i915_cache_level cache_level,
+				      u32 unused)
+{
-		pt_vaddr[pte] =
+	struct i915_hw_ppgtt *ppgtt =
-			gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
+		container_of(vm, struct i915_hw_ppgtt, base);
-					cache_level, true);
+	struct sg_page_iter sg_iter;
-		if (++pte == GEN8_PTES_PER_PAGE) {
-			if (!HAS_LLC(ppgtt->base.dev))
+	__sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
+	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
-				drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
+		gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
+					      cache_level);
+	} else {
-			kunmap_atomic(pt_vaddr);
+		struct i915_page_directory_pointer *pdp;
-			pt_vaddr = NULL;
+		uint64_t templ4, pml4e;
-			if (++pde == GEN8_PDES_PER_PAGE) {
+		uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
+		gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
+			gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
+						      start, cache_level);
+		}
+	}
+}
+static void gen8_free_page_tables(struct drm_device *dev,
+				  struct i915_page_directory *pd)
+{
+	int i;
+	if (!px_page(pd))
+		return;
+	for_each_set_bit(i, pd->used_pdes, I915_PDES) {
+		if (WARN_ON(!pd->page_table[i]))
+			continue;
+		free_pt(dev, pd->page_table[i]);
+		pd->page_table[i] = NULL;
+	}
+}
+static int gen8_init_scratch(struct i915_address_space *vm)
+{
+	struct drm_device *dev = vm->dev;
+	vm->scratch_page = alloc_scratch_page(dev);
+	if (IS_ERR(vm->scratch_page))
+		return PTR_ERR(vm->scratch_page);
+	vm->scratch_pt = alloc_pt(dev);
+	if (IS_ERR(vm->scratch_pt)) {
+		free_scratch_page(dev, vm->scratch_page);
+		return PTR_ERR(vm->scratch_pt);
+	}
+	vm->scratch_pd = alloc_pd(dev);
+	if (IS_ERR(vm->scratch_pd)) {
+		free_pt(dev, vm->scratch_pt);
+		free_scratch_page(dev, vm->scratch_page);
-				pdpe++;
+		return PTR_ERR(vm->scratch_pd);
+	}
+	if (USES_FULL_48BIT_PPGTT(dev)) {
+		vm->scratch_pdp = alloc_pdp(dev);
+		if (IS_ERR(vm->scratch_pdp)) {
+			free_pd(dev, vm->scratch_pd);
+			free_pt(dev, vm->scratch_pt);
+			free_scratch_page(dev, vm->scratch_page);
+			return PTR_ERR(vm->scratch_pdp);
-				pde = 0;
+		}
-			}
+	}
-			pte = 0;
+	gen8_initialize_pt(vm, vm->scratch_pt);
+	gen8_initialize_pd(vm, vm->scratch_pd);
+	if (USES_FULL_48BIT_PPGTT(dev))
+		gen8_initialize_pdp(vm, vm->scratch_pdp);
+	return 0;
+}
+static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
+{
-		}
+	enum vgt_g2v_type msg;
+	struct drm_device *dev = ppgtt->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned int offset = vgtif_reg(pdp0_lo);
+	int i;
+	if (USES_FULL_48BIT_PPGTT(dev)) {
+		u64 daddr = px_dma(&ppgtt->pml4);
+		I915_WRITE(offset, lower_32_bits(daddr));
+		I915_WRITE(offset + 4, upper_32_bits(daddr));
-	if (pt_vaddr) {
+		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
-		if (!HAS_LLC(ppgtt->base.dev))
+				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
-			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
+	} else {
+		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
-		kunmap_atomic(pt_vaddr);
+			u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
-	}
-}
+			I915_WRITE(offset, lower_32_bits(daddr));
-static void gen8_free_page_tables(struct page **pt_pages)
-{
-	int i;
+			I915_WRITE(offset + 4, upper_32_bits(daddr));
-	if (pt_pages == NULL)
+			offset += 8;
-		return;
+		}
-//   for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
-//       if (pt_pages[i])
+		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
-//           __free_pages(pt_pages[i], 0);
-}
 				VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
+	}
+	I915_WRITE(vgtif_reg(g2v_notify), msg);
+	return 0;
+}
+static void gen8_free_scratch(struct i915_address_space *vm)
+{
+	struct drm_device *dev = vm->dev;
 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
+	if (USES_FULL_48BIT_PPGTT(dev))
+		free_pdp(dev, vm->scratch_pdp);
 	free_pd(dev, vm->scratch_pd);
-	int i;
+	free_pt(dev, vm->scratch_pt);
 	free_scratch_page(dev, vm->scratch_page);
 	for (i = 0; i < ppgtt->num_pd_pages; i++) {
 		gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
+static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
-		kfree(ppgtt->gen8_pt_pages[i]);
+				    struct i915_page_directory_pointer *pdp)
+{
+	int i;
+	for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
-		kfree(ppgtt->gen8_pt_dma_addr[i]);
+		if (WARN_ON(!pdp->page_directory[i]))
+			continue;
 		gen8_free_page_tables(dev, pdp->page_directory[i]);
+		free_pd(dev, pdp->page_directory[i]);
+	}
+	free_pdp(dev, pdp);
+}
+static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
+{
+	int i;
+	for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
+		if (WARN_ON(!ppgtt->pml4.pdps[i]))
+			continue;
+		gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
+	}
+	cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
+}
+static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
+{
+	struct i915_hw_ppgtt *ppgtt =
-//	__free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
+		container_of(vm, struct i915_hw_ppgtt, base);
-}
+	if (intel_vgpu_active(vm->dev))
+		gen8_ppgtt_notify_vgt(ppgtt, false);
+	if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
+		gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
+	else
+		gen8_ppgtt_cleanup_4lvl(ppgtt);
+	gen8_free_scratch(vm);
+}
-static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
+/**
-{
+ * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
-	struct pci_dev *hwdev = ppgtt->base.dev->pdev;
+ * @vm:	Master vm structure.
-	int i, j;
+ * @pd:	Page directory for this address range.
+ * @start:	Starting virtual address to begin allocations.
-	for (i = 0; i < ppgtt->num_pd_pages; i++) {
+ * @length:	Size of the allocations.
-		/* TODO: In the future we'll support sparse mappings, so this
+ * @new_pts:	Bitmap set by function with new allocations. Likely used by the
-		 * will have to change. */
+ *		caller to free on error.
-		if (!ppgtt->pd_dma_addr[i])
+ *
-			continue;
+ * Allocate the required number of page tables. Extremely similar to
+ * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
-		pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
+ * the page directory boundary (instead of the page directory pointer). That
+ * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
-			       PCI_DMA_BIDIRECTIONAL);
+ * possible, and likely that the caller will need to use multiple calls of this
  * function to achieve the appropriate allocation.
+ *
+ * Return: 0 if success; negative error code otherwise.
+ */
+static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
+				     struct i915_page_directory *pd,
+				     uint64_t start,
+				     uint64_t length,
+				     unsigned long *new_pts)
+{
+	struct drm_device *dev = vm->dev;
+	struct i915_page_table *pt;
+	uint64_t temp;
+	uint32_t pde;
+	gen8_for_each_pde(pt, pd, start, length, temp, pde) {
+		/* Don't reallocate page tables */
+		if (test_bit(pde, pd->used_pdes)) {
+			/* Scratch is never allocated this way */
+			WARN_ON(pt == vm->scratch_pt);
+			continue;
+		}
+		pt = alloc_pt(dev);
+		if (IS_ERR(pt))
-			for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+			goto unwind_out;
+		gen8_initialize_pt(vm, pt);
+		pd->page_table[pde] = pt;
-				dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+		__set_bit(pde, new_pts);
-				if (addr)
+		trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
+	}
-				pci_unmap_page(hwdev, addr, PAGE_SIZE,
-						       PCI_DMA_BIDIRECTIONAL);
+	return 0;
+unwind_out:
+	for_each_set_bit(pde, new_pts, I915_PDES)
+		free_pt(dev, pd->page_table[pde]);
-		}
-	}
+	return -ENOMEM;
+}
-}
+/**
+ * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
-static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
+ * @vm:	Master vm structure.
-{
-	struct i915_hw_ppgtt *ppgtt =
-		container_of(vm, struct i915_hw_ppgtt, base);
+ * @pdp:	Page directory pointer for this address range.
+ * @start:	Starting virtual address to begin allocations.
-	gen8_ppgtt_unmap_pages(ppgtt);
-	gen8_ppgtt_free(ppgtt);
+ * @length:	Size of the allocations.
-}
+ * @new_pds:	Bitmap set by function with new allocations. Likely used by the
+ *		caller to free on error.
+ *
-static struct page **__gen8_alloc_page_tables(void)
+ * Allocate the required number of page directories starting at the pde index of
-{
-	struct page **pt_pages;
+ * @start, and ending at the pde index @start + @length. This function will skip
-	int i;
+ * over already allocated page directories within the range, and only allocate
-	pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
+ * new ones, setting the appropriate pointer within the pdp as well as the
-	if (!pt_pages)
+ * correct position in the bitmap @new_pds.
+ *
+ * The function will only allocate the pages within the range for a give page
+ * directory pointer. In other words, if @start + @length straddles a virtually
+ * addressed PDP boundary (512GB for 4k pages), there will be more allocations
+ * required by the caller, This is not currently possible, and the BUG in the
+ * code will prevent it.
+ *
+ * Return: 0 if success; negative error code otherwise.
+ */
+static int
+gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
+				  struct i915_page_directory_pointer *pdp,
+				  uint64_t start,
+				  uint64_t length,
+				  unsigned long *new_pds)
+{
+	struct drm_device *dev = vm->dev;
-		return ERR_PTR(-ENOMEM);
+	struct i915_page_directory *pd;
+	uint64_t temp;
+	uint32_t pdpe;
+	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
 	WARN_ON(!bitmap_empty(new_pds, pdpes));
+	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
-	for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
+		if (test_bit(pdpe, pdp->used_pdpes))
+			continue;
+		pd = alloc_pd(dev);
+		if (IS_ERR(pd))
+			goto unwind_out;
+		gen8_initialize_pd(vm, pd);
+		pdp->page_directory[pdpe] = pd;
+		__set_bit(pdpe, new_pds);
+		trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
+	}
-		pt_pages[i] = alloc_page(GFP_KERNEL);
-		if (!pt_pages[i])
+	return 0;
-			goto bail;
-			}
+unwind_out:
+	for_each_set_bit(pdpe, new_pds, pdpes)
-	return pt_pages;
+		free_pd(dev, pdp->page_directory[pdpe]);
-bail:
+	return -ENOMEM;
+}
+/**
+ * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
+ * @vm:	Master vm structure.
+ * @pml4:	Page map level 4 for this address range.
-	gen8_free_page_tables(pt_pages);
+ * @start:	Starting virtual address to begin allocations.
+ * @length:	Size of the allocations.
+ * @new_pdps:	Bitmap set by function with new allocations. Likely used by the
+ *		caller to free on error.
+ *
+ * Allocate the required number of page directory pointers. Extremely similar to
+ * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
+ * The main difference is here we are limited by the pml4 boundary (instead of
+ * the page directory pointer).
+ *
+ * Return: 0 if success; negative error code otherwise.
+ */
-	kfree(pt_pages);
+static int
+gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
-	return ERR_PTR(-ENOMEM);
+				  struct i915_pml4 *pml4,
 				  uint64_t start,
+				  uint64_t length,
+				  unsigned long *new_pdps)
+{
+	struct drm_device *dev = vm->dev;
-static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
+	struct i915_page_directory_pointer *pdp;
-					   const int max_pdp)
+	uint64_t temp;
-{
+	uint32_t pml4e;
-	struct page **pt_pages[GEN8_LEGACY_PDPS];
+	WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
+	gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
+		if (!test_bit(pml4e, pml4->used_pml4es)) {
+			pdp = alloc_pdp(dev);
-	int i, ret;
+			if (IS_ERR(pdp))
+				goto unwind_out;
+			gen8_initialize_pdp(vm, pdp);
+			pml4->pdps[pml4e] = pdp;
+			__set_bit(pml4e, new_pdps);
+			trace_i915_page_directory_pointer_entry_alloc(vm,
+								      pml4e,
+								      start,
+								      GEN8_PML4E_SHIFT);
+		}
+	}
+	return 0;
 unwind_out:
-	for (i = 0; i < max_pdp; i++) {
+	for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
+		free_pdp(dev, pml4->pdps[pml4e]);
-		pt_pages[i] = __gen8_alloc_page_tables();
+	return -ENOMEM;
 		if (IS_ERR(pt_pages[i])) {
+static void
+free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
+{
+	kfree(new_pts);
+	kfree(new_pds);
+}
+/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
+ * of these are based on the number of PDPEs in the system.
-			ret = PTR_ERR(pt_pages[i]);
+ */
+static
+int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
+					 unsigned long **new_pts,
+					 uint32_t pdpes)
+{
+	unsigned long *pds;
+	unsigned long *pts;
+	pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
-			goto unwind_out;
+	if (!pds)
 		return -ENOMEM;
+	pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
+		      GFP_TEMPORARY);
+	if (!pts)
-	/* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
+		goto err_out;
-	 * "atomic" - for cleanup purposes.
-	 */
+	*new_pds = pds;
-	for (i = 0; i < max_pdp; i++)
+	*new_pts = pts;
-		ppgtt->gen8_pt_pages[i] = pt_pages[i];
+	return 0;
-	return 0;
+err_out:
 	free_gen8_temp_bitmaps(pds, pts);
+	return -ENOMEM;
+}
+/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
+ * the page table structures, we mark them dirty so that
+ * context switching/execlist queuing code takes extra steps
+ * to ensure that tlbs are flushed.
+ */
+static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
+{
+	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
+}
+static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
+				    struct i915_page_directory_pointer *pdp,
+				    uint64_t start,
+				    uint64_t length)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	unsigned long *new_page_dirs, *new_page_tables;
+	struct drm_device *dev = vm->dev;
+	struct i915_page_directory *pd;
+	const uint64_t orig_start = start;
+	const uint64_t orig_length = length;
+	uint64_t temp;
+	uint32_t pdpe;
+	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
+	int ret;
+	/* Wrap is never okay since we can only represent 48b, and we don't
+	 * actually use the other side of the canonical address space.
+	 */
+	if (WARN_ON(start + length < start))
+		return -ENODEV;
+	if (WARN_ON(start + length > vm->total))
+		return -ENODEV;
+	ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
+	if (ret)
+		return ret;
+	/* Do the allocations first so we can easily bail out */
+	ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
+						new_page_dirs);
+	if (ret) {
+		free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
+		return ret;
+	}
-unwind_out:
+	/* For every page directory referenced, allocate page tables */
+	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
+		ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
+						new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
+		if (ret)
+			goto err_out;
+	}
+	start = orig_start;
+	length = orig_length;
+	/* Allocations have completed successfully, so set the bitmaps, and do
+	 * the mappings. */
-	while (i--) {
+	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
-		gen8_free_page_tables(pt_pages[i]);
+		gen8_pde_t *const page_directory = kmap_px(pd);
-		kfree(pt_pages[i]);
+		struct i915_page_table *pt;
+		uint64_t pd_len = length;
+		uint64_t pd_start = start;
-	}
+		uint32_t pde;
+		/* Every pd should be allocated, we just did that above. */
+		WARN_ON(!pd);
+		gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
-	return ret;
+			/* Same reasoning as pd */
-}
+			WARN_ON(!pt);
+			WARN_ON(!pd_len);
+			WARN_ON(!gen8_pte_count(pd_start, pd_len));
+			/* Set our used ptes within the page table */
+			bitmap_set(pt->used_ptes,
+				   gen8_pte_index(pd_start),
+				   gen8_pte_count(pd_start, pd_len));
-static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
+			/* Our pde is now pointing to the pagetable, pt */
+			__set_bit(pde, pd->used_pdes);
+			/* Map the PDE to the page table */
+			page_directory[pde] = gen8_pde_encode(px_dma(pt),
+							      I915_CACHE_LLC);
-{
+			trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
-	int i;
+							gen8_pte_index(start),
+							gen8_pte_count(start, length),
-	for (i = 0; i < ppgtt->num_pd_pages; i++) {
+							GEN8_PTES);
+			/* NB: We haven't yet mapped ptes to pages. At this
+			 * point we're still relying on insert_entries() */
+		}
+		kunmap_px(ppgtt, page_directory);
-		ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
+		__set_bit(pdpe, pdp->used_pdpes);
+		gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
 						     sizeof(dma_addr_t),
+	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
+	mark_tlbs_dirty(ppgtt);
+	return 0;
+err_out:
-						     GFP_KERNEL);
+	while (pdpe--) {
-		if (!ppgtt->gen8_pt_dma_addr[i])
+		for_each_set_bit(temp, new_page_tables + pdpe *
-			return -ENOMEM;
-		}
+				BITS_TO_LONGS(I915_PDES), I915_PDES)
 			free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
+	}
+	for_each_set_bit(pdpe, new_page_dirs, pdpes)
+		free_pd(dev, pdp->page_directory[pdpe]);
+	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
+	mark_tlbs_dirty(ppgtt);
+	return ret;
+}
+static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
+				    struct i915_pml4 *pml4,
+				    uint64_t start,
+				    uint64_t length)
+{
+	DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
-	return 0;
+	struct i915_hw_ppgtt *ppgtt =
+			container_of(vm, struct i915_hw_ppgtt, base);
+	struct i915_page_directory_pointer *pdp;
-}
+	uint64_t temp, pml4e;
+	int ret = 0;
+	/* Do the pml4 allocations first, so we don't need to track the newly
+	 * allocated tables below the pdp */
+	bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
+	/* The pagedirectory and pagetable allocations are done in the shared 3
+	 * and 4 level code. Just allocate the pdps.
+	 */
+	ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
+						new_pdps);
+	if (ret)
+		return ret;
+	WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
+	     "The allocation has spanned more than 512GB. "
+	     "It is highly likely this is incorrect.");
+	gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
+		WARN_ON(!pdp);
+		ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
+		if (ret)
+			goto err_out;
+		gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
+	}
+	bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
+		  GEN8_PML4ES_PER_PML4);
+	return 0;
+err_out:
+	for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
+		gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
+	return ret;
+}
+static int gen8_alloc_va_range(struct i915_address_space *vm,
+			       uint64_t start, uint64_t length)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
+	if (USES_FULL_48BIT_PPGTT(vm->dev))
+		return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
+	else
+		return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
+}
+static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
+			  uint64_t start, uint64_t length,
+			  gen8_pte_t scratch_pte,
+			  struct seq_file *m)
+{
+	struct i915_page_directory *pd;
+	uint64_t temp;
+	uint32_t pdpe;
+	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
+		struct i915_page_table *pt;
+		uint64_t pd_len = length;
+		uint64_t pd_start = start;
+		uint32_t pde;
+		if (!test_bit(pdpe, pdp->used_pdpes))
+			continue;
+		seq_printf(m, "\tPDPE #%d\n", pdpe);
+		gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
+			uint32_t  pte;
+			gen8_pte_t *pt_vaddr;
+			if (!test_bit(pde, pd->used_pdes))
 				continue;
-static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
-						const int max_pdp)
-{
+			pt_vaddr = kmap_px(pt);
+			for (pte = 0; pte < GEN8_PTES; pte += 4) {
-//	ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
+				uint64_t va =
-	if (!ppgtt->pd_pages)
+					(pdpe << GEN8_PDPE_SHIFT) |
-		return -ENOMEM;
+					(pde << GEN8_PDE_SHIFT) |
+					(pte << GEN8_PTE_SHIFT);
+				int i;
+				bool found = false;
+				for (i = 0; i < 4; i++)
+					if (pt_vaddr[pte + i] != scratch_pte)
+						found = true;
+				if (!found)
+					continue;
-//   ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
+				seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
-	BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
+				for (i = 0; i < 4; i++) {
+					if (pt_vaddr[pte + i] != scratch_pte)
-	return 0;
+						seq_printf(m, " %llx", pt_vaddr[pte + i]);
 					else
 						seq_puts(m, "  SCRATCH ");
 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
-			    const int max_pdp)
+				seq_puts(m, "\n");
-{
-	int ret;
 	ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
-	if (ret)
+			/* don't use kunmap_px, it could trigger
-		return ret;
+			 * an unnecessary flush.
-	ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
-	if (ret) {
+			 */
-//		__free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
-		return ret;
-	}
-	ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
+			kunmap_atomic(pt_vaddr);
+		}
 	ret = gen8_ppgtt_allocate_dma(ppgtt);
-	if (ret)
+}
+static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
-		gen8_ppgtt_free(ppgtt);
+{
+	struct i915_address_space *vm = &ppgtt->base;
+	uint64_t start = ppgtt->base.start;
+	uint64_t length = ppgtt->base.total;
+	gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
+						 I915_CACHE_LLC, true);
-	return ret;
-}
+	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 		gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
-static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
+	} else {
+		uint64_t templ4, pml4e;
+		struct i915_pml4 *pml4 = &ppgtt->pml4;
+		struct i915_page_directory_pointer *pdp;
-					     const int pd)
+		gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
-{
+			if (!test_bit(pml4e, pml4->used_pml4es))
-	dma_addr_t pd_addr;
+				continue;
-	int ret;
-	pd_addr = pci_map_page(ppgtt->base.dev->pdev,
-			       &ppgtt->pd_pages[pd], 0,
-			       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+			seq_printf(m, "    PML4E #%llu\n", pml4e);
-//   ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
-//   if (ret)
+			gen8_dump_pdp(pdp, start, length, scratch_pte, m);
-//       return ret;
+		}
-	ppgtt->pd_dma_addr[pd] = pd_addr;
+	}
-	return 0;
+}
-}
+static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
+{
-static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
+	unsigned long *new_page_dirs, *new_page_tables;
-					const int pd,
-					const int pt)
+	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
 	int ret;
-	dma_addr_t pt_addr;
-	struct page *p;
-	int ret;
-	p = ppgtt->gen8_pt_pages[pd][pt];
-	pt_addr = pci_map_page(ppgtt->base.dev->pdev,
+	/* We allocate temp bitmap for page tables for no gain
-			       p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-//   ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
+	 * but as this is for init only, lets keep the things simple
-//   if (ret)
-//       return ret;
-	ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
-	return 0;
-}
-/**
- * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
+	 */
- * with a net effect resembling a 2-level page table in normal x86 terms. Each
+	ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
- * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
- * space.
+	if (ret)
 		return ret;
  * FIXME: split allocation into smaller pieces. For now we only ever do this
- * once, but with full PPGTT, the multiple contiguous allocations will be bad.
+	/* Allocate for all pdps regardless of how the ppgtt
- * TODO: Do something with the size parameter
+	 * was defined.
- */
+	 */
+	ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
-static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
+, 1ULL << 32,
 						new_page_dirs);
+	if (!ret)
+		*ppgtt->pdp.used_pdpes = *new_page_dirs;
+	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
+	return ret;
+}
+/*
+ * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
+ * with a net effect resembling a 2-level page table in normal x86 terms. Each
+ * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
+ * space.
+ *
+ */
+static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+{
+	int ret;
+	ret = gen8_init_scratch(&ppgtt->base);
+	if (ret)
+		return ret;
+	ppgtt->base.start = 0;
+	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
+	ppgtt->base.allocate_va_range = gen8_alloc_va_range;
-	const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
+	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
+	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
+	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
+	ppgtt->base.bind_vma = ppgtt_bind_vma;
+	ppgtt->debug_dump = gen8_dump_ppgtt;
+	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
+		ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
+		if (ret)
+			goto free_scratch;
+		gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
+		ppgtt->base.total = 1ULL << 48;
+		ppgtt->switch_mm = gen8_48b_mm_switch;
+	} else {
+		ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
+		if (ret)
+			goto free_scratch;
-	const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
+		ppgtt->base.total = 1ULL << 32;
-	int i, j, ret;
+		ppgtt->switch_mm = gen8_legacy_mm_switch;
+		trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
+, 0,
+							      GEN8_PML4E_SHIFT);
-	if (size % (1<<30))
+		if (intel_vgpu_active(ppgtt->base.dev)) {
-		DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
+			ret = gen8_preallocate_top_level_pdps(ppgtt);
-	/* 1. Do all our allocations for page directories and page tables. */
+			if (ret)
-	ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
+				goto free_scratch;
-	if (ret)
+		}
 		return ret;
+	if (intel_vgpu_active(ppgtt->base.dev))
+		gen8_ppgtt_notify_vgt(ppgtt, true);
+	return 0;
+free_scratch:
+	gen8_free_scratch(&ppgtt->base);
+	return ret;
+}
+static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
+{
+	struct i915_address_space *vm = &ppgtt->base;
+	struct i915_page_table *unused;
+	gen6_pte_t scratch_pte;
-	/*
+	uint32_t pd_entry;
-	 * 2. Create DMA mappings for the page directories and page tables.
+	uint32_t  pte, pde, temp;
-	 */
+	uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
-	for (i = 0; i < max_pdp; i++) {
-		ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
+	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
-		if (ret)
+				     I915_CACHE_LLC, true, 0);
 			goto bail;
+	gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
-		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
+		u32 expected;
+		gen6_pte_t *pt_vaddr;
-			ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
+		const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
-			if (ret)
+		pd_entry = readl(ppgtt->pd_addr + pde);
-				goto bail;
+		expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 		if (pd_entry != expected)
+			seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
-	/*
+				   pde,
-	 * 3. Map all the page directory entires to point to the page tables
+				   pd_entry,
-	 * we've allocated.
+				   expected);
 		seq_printf(m, "\tPDE: %x\n", pd_entry);
 	intel_ring_advance(ring);
 	return 0;
+}
+static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
+			  struct drm_i915_gem_request *req)
+{
+	struct intel_engine_cs *ring = req->ring;
+	struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
+	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
+	return 0;
+}
 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
+			  struct drm_i915_gem_request *req)
 			  struct intel_engine_cs *ring)
 	struct intel_engine_cs *ring = req->ring;
 	int ret;
 	/* NB: TLBs must be flushed and invalidated before a switch */
-	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
-	ret = intel_ring_begin(ring, 6);
+	ret = intel_ring_begin(req, 6);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	/* XXX: RCS is the only one to auto invalidate the TLBs? */
 	if (ring->id != RCS) {
-		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 		if (ret)
 			return ret;
+	}
 	return 0;
 }
+static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
-static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
+			  struct drm_i915_gem_request *req)
 			  struct intel_engine_cs *ring)
 	struct intel_engine_cs *ring = req->ring;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
 	int j;
+	for_each_ring(ring, dev_priv, j) {
-	for_each_ring(ring, dev_priv, j) {
+		u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(ring),
-			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
+	}
+}
 				   uint64_t length,
 				   bool use_scratch)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
-	gen6_gtt_pte_t *pt_vaddr, scratch_pte;
+	gen6_pte_t *pt_vaddr, scratch_pte;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
-	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
+	unsigned act_pt = first_entry / GEN6_PTES;
-	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
+	unsigned first_pte = first_entry % GEN6_PTES;
 	unsigned last_pte, i;
+	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
-	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
+				     I915_CACHE_LLC, true, 0);
 	while (num_entries) {
-            last_pte = first_pte + num_entries;
+		last_pte = first_pte + num_entries;
-            if (last_pte > I915_PPGTT_PT_ENTRIES)
+		if (last_pte > GEN6_PTES)
-                last_pte = I915_PPGTT_PT_ENTRIES;
+			last_pte = GEN6_PTES;
-		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
+		pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
-            for (i = first_pte; i < last_pte; i++)
+		for (i = first_pte; i < last_pte; i++)
-                pt_vaddr[i] = scratch_pte;
+			pt_vaddr[i] = scratch_pte;
 				      uint64_t start,
 				      enum i915_cache_level cache_level, u32 flags)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
-	gen6_gtt_pte_t *pt_vaddr;
+	gen6_pte_t *pt_vaddr;
 	unsigned first_entry = start >> PAGE_SHIFT;
-	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
+	unsigned act_pt = first_entry / GEN6_PTES;
-	unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
+	unsigned act_pte = first_entry % GEN6_PTES;
 	struct sg_page_iter sg_iter;
 	pt_vaddr = NULL;
 	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 		if (pt_vaddr == NULL)
-			pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
+			pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
 		pt_vaddr[act_pte] =
 			vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
 				       cache_level, true, flags);
-		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
+		if (++act_pte == GEN6_PTES) {
-			kunmap_atomic(pt_vaddr);
+			kunmap_px(ppgtt, pt_vaddr);
 			pt_vaddr = NULL;
 			act_pt++;
 			act_pte = 0;
-			}
+		}
+	}
 	if (pt_vaddr)
+		kunmap_px(ppgtt, pt_vaddr);
 		kunmap_atomic(pt_vaddr);
+static int gen6_alloc_va_range(struct i915_address_space *vm,
+			       uint64_t start_in, uint64_t length_in)
+{
+	DECLARE_BITMAP(new_page_tables, I915_PDES);
+	struct drm_device *dev = vm->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_hw_ppgtt *ppgtt =
-}
+				container_of(vm, struct i915_hw_ppgtt, base);
+	struct i915_page_table *pt;
+	uint32_t start, length, start_save, length_save;
+	uint32_t pde, temp;
+	int ret;
+	if (WARN_ON(start_in + length_in > ppgtt->base.total))
+		return -ENODEV;
+	start = start_save = start_in;
+	length = length_save = length_in;
+	bitmap_zero(new_page_tables, I915_PDES);
+	/* The allocation is done in two stages so that we can bail out with
+	 * minimal amount of pain. The first stage finds new page tables that
+	 * need allocation. The second stage marks use ptes within the page
+	 * tables.
+	 */
+	gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
+		if (pt != vm->scratch_pt) {
+			WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
+			continue;
+		}
+		/* We've already allocated a page table */
+		WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
+		pt = alloc_pt(dev);
+		if (IS_ERR(pt)) {
-static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
+			ret = PTR_ERR(pt);
-{
+			goto unwind_out;
-	int i;
+		}
-	if (ppgtt->pt_dma_addr) {
+		gen6_initialize_pt(vm, pt);
+		ppgtt->pd.page_table[pde] = pt;
+		__set_bit(pde, new_page_tables);
+		trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
+	}
+	start = start_save;
+	length = length_save;
+	gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
+		DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
+		bitmap_zero(tmp_bitmap, GEN6_PTES);
+		bitmap_set(tmp_bitmap, gen6_pte_index(start),
+			   gen6_pte_count(start, length));
+		if (__test_and_clear_bit(pde, new_page_tables))
+			gen6_write_pde(&ppgtt->pd, pde, pt);
+		trace_i915_page_table_entry_map(vm, pde, pt,
-		for (i = 0; i < ppgtt->num_pd_entries; i++)
+					 gen6_pte_index(start),
+					 gen6_pte_count(start, length),
+					 GEN6_PTES);
+		bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
+				GEN6_PTES);
+	}
+	WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
+	/* Make sure write is complete before other code can use this page
+	 * table. Also require for WC mapped PTEs */
+	readl(dev_priv->gtt.gsm);
+	mark_tlbs_dirty(ppgtt);
+	return 0;
+unwind_out:
+	for_each_set_bit(pde, new_page_tables, I915_PDES) {
+		struct i915_page_table *pt = ppgtt->pd.page_table[pde];
+		ppgtt->pd.page_table[pde] = vm->scratch_pt;
+		free_pt(vm->dev, pt);
-			pci_unmap_page(ppgtt->base.dev->pdev,
+	}
 				       ppgtt->pt_dma_addr[i],
+	mark_tlbs_dirty(ppgtt);
+	return ret;
+}
+static int gen6_init_scratch(struct i915_address_space *vm)
+{
+	struct drm_device *dev = vm->dev;
+	vm->scratch_page = alloc_scratch_page(dev);
+	if (IS_ERR(vm->scratch_page))
-, PCI_DMA_BIDIRECTIONAL);
+		return PTR_ERR(vm->scratch_page);
+	vm->scratch_pt = alloc_pt(dev);
+	if (IS_ERR(vm->scratch_pt)) {
+		free_scratch_page(dev, vm->scratch_page);
+		return PTR_ERR(vm->scratch_pt);
 	}
-}
+	gen6_initialize_pt(vm, vm->scratch_pt);
+	return 0;
-static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
+}
-	int i;
+static void gen6_free_scratch(struct i915_address_space *vm)
+{
-	kfree(ppgtt->pt_dma_addr);
+	struct drm_device *dev = vm->dev;
 	for (i = 0; i < ppgtt->num_pd_entries; i++)
+	free_pt(dev, vm->scratch_pt);
+	free_scratch_page(dev, vm->scratch_page);
 		__free_page(ppgtt->pt_pages[i]);
-	kfree(ppgtt->pt_pages);
+static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
-}
+	struct i915_page_table *pt;
 	uint32_t pde;
 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 	drm_mm_remove_node(&ppgtt->node);
-	struct i915_hw_ppgtt *ppgtt =
+	gen6_for_all_pdes(pt, ppgtt, pde) {
-		container_of(vm, struct i915_hw_ppgtt, base);
+		if (pt != vm->scratch_pt)
 			free_pt(ppgtt->base.dev, pt);
 	drm_mm_remove_node(&ppgtt->node);
-	gen6_ppgtt_unmap_pages(ppgtt);
+	gen6_free_scratch(vm);
 	gen6_ppgtt_free(ppgtt);
 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
+{
+	struct i915_address_space *vm = &ppgtt->base;
+	struct drm_device *dev = ppgtt->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	bool retried = false;
-static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
+	int ret;
-	struct drm_device *dev = ppgtt->base.dev;
+	/* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	 * allocator works in address space sizes, so it's multiplied by page
-	bool retried = false;
+	 * size. We allocate at the top of the GTT to avoid fragmentation.
 					       GEN6_PD_SIZE, GEN6_PD_ALIGN,
 					       I915_CACHE_NONE,
 , dev_priv->gtt.base.total,
 );
 		if (ret)
-			return ret;
+			goto err_out;
 		retried = true;
 		goto alloc;
-	}
-	if (ppgtt->node.start < dev_priv->gtt.mappable_end)
-		DRM_DEBUG("Forced to use aperture for PDEs\n");
+	}
-	ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
-	return ret;
-}
-static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
-{
-	int i;
-	ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
-				  GFP_KERNEL);
+	if (ret)
-	if (!ppgtt->pt_pages)
+		goto err_out;
-		return -ENOMEM;
-	for (i = 0; i < ppgtt->num_pd_entries; i++) {
-		ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
-		if (!ppgtt->pt_pages[i]) {
 			gen6_ppgtt_free(ppgtt);
-			return -ENOMEM;
-		}
-	}
-	return 0;
-}
+	if (ppgtt->node.start < dev_priv->gtt.mappable_end)
-static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
+		DRM_DEBUG("Forced to use aperture for PDEs\n");
-{
-	int ret;
-	ret = gen6_ppgtt_allocate_page_directories(ppgtt);
-	if (ret)
-		return ret;
-	ret = gen6_ppgtt_allocate_page_tables(ppgtt);
-	if (ret) {
-		drm_mm_remove_node(&ppgtt->node);
-		return ret;
-	}
 	ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
+	return 0;
-				     GFP_KERNEL);
+err_out:
-	if (!ppgtt->pt_dma_addr) {
+	gen6_free_scratch(vm);
-		drm_mm_remove_node(&ppgtt->node);
+	return ret;
+}
 		gen6_ppgtt_free(ppgtt);
-		return -ENOMEM;
+static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
-	}
-	return 0;
-}
+{
+	return gen6_ppgtt_allocate_page_directories(ppgtt);
-static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
-{
-	struct drm_device *dev = ppgtt->base.dev;
-	int i;
-	for (i = 0; i < ppgtt->num_pd_entries; i++) {
-		dma_addr_t pt_addr;
+}
-		pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
-				       PCI_DMA_BIDIRECTIONAL);
 //       if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
-//           gen6_ppgtt_unmap_pages(ppgtt);
+static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
-//           return -EIO;
+				  uint64_t start, uint64_t length)
 //       }
 	} else if (IS_GEN7(dev)) {
 		ppgtt->switch_mm = gen7_mm_switch;
 	} else
 		BUG();
+	if (intel_vgpu_active(dev))
+		ppgtt->switch_mm = vgpu_mm_switch;
 	ret = gen6_ppgtt_alloc(ppgtt);
 	if (ret)
 		return ret;
-	ret = gen6_ppgtt_setup_page_tables(ppgtt);
-	if (ret) {
-		gen6_ppgtt_free(ppgtt);
-		return ret;
 	ppgtt->base.allocate_va_range = gen6_alloc_va_range;
+	ppgtt->base.clear_range = gen6_ppgtt_clear_range;
+	ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
-	ppgtt->base.clear_range = gen6_ppgtt_clear_range;
+	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
-	ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
+	ppgtt->base.bind_vma = ppgtt_bind_vma;
 	ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.start = 0;
+	ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
+	ppgtt->debug_dump = gen6_dump_ppgtt;
-	ppgtt->base.total =  ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
+	ppgtt->pd.base.ggtt_offset =
-//	ppgtt->debug_dump = gen6_dump_ppgtt;
+		ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
+	ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
+		ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
-	ppgtt->pd_offset =
-		ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
+	gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
-	ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
 	gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
-	DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
-			 ppgtt->node.size >> 20,
+	DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
-			 ppgtt->node.start / PAGE_SIZE);
+			 ppgtt->node.size >> 20,
 			 ppgtt->node.start / PAGE_SIZE);
 	gen6_write_pdes(ppgtt);
-	DRM_DEBUG("Adding PPGTT at offset %x\n",
-		  ppgtt->pd_offset << 10);
 	DRM_DEBUG("Adding PPGTT at offset %x\n",
-	return 0;
 		  ppgtt->pd.base.ggtt_offset << 10);
-static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	return 0;
+}
+static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+{
+	ppgtt->base.dev = dev;
+	if (INTEL_INFO(dev)->gen < 8)
+		return gen6_ppgtt_init(ppgtt);
+	else
+		return gen8_ppgtt_init(ppgtt);
+}
 	ppgtt->base.dev = dev;
+static void i915_address_space_init(struct i915_address_space *vm,
-	ppgtt->base.scratch = dev_priv->gtt.base.scratch;
+				    struct drm_i915_private *dev_priv)
+{
-	if (INTEL_INFO(dev)->gen < 8)
+	drm_mm_init(&vm->mm, vm->start, vm->total);
-		return gen6_ppgtt_init(ppgtt);
+	vm->dev = dev_priv->dev;
-	else if (IS_GEN8(dev) || IS_GEN9(dev))
+	INIT_LIST_HEAD(&vm->active_list);
-		return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
+	INIT_LIST_HEAD(&vm->inactive_list);
-	else
+	list_add_tail(&vm->global_link, &dev_priv->vm_list);
-		BUG();
-}
-int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+}
-	struct drm_i915_private *dev_priv = dev->dev_private;
+int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 	int ret = 0;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	ret = __hw_ppgtt_init(dev, ppgtt);
+	int ret = 0;
-	if (ret == 0) {
-		kref_init(&ppgtt->ref);
-		drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
-			    ppgtt->base.total);
-		i915_init_vm(dev_priv, &ppgtt->base);
 	ret = __hw_ppgtt_init(dev, ppgtt);
-	return ret;
+	if (ret == 0) {
 		kref_init(&ppgtt->ref);
 		i915_address_space_init(&ppgtt->base, dev_priv);
 	else if (IS_GEN7(dev))
 		gen7_ppgtt_enable(dev);
 	else if (INTEL_INFO(dev)->gen >= 8)
 		gen8_ppgtt_enable(dev);
 	else
-		WARN_ON(1);
+		MISSING_CASE(INTEL_INFO(dev)->gen);
-	if (ppgtt) {
-		for_each_ring(ring, dev_priv, i) {
-			ret = ppgtt->switch_mm(ppgtt, ring);
-			if (ret != 0)
-				return ret;
 	return 0;
+}
+int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
+{
+	struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
-	}
+	if (i915.enable_execlists)
+		return 0;
+	if (!ppgtt)
+		return 0;
+	return ppgtt->switch_mm(ppgtt, req);
 	return ret;
 struct i915_hw_ppgtt *
 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
+{
 	ppgtt->base.cleanup(&ppgtt->base);
 	kfree(ppgtt);
-}
-static void
-ppgtt_bind_vma(struct i915_vma *vma,
-	       enum i915_cache_level cache_level,
-	       u32 flags)
-{
-	/* Currently applicable only to VLV */
-	if (vma->obj->gt_ro)
-		flags |= PTE_READ_ONLY;
-	vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
-				cache_level, flags);
-}
-static void ppgtt_unbind_vma(struct i915_vma *vma)
-{
-	vma->vm->clear_range(vma->vm,
-			     vma->node.start,
-			     vma->obj->base.size,
-				true);
+}
 extern int intel_iommu_gfx_mapped;
 /* Certain Gen5 chipsets require require idling the GPU before
  * unmapping anything from the GTT when VT-d is enabled.
  */
-static inline bool needs_idle_maps(struct drm_device *dev)
+static bool needs_idle_maps(struct drm_device *dev)
+{
 #ifdef CONFIG_INTEL_IOMMU
 	/* Query intel_iommu to see if we need the workaround. Presumably that
 				       true);
 	i915_ggtt_flush(dev_priv);
-}
-void i915_gem_restore_gtt_mappings(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_gem_object *obj;
-	struct i915_address_space *vm;
-	i915_check_and_clear_faults(dev);
-	/* First fill our portion of the GTT with scratch pages */
-	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
-				       dev_priv->gtt.base.start,
-				       dev_priv->gtt.base.total,
-				       true);
-	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
-		struct i915_vma *vma = i915_gem_obj_to_vma(obj,
-							   &dev_priv->gtt.base);
-		if (!vma)
-			continue;
-		i915_gem_clflush_object(obj, obj->pin_display);
-		/* The bind_vma code tries to be smart about tracking mappings.
-		 * Unfortunately above, we've just wiped out the mappings
-		 * without telling our object about it. So we need to fake it.
-		 */
-		vma->bound &= ~GLOBAL_BIND;
-		vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
-	}
-	if (INTEL_INFO(dev)->gen >= 8) {
-		if (IS_CHERRYVIEW(dev))
-			chv_setup_private_ppat(dev_priv);
-		else
-			bdw_setup_private_ppat(dev_priv);
-		return;
-	}
-	list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
-		/* TODO: Perhaps it shouldn't be gen6 specific */
-		if (i915_is_ggtt(vm)) {
-			if (dev_priv->mm.aliasing_ppgtt)
-				gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
-			continue;
-		}
-		gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
-	}
-	i915_ggtt_flush(dev_priv);
+}
-int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
-{
-	if (obj->has_dma_mapping)
-		return 0;
+int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
+{
 	if (!dma_map_sg(&obj->base.dev->pdev->dev,
 			obj->pages->sgl, obj->pages->nents,
 			PCI_DMA_BIDIRECTIONAL))
 		return -ENOSPC;
 	return 0;
+}
-static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
 				     uint64_t start,
 				     enum i915_cache_level level, u32 unused)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
-	gen8_gtt_pte_t __iomem *gtt_entries =
+	gen8_pte_t __iomem *gtt_entries =
-		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
+		(gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 	int i = 0;
 	struct sg_page_iter sg_iter;
 	dma_addr_t addr = 0; /* shut up gcc */
 				     uint64_t start,
 				     enum i915_cache_level level, u32 flags)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
-	gen6_gtt_pte_t __iomem *gtt_entries =
+	gen6_pte_t __iomem *gtt_entries =
-		(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
+		(gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 	int i = 0;
 	struct sg_page_iter sg_iter;
 	dma_addr_t addr = 0;
 				  bool use_scratch)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
-	gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
+	gen8_pte_t scratch_pte, __iomem *gtt_base =
-		(gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
+		(gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 	int i;
 	if (WARN(num_entries > max_entries,
 		 "First entry = %d; Num entries = %d (max=%d)\n",
 		 first_entry, num_entries, max_entries))
 		num_entries = max_entries;
-	scratch_pte = gen8_pte_encode(vm->scratch.addr,
+	scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 				      I915_CACHE_LLC,
 				      use_scratch);
 	for (i = 0; i < num_entries; i++)
 				  bool use_scratch)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
-	gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
+	gen6_pte_t scratch_pte, __iomem *gtt_base =
-		(gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
+		(gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 	int i;
 	if (WARN(num_entries > max_entries,
 		 "First entry = %d; Num entries = %d (max=%d)\n",
 		 first_entry, num_entries, max_entries))
-        num_entries = max_entries;
+		num_entries = max_entries;
 	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
-	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
+				     I915_CACHE_LLC, use_scratch, 0);
 	for (i = 0; i < num_entries; i++)
-		iowrite32(scratch_pte, >t_base[i]);
-	readl(gtt_base);
+		iowrite32(scratch_pte, >t_base[i]);
-}
+	readl(gtt_base);
+}
 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
-static void i915_ggtt_bind_vma(struct i915_vma *vma,
-			       enum i915_cache_level cache_level,
+				     struct sg_table *pages,
-			       u32 unused)
+				     uint64_t start,
-{
-	const unsigned long entry = vma->node.start >> PAGE_SHIFT;
+				     enum i915_cache_level cache_level, u32 unused)
-	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+{
-		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 	BUG_ON(!i915_is_ggtt(vma->vm));
-	intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
+	intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
 	intel_gtt_clear_range(first_entry, num_entries);
+}
+static int ggtt_bind_vma(struct i915_vma *vma,
+			 enum i915_cache_level cache_level,
-static void i915_ggtt_unbind_vma(struct i915_vma *vma)
+			 u32 flags)
 {
-	const unsigned int first = vma->node.start >> PAGE_SHIFT;
+	struct drm_i915_gem_object *obj = vma->obj;
+	u32 pte_flags = 0;
-	const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
+	int ret;
+	ret = i915_get_ggtt_vma_pages(vma);
+	if (ret)
+		return ret;
+	/* Currently applicable only to VLV */
+	if (obj->gt_ro)
+		pte_flags |= PTE_READ_ONLY;
-	BUG_ON(!i915_is_ggtt(vma->vm));
+	vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
+				vma->node.start,
+				cache_level, pte_flags);
+	/*
+	 * Without aliasing PPGTT there's no difference between
+	 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
+	 * upgrade to both bound if we bind either to avoid double-binding.
+	 */
+	vma->bound |= GLOBAL_BIND | LOCAL_BIND;
 	vma->bound = 0;
-	intel_gtt_clear_range(first, size);
+	return 0;
+}
-static void ggtt_bind_vma(struct i915_vma *vma,
+static int aliasing_gtt_bind_vma(struct i915_vma *vma,
-			  enum i915_cache_level cache_level,
+				 enum i915_cache_level cache_level,
-			  u32 flags)
+				 u32 flags)
+{
+	struct drm_device *dev = vma->vm->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj = vma->obj;
+	struct sg_table *pages = obj->pages;
+	u32 pte_flags = 0;
+	int ret;
+	ret = i915_get_ggtt_vma_pages(vma);
-	struct drm_device *dev = vma->vm->dev;
+	if (ret)
-	struct drm_i915_private *dev_priv = dev->dev_private;
+		return ret;
-	struct drm_i915_gem_object *obj = vma->obj;
+	pages = vma->ggtt_view.pages;
-	/* Currently applicable only to VLV */
-	if (obj->gt_ro)
-		flags |= PTE_READ_ONLY;
-	/* If there is no aliasing PPGTT, or the caller needs a global mapping,
-	 * or we have a global mapping already but the cacheability flags have
-	 * changed, set the global PTEs.
-	 *
-	 * If there is an aliasing PPGTT it is anecdotally faster, so use that
-	 * instead if none of the above hold true.
-	 *
-	 * NB: A global mapping should only be needed for special regions like
+	/* Currently applicable only to VLV */
-	 * "gtt mappable", SNB errata, or if specified via special execbuf
-	 * flags. At all other times, the GPU will use the aliasing PPGTT.
+	if (obj->gt_ro)
-	 */
+		pte_flags |= PTE_READ_ONLY;
-	if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
-		if (!(vma->bound & GLOBAL_BIND) ||
-		    (cache_level != obj->cache_level)) {
 			vma->vm->insert_entries(vma->vm, obj->pages,
-						vma->node.start,
-						cache_level, flags);
+	if (flags & GLOBAL_BIND) {
-			vma->bound |= GLOBAL_BIND;
 		vma->vm->insert_entries(vma->vm, pages,
-	}
+					vma->node.start,
-	if (dev_priv->mm.aliasing_ppgtt &&
+					cache_level, pte_flags);
-	    (!(vma->bound & LOCAL_BIND) ||
+	}
-	     (cache_level != obj->cache_level))) {
 		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
+	if (flags & LOCAL_BIND) {
+		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
-		appgtt->base.insert_entries(&appgtt->base,
+		appgtt->base.insert_entries(&appgtt->base, pages,
-					    vma->obj->pages,
+					    vma->node.start,
-					    vma->node.start,
+					    cache_level, pte_flags);
 					    cache_level, flags);
 		vma->bound |= LOCAL_BIND;
 	return 0;
+}
+static void ggtt_unbind_vma(struct i915_vma *vma)
+{
 	struct drm_device *dev = vma->vm->dev;
-static void ggtt_unbind_vma(struct i915_vma *vma)
+	struct drm_i915_private *dev_priv = dev->dev_private;
-{
+	struct drm_i915_gem_object *obj = vma->obj;
-	struct drm_device *dev = vma->vm->dev;
+	const uint64_t size = min_t(uint64_t,
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_gem_object *obj = vma->obj;
+				    obj->base.size,
+				    vma->node.size);
 	if (vma->bound & GLOBAL_BIND) {
+	if (vma->bound & GLOBAL_BIND) {
 		vma->vm->clear_range(vma->vm,
 				     vma->node.start,
-				     obj->base.size,
+				     size,
-				       true);
+				     true);
-		vma->bound &= ~GLOBAL_BIND;
+	}
-	if (vma->bound & LOCAL_BIND) {
+	if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
 		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	bool interruptible;
-	interruptible = do_idling(dev_priv);
-	if (!obj->has_dma_mapping)
+	interruptible = do_idling(dev_priv);
 		dma_unmap_sg(&dev->pdev->dev,
-			     obj->pages->sgl, obj->pages->nents,
+	dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
-			     PCI_DMA_BIDIRECTIONAL);
+		     PCI_DMA_BIDIRECTIONAL);
 	undo_idling(dev_priv, interruptible);
 }
 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 				  unsigned long color,
-				  unsigned long *start,
+				  u64 *start,
-				  unsigned long *end)
+				  u64 *end)
 			*end -= 4096;
+	}
+}
 static int i915_gem_setup_global_gtt(struct drm_device *dev,
-			      unsigned long start,
+				     u64 start,
-			      unsigned long mappable_end,
+				     u64 mappable_end,
-			      unsigned long end)
+				     u64 end)
+{
 	/* Let GEM Manage all of the aperture.
+	 *
 	 * However, leave one page at the end still bound to the scratch page.
 	unsigned long hole_start, hole_end;
 	int ret;
+	BUG_ON(mappable_end > end);
+	ggtt_vm->start = start;
-	BUG_ON(mappable_end > end);
+	/* Subtract the guard page before address space initialization to
+	 * shrink the range used by drm_mm */
+	ggtt_vm->total = end - start - PAGE_SIZE;
+	i915_address_space_init(ggtt_vm, dev_priv);
+	ggtt_vm->total += PAGE_SIZE;
+	if (intel_vgpu_active(dev)) {
+		ret = intel_vgt_balloon(dev);
+		if (ret)
+			return ret;
 	/* Subtract the guard page ... */
-	drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
 	if (!HAS_LLC(dev))
-		dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
+		ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
 	/* Mark any preallocated objects as occupied */
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 		struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
-		DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
+		DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
 			      i915_gem_obj_ggtt_offset(obj), obj->base.size);
 		WARN_ON(i915_gem_obj_ggtt_bound(obj));
 		ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
+		if (ret) {
+			DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
-		if (ret) {
+			return ret;
-			DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
-			return ret;
-		}
 		vma->bound |= GLOBAL_BIND;
 		vma->bound |= GLOBAL_BIND;
 		__i915_vma_set_map_and_fenceable(vma);
-	dev_priv->gtt.base.start = start;
+		list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
 	dev_priv->gtt.base.total = end - start;
 		ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 		if (!ppgtt)
 			return -ENOMEM;
 		ret = __hw_ppgtt_init(dev, ppgtt);
+		if (ret) {
+			ppgtt->base.cleanup(&ppgtt->base);
+			kfree(ppgtt);
+			return ret;
+		}
+		if (ppgtt->base.allocate_va_range)
+			ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
+							    ppgtt->base.total);
+		if (ret) {
+			ppgtt->base.cleanup(&ppgtt->base);
-		if (ret != 0)
+			kfree(ppgtt);
+			return ret;
+		}
+		ppgtt->base.clear_range(&ppgtt->base,
+					ppgtt->base.start,
+					ppgtt->base.total,
-			return ret;
+					true);
+		dev_priv->mm.aliasing_ppgtt = ppgtt;
 		WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
-		dev_priv->mm.aliasing_ppgtt = ppgtt;
+		dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
+	}
 	return 0;
+}
 void i915_gem_init_global_gtt(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 		ppgtt->base.cleanup(&ppgtt->base);
+	}
+	if (drm_mm_initialized(&vm->mm)) {
+		if (intel_vgpu_active(dev))
 			intel_vgt_deballoon();
 	if (drm_mm_initialized(&vm->mm)) {
 		drm_mm_takedown(&vm->mm);
 		list_del(&vm->global_link);
+	}
-	vm->cleanup(vm);
-}
-static int setup_scratch_page(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct page *page;
-	dma_addr_t dma_addr;
-	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
-	if (page == NULL)
-		return -ENOMEM;
-	set_pages_uc(page, 1);
-#ifdef CONFIG_INTEL_IOMMU
-	dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
-				PCI_DMA_BIDIRECTIONAL);
-	if (pci_dma_mapping_error(dev->pdev, dma_addr))
-		return -EINVAL;
-#else
-	dma_addr = page_to_phys(page);
-#endif
-	dev_priv->gtt.base.scratch.page = page;
-	dev_priv->gtt.base.scratch.addr = dma_addr;
-	return 0;
-}
-static void teardown_scratch_page(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct page *page = dev_priv->gtt.base.scratch.page;
-	set_pages_wb(page, 1);
-	pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
-		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-	__free_page(page);
+	vm->cleanup(vm);
+}
-static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
+static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
+{
 	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 	return snb_gmch_ctl << 20;
+}
-static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
+static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 #endif
 	return bdw_gmch_ctl << 20;
 }
-static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
+static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
+{
 	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
 	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
 	if (gmch_ctrl)
 		return 1 << (20 + gmch_ctrl);
 	return 0;
+}
-static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
+static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 {
 	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 	snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 	return snb_gmch_ctl << 25; /* 32 MB units */
+}
 static int ggtt_probe_common(struct drm_device *dev,
 			     size_t gtt_size)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_page_scratch *scratch_page;
-	phys_addr_t gtt_phys_addr;
-	int ret;
+	phys_addr_t gtt_phys_addr;
 	/* For Modern GENs the PTEs and register space are split in the BAR */
+	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
+		(pci_resource_len(dev->pdev, 0) / 2);
+	/*
+	 * On BXT writes larger than 64 bit to the GTT pagetable range will be
+	 * dropped. For WC mappings in general we have 64 byte burst writes
+	 * when the WC buffer is flushed, so we can't use it, but have to
+	 * resort to an uncached mapping. The WC issue is easily caught by the
+	 * readback check when writing GTT PTE entries.
+	 */
-	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
+	if (IS_BROXTON(dev))
-		(pci_resource_len(dev->pdev, 0) / 2);
+		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
 	else
-	dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
+		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
 	if (!dev_priv->gtt.gsm) {
 		DRM_ERROR("Failed to map the gtt page table\n");
 		return -ENOMEM;
+	}
-	ret = setup_scratch_page(dev);
+	scratch_page = alloc_scratch_page(dev);
+	if (IS_ERR(scratch_page)) {
-	if (ret) {
+		DRM_ERROR("Scratch setup failed\n");
+		/* iounmap will also get called at remove, but meh */
+		iounmap(dev_priv->gtt.gsm);
-		DRM_ERROR("Scratch setup failed\n");
+		return PTR_ERR(scratch_page);
 		/* iounmap will also get called at remove, but meh */
 		iounmap(dev_priv->gtt.gsm);
 	dev_priv->gtt.base.scratch_page = scratch_page;
 		 */
 		pat = GEN8_PPAT(0, GEN8_PPAT_UC);
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
-	I915_WRITE(GEN8_PRIVATE_PAT, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+}
 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
 	      GEN8_PPAT(4, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(5, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
-	I915_WRITE(GEN8_PRIVATE_PAT, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+}
 static int gen8_gmch_probe(struct drm_device *dev,
-			   size_t *gtt_total,
+			   u64 *gtt_total,
 			   size_t *stolen,
 			   phys_addr_t *mappable_base,
-			   unsigned long *mappable_end)
+			   u64 *mappable_end)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned int gtt_size;
+	u64 gtt_size;
 	u16 snb_gmch_ctl;
 	int ret;
 	} else {
-	*stolen = gen8_get_stolen_size(snb_gmch_ctl);
+		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
 		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+	}
-	*gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
+	*gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
-	if (IS_CHERRYVIEW(dev))
+	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 		chv_setup_private_ppat(dev_priv);
 	else
 		bdw_setup_private_ppat(dev_priv);
+	ret = ggtt_probe_common(dev, gtt_size);
-	ret = ggtt_probe_common(dev, gtt_size);
+	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
 	dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
-	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
+	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
-	dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
+	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
 	return ret;
 }
 static int gen6_gmch_probe(struct drm_device *dev,
-			   size_t *gtt_total,
+			   u64 *gtt_total,
 			   size_t *stolen,
 			   phys_addr_t *mappable_base,
 	/* 64/512MB is the current min/max we actually know of, but this is just
 	 * a coarse sanity check.
 	 */
 	if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
-		DRM_ERROR("Unknown GMADR size (%lx)\n",
+		DRM_ERROR("Unknown GMADR size (%llx)\n",
 			  dev_priv->gtt.mappable_end);
 		return -ENXIO;
+	}
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
 	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
-	*gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
+	*gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
+	ret = ggtt_probe_common(dev, gtt_size);
-	ret = ggtt_probe_common(dev, gtt_size);
+	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
 	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
-	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
+	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
-	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
+	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
 	return ret;
 }
 static void gen6_gmch_remove(struct i915_address_space *vm)
 {
 	struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
 	iounmap(gtt->gsm);
-	teardown_scratch_page(vm->dev);
+	free_scratch_page(vm->dev, vm->scratch_page);
+}
+	}
 	intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 	dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
+	dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
+	dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
-	dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
+	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
-	dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
+	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
 	} else {
 		dev_priv->gtt.gtt_probe = gen8_gmch_probe;
 		dev_priv->gtt.base.cleanup = gen6_gmch_remove;
+	}
+	gtt->base.dev = dev;
 	ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
 			     >t->mappable_base, >t->mappable_end);
 	if (ret)
-		return ret;
-	gtt->base.dev = dev;
+		return ret;
 	/* GMADR is the PCI mmio aperture into the global GTT. */
-	DRM_INFO("Memory usable by graphics device = %zdM\n",
+	DRM_INFO("Memory usable by graphics device = %lluM\n",
 		 gtt->base.total >> 20);
-	DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
+	DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
 	DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
 #ifdef CONFIG_INTEL_IOMMU
 	if (intel_iommu_gfx_mapped)
 	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 	return 0;
 }
 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
+void i915_gem_restore_gtt_mappings(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct i915_address_space *vm;
+	struct i915_vma *vma;
+	bool flush;
+	i915_check_and_clear_faults(dev);
+	/* First fill our portion of the GTT with scratch pages */
+	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
+				       dev_priv->gtt.base.start,
+				       dev_priv->gtt.base.total,
+				       true);
+	/* Cache flush objects bound into GGTT and rebind them. */
+	vm = &dev_priv->gtt.base;
+	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
+		flush = false;
+		list_for_each_entry(vma, &obj->vma_list, vma_link) {
+			if (vma->vm != vm)
+				continue;
+			WARN_ON(i915_vma_bind(vma, obj->cache_level,
+					      PIN_UPDATE));
+			flush = true;
+		}
+		if (flush)
+			i915_gem_clflush_object(obj, obj->pin_display);
+	}
+	if (INTEL_INFO(dev)->gen >= 8) {
+		if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+			chv_setup_private_ppat(dev_priv);
+		else
+			bdw_setup_private_ppat(dev_priv);
+		return;
+	}
+	if (USES_PPGTT(dev)) {
+		list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
+			/* TODO: Perhaps it shouldn't be gen6 specific */
+			struct i915_hw_ppgtt *ppgtt =
+					container_of(vm, struct i915_hw_ppgtt,
+						     base);
+			if (i915_is_ggtt(vm))
+				ppgtt = dev_priv->mm.aliasing_ppgtt;
+			gen6_write_page_range(dev_priv, &ppgtt->pd,
+, ppgtt->base.total);
+		}
+	}
+	i915_ggtt_flush(dev_priv);
+}
+static struct i915_vma *
+__i915_gem_vma_create(struct drm_i915_gem_object *obj,
+		      struct i915_address_space *vm,
+		      const struct i915_ggtt_view *ggtt_view)
+{
+	struct i915_vma *vma;
+	if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
+		return ERR_PTR(-EINVAL);
-					      struct i915_address_space *vm)
 //	vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
-	struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
+	vma = kzalloc(sizeof(*vma), GFP_KERNEL);
 	if (vma == NULL)
 		return ERR_PTR(-ENOMEM);
 	INIT_LIST_HEAD(&vma->vma_link);
 	INIT_LIST_HEAD(&vma->mm_list);
-	INIT_LIST_HEAD(&vma->exec_list);
-	vma->vm = vm;
-	vma->obj = obj;
-	switch (INTEL_INFO(vm->dev)->gen) {
-	case 9:
-	case 8:
-	case 7:
-	case 6:
-		if (i915_is_ggtt(vm)) {
-			vma->unbind_vma = ggtt_unbind_vma;
-			vma->bind_vma = ggtt_bind_vma;
-		} else {
-			vma->unbind_vma = ppgtt_unbind_vma;
-			vma->bind_vma = ppgtt_bind_vma;
-		}
-		break;
-	case 5:
-	case 4:
-	case 3:
-	case 2:
-		BUG_ON(!i915_is_ggtt(vm));
-		vma->unbind_vma = i915_ggtt_unbind_vma;
-		vma->bind_vma = i915_ggtt_bind_vma;
-		break;
-	default:
-		BUG();
+	INIT_LIST_HEAD(&vma->exec_list);
-	}
+	vma->vm = vm;
+	vma->obj = obj;
 	/* Keep GGTT vmas first to make debug easier */
+	if (i915_is_ggtt(vm))
-	if (i915_is_ggtt(vm))
+		vma->ggtt_view = *ggtt_view;
-		list_add(&vma->vma_link, &obj->vma_list);
 	else {
-		list_add_tail(&vma->vma_link, &obj->vma_list);
+	list_add_tail(&vma->vma_link, &obj->vma_list);
-		i915_ppgtt_get(i915_vm_to_ppgtt(vm));
+	if (!i915_is_ggtt(vm))
+{
 	struct i915_vma *vma;
 	vma = i915_gem_obj_to_vma(obj, vm);
 	if (!vma)
+		vma = __i915_gem_vma_create(obj, vm,
-		vma = __i915_gem_vma_create(obj, vm);
+					    i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
+	return vma;
+}
-	return vma;
 struct i915_vma *
+i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
-struct scatterlist *sg_next(struct scatterlist *sg)
+				       const struct i915_ggtt_view *view)
-{
-    if (sg_is_last(sg))
+{
-        return NULL;
+	struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
+	struct i915_vma *vma;
-    sg++;
+	if (WARN_ON(!view))
-    if (unlikely(sg_is_chain(sg)))
-            sg = sg_chain_ptr(sg);
+		return ERR_PTR(-EINVAL);
-    return sg;
-}
-void __sg_free_table(struct sg_table *table, unsigned int max_ents,
+	vma = i915_gem_obj_to_ggtt_view(obj, view);
-             bool skip_first_chunk, sg_free_fn *free_fn)
-{
-    struct scatterlist *sgl, *next;
-    if (unlikely(!table->sgl))
-        return;
-    sgl = table->sgl;
-    while (table->orig_nents) {
-        unsigned int alloc_size = table->orig_nents;
-        unsigned int sg_size;
-        /*
-         * If we have more than max_ents segments left,
-         * then assign 'next' to the sg table after the current one.
-         * sg_size is then one less than alloc size, since the last
          * element is the chain pointer.
+	if (IS_ERR(vma))
+		return vma;
-         */
+	if (!vma)
+		vma = __i915_gem_vma_create(obj, ggtt, view);
+	return vma;
+}
+static struct scatterlist *
+rotate_pages(dma_addr_t *in, unsigned int offset,
+	     unsigned int width, unsigned int height,
+	     struct sg_table *st, struct scatterlist *sg)
+{
-        if (alloc_size > max_ents) {
+	unsigned int column, row;
+	unsigned int src_idx;
+	if (!sg) {
+		st->nents = 0;
+		sg = st->sgl;
+	}
+	for (column = 0; column < width; column++) {
-            next = sg_chain_ptr(&sgl[max_ents - 1]);
+		src_idx = width * (height - 1) + column;
-            alloc_size = max_ents;
+		for (row = 0; row < height; row++) {
-            sg_size = alloc_size - 1;
+			st->nents++;
-        } else {
-            sg_size = alloc_size;
+			/* We don't need the pages, but need to initialize
-            next = NULL;
+			 * the entries so the sg list can be happily traversed.
-        }
-        table->orig_nents -= sg_size;
-        if (!skip_first_chunk) {
-            kfree(sgl);
+			 * The only thing we need are DMA addresses.
+			 */
-            skip_first_chunk = false;
+			sg_set_page(sg, NULL, PAGE_SIZE, 0);
+			sg_dma_address(sg) = in[offset + src_idx];
-        }
+			sg_dma_len(sg) = PAGE_SIZE;
+			sg = sg_next(sg);
+			src_idx -= width;
+		}
-        sgl = next;
+	}
-    }
+	return sg;
+}
+static struct sg_table *
+intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
-    table->sgl = NULL;
+			  struct drm_i915_gem_object *obj)
+{
-}
+	struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
-void sg_free_table(struct sg_table *table)
+	unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
-{
+	unsigned int size_pages_uv;
+	struct sg_page_iter sg_iter;
-    __sg_free_table(table, SG_MAX_SINGLE_ALLOC, false, NULL);
+	unsigned long i;
+	dma_addr_t *page_addr_list;
+	struct sg_table *st;
+	unsigned int uv_start_page;
+	struct scatterlist *sg;
-}
+	int ret = -ENOMEM;
-int sg_alloc_table(struct sg_table *table, unsigned int nents, gfp_t gfp_mask)
-{
-    struct scatterlist *sg, *prv;
-    unsigned int left;
-    unsigned int max_ents = SG_MAX_SINGLE_ALLOC;
-#ifndef ARCH_HAS_SG_CHAIN
+	/* Allocate a temporary list of source pages for random access. */
-    BUG_ON(nents > max_ents);
+	page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
+				       sizeof(dma_addr_t));
+	if (!page_addr_list)
-#endif
+		return ERR_PTR(ret);
-    memset(table, 0, sizeof(*table));
+	/* Account for UV plane with NV12. */
-    left = nents;
+	if (rot_info->pixel_format == DRM_FORMAT_NV12)
-    prv = NULL;
-    do {
+		size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
-        unsigned int sg_size, alloc_size = left;
+	else
-        if (alloc_size > max_ents) {
-                alloc_size = max_ents;
+		size_pages_uv = 0;
+	/* Allocate target SG list. */
+	st = kmalloc(sizeof(*st), GFP_KERNEL);
+	if (!st)
+		goto err_st_alloc;
+	ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
+	if (ret)
+		goto err_sg_alloc;
+	/* Populate source page list from the object. */
+	i = 0;
+	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
+		page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
+		i++;
+	}
+	/* Rotate the pages. */
+	sg = rotate_pages(page_addr_list, 0,
+		     rot_info->width_pages, rot_info->height_pages,
+		     st, NULL);
+	/* Append the UV plane if NV12. */
+	if (rot_info->pixel_format == DRM_FORMAT_NV12) {
+		uv_start_page = size_pages;
+		/* Check for tile-row un-alignment. */
+		if (offset_in_page(rot_info->uv_offset))
+			uv_start_page--;
+		rot_info->uv_start_page = uv_start_page;
+		rotate_pages(page_addr_list, uv_start_page,
+			     rot_info->width_pages_uv,
+			     rot_info->height_pages_uv,
+			     st, sg);
+	}
+	DRM_DEBUG_KMS(
+		      "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
+		      obj->base.size, rot_info->pitch, rot_info->height,
+		      rot_info->pixel_format, rot_info->width_pages,
-                sg_size = alloc_size - 1;
+		      rot_info->height_pages, size_pages + size_pages_uv,
+		      size_pages);
         } else
+	drm_free_large(page_addr_list);
+	return st;
+err_sg_alloc:
+	kfree(st);
-                sg_size = alloc_size;
+err_st_alloc:
+	drm_free_large(page_addr_list);
+	DRM_DEBUG_KMS(
+		      "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
+		      obj->base.size, ret, rot_info->pitch, rot_info->height,
-        left -= sg_size;
+		      rot_info->pixel_format, rot_info->width_pages,
-        sg = kmalloc(alloc_size * sizeof(struct scatterlist), gfp_mask);
-        if (unlikely(!sg)) {
-                /*
+		      rot_info->height_pages, size_pages + size_pages_uv,
-                 * Adjust entry count to reflect that the last
-                 * entry of the previous table won't be used for
-                 * linkage.  Without this, sg_kfree() may get
+		      size_pages);
-                 * confused.
+	return ERR_PTR(ret);
-                 */
-                if (prv)
+}
-                        table->nents = ++table->orig_nents;
+static struct sg_table *
+intel_partial_pages(const struct i915_ggtt_view *view,
+		    struct drm_i915_gem_object *obj)
+{
-                goto err;
+	struct sg_table *st;
+	struct scatterlist *sg;
-        }
+	struct sg_page_iter obj_sg_iter;
+	int ret = -ENOMEM;
+	st = kmalloc(sizeof(*st), GFP_KERNEL);
-        sg_init_table(sg, alloc_size);
+	if (!st)
-        table->nents = table->orig_nents += sg_size;
+		goto err_st_alloc;
+	ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
+	if (ret)
-        /*
+		goto err_sg_alloc;
-         * If this is the first mapping, assign the sg table header.
-         * If this is not the first mapping, chain previous part.
-         */
-        if (prv)
+	sg = st->sgl;
-                sg_chain(prv, max_ents, sg);
-        else
+	st->nents = 0;
-                table->sgl = sg;
-        /*
-         * If no more entries after this one, mark the end
+	for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
-         */
-        if (!left)
-                sg_mark_end(&sg[sg_size - 1]);
+		view->params.partial.offset)
+	{
+		if (st->nents >= view->params.partial.size)
+			break;
+		sg_set_page(sg, NULL, PAGE_SIZE, 0);
-        prv = sg;
+		sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
+		sg_dma_len(sg) = PAGE_SIZE;
-    } while (left);
+		sg = sg_next(sg);
+		st->nents++;
-    return 0;
+	}
+	return st;
-err:
+err_sg_alloc:
+	kfree(st);
+err_st_alloc:
+	return ERR_PTR(ret);
+}
-    __sg_free_table(table, SG_MAX_SINGLE_ALLOC, false, NULL);
+static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma)
-    return -ENOMEM;
+{
-}
 	int ret = 0;
+	if (vma->ggtt_view.pages)
+		return 0;
-void sg_init_table(struct scatterlist *sgl, unsigned int nents)
+	if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
+		vma->ggtt_view.pages = vma->obj->pages;
+	else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+		vma->ggtt_view.pages =
+			intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
+	else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
+		vma->ggtt_view.pages =
+			intel_partial_pages(&vma->ggtt_view, vma->obj);
 	else
-    memset(sgl, 0, sizeof(*sgl) * nents);
+		WARN_ONCE(1, "GGTT view %u not implemented!\n",
-#ifdef CONFIG_DEBUG_SG
+			  vma->ggtt_view.type);
-    {
-            unsigned int i;
+	if (!vma->ggtt_view.pages) {
-            for (i = 0; i < nents; i++)
+		DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
-                    sgl[i].sg_magic = SG_MAGIC;
+			  vma->ggtt_view.type);
-    }
+		ret = -EINVAL;
-#endif
+	} else if (IS_ERR(vma->ggtt_view.pages)) {
-    sg_mark_end(&sgl[nents - 1]);
+		ret = PTR_ERR(vma->ggtt_view.pages);
-}
+		vma->ggtt_view.pages = NULL;
+		DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
+			  vma->ggtt_view.type, ret);
+	}
+	return ret;
+}
+/**
+ * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
+ * @vma: VMA to map
+ * @cache_level: mapping cache level
+ * @flags: flags like global or local mapping
+ *
+ * DMA addresses are taken from the scatter-gather table of this object (or of
+ * this VMA in case of non-default GGTT views) and PTE entries set up.
+ * Note that DMA addresses are also the only part of the SG table we care about.
+ */
+int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
+		  u32 flags)
+{
+	int ret;
 	u32 bind_flags;
-void __sg_page_iter_start(struct sg_page_iter *piter,
+	if (WARN_ON(flags == 0))
+		return -EINVAL;
+	bind_flags = 0;
+	if (flags & PIN_GLOBAL)
+		bind_flags |= GLOBAL_BIND;
+	if (flags & PIN_USER)
+		bind_flags |= LOCAL_BIND;
+	if (flags & PIN_UPDATE)
+		bind_flags |= vma->bound;
+	else
+		bind_flags &= ~vma->bound;
+	if (bind_flags == 0)
+		return 0;
+	if (vma->bound == 0 && vma->vm->allocate_va_range) {
+		trace_i915_va_alloc(vma->vm,
+				    vma->node.start,
+				    vma->node.size,
+				    VM_TO_TRACE_NAME(vma->vm));
+		/* XXX: i915_vma_pin() will fix this +- hack */
+		vma->pin_count++;
+		ret = vma->vm->allocate_va_range(vma->vm,
+						 vma->node.start,
+						 vma->node.size);
+		vma->pin_count--;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_gtt.c – Rev 5354 → 6084