WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_gtt.c

  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
+ *
  */
-#define AGP_NORMAL_MEMORY 0
-#define AGP_USER_TYPES (1 << 16)
-#define AGP_USER_MEMORY (AGP_USER_TYPES)
-#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
 #include
 #include
 #include
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include "intel_drv.h"
-#include "intel_drv.h"
+#include
 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
-bool intel_enable_ppgtt(struct drm_device *dev, bool full)
+static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 {
+	bool has_aliasing_ppgtt;
-	if (i915.enable_ppgtt == 0)
+	bool has_full_ppgtt;
-		return false;
+	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
-	if (i915.enable_ppgtt == 1 && full)
-		return false;
+	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
+	if (IS_GEN8(dev))
+		has_full_ppgtt = false; /* XXX why? */
-	return true;
+	/*
 	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 	 * execlists, the sole mechanism available to submit work.
-static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+	 */
-{
+	if (INTEL_INFO(dev)->gen < 9 &&
-	if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
+	    (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 		return 0;
 	if (enable_ppgtt == 1)
 	    dev->pdev->revision < 0xb) {
 		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 		return 0;
+	}
-	return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
+	return has_aliasing_ppgtt ? 1 : 0;
+}
 static void ppgtt_bind_vma(struct i915_vma *vma,
-			   enum i915_cache_level cache_level,
-			   u32 flags);
+			   enum i915_cache_level cache_level,
-static void ppgtt_unbind_vma(struct i915_vma *vma);
+			   u32 flags);
-static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
+static void ppgtt_unbind_vma(struct i915_vma *vma);
 				     bool valid, u32 flags)
+{
 	gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
-	/* Mark the page as writeable.  Other platforms don't have a
-	 * setting for read-only/writable, so this matches that behavior.
 	 */
 	if (!(flags & PTE_READ_ONLY))
 	pte |= BYT_PTE_WRITEABLE;
 	return pte;
+}
 /* Broadwell Page Directory Pointer Descriptors */
 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
-			   uint64_t val, bool synchronous)
+			   uint64_t val)
-{
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 	int ret;
-	BUG_ON(entry >= 4);
-	if (synchronous) {
-		I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
-		I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
 		return 0;
 	BUG_ON(entry >= 4);
 	ret = intel_ring_begin(ring, 6);
 	return 0;
+}
-static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  struct intel_engine_cs *ring,
+static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  bool synchronous)
+			  struct intel_engine_cs *ring)
+{
 	int i, ret;
 	/* bit of a hack to find the actual last used pd */
 	int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 	for (i = used_pd - 1; i >= 0; i--) {
 		dma_addr_t addr = ppgtt->pd_dma_addr[i];
-		ret = gen8_write_pdp(ring, i, addr, synchronous);
+		ret = gen8_write_pdp(ring, i, addr);
 	unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 	unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 	unsigned num_entries = length >> PAGE_SHIFT;
 	unsigned last_pte, i;
-    pt_vaddr = (gen8_gtt_pte_t*)AllocKernelSpace(4096);
-    if(pt_vaddr == NULL)
-        return;
     scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
                       I915_CACHE_LLC, use_scratch);
 	while (num_entries) {
 		struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
 		last_pte = pte + num_entries;
 		if (last_pte > GEN8_PTES_PER_PAGE)
 			last_pte = GEN8_PTES_PER_PAGE;
-        MapPage(pt_vaddr,(addr_t)page_table, PG_SW);
+		pt_vaddr = kmap_atomic(page_table);
 		for (i = pte; i < last_pte; i++) {
+			pt_vaddr[i] = scratch_pte;
-			pt_vaddr[i] = scratch_pte;
+			num_entries--;
 			num_entries--;
 		if (!HAS_LLC(ppgtt->base.dev))
-		if (!HAS_LLC(ppgtt->base.dev))
+			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
-			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
+		kunmap_atomic(pt_vaddr);
 		pte = 0;
-		if (++pde == GEN8_PDES_PER_PAGE) {
+		pte = 0;
-			pdpe++;
+		if (++pde == GEN8_PDES_PER_PAGE) {
-			pde = 0;
+			pdpe++;
 	unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 	unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 	unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 	struct sg_page_iter sg_iter;
-    pt_vaddr = AllocKernelSpace(4096);
-    if(pt_vaddr == NULL)
-        return;
-    MapPage(pt_vaddr,(addr_t)(ppgtt->gen8_pt_pages[pdpe][pde]), 3);
+	pt_vaddr = NULL;
 	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
+		if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
+			break;
-		if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
+		if (pt_vaddr == NULL)
-			break;
+			pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
 		pt_vaddr[pte] =
 			gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 					cache_level, true);
+		if (++pte == GEN8_PTES_PER_PAGE) {
+			if (!HAS_LLC(ppgtt->base.dev))
-		if (++pte == GEN8_PTES_PER_PAGE) {
+				drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
-			if (!HAS_LLC(ppgtt->base.dev))
+			kunmap_atomic(pt_vaddr);
-				drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
+			pt_vaddr = NULL;
 			if (++pde == GEN8_PDES_PER_PAGE) {
 				pdpe++;
-				pde = 0;
 				pde = 0;
 			pte = 0;
+			pte = 0;
+		}
+	}
-            MapPage(pt_vaddr,(addr_t)(ppgtt->gen8_pt_pages[pdpe][pde]), 3);
+	if (pt_vaddr) {
+		if (!HAS_LLC(ppgtt->base.dev))
 			drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 		kunmap_atomic(pt_vaddr);
     FreeKernelSpace(pt_vaddr);
+}
 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
-	list_del(&vm->global_link);
-	drm_mm_takedown(&vm->mm);
 	gen8_ppgtt_unmap_pages(ppgtt);
 	gen8_ppgtt_free(ppgtt);
+}
 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
+{
 	const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 	const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 	int i, j, ret;
-	gen8_ppgtt_pde_t *pd_vaddr;
 	if (size % (1<<30))
 		DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
+	 *
 	 * For now, the PPGTT helper functions all require that the PDEs are
 	 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 	 * will never need to touch the PDEs again.
 	 */
-    pd_vaddr = AllocKernelSpace(4096);
     for (i = 0; i < max_pdp; i++) {
+		gen8_ppgtt_pde_t *pd_vaddr;
-        MapPage(pd_vaddr,(addr_t)(&ppgtt->pd_pages[i]), 3);
+		pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 		for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 			dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 			pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 						      I915_CACHE_LLC);
+		}
 		if (!HAS_LLC(ppgtt->base.dev))
 			drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
+		kunmap_atomic(pd_vaddr);
+	}
-    FreeKernelSpace(pd_vaddr);
 	ppgtt->enable = gen8_ppgtt_enable;
 	ppgtt->switch_mm = gen8_mm_switch;
 	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 	return (ppgtt->pd_offset / 64) << 16;
+}
-static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			 struct intel_engine_cs *ring,
+static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			 bool synchronous)
-{
-	struct drm_device *dev = ppgtt->base.dev;
+			 struct intel_engine_cs *ring)
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int ret;
-	/* If we're in reset, we can assume the GPU is sufficiently idle to
-	 * manually frob these bits. Ideally we could use the ring functions,
-	 * except our error handling makes it quite difficult (can't use
-	 * intel_ring_begin, ring->flush, or intel_ring_advance)
-	 *
-	 * FIXME: We should try not to special case reset
-	 */
-	if (synchronous ||
-	    i915_reset_in_progress(&dev_priv->gpu_error)) {
-		WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
-		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
-		I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
-		POSTING_READ(RING_PP_DIR_BASE(ring));
 		return 0;
 	int ret;
 	/* NB: TLBs must be flushed and invalidated before a switch */
 	return 0;
+}
-static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  struct intel_engine_cs *ring,
+static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  bool synchronous)
-{
-	struct drm_device *dev = ppgtt->base.dev;
+			  struct intel_engine_cs *ring)
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int ret;
-	/* If we're in reset, we can assume the GPU is sufficiently idle to
-	 * manually frob these bits. Ideally we could use the ring functions,
-	 * except our error handling makes it quite difficult (can't use
-	 * intel_ring_begin, ring->flush, or intel_ring_advance)
-	 *
-	 * FIXME: We should try not to special case reset
-	 */
-	if (synchronous ||
-	    i915_reset_in_progress(&dev_priv->gpu_error)) {
-		WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
-		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
-		I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
-		POSTING_READ(RING_PP_DIR_BASE(ring));
 		return 0;
 	int ret;
 	/* NB: TLBs must be flushed and invalidated before a switch */
 	return 0;
+}
-static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  struct intel_engine_cs *ring,
+static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
-			  bool synchronous)
+			  struct intel_engine_cs *ring)
+{
-	struct drm_device *dev = ppgtt->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_device *dev = ppgtt->base.dev;
-	if (!synchronous)
+	struct drm_i915_private *dev_priv = dev->dev_private;
 		return 0;
 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
-	POSTING_READ(RING_PP_DIR_DCLV(ring));
 	POSTING_READ(RING_PP_DIR_DCLV(ring));
 	return 0;
-}
+	return 0;
+}
 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 static void gen8_ppgtt_enable(struct drm_device *dev)
-	struct drm_device *dev = ppgtt->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_engine_cs *ring;
-	int j, ret;
-	for_each_ring(ring, dev_priv, j) {
-		I915_WRITE(RING_MODE_GEN7(ring),
-			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 		/* We promise to do a switch later with FULL PPGTT. If this is
-		 * aliasing, this is the one and only switch we'll do */
-		if (USES_FULL_PPGTT(dev))
-			continue;
-		ret = ppgtt->switch_mm(ppgtt, ring, true);
-		if (ret)
-			goto err_out;
-	}
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	return 0;
+	struct intel_engine_cs *ring;
 	int j;
-err_out:
 	for_each_ring(ring, dev_priv, j)
-		I915_WRITE(RING_MODE_GEN7(ring),
+	for_each_ring(ring, dev_priv, j) {
-			   _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
+		I915_WRITE(RING_MODE_GEN7(ring),
-	return ret;
+			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 			ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
+		}
 		I915_WRITE(GAM_ECOCHK, ecochk);
-	for_each_ring(ring, dev_priv, i) {
-		int ret;
+	for_each_ring(ring, dev_priv, i) {
 		/* GFX_MODE is per-ring on gen7+ */
 			I915_WRITE(RING_MODE_GEN7(ring),
-				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-		/* We promise to do a switch later with FULL PPGTT. If this is
-		 * aliasing, this is the one and only switch we'll do */
-		if (USES_FULL_PPGTT(dev))
-			continue;
-		ret = ppgtt->switch_mm(ppgtt, ring, true);
-		if (ret)
-			return ret;
+				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-	}
 	return 0;
 }
-static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 static void gen6_ppgtt_enable(struct drm_device *dev)
-	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_engine_cs *ring;
-	uint32_t ecochk, gab_ctl, ecobits;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i;
+	uint32_t ecochk, gab_ctl, ecobits;
 	ecochk = I915_READ(GAM_ECOCHK);
 	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
-	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-	for_each_ring(ring, dev_priv, i) {
-		int ret = ppgtt->switch_mm(ppgtt, ring, true);
-		if (ret)
-			return ret;
-	}
-	return 0;
+	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+}
 	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 	unsigned last_pte, i;
-	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
-    pt_vaddr = AllocKernelSpace(4096);
-    if(pt_vaddr == NULL)
-        return;
+	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 	while (num_entries) {
             last_pte = first_pte + num_entries;
             if (last_pte > I915_PPGTT_PT_ENTRIES)
                 last_pte = I915_PPGTT_PT_ENTRIES;
+		pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
-            MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
+            for (i = first_pte; i < last_pte; i++)
                 pt_vaddr[i] = scratch_pte;
             for (i = first_pte; i < last_pte; i++)
-                pt_vaddr[i] = scratch_pte;
+		kunmap_atomic(pt_vaddr);
-            num_entries -= last_pte - first_pte;
             first_pte = 0;
-            act_pt++;
+            num_entries -= last_pte - first_pte;
-    };
+            first_pte = 0;
             act_pt++;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 	unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 	struct sg_page_iter sg_iter;
-    pt_vaddr = AllocKernelSpace(4096);
-    if(pt_vaddr == NULL)
-        return;
-    MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
+	pt_vaddr = NULL;
+	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
+		if (pt_vaddr == NULL)
-	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
+			pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 		pt_vaddr[act_pte] =
 			vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
+				       cache_level, true, flags);
-				       cache_level, true, flags);
+		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
-		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
+			kunmap_atomic(pt_vaddr);
-			act_pt++;
+			pt_vaddr = NULL;
-    		MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
+			act_pt++;
+			act_pte = 0;
-			act_pte = 0;
+			}
+		}
 	if (pt_vaddr)
-    FreeKernelSpace(pt_vaddr);
+		kunmap_atomic(pt_vaddr);
+}
 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
-	list_del(&vm->global_link);
 	drm_mm_takedown(&ppgtt->base.mm);
 	drm_mm_remove_node(&ppgtt->node);
 	gen6_ppgtt_unmap_pages(ppgtt);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
-	if (IS_GEN6(dev)) {
-	ppgtt->enable = gen6_ppgtt_enable;
+	if (IS_GEN6(dev)) {
 		ppgtt->switch_mm = gen6_mm_switch;
-	} else if (IS_HASWELL(dev)) {
-		ppgtt->enable = gen7_ppgtt_enable;
+	} else if (IS_HASWELL(dev)) {
 		ppgtt->switch_mm = hsw_mm_switch;
-	} else if (IS_GEN7(dev)) {
-		ppgtt->enable = gen7_ppgtt_enable;
+	} else if (IS_GEN7(dev)) {
 		ppgtt->switch_mm = gen7_mm_switch;
 	} else
 		BUG();
 	DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
 			 ppgtt->node.size >> 20,
+			 ppgtt->node.start / PAGE_SIZE);
+	gen6_write_pdes(ppgtt);
+	DRM_DEBUG("Adding PPGTT at offset %x\n",
-			 ppgtt->node.start / PAGE_SIZE);
+		  ppgtt->pd_offset << 10);
 	return 0;
+}
-int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int ret = 0;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	ppgtt->base.dev = dev;
 	ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 	if (INTEL_INFO(dev)->gen < 8)
-		ret = gen6_ppgtt_init(ppgtt);
+		return gen6_ppgtt_init(ppgtt);
+	else if (IS_GEN8(dev) || IS_GEN9(dev))
-	else if (IS_GEN8(dev))
+		return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
-		ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
+	else
+		BUG();
+}
+int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+{
-	else
+	struct drm_i915_private *dev_priv = dev->dev_private;
-		BUG();
+	int ret = 0;
-	if (!ret) {
+	ret = __hw_ppgtt_init(dev, ppgtt);
-		struct drm_i915_private *dev_priv = dev->dev_private;
-		kref_init(&ppgtt->ref);
-		drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
-			    ppgtt->base.total);
-		i915_init_vm(dev_priv, &ppgtt->base);
+	if (ret == 0) {
+		kref_init(&ppgtt->ref);
+		drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
-		if (INTEL_INFO(dev)->gen < 8) {
+			    ppgtt->base.total);
+		i915_init_vm(dev_priv, &ppgtt->base);
+	}
+	return ret;
+}
+int i915_ppgtt_init_hw(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_engine_cs *ring;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	int i, ret = 0;
+	/* In the case of execlists, PPGTT is enabled by the context descriptor
+	 * and the PDPs are contained within the context itself.  We don't
+	 * need to do anything here. */
+	if (i915.enable_execlists)
+		return 0;
+	if (!USES_PPGTT(dev))
+		return 0;
+	if (IS_GEN6(dev))
+		gen6_ppgtt_enable(dev);
+	else if (IS_GEN7(dev))
+		gen7_ppgtt_enable(dev);
+	else if (INTEL_INFO(dev)->gen >= 8)
+		gen8_ppgtt_enable(dev);
+	else
-			gen6_write_pdes(ppgtt);
+		WARN_ON(1);
 			DRM_DEBUG("Adding PPGTT at offset %x\n",
+	if (ppgtt) {
+		for_each_ring(ring, dev_priv, i) {
+			ret = ppgtt->switch_mm(ppgtt, ring);
+			if (ret != 0)
+				return ret;
+		}
+	}
+	return ret;
+}
+struct i915_hw_ppgtt *
+i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
+{
+	struct i915_hw_ppgtt *ppgtt;
+	int ret;
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ERR_PTR(-ENOMEM);
+	ret = i915_ppgtt_init(dev, ppgtt);
+	if (ret) {
+		kfree(ppgtt);
+		return ERR_PTR(ret);
+	}
+	ppgtt->file_priv = fpriv;
+	trace_i915_ppgtt_create(&ppgtt->base);
+	return ppgtt;
+}
+void  i915_ppgtt_release(struct kref *kref)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(kref, struct i915_hw_ppgtt, ref);
+	trace_i915_ppgtt_release(&ppgtt->base);
+	/* vmas should already be unbound */
+	WARN_ON(!list_empty(&ppgtt->base.active_list));
+	WARN_ON(!list_empty(&ppgtt->base.inactive_list));
-				  ppgtt->pd_offset << 10);
+	list_del(&ppgtt->base.global_link);
 	drm_mm_takedown(&ppgtt->base.mm);
 	ppgtt->base.cleanup(&ppgtt->base);
 	for_each_ring(ring, dev_priv, i) {
 		u32 fault_reg;
 		fault_reg = I915_READ(RING_FAULT_REG(ring));
 		if (fault_reg & RING_FAULT_VALID) {
 			DRM_DEBUG_DRIVER("Unexpected fault\n"
-					 "\tAddr: 0x%08lx\\n"
+					 "\tAddr: 0x%08lx\n"
 					 "\tAddress space: %s\n"
 					 "\tSource ID: %d\n"
 					 "\tType: %d\n",
 					 fault_reg & PAGE_MASK,
 					 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+		}
+	}
 	POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
+}
+static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
+{
+	if (INTEL_INFO(dev_priv->dev)->gen < 6) {
+		intel_gtt_chipset_flush();
+	} else {
+		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+		POSTING_READ(GFX_FLSH_CNTL_GEN6);
+	}
+}
 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 				       dev_priv->gtt.base.start,
 				       dev_priv->gtt.base.total,
+				       true);
-				       true);
+	i915_ggtt_flush(dev_priv);
+}
 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 		i915_gem_clflush_object(obj, obj->pin_display);
 		/* The bind_vma code tries to be smart about tracking mappings.
 		 * Unfortunately above, we've just wiped out the mappings
 		 * without telling our object about it. So we need to fake it.
 		 */
-		obj->has_global_gtt_mapping = 0;
+		vma->bound &= ~GLOBAL_BIND;
 		vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
+	}
+		}
 		gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
 	}
-	i915_gem_chipset_flush(dev);
+	i915_ggtt_flush(dev_priv);
+}
 	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 	BUG_ON(!i915_is_ggtt(vma->vm));
 	intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
-	vma->obj->has_global_gtt_mapping = 1;
+	vma->bound = GLOBAL_BIND;
+}
 static void i915_ggtt_clear_range(struct i915_address_space *vm,
+{
 	const unsigned int first = vma->node.start >> PAGE_SHIFT;
 	const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
 	BUG_ON(!i915_is_ggtt(vma->vm));
-	vma->obj->has_global_gtt_mapping = 0;
+	vma->bound = 0;
 	intel_gtt_clear_range(first, size);
+}
 	 * NB: A global mapping should only be needed for special regions like
 	 * "gtt mappable", SNB errata, or if specified via special execbuf
 	 * flags. At all other times, the GPU will use the aliasing PPGTT.
 	 */
 	if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
-		if (!obj->has_global_gtt_mapping ||
+		if (!(vma->bound & GLOBAL_BIND) ||
 		    (cache_level != obj->cache_level)) {
 			vma->vm->insert_entries(vma->vm, obj->pages,
 						vma->node.start,
 						cache_level, flags);
-			obj->has_global_gtt_mapping = 1;
+			vma->bound |= GLOBAL_BIND;
+		}
+	}
 	if (dev_priv->mm.aliasing_ppgtt &&
-	    (!obj->has_aliasing_ppgtt_mapping ||
+	    (!(vma->bound & LOCAL_BIND) ||
 	     (cache_level != obj->cache_level))) {
 		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
 		appgtt->base.insert_entries(&appgtt->base,
 					    vma->obj->pages,
 					    vma->node.start,
 					    cache_level, flags);
-		vma->obj->has_aliasing_ppgtt_mapping = 1;
+		vma->bound |= LOCAL_BIND;
+	}
+}
 static void ggtt_unbind_vma(struct i915_vma *vma)
+{
 	struct drm_device *dev = vma->vm->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj = vma->obj;
-	if (obj->has_global_gtt_mapping) {
+	if (vma->bound & GLOBAL_BIND) {
 		vma->vm->clear_range(vma->vm,
 				     vma->node.start,
 				     obj->base.size,
 				       true);
-		obj->has_global_gtt_mapping = 0;
+		vma->bound &= ~GLOBAL_BIND;
+	}
-	if (obj->has_aliasing_ppgtt_mapping) {
+	if (vma->bound & LOCAL_BIND) {
 		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
 		appgtt->base.clear_range(&appgtt->base,
 					 vma->node.start,
 					 obj->base.size,
 					 true);
-		obj->has_aliasing_ppgtt_mapping = 0;
+		vma->bound &= ~LOCAL_BIND;
 		if (node->allocated && node->color != color)
 			*end -= 4096;
+	}
+}
-void i915_gem_setup_global_gtt(struct drm_device *dev,
+static int i915_gem_setup_global_gtt(struct drm_device *dev,
 			      unsigned long start,
 			      unsigned long mappable_end,
 			      unsigned long end)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
 	struct drm_mm_node *entry;
 	struct drm_i915_gem_object *obj;
 	unsigned long hole_start, hole_end;
+	int ret;
 	BUG_ON(mappable_end > end);
 		dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
 	/* Mark any preallocated objects as occupied */
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 		struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
 		int ret;
 		DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
 			      i915_gem_obj_ggtt_offset(obj), obj->base.size);
 		WARN_ON(i915_gem_obj_ggtt_bound(obj));
 		ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
+		if (ret) {
+			DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
-		if (ret)
+			return ret;
 			DRM_DEBUG_KMS("Reservation failed\n");
-		obj->has_global_gtt_mapping = 1;
+		vma->bound |= GLOBAL_BIND;
+	}
 				     hole_end - hole_start, true);
+	}
 	/* And finally clear the reserved guard page */
+	ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
+	if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
+		struct i915_hw_ppgtt *ppgtt;
+		ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+		if (!ppgtt)
+			return -ENOMEM;
+		ret = __hw_ppgtt_init(dev, ppgtt);
+		if (ret != 0)
+			return ret;
+		dev_priv->mm.aliasing_ppgtt = ppgtt;
+	}
-	ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
+	return 0;
+}
 void i915_gem_init_global_gtt(struct drm_device *dev)
 	mappable_size = dev_priv->gtt.mappable_end;
 	i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
+}
+void i915_global_gtt_cleanup(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_address_space *vm = &dev_priv->gtt.base;
+	if (dev_priv->mm.aliasing_ppgtt) {
+		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+		ppgtt->base.cleanup(&ppgtt->base);
+	}
+	if (drm_mm_initialized(&vm->mm)) {
+		drm_mm_takedown(&vm->mm);
+		list_del(&vm->global_link);
+	}
+	vm->cleanup(vm);
+}
 static int setup_scratch_page(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct page *page;
 	dma_addr_t dma_addr;
-	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
-	if (page == NULL)
+	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
-		return -ENOMEM;
+	if (page == NULL)
-    get_page(page);
+		return -ENOMEM;
 	set_pages_uc(page, 1);
 	struct page *page = dev_priv->gtt.base.scratch.page;
 	set_pages_wb(page, 1);
 	pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
-		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-	put_page(page);
+		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 	__free_page(page);
+}
 		return (gmch_ctrl - 0x11 + 2) << 22;
 	else
 		return (gmch_ctrl - 0x17 + 9) << 22;
+}
+static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
+{
+	gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
+	gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
+	if (gen9_gmch_ctl < 0xf0)
+		return gen9_gmch_ctl << 25; /* 32 MB units */
+	else
+		/* 4MB increments starting at 0xf0 for 4MB */
+		return (gen9_gmch_ctl - 0xf0 + 1) << 22;
+}
 static int ggtt_probe_common(struct drm_device *dev,
 			     size_t gtt_size)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
 	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
 	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
 	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+	if (!USES_PPGTT(dev_priv->dev))
+		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
+		 * so RTL will always use the value corresponding to
+		 * pat_sel = 000".
+		 * So let's disable cache for GGTT to avoid screen corruptions.
+		 * MOCS still can be used though.
+		 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
+		 * before this patch, i.e. the same uncached + snooping access
+		 * like on gen6/7 seems to be in effect.
+		 * - So this just fixes blitter/render access. Again it looks
+		 * like it's not just uncached access, but uncached + snooping.
+		 * So we can still hold onto all our assumptions wrt cpu
+		 * clflushing on LLC machines.
+		 */
+		pat = GEN8_PPAT(0, GEN8_PPAT_UC);
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
 	I915_WRITE(GEN8_PRIVATE_PAT, pat);
 	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
 	 * Map WB on BDW to snooped on CHV.
+	 *
 	 * Only the snoop bit has meaning for CHV, the rest is
 	 * ignored.
+	 *
-	 * Note that the harware enforces snooping for all page
+	 * The hardware will never snoop for certain types of accesses:
+	 * - CPU GTT (GMADR->GGTT->no snoop->memory)
+	 * - PPGTT page tables
+	 * - some other special cycles
+	 *
+	 * As with BDW, we also need to consider the following for GT accesses:
+	 * "For GGTT, there is NO pat_sel[2:0] from the entry,
-	 * table accesses. The snoop bit is actually ignored for
+	 * so RTL will always use the value corresponding to
-	 * PDEs.
+	 * pat_sel = 000".
+	 * Which means we must set the snoop bit in PAT entry 0
+	 * in order to keep the global status page working.
 	 */
 	pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(1, 0) |
 	      GEN8_PPAT(2, 0) |
 	      GEN8_PPAT(3, 0) |
 	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
+	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+	if (INTEL_INFO(dev)->gen >= 9) {
-	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+		*stolen = gen9_get_stolen_size(snb_gmch_ctl);
 		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
-	if (IS_CHERRYVIEW(dev)) {
+	} else if (IS_CHERRYVIEW(dev)) {
 		*stolen = chv_get_stolen_size(snb_gmch_ctl);
 		gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
 	} else {
 static void gen6_gmch_remove(struct i915_address_space *vm)
+{
-	struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
-	if (drm_mm_initialized(&vm->mm)) {
-		drm_mm_takedown(&vm->mm);
-		list_del(&vm->global_link);
+	struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
 	iounmap(gtt->gsm);
 	teardown_scratch_page(vm->dev);
 	INIT_LIST_HEAD(&vma->exec_list);
 	vma->vm = vm;
 	vma->obj = obj;
+	switch (INTEL_INFO(vm->dev)->gen) {
-	switch (INTEL_INFO(vm->dev)->gen) {
+	case 9:
 	case 8:
 	case 7:
 	case 6:
 		if (i915_is_ggtt(vm)) {
+	}
 	/* Keep GGTT vmas first to make debug easier */
 	if (i915_is_ggtt(vm))
 		list_add(&vma->vma_link, &obj->vma_list);
-	else
+	else {
+		list_add_tail(&vma->vma_link, &obj->vma_list);
+		i915_ppgtt_get(i915_vm_to_ppgtt(vm));
 		list_add_tail(&vma->vma_link, &obj->vma_list);
 	return vma;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_gtt.c – Rev 5060 → 5354