WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_gtt.c

 #include
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
+#define GEN6_PPGTT_PD_ENTRIES 512
-typedef uint32_t gen6_gtt_pte_t;
+#define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
+/* PPGTT stuff */
-/* PPGTT stuff */
+#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
-#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
+#define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
 #define GEN6_PDE_VALID			(1 << 0)
 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
 #define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 #define GEN6_PTE_VALID			(1 << 0)
 #define GEN6_PTE_UNCACHED		(1 << 1)
+#define HSW_PTE_UNCACHED		(0)
+#define GEN6_PTE_CACHE_LLC		(2 << 1)
-#define HSW_PTE_UNCACHED		(0)
+#define GEN7_PTE_CACHE_L3_LLC		(3 << 1)
+#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
+#define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)
-#define GEN6_PTE_CACHE_LLC		(2 << 1)
+/* Cacheability Control is a 4-bit value. The low three bits are stored in *
+ * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
+ */
+#define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
+					 (((bits) & 0x8) << (11 - 3)))
+#define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
-#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)
+#define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
-#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
+#define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
-				   dma_addr_t addr,
+static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
-				   enum i915_cache_level level)
+				     enum i915_cache_level level)
-{
-	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+{
-	pte |= GEN6_PTE_ADDR_ENCODE(addr);
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= GEN6_PTE_ADDR_ENCODE(addr);
+	switch (level) {
+	case I915_CACHE_L3_LLC:
+	case I915_CACHE_LLC:
+		pte |= GEN6_PTE_CACHE_LLC;
+		break;
+	case I915_CACHE_NONE:
+		pte |= GEN6_PTE_UNCACHED;
+		break;
+	default:
+		WARN_ON(1);
+	}
+	return pte;
+}
+static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
+				   enum i915_cache_level level)
-	switch (level) {
+{
-	case I915_CACHE_LLC_MLC:
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
-		/* Haswell doesn't set L3 this way */
+	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 		if (IS_HASWELL(dev))
-			pte |= GEN6_PTE_CACHE_LLC;
+	switch (level) {
-		else
+	case I915_CACHE_L3_LLC:
-			pte |= GEN6_PTE_CACHE_LLC_MLC;
-		break;
-	case I915_CACHE_LLC:
-		pte |= GEN6_PTE_CACHE_LLC;
+		pte |= GEN7_PTE_CACHE_L3_LLC;
 		break;
-	case I915_CACHE_NONE:
+	case I915_CACHE_LLC:
-		if (IS_HASWELL(dev))
+		pte |= GEN6_PTE_CACHE_LLC;
-			pte |= HSW_PTE_UNCACHED;
+		break;
-		else
+	case I915_CACHE_NONE:
 			pte |= GEN6_PTE_UNCACHED;
+		break;
+	default:
+		WARN_ON(1);
-		break;
+	}
-	default:
+	return pte;
-		BUG();
+}
+#define BYT_PTE_WRITEABLE		(1 << 1)
+#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
+static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
+				     enum i915_cache_level level)
+{
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= GEN6_PTE_ADDR_ENCODE(addr);
+	/* Mark the page as writeable.  Other platforms don't have a
+	 * setting for read-only/writable, so this matches that behavior.
+	 */
+	pte |= BYT_PTE_WRITEABLE;
+	if (level != I915_CACHE_NONE)
+		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
+	return pte;
+}
+static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
-	}
+				     enum i915_cache_level level)
+{
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= HSW_PTE_ADDR_ENCODE(addr);
+	if (level != I915_CACHE_NONE)
+		pte |= HSW_WB_LLC_AGE3;
+	return pte;
+}
+static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
+				      enum i915_cache_level level)
+{
+	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
+	pte |= HSW_PTE_ADDR_ENCODE(addr);
+	switch (level) {
+	case I915_CACHE_NONE:
+		break;
+	case I915_CACHE_WT:
+		pte |= HSW_WT_ELLC_LLC_AGE0;
+		break;
+	default:
+		pte |= HSW_WB_ELLC_LLC_AGE0;
-	return pte;
+		break;
+	}
-static int gen6_ppgtt_enable(struct drm_device *dev)
+	return pte;
+}
-	drm_i915_private_t *dev_priv = dev->dev_private;
+static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 	uint32_t pd_offset;
-	struct intel_ring_buffer *ring;
+	struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 		pd_entry |= GEN6_PDE_VALID;
 		writel(pd_entry, pd_addr + i);
+	}
+	readl(pd_addr);
+}
+static int gen6_ppgtt_enable(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t pd_offset;
+	struct intel_ring_buffer *ring;
+	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+	int i;
+	BUG_ON(ppgtt->pd_offset & 0x3f);
-	readl(pd_addr);
+	gen6_write_pdes(ppgtt);
 	pd_offset = ppgtt->pd_offset;
+	}
 	return 0;
+}
 /* PPGTT support for Sandybdrige/Gen6 and later */
-static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
+static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 				   unsigned first_entry,
 				   unsigned num_entries)
+{
+	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 	unsigned last_pte, i;
-	scratch_pte = gen6_pte_encode(ppgtt->dev,
 				      ppgtt->scratch_page_dma_addr,
-				 I915_CACHE_LLC);
+	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
     };
     FreeKernelSpace(pt_vaddr);
 }
-static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
+static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 				      struct sg_table *pages,
 				      unsigned first_entry,
+				      enum i915_cache_level cache_level)
+{
-				      enum i915_cache_level cache_level)
+	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen6_gtt_pte_t *pt_vaddr;
 	unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 	unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
     MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
 	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 		dma_addr_t page_addr;
 		page_addr = sg_page_iter_dma_address(&sg_iter);
-		pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
-						      cache_level);
+		pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level);
 		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 			act_pt++;
     		MapPage(pt_vaddr,(addr_t)(ppgtt->pt_pages[act_pt]), 3);
 			act_pte = 0;
+			}
+		}
-        FreeKernelSpace(pt_vaddr);
+    FreeKernelSpace(pt_vaddr);
+}
+static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
+	struct i915_hw_ppgtt *ppgtt =
+		container_of(vm, struct i915_hw_ppgtt, base);
-static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
+	int i;
-	int i;
+	drm_mm_takedown(&ppgtt->base.mm);
 	if (ppgtt->pt_dma_addr) {
 		for (i = 0; i < ppgtt->num_pd_entries; i++)
-			pci_unmap_page(ppgtt->dev->pdev,
+			pci_unmap_page(ppgtt->base.dev->pdev,
 	kfree(ppgtt);
+}
 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 {
-	struct drm_device *dev = ppgtt->dev;
+	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned first_pd_entry_in_global_pt;
 	int i;
 	int ret = -ENOMEM;
 	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 	 * entries. For aliasing ppgtt support we just steal them at the end for
+	 * now. */
-	 * now. */
+       first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
        first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
+	ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
-	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
+	ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 	ppgtt->enable = gen6_ppgtt_enable;
+	ppgtt->base.clear_range = gen6_ppgtt_clear_range;
-	ppgtt->clear_range = gen6_ppgtt_clear_range;
+	ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
-	ppgtt->insert_entries = gen6_ppgtt_insert_entries;
+	ppgtt->base.cleanup = gen6_ppgtt_cleanup;
-	ppgtt->cleanup = gen6_ppgtt_cleanup;
+	ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 	ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 					       PCI_DMA_BIDIRECTIONAL);
-			ppgtt->pt_dma_addr[i] = pt_addr;
+        ppgtt->pt_dma_addr[i] = pt_addr;
-		}
+    }
-	ppgtt->clear_range(ppgtt, 0,
+	ppgtt->base.clear_range(&ppgtt->base, 0,
 			       ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 	if (!ppgtt)
 		return -ENOMEM;
 	ppgtt->dev = dev;
-	ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
+	ppgtt->base.dev = dev;
 	if (INTEL_INFO(dev)->gen < 8)
 	ret = gen6_ppgtt_init(ppgtt);
 	else
 		BUG();
+	if (ret)
+        kfree(ppgtt);
+	else {
-	if (ret)
+		dev_priv->mm.aliasing_ppgtt = ppgtt;
-	kfree(ppgtt);
+		drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
-	else
+			    ppgtt->base.total);
 	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 	if (!ppgtt)
 		return;
-	ppgtt->cleanup(ppgtt);
+	ppgtt->base.cleanup(&ppgtt->base);
 	dev_priv->mm.aliasing_ppgtt = NULL;
+}
 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 			    struct drm_i915_gem_object *obj,
 			    enum i915_cache_level cache_level)
+{
-	ppgtt->insert_entries(ppgtt, obj->pages,
+	ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
-				     obj->gtt_space->start >> PAGE_SHIFT,
+				   i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 				     cache_level);
+}
 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 			      struct drm_i915_gem_object *obj)
+{
-	ppgtt->clear_range(ppgtt,
+	ppgtt->base.clear_range(&ppgtt->base,
-			       obj->gtt_space->start >> PAGE_SHIFT,
+				i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	/* First fill our portion of the GTT with scratch pages */
+	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
-	dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
+				       dev_priv->gtt.base.start / PAGE_SIZE,
-				      dev_priv->gtt.total / PAGE_SIZE);
+				       dev_priv->gtt.base.total / PAGE_SIZE);
-	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
+	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
-		i915_gem_clflush_object(obj);
+		i915_gem_clflush_object(obj, obj->pin_display);
 		i915_gem_gtt_bind_object(obj, obj->cache_level);
+	}
  * Binds an object into the global gtt with the specified cache level. The object
  * will be accessible to the GPU via commands whose operands reference offsets
  * within the global GTT as well as accessible by the GPU through the GMADR
  * mapped BAR (dev_priv->mm.gtt->gtt).
  */
-static void gen6_ggtt_insert_entries(struct drm_device *dev,
+static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *st,
 				     unsigned int first_entry,
 				  enum i915_cache_level level)
+{
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	gen6_gtt_pte_t __iomem *gtt_entries =
 		(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 	int i = 0;
 	struct sg_page_iter sg_iter;
 	dma_addr_t addr;
 	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 		addr = sg_page_iter_dma_address(&sg_iter);
-		iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]);
+		iowrite32(vm->pte_encode(addr, level), >t_entries[i]);
 			i++;
+		}
 	/* XXX: This serves as a posting read to make sure that the PTE has
 	 * actually been updated. There is some concern that even though
 	 * registers and PTEs are within the same BAR that they are potentially
 	 * of NUMA access patterns. Therefore, even with the way we assume
 	 * hardware should work, we must keep this posting read for paranoia.
 	 */
 	if (i != 0)
-		WARN_ON(readl(>t_entries[i-1])
+		WARN_ON(readl(>t_entries[i-1]) !=
-			!= gen6_pte_encode(dev, addr, level));
+			vm->pte_encode(addr, level));
 	/* This next bit makes the above posting read even more important. We
 	 * want to flush the TLBs only after we're certain all the PTE updates
 	 * have finished.
 	 */
 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+}
-static void gen6_ggtt_clear_range(struct drm_device *dev,
+static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 				  unsigned int first_entry,
 				  unsigned int num_entries)
+{
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 //        "First entry = %d; Num entries = %d (max=%d)\n",
 //        first_entry, num_entries, max_entries))
    if (num_entries > max_entries)
-		num_entries = max_entries;
+        num_entries = max_entries;
-	scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
-				      I915_CACHE_LLC);
+	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
 	for (i = 0; i < num_entries; i++)
 		iowrite32(scratch_pte, >t_base[i]);
 	readl(gtt_base);
 }
-static void i915_ggtt_insert_entries(struct drm_device *dev,
+static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *st,
 				     unsigned int pg_start,
 	intel_gtt_insert_sg_entries(st, pg_start, flags);
+}
-static void i915_ggtt_clear_range(struct drm_device *dev,
+static void i915_ggtt_clear_range(struct i915_address_space *vm,
 				  unsigned int first_entry,
 				  unsigned int num_entries)
 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 				enum i915_cache_level cache_level)
+{
 	struct drm_device *dev = obj->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
-	dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
+	dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
-					    obj->gtt_space->start >> PAGE_SHIFT,
+					  entry,
 					 cache_level);
 	obj->has_global_gtt_mapping = 1;
+}
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
+{
-{
+	struct drm_device *dev = obj->base.dev;
-	struct drm_device *dev = obj->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
-	dev_priv->gtt.gtt_clear_range(obj->base.dev,
+	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 	 * past the end of the object, and we've seen multiple hangs with the
 	 * GPU head pointer stuck in a batchbuffer bound at the last page of the
 	 * aperture.  One page should be enough to keep any prefetching inside
 	 * of the aperture.
 	 */
-	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
 	struct drm_mm_node *entry;
 	struct drm_i915_gem_object *obj;
 	unsigned long hole_start, hole_end;
 	BUG_ON(mappable_end > end);
 	/* Subtract the guard page ... */
-	drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
+	drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
 	if (!HAS_LLC(dev))
-		dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
+		dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
+	/* Mark any preallocated objects as occupied */
+	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
-	/* Mark any preallocated objects as occupied */
+		struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
-	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
+		int ret;
-		DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
+		DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
-			      obj->gtt_offset, obj->base.size);
+			      i915_gem_obj_ggtt_offset(obj), obj->base.size);
-		BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
+		WARN_ON(i915_gem_obj_ggtt_bound(obj));
-		obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
-						     obj->gtt_offset,
+		ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
+		if (ret)
-						     obj->base.size,
+			DRM_DEBUG_KMS("Reservation failed\n");
-						     false);
+		obj->has_global_gtt_mapping = 1;
-		obj->has_global_gtt_mapping = 1;
+		list_add(&vma->vma_link, &obj->vma_list);
+	}
-	dev_priv->gtt.start = start;
+	dev_priv->gtt.base.start = start;
-	dev_priv->gtt.total = end - start;
+	dev_priv->gtt.base.total = end - start;
 	/* Clear any non-preallocated blocks */
-	drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
-			     hole_start, hole_end) {
+	drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
-		DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
+		const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
-			      hole_start, hole_end);
+		DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
-		dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
+			      hole_start, hole_end);
-					      (hole_end-hole_start) / PAGE_SIZE);
+		ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count);
+	}
 void i915_gem_init_global_gtt(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long gtt_size, mappable_size;
-	gtt_size = dev_priv->gtt.total;
+	gtt_size = dev_priv->gtt.base.total;
 	mappable_size = dev_priv->gtt.mappable_end;
 #if 0
 	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 		int ret;
 		if (INTEL_INFO(dev)->gen <= 7) {
 		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
 		 * aperture accordingly when using aliasing ppgtt. */
-        gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
+			gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
+		}
-        i915_gem_setup_global_gtt(dev, LFB_SIZE, mappable_size, gtt_size);
+        i915_gem_setup_global_gtt(dev, LFB_SIZE, mappable_size, gtt_size-LFB_SIZE);
 		ret = i915_gem_init_aliasing_ppgtt(dev);
 		if (!ret)
 			return;
 		DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
-		drm_mm_takedown(&dev_priv->mm.gtt_space);
+		drm_mm_takedown(&dev_priv->gtt.base.mm);
-		gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
+		gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
+}
 	if (pci_dma_mapping_error(dev->pdev, dma_addr))
 		return -EINVAL;
 #else
 	dma_addr = page_to_phys(page);
 #endif
-	dev_priv->gtt.scratch_page = page;
+	dev_priv->gtt.base.scratch.page = page;
-	dev_priv->gtt.scratch_page_dma = dma_addr;
+	dev_priv->gtt.base.scratch.addr = dma_addr;
 	return 0;
+}
 static void teardown_scratch_page(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct page *page = dev_priv->gtt.base.scratch.page;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	set_pages_wb(dev_priv->gtt.scratch_page, 1);
+	set_pages_wb(page, 1);
-	pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
+	pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
 		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-	put_page(dev_priv->gtt.scratch_page);
+	put_page(page);
-	__free_page(dev_priv->gtt.scratch_page);
+	__free_page(page);
+}
 	ret = setup_scratch_page(dev);
 	if (ret)
 		DRM_ERROR("Scratch setup failed\n");
-	dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
+	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
-	dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
+	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
 	return ret;
+}
-}
+static void gen6_gmch_remove(struct i915_address_space *vm)
-static void gen6_gmch_remove(struct drm_device *dev)
+{
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
-	iounmap(dev_priv->gtt.gsm);
+	iounmap(gtt->gsm);
-	teardown_scratch_page(dev_priv->dev);
+	teardown_scratch_page(vm->dev);
+	}
 	intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 	dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
-	dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
+	dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
-	dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
+	dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
 	return 0;
+}
-static void i915_gmch_remove(struct drm_device *dev)
+static void i915_gmch_remove(struct i915_address_space *vm)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_gtt *gtt = &dev_priv->gtt;
 	int ret;
 	if (INTEL_INFO(dev)->gen <= 5) {
-		dev_priv->gtt.gtt_probe = i915_gmch_probe;
+		gtt->gtt_probe = i915_gmch_probe;
-		dev_priv->gtt.gtt_remove = i915_gmch_remove;
+		gtt->base.cleanup = i915_gmch_remove;
 	} else {
-		dev_priv->gtt.gtt_probe = gen6_gmch_probe;
+		gtt->gtt_probe = gen6_gmch_probe;
+		gtt->base.cleanup = gen6_gmch_remove;
+		if (IS_HASWELL(dev) && dev_priv->ellc_size)
+			gtt->base.pte_encode = iris_pte_encode;
+		else if (IS_HASWELL(dev))
+			gtt->base.pte_encode = hsw_pte_encode;
+		else if (IS_VALLEYVIEW(dev))
+			gtt->base.pte_encode = byt_pte_encode;
+		else if (INTEL_INFO(dev)->gen >= 7)
+			gtt->base.pte_encode = ivb_pte_encode;
+		else
-		dev_priv->gtt.gtt_remove = gen6_gmch_remove;
+			gtt->base.pte_encode = snb_pte_encode;
 	}
-	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
-				     &dev_priv->gtt.stolen_size,
-				     >t->mappable_base,
+	ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
-				     >t->mappable_end);
+			     >t->mappable_base, >t->mappable_end);
+	if (ret)
+		return ret;
 	if (ret)
-	return ret;
+	gtt->base.dev = dev;
 	/* GMADR is the PCI mmio aperture into the global GTT. */
-	DRM_INFO("Memory usable by graphics device = %zdM\n",
-		 dev_priv->gtt.total >> 20);
+	DRM_INFO("Memory usable by graphics device = %zdM\n",
-	DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
-			 dev_priv->gtt.mappable_end >> 20);
+		 gtt->base.total >> 20);
-	DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
+	DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
-			 dev_priv->gtt.stolen_size >> 20);
+	DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_gtt.c – Rev 3764 → 4104