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#define iowrite32(v, addr)      writel((v), (addr))

#define AGP_USER_MEMORY         (AGP_USER_TYPES)

#define AGP_USER_CACHED_MEMORY  (AGP_USER_TYPES + 1)

typedef uint32_t gtt_pte_t;

/* PPGTT stuff */

#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))

#define GEN6_PDE_VALID			(1 << 0)

/* gen6+ has bit 11-4 for physical addr bit 39-32 */

#define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)

#define GEN6_PTE_VALID			(1 << 0)

#define GEN6_PTE_UNCACHED		(1 << 1)

#define HSW_PTE_UNCACHED		(0)

#define GEN6_PTE_CACHE_LLC		(2 << 1)

#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)

#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)

static inline gtt_pte_t pte_encode(struct drm_device *dev,

				   dma_addr_t addr,

				   enum i915_cache_level level)

{

	gtt_pte_t pte = GEN6_PTE_VALID;

	pte |= GEN6_PTE_ADDR_ENCODE(addr);

	switch (level) {

	case I915_CACHE_LLC_MLC:

		/* Haswell doesn't set L3 this way */

		if (IS_HASWELL(dev))

			pte |= GEN6_PTE_CACHE_LLC;

		else

			pte |= GEN6_PTE_CACHE_LLC_MLC;

		break;

	case I915_CACHE_LLC:

		pte |= GEN6_PTE_CACHE_LLC;

		break;

	case I915_CACHE_NONE:

		if (IS_HASWELL(dev))

			pte |= HSW_PTE_UNCACHED;

		else

			pte |= GEN6_PTE_UNCACHED;

		break;

	default:

		BUG();

	}

	unsigned i, j, m, segment_len;

	dma_addr_t page_addr;

	struct scatterlist *sg;

	/* init sg walking */

	sg = pages->sgl;

	segment_len = sg_dma_len(sg) >> PAGE_SHIFT;

	m = 0;

    pt_vaddr = AllocKernelSpace(4096);

		return;

	while (i < pages->nents) {

		MapPage(pt_vaddr,(addr_t)ppgtt->pt_pages[act_pd], 3);

						 cache_level);

					break;

void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,

{

	i915_ppgtt_clear_range(ppgtt,

}

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	uint32_t pd_offset;

	uint32_t pd_entry;

	int i;

		return;

	for (i = 0; i < ppgtt->num_pd_entries; i++) {

			pt_addr = ppgtt->pt_dma_addr[i];

		else

			pt_addr = page_to_phys(ppgtt->pt_pages[i]);

		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);

		pd_entry |= GEN6_PDE_VALID;

		writel(pd_entry, pd_addr + i);

	}

	readl(pd_addr);

	pd_offset /= 64; /* in cachelines, */

	pd_offset <<= 16;

	if (INTEL_INFO(dev)->gen == 6) {

		uint32_t ecochk, gab_ctl, ecobits;

		ecobits = I915_READ(GAC_ECO_BITS);

		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);

		gab_ctl = I915_READ(GAB_CTL);

		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);

		ecochk = I915_READ(GAM_ECOCHK);

		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |

				       ECOCHK_PPGTT_CACHE64B);

		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

	} else if (INTEL_INFO(dev)->gen >= 7) {

		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);

static void i915_ggtt_clear_range(struct drm_device *dev,

				 unsigned first_entry,

				 unsigned num_entries)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	gtt_pte_t scratch_pte;

	gtt_pte_t __iomem *gtt_base = dev_priv->mm.gtt->gtt + first_entry;

	const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;

	int i;

	if (INTEL_INFO(dev)->gen < 6) {

		intel_gtt_clear_range(first_entry, num_entries);

		return;

	}

	if (WARN(num_entries > max_entries,

		 "First entry = %d; Num entries = %d (max=%d)\n",

		 first_entry, num_entries, max_entries))

		num_entries = max_entries;

	scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC);

	for (i = 0; i < num_entries; i++)

		iowrite32(scratch_pte, >t_base[i]);

	readl(gtt_base);

}

}

#endif

int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)

{

    struct scatterlist *sg, *s;

    unsigned int nents ;

    int i;

	if (obj->has_dma_mapping)

		return 0;

    sg    = obj->pages->sgl;

    nents = obj->pages->nents;

    WARN_ON(nents == 0 || sg[0].length == 0);

    for_each_sg(sg, s, nents, i) {

             BUG_ON(!sg_page(s));

    asm volatile("lock; addl $0,0(%%esp)": : :"memory");

	return 0;

}

/*

 * Binds an object into the global gtt with the specified cache level. The object

 * will be accessible to the GPU via commands whose operands reference offsets

 * within the global GTT as well as accessible by the GPU through the GMADR

 * mapped BAR (dev_priv->mm.gtt->gtt).

 */

static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,

				  enum i915_cache_level level)

{

	struct drm_device *dev = obj->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct sg_table *st = obj->pages;

	struct scatterlist *sg = st->sgl;

	const int first_entry = obj->gtt_space->start >> PAGE_SHIFT;

	const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;

	gtt_pte_t __iomem *gtt_entries = dev_priv->mm.gtt->gtt + first_entry;

	int unused, i = 0;

	unsigned int len, m = 0;

	dma_addr_t addr;

	for_each_sg(st->sgl, sg, st->nents, unused) {

		len = sg_dma_len(sg) >> PAGE_SHIFT;

		for (m = 0; m < len; m++) {

			addr = sg_dma_address(sg) + (m << PAGE_SHIFT);

			iowrite32(pte_encode(dev, addr, level), >t_entries[i]);

			i++;

		}

	}

	BUG_ON(i > max_entries);

	BUG_ON(i != obj->base.size / PAGE_SIZE);

	/* XXX: This serves as a posting read to make sure that the PTE has

	 * actually been updated. There is some concern that even though

	 * registers and PTEs are within the same BAR that they are potentially

	 * of NUMA access patterns. Therefore, even with the way we assume

	 * hardware should work, we must keep this posting read for paranoia.

	 */

	if (i != 0)

		WARN_ON(readl(>t_entries[i-1]) != pte_encode(dev, addr, level));

	/* This next bit makes the above posting read even more important. We

	 * want to flush the TLBs only after we're certain all the PTE updates

}

void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,

	if (INTEL_INFO(dev)->gen < 6) {

		unsigned int flags = (cache_level == I915_CACHE_NONE) ?

			AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;

		intel_gtt_insert_sg_entries(obj->pages,

	}

}

static int setup_scratch_page(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct page *page;

	dma_addr_t dma_addr;

	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);

	if (page == NULL)

		return -ENOMEM;

#ifdef CONFIG_INTEL_IOMMU

	dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,

				PCI_DMA_BIDIRECTIONAL);

	if (pci_dma_mapping_error(dev->pdev, dma_addr))

		return -EINVAL;

#else

	dma_addr = page_to_phys(page);

#endif

	dev_priv->mm.gtt->scratch_page = page;

	dev_priv->mm.gtt->scratch_page_dma = dma_addr;

	return 0;

}

static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)

{

	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;

	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;

	return snb_gmch_ctl << 20;

}

static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)

{

	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;

	snb_gmch_ctl &= SNB_GMCH_GMS_MASK;

	return snb_gmch_ctl << 25; /* 32 MB units */

}

static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)

{

	static const int stolen_decoder[] = {

		0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};

	snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;

	snb_gmch_ctl &= IVB_GMCH_GMS_MASK;

	return stolen_decoder[snb_gmch_ctl] << 20;

}

int i915_gem_gtt_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	phys_addr_t gtt_bus_addr;

	u16 snb_gmch_ctl;

	int ret;

	/* On modern platforms we need not worry ourself with the legacy

	 * hostbridge query stuff. Skip it entirely

	 */

	if (INTEL_INFO(dev)->gen < 6) {

		ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);

		if (!ret) {

			DRM_ERROR("failed to set up gmch\n");

			return -EIO;

		}

		dev_priv->mm.gtt = intel_gtt_get();

		if (!dev_priv->mm.gtt) {

			DRM_ERROR("Failed to initialize GTT\n");

			return -ENODEV;

		}

		return 0;

	}

	dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL);

	if (!dev_priv->mm.gtt)

		return -ENOMEM;

#ifdef CONFIG_INTEL_IOMMU

	dev_priv->mm.gtt->needs_dmar = 1;

#endif

	/* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */

	gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);

	dev_priv->mm.gtt->gma_bus_addr = pci_resource_start(dev->pdev, 2);

	/* i9xx_setup */

	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);

	dev_priv->mm.gtt->gtt_total_entries =

		gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);

	if (INTEL_INFO(dev)->gen < 7)

		dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);

	else

		dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);

	dev_priv->mm.gtt->gtt_mappable_entries = pci_resource_len(dev->pdev, 2) >> PAGE_SHIFT;

	/* 64/512MB is the current min/max we actually know of, but this is just a

	 * coarse sanity check.

	 */

	if ((dev_priv->mm.gtt->gtt_mappable_entries >> 8) < 64 ||

	    dev_priv->mm.gtt->gtt_mappable_entries > dev_priv->mm.gtt->gtt_total_entries) {

		DRM_ERROR("Unknown GMADR entries (%d)\n",

			  dev_priv->mm.gtt->gtt_mappable_entries);

		ret = -ENXIO;

		goto err_out;

	}

	ret = setup_scratch_page(dev);

	if (ret) {

		DRM_ERROR("Scratch setup failed\n");

		goto err_out;

	}

	dev_priv->mm.gtt->gtt = ioremap(gtt_bus_addr,

					   dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t));

	if (!dev_priv->mm.gtt->gtt) {

		DRM_ERROR("Failed to map the gtt page table\n");

		ret = -ENOMEM;

		goto err_out;

	}

	/* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */

	DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);

	DRM_DEBUG_DRIVER("GMADR size = %dM\n", dev_priv->mm.gtt->gtt_mappable_entries >> 8);

	DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);

	return 0;

err_out:

	kfree(dev_priv->mm.gtt);

	return ret;

}

struct scatterlist *sg_next(struct scatterlist *sg)

{

    if (sg_is_last(sg))

        return NULL;

    sg++;

    if (unlikely(sg_is_chain(sg)))

            sg = sg_chain_ptr(sg);

    return sg;

}

void __sg_free_table(struct sg_table *table, unsigned int max_ents,

                     sg_free_fn *free_fn)

{

    struct scatterlist *sgl, *next;

    if (unlikely(!table->sgl))

            return;

    sgl = table->sgl;

    while (table->orig_nents) {

        unsigned int alloc_size = table->orig_nents;

        unsigned int sg_size;

        /*

         * If we have more than max_ents segments left,

         * then assign 'next' to the sg table after the current one.

         * sg_size is then one less than alloc size, since the last

         * element is the chain pointer.

         */

        if (alloc_size > max_ents) {

                next = sg_chain_ptr(&sgl[max_ents - 1]);

                alloc_size = max_ents;

                sg_size = alloc_size - 1;

        } else {

                sg_size = alloc_size;

                next = NULL;

        }

        table->orig_nents -= sg_size;

        kfree(sgl);

        sgl = next;

    }

    table->sgl = NULL;

}

void sg_free_table(struct sg_table *table)

{

    __sg_free_table(table, SG_MAX_SINGLE_ALLOC, NULL);

}

int sg_alloc_table(struct sg_table *table, unsigned int nents, gfp_t gfp_mask)

{

    struct scatterlist *sg, *prv;

    unsigned int left;

    unsigned int max_ents = SG_MAX_SINGLE_ALLOC;

#ifndef ARCH_HAS_SG_CHAIN

    BUG_ON(nents > max_ents);

#endif

    memset(table, 0, sizeof(*table));

    left = nents;

    prv = NULL;

    do {

        unsigned int sg_size, alloc_size = left;

        if (alloc_size > max_ents) {

                alloc_size = max_ents;

                sg_size = alloc_size - 1;

        } else

                sg_size = alloc_size;

        left -= sg_size;

        sg = kmalloc(alloc_size * sizeof(struct scatterlist), gfp_mask);

        if (unlikely(!sg)) {

                /*

                 * Adjust entry count to reflect that the last

                 * entry of the previous table won't be used for

                 * linkage.  Without this, sg_kfree() may get

                 * confused.

                 */

                if (prv)

                        table->nents = ++table->orig_nents;

                goto err;

        }

        sg_init_table(sg, alloc_size);

        table->nents = table->orig_nents += sg_size;

        /*

         * If this is the first mapping, assign the sg table header.

         * If this is not the first mapping, chain previous part.

         */

        if (prv)

                sg_chain(prv, max_ents, sg);

        else

                table->sgl = sg;

        /*

         * If no more entries after this one, mark the end

         */

        if (!left)

                sg_mark_end(&sg[sg_size - 1]);

        prv = sg;

    } while (left);

    return 0;

err:

    __sg_free_table(table, SG_MAX_SINGLE_ALLOC, NULL);

    return -ENOMEM;

}

void sg_init_table(struct scatterlist *sgl, unsigned int nents)

{

    memset(sgl, 0, sizeof(*sgl) * nents);

#ifdef CONFIG_DEBUG_SG

    {

            unsigned int i;

            for (i = 0; i < nents; i++)

                    sgl[i].sg_magic = SG_MAGIC;

    }

#endif

    sg_mark_end(&sgl[nents - 1]);

}