WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_gem_execbuffer.c

 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
+{
 	return (HAS_LLC(obj->base.dev) ||
-		obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
-		!obj->map_and_fenceable ||
+		obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 		obj->cache_level != I915_CACHE_NONE);
+}
     MapPage(dev_priv->gtt.mappable,dev_priv->gtt.mappable_base +
                                  (offset & PAGE_MASK), PG_SW);
 	reloc_page = dev_priv->gtt.mappable;
 	iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
+//	io_mapping_unmap_atomic(reloc_page);
+	return 0;
+}
+static void
+clflush_write32(void *addr, uint32_t value)
+{
+	/* This is not a fast path, so KISS. */
+	drm_clflush_virt_range(addr, sizeof(uint32_t));
+	*(uint32_t *)addr = value;
+	drm_clflush_virt_range(addr, sizeof(uint32_t));
+}
+static int
+relocate_entry_clflush(struct drm_i915_gem_object *obj,
+		       struct drm_i915_gem_relocation_entry *reloc,
+		       uint64_t target_offset)
+{
+	struct drm_device *dev = obj->base.dev;
+	uint32_t page_offset = offset_in_page(reloc->offset);
+	uint64_t delta = (int)reloc->delta + target_offset;
+	char *vaddr;
+	int ret;
+	ret = i915_gem_object_set_to_gtt_domain(obj, true);
+	if (ret)
+		return ret;
+	vaddr = kmap_atomic(i915_gem_object_get_page(obj,
+				reloc->offset >> PAGE_SHIFT));
+	clflush_write32(vaddr + page_offset, lower_32_bits(delta));
+	if (INTEL_INFO(dev)->gen >= 8) {
+		page_offset = offset_in_page(page_offset + sizeof(uint32_t));
+		if (page_offset == 0) {
+			kunmap_atomic(vaddr);
+			vaddr = kmap_atomic(i915_gem_object_get_page(obj,
+			    (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
+		}
+		clflush_write32(vaddr + page_offset, upper_32_bits(delta));
+	}
 	kunmap_atomic(vaddr);
 	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 	 * pipe_control writes because the gpu doesn't properly redirect them
 	 * through the ppgtt for non_secure batchbuffers. */
 	if (unlikely(IS_GEN6(dev) &&
-	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
-	    !(target_vma->bound & GLOBAL_BIND)))
+	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
-		target_vma->bind_vma(target_vma, target_i915_obj->cache_level,
+		ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
+				    PIN_GLOBAL);
+		if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
+			return ret;
 				GLOBAL_BIND);
 	/* Validate that the target is in a valid r/w GPU domain */
 	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 	/* We can't wait for rendering with pagefaults disabled */
 	if (use_cpu_reloc(obj))
 		ret = relocate_entry_cpu(obj, reloc, target_offset);
+	else if (obj->map_and_fenceable)
+		ret = relocate_entry_gtt(obj, reloc, target_offset);
+    else if (1)
+		ret = relocate_entry_clflush(obj, reloc, target_offset);
+	else {
+		WARN_ONCE(1, "Impossible case in relocation handling\n");
-	else
+		ret = -ENODEV;
 		ret = relocate_entry_gtt(obj, reloc, target_offset);
 //   pagefault_enable();
 	return ret;
+}
+static bool only_mappable_for_reloc(unsigned int flags)
+{
+	return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
+		__EXEC_OBJECT_NEEDS_MAP;
+}
 static int
 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 				struct intel_engine_cs *ring,
-				   bool *need_reloc)
+				bool *need_reloc)
+{
 	struct drm_i915_gem_object *obj = vma->obj;
 	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 	uint64_t flags;
-	int ret;
-	flags = 0;
+	int ret;
 	if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
+	flags = PIN_USER;
+	if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
+		flags |= PIN_GLOBAL;
+	if (!drm_mm_node_allocated(&vma->node)) {
+		/* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
+		 * limit address to the first 4GBs for unflagged objects.
+		 */
+		if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
-		flags |= PIN_GLOBAL | PIN_MAPPABLE;
+			flags |= PIN_ZONE_4G;
-	if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
+		if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
+			flags |= PIN_GLOBAL | PIN_MAPPABLE;
+		if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
+			flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
-		flags |= PIN_GLOBAL;
+		if ((flags & PIN_MAPPABLE) == 0)
+			flags |= PIN_HIGH;
+	}
+	ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
+	if ((ret == -ENOSPC  || ret == -E2BIG) &&
-	if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
+	    only_mappable_for_reloc(entry->flags))
-		flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
+		ret = i915_gem_object_pin(obj, vma->vm,
 					  entry->alignment,
 	if (entry->alignment &&
 	    vma->node.start & (entry->alignment - 1))
-		return true;
-	if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
 		return true;
 	if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
+	    vma->node.start < BATCH_OFFSET_BIAS)
+		return true;
+	/* avoid costly ping-pong once a batch bo ended up non-mappable */
+	if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
+		return !only_mappable_for_reloc(entry->flags);
+	if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
-	    vma->node.start < BATCH_OFFSET_BIAS)
+	    (vma->node.start + vma->node.size - 1) >> 32)
 		return true;
 	return false;
+}
 static int
-static int
+i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
-i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
+			    struct list_head *vmas,
-			    struct list_head *vmas,
+			    struct intel_context *ctx,
 			    bool *need_relocs)
 		vma = list_first_entry(vmas, struct i915_vma, exec_list);
 		obj = vma->obj;
+		entry = vma->exec_entry;
+		if (ctx->flags & CONTEXT_NO_ZEROMAP)
-		entry = vma->exec_entry;
+			entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 		if (!has_fenced_gpu_access)
 			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 		need_fence =
 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 				  struct drm_i915_gem_execbuffer2 *args,
 				  struct drm_file *file,
 				  struct intel_engine_cs *ring,
 				  struct eb_vmas *eb,
-				  struct drm_i915_gem_exec_object2 *exec)
+				  struct drm_i915_gem_exec_object2 *exec,
+				  struct intel_context *ctx)
+{
 	struct drm_i915_gem_relocation_entry *reloc;
 	struct i915_address_space *vm;
 	struct i915_vma *vma;
 	bool need_relocs;
 	total = 0;
 	for (i = 0; i < count; i++)
 		total += exec[i].relocation_count;
-    reloc_offset = malloc(count * sizeof(*reloc_offset));
+    reloc_offset = __builtin_malloc(count * sizeof(*reloc_offset));
-    reloc = malloc(total * sizeof(*reloc));
+    reloc = __builtin_malloc(total * sizeof(*reloc));
 	if (reloc == NULL || reloc_offset == NULL) {
         kfree(reloc);
         kfree(reloc_offset);
 	ret = eb_lookup_vmas(eb, exec, args, vm, file);
 	if (ret)
-			goto err;
+		goto err;
 	need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
-	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
+	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
 	if (ret)
 		goto err;
     kfree(reloc_offset);
 	return ret;
+}
 static int
-i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
+i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
 				struct list_head *vmas)
+{
 	const unsigned other_rings = ~intel_ring_flag(req->ring);
 	struct i915_vma *vma;
 	uint32_t flush_domains = 0;
 	bool flush_chipset = false;
 	int ret;
+	list_for_each_entry(vma, vmas, exec_list) {
+		struct drm_i915_gem_object *obj = vma->obj;
-	list_for_each_entry(vma, vmas, exec_list) {
-		struct drm_i915_gem_object *obj = vma->obj;
+		if (obj->active & other_rings) {
-		ret = i915_gem_object_sync(obj, ring);
+			ret = i915_gem_object_sync(obj, req->ring, &req);
+			if (ret)
-		if (ret)
+				return ret;
 			return ret;
 		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 			flush_chipset |= i915_gem_clflush_object(obj, false);
 		flush_domains |= obj->base.write_domain;
+	}
 	if (flush_chipset)
-		i915_gem_chipset_flush(ring->dev);
+		i915_gem_chipset_flush(req->ring->dev);
 	if (flush_domains & I915_GEM_DOMAIN_GTT)
 		wmb();
 	/* Unconditionally invalidate gpu caches and ensure that we do flush
 	 * any residual writes from the previous batch.
 	 */
+	return intel_ring_invalidate_all_caches(req);
+}
+static bool
+i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
+{
+	if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
+		return false;
+	/* Kernel clipping was a DRI1 misfeature */
+	if (exec->num_cliprects || exec->cliprects_ptr)
-	return intel_ring_invalidate_all_caches(ring);
+		return false;
+	if (exec->DR4 == 0xffffffff) {
+		DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 		exec->DR4 = 0;
+	}
-static bool
+	if (exec->DR1 || exec->DR4)
-i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
+		return false;
 		int length; /* limited by fault_in_pages_readable() */
 		if (exec[i].flags & invalid_flags)
+			return -EINVAL;
+		if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
 			return -EINVAL;
 		/* First check for malicious input causing overflow in
 		 * the worst case where we need to allocate the entire
 		 * relocation tree as a single array.
 		DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
 		return ERR_PTR(-EIO);
+	}
 	if (i915.enable_execlists && !ctx->engine[ring->id].state) {
-		int ret = intel_lr_context_deferred_create(ctx, ring);
+		int ret = intel_lr_context_deferred_alloc(ctx, ring);
 		if (ret) {
 			DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
 			return ERR_PTR(ret);
+		}
 	return ctx;
+}
 void
 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
-				   struct intel_engine_cs *ring)
+				   struct drm_i915_gem_request *req)
 {
-	u32 seqno = intel_ring_get_seqno(ring);
+	struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
 	struct i915_vma *vma;
 	list_for_each_entry(vma, vmas, exec_list) {
 		struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 		struct drm_i915_gem_object *obj = vma->obj;
+		u32 old_read = obj->base.read_domains;
-		u32 old_read = obj->base.read_domains;
+		u32 old_write = obj->base.write_domain;
 		u32 old_write = obj->base.write_domain;
 		obj->dirty = 1; /* be paranoid  */
 		obj->base.write_domain = obj->base.pending_write_domain;
 		if (obj->base.write_domain == 0)
 			obj->base.pending_read_domains |= obj->base.read_domains;
-		obj->base.read_domains = obj->base.pending_read_domains;
+		obj->base.read_domains = obj->base.pending_read_domains;
-		i915_vma_move_to_active(vma, ring);
-		if (obj->base.write_domain) {
+		i915_vma_move_to_active(vma, req);
-			obj->dirty = 1;
+		if (obj->base.write_domain) {
-			obj->last_write_seqno = seqno;
+			i915_gem_request_assign(&obj->last_write_req, req);
-			intel_fb_obj_invalidate(obj, ring);
+			intel_fb_obj_invalidate(obj, ORIGIN_CS);
 			/* update for the implicit flush after a batch */
 			obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+		}
 		if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 		trace_i915_gem_object_change_domain(obj, old_read, old_write);
+	}
+}
 void
-i915_gem_execbuffer_retire_commands(struct drm_device *dev,
-				    struct drm_file *file,
-				    struct intel_engine_cs *ring,
-				    struct drm_i915_gem_object *obj)
+i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
+{
 	/* Unconditionally force add_request to emit a full flush. */
-	ring->gpu_caches_dirty = true;
+	params->ring->gpu_caches_dirty = true;
 	/* Add a breadcrumb for the completion of the batch buffer */
-	(void)__i915_add_request(ring, file, obj, NULL);
+	__i915_add_request(params->request, params->batch_obj, true);
+}
 static int
+i915_reset_gen7_sol_offsets(struct drm_device *dev,
-i915_reset_gen7_sol_offsets(struct drm_device *dev,
+			    struct drm_i915_gem_request *req)
 			    struct intel_engine_cs *ring)
 	struct intel_engine_cs *ring = req->ring;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret, i;
 	if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
 		DRM_DEBUG("sol reset is gen7/rcs only\n");
 		return -EINVAL;
+	}
 	intel_ring_advance(ring);
 	return 0;
 }
+static struct drm_i915_gem_object*
+i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
-static int
+			  struct drm_i915_gem_exec_object2 *shadow_exec_entry,
+			  struct eb_vmas *eb,
+			  struct drm_i915_gem_object *batch_obj,
-i915_emit_box(struct intel_engine_cs *ring,
+			  u32 batch_start_offset,
-	      struct drm_clip_rect *box,
+			  u32 batch_len,
+			  bool is_master)
+{
-	      int DR1, int DR4)
+	struct drm_i915_gem_object *shadow_batch_obj;
-{
+	struct i915_vma *vma;
 	int ret;
-	if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
-	    box->y2 <= 0 || box->x2 <= 0) {
+	shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
-		DRM_ERROR("Bad box %d,%d..%d,%d\n",
-			  box->x1, box->y1, box->x2, box->y2);
+						   PAGE_ALIGN(batch_len));
+	if (IS_ERR(shadow_batch_obj))
-		return -EINVAL;
+		return shadow_batch_obj;
+	ret = i915_parse_cmds(ring,
+			      batch_obj,
 			      shadow_batch_obj,
+			      batch_start_offset,
-	if (INTEL_INFO(ring->dev)->gen >= 4) {
-		ret = intel_ring_begin(ring, 4);
-		if (ret)
-			return ret;
-		intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
+			      batch_len,
-		intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
+			      is_master);
-		intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
+	if (ret)
-		intel_ring_emit(ring, DR4);
+		goto err;
-	} else {
-		ret = intel_ring_begin(ring, 6);
-		if (ret)
-			return ret;
-		intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
-		intel_ring_emit(ring, DR1);
+	ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
+	if (ret)
-		intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
+		goto err;
+	i915_gem_object_unpin_pages(shadow_batch_obj);
+	memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
-		intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
+	vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
+	vma->exec_entry = shadow_exec_entry;
+	vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
+	drm_gem_object_reference(&shadow_batch_obj->base);
+	list_add_tail(&vma->exec_list, &eb->vmas);
+	shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
+	return shadow_batch_obj;
 		intel_ring_emit(ring, DR4);
-		intel_ring_emit(ring, 0);
+err:
-	}
-	intel_ring_advance(ring);
 	i915_gem_object_unpin_pages(shadow_batch_obj);
-	return 0;
+	if (ret == -EACCES) /* unhandled chained batch */
-}
 		return batch_obj;
-int
+	else
+		return ERR_PTR(ret);
 i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
-			     struct intel_engine_cs *ring,
-			     struct intel_context *ctx,
+int
-			     struct drm_i915_gem_execbuffer2 *args,
+i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
-			     struct list_head *vmas,
+			       struct drm_i915_gem_execbuffer2 *args,
-			     struct drm_i915_gem_object *batch_obj,
-			     u64 exec_start, u32 flags)
-{
-	struct drm_clip_rect *cliprects = NULL;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	u64 exec_len;
-	int instp_mode;
-	u32 instp_mask;
-	int i, ret = 0;
-	if (args->num_cliprects != 0) {
-		if (ring != &dev_priv->ring[RCS]) {
-			DRM_DEBUG("clip rectangles are only valid with the render ring\n");
-			return -EINVAL;
-		}
-		if (INTEL_INFO(dev)->gen >= 5) {
-			DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
-			return -EINVAL;
-		}
-		if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
-			DRM_DEBUG("execbuf with %u cliprects\n",
-				  args->num_cliprects);
-			return -EINVAL;
-		}
-		cliprects = kcalloc(args->num_cliprects,
-				    sizeof(*cliprects),
-				    GFP_KERNEL);
-		if (cliprects == NULL) {
-			ret = -ENOMEM;
-			goto error;
-		}
-		if (copy_from_user(cliprects,
-				   to_user_ptr(args->cliprects_ptr),
-				   sizeof(*cliprects)*args->num_cliprects)) {
-			ret = -EFAULT;
-			goto error;
-		}
-	} else {
-		if (args->DR4 == 0xffffffff) {
-			DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
+			       struct list_head *vmas)
 			args->DR4 = 0;
-		}
+	struct drm_device *dev = params->dev;
+	struct intel_engine_cs *ring = params->ring;
-		if (args->DR1 || args->DR4 || args->cliprects_ptr) {
+	struct drm_i915_private *dev_priv = dev->dev_private;
-			DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
+	u64 exec_start, exec_len;
+	int instp_mode;
+	u32 instp_mask;
+	int ret;
 			return -EINVAL;
 	ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
 	if (ret)
 		return ret;
 	ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
-	if (ret)
+	ret = i915_switch_context(params->request);
-		goto error;
+	if (ret)
 		return ret;
-	ret = i915_switch_context(ring, ctx);
-	if (ret)
-		goto error;
+	WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<id),
 	     "%s didn't clear reload\n", ring->name);
 	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
-	instp_mask = I915_EXEC_CONSTANTS_MASK;
+	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
-	switch (instp_mode) {
+	instp_mask = I915_EXEC_CONSTANTS_MASK;
-	case I915_EXEC_CONSTANTS_REL_GENERAL:
-	case I915_EXEC_CONSTANTS_ABSOLUTE:
+	switch (instp_mode) {
-	case I915_EXEC_CONSTANTS_REL_SURFACE:
+	case I915_EXEC_CONSTANTS_REL_GENERAL:
-		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
+	case I915_EXEC_CONSTANTS_ABSOLUTE:
-			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
+	case I915_EXEC_CONSTANTS_REL_SURFACE:
-			ret = -EINVAL;
+		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
-			goto error;
 			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 			return -EINVAL;
 		if (instp_mode != dev_priv->relative_constants_mode) {
 			if (INTEL_INFO(dev)->gen < 4) {
-				DRM_DEBUG("no rel constants on pre-gen4\n");
+		if (instp_mode != dev_priv->relative_constants_mode) {
-				ret = -EINVAL;
+			if (INTEL_INFO(dev)->gen < 4) {
-				goto error;
+				DRM_DEBUG("no rel constants on pre-gen4\n");
 				return -EINVAL;
+			}
-			if (INTEL_INFO(dev)->gen > 5 &&
 			    instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
-				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
+			if (INTEL_INFO(dev)->gen > 5 &&
-				ret = -EINVAL;
+			    instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
-				goto error;
+				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 				return -EINVAL;
+			}
 			/* The HW changed the meaning on this bit on gen6 */
-			if (INTEL_INFO(dev)->gen >= 6)
+			/* The HW changed the meaning on this bit on gen6 */
-				instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
+			if (INTEL_INFO(dev)->gen >= 6)
 				instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 		dev_priv->relative_constants_mode = instp_mode;
+	}
 	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
-		ret = i915_reset_gen7_sol_offsets(dev, ring);
+		ret = i915_reset_gen7_sol_offsets(dev, params->request);
 		if (ret)
-			goto error;
+			return ret;
-	}
+	}
-	exec_len = args->batch_len;
-	if (cliprects) {
-		for (i = 0; i < args->num_cliprects; i++) {
-			ret = i915_emit_box(ring, &cliprects[i],
-					    args->DR1, args->DR4);
-			if (ret)
-				goto error;
-			ret = ring->dispatch_execbuffer(ring,
-							exec_start, exec_len,
-							flags);
-			if (ret)
+	exec_len   = args->batch_len;
-				goto error;
+	exec_start = params->batch_obj_vm_offset +
-		}
+		     params->args_batch_start_offset;
 	} else {
-		ret = ring->dispatch_execbuffer(ring,
+	ret = ring->dispatch_execbuffer(params->request,
-						exec_start, exec_len,
-						flags);
+					exec_start, exec_len,
-		if (ret)
+					params->dispatch_flags);
-			return ret;
+	if (ret)
-	}
-	trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
+		return ret;
-	i915_gem_execbuffer_move_to_active(vmas, ring);
+	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
 	i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 	i915_gem_execbuffer_move_to_active(vmas, params->request);
 		       struct drm_i915_gem_exec_object2 *exec)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct eb_vmas *eb;
 	struct drm_i915_gem_object *batch_obj;
+	struct drm_i915_gem_exec_object2 shadow_exec_entry;
 	struct intel_engine_cs *ring;
 	struct intel_context *ctx;
 	struct i915_address_space *vm;
+	struct i915_execbuffer_params params_master; /* XXX: will be removed later */
+	struct i915_execbuffer_params *params = ¶ms_master;
 	const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
-	u64 exec_start = args->batch_start_offset;
-	u32 flags;
+	u32 dispatch_flags;
 	int ret;
 	bool need_relocs;
 	if (!i915_gem_check_execbuffer(args))
 		return -EINVAL;
 	ret = validate_exec_list(dev, exec, args->buffer_count);
 	if (ret)
 		return ret;
-	flags = 0;
+	dispatch_flags = 0;
 	if (args->flags & I915_EXEC_SECURE) {
-		flags |= I915_DISPATCH_SECURE;
+		dispatch_flags |= I915_DISPATCH_SECURE;
+	}
 	if (args->flags & I915_EXEC_IS_PINNED)
-		flags |= I915_DISPATCH_PINNED;
+		dispatch_flags |= I915_DISPATCH_PINNED;
+	if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
+		DRM_DEBUG("execbuf with unknown ring: %d\n",
+			  (int)(args->flags & I915_EXEC_RING_MASK));
+		return -EINVAL;
+	}
+	if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
-	if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
+	    ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
-		DRM_DEBUG("execbuf with unknown ring: %d\n",
+		DRM_DEBUG("execbuf with non bsd ring but with invalid "
-			  (int)(args->flags & I915_EXEC_RING_MASK));
+			"bsd dispatch flags: %d\n", (int)(args->flags));
 		return -EINVAL;
+	}
+	if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
+		ring = &dev_priv->ring[RCS];
 	else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
-	if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
+		if (HAS_BSD2(dev)) {
+			int ring_id;
+			switch (args->flags & I915_EXEC_BSD_MASK) {
+			case I915_EXEC_BSD_DEFAULT:
+				ring_id = gen8_dispatch_bsd_ring(dev, file);
+				ring = &dev_priv->ring[ring_id];
+				break;
+			case I915_EXEC_BSD_RING1:
+				ring = &dev_priv->ring[VCS];
+				break;
+			case I915_EXEC_BSD_RING2:
+				ring = &dev_priv->ring[VCS2];
-		ring = &dev_priv->ring[RCS];
+				break;
-	else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
+			default:
-		if (HAS_BSD2(dev)) {
+				DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
-			int ring_id;
+					  (int)(args->flags & I915_EXEC_BSD_MASK));
 	if (args->buffer_count < 1) {
 		DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
 		return -EINVAL;
+	}
+	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+		if (!HAS_RESOURCE_STREAMER(dev)) {
+			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
+			return -EINVAL;
+		}
+		if (ring->id != RCS) {
+			DRM_DEBUG("RS is not available on %s\n",
+				 ring->name);
+			return -EINVAL;
+		}
+		dispatch_flags |= I915_DISPATCH_RS;
+	}
 	intel_runtime_pm_get(dev_priv);
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ctx->ppgtt)
 		vm = &ctx->ppgtt->base;
 	else
 		vm = &dev_priv->gtt.base;
+	memset(¶ms_master, 0x00, sizeof(params_master));
 	eb = eb_create(args);
 	if (eb == NULL) {
 		i915_gem_context_unreference(ctx);
 		mutex_unlock(&dev->struct_mutex);
 	/* take note of the batch buffer before we might reorder the lists */
 	batch_obj = eb_get_batch(eb);
 	/* Move the objects en-masse into the GTT, evicting if necessary. */
 	need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
-	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
+	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
 	if (ret)
 		goto err;
 	/* The objects are in their final locations, apply the relocations. */
 	if (need_relocs)
 		ret = i915_gem_execbuffer_relocate(eb);
 	if (ret) {
 		if (ret == -EFAULT) {
 			ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
-								eb, exec);
+								eb, exec, ctx);
 			BUG_ON(!mutex_is_locked(&dev->struct_mutex));
+		}
 		if (ret)
 	if (batch_obj->base.pending_write_domain) {
 		DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
 		ret = -EINVAL;
 		goto err;
+	}
-	batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
+	params->args_batch_start_offset = args->batch_start_offset;
 #if 0
-	if (i915_needs_cmd_parser(ring)) {
+	if (i915_needs_cmd_parser(ring) && args->batch_len) {
+		struct drm_i915_gem_object *parsed_batch_obj;
-		ret = i915_parse_cmds(ring,
+		parsed_batch_obj = i915_gem_execbuffer_parse(ring,
+						      &shadow_exec_entry,
+						      eb,
-				      batch_obj,
+						      batch_obj,
-				      args->batch_start_offset,
+						      args->batch_start_offset,
+						      args->batch_len,
-				      file->is_master);
+						      file->is_master);
-		if (ret) {
+		if (IS_ERR(parsed_batch_obj)) {
-			if (ret != -EACCES)
+			ret = PTR_ERR(parsed_batch_obj);
 			goto err;
-		} else {
+		}
 		/*
-		 * XXX: Actually do this when enabling batch copy...
+		 * parsed_batch_obj == batch_obj means batch not fully parsed:
+		 * Accept, but don't promote to secure.
+		 */
+		if (parsed_batch_obj != batch_obj) {
+			/*
+			 * Batch parsed and accepted:
+			 *
-		 * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
+			 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
-		 * from MI_BATCH_BUFFER_START commands issued in the
+			 * bit from MI_BATCH_BUFFER_START commands issued in
-		 * dispatch_execbuffer implementations. We specifically don't
+			 * the dispatch_execbuffer implementations. We
+			 * specifically don't want that set on batches the
-		 * want that set when the command parser is enabled.
+			 * command parser has accepted.
-		 */
+			 */
+			dispatch_flags |= I915_DISPATCH_SECURE;
+			params->args_batch_start_offset = 0;
+			batch_obj = parsed_batch_obj;
+		}
+	}
 #endif
+	batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
 	/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
 	 * batch" bit. Hence we need to pin secure batches into the global gtt.
 	 * hsw should have this fixed, but bdw mucks it up again. */
-	if (flags & I915_DISPATCH_SECURE) {
+	if (dispatch_flags & I915_DISPATCH_SECURE) {
 		/*
 		 * So on first glance it looks freaky that we pin the batch here
 		 * outside of the reservation loop. But:
 		 * - The batch is already pinned into the relevant ppgtt, so we
 		 *   already have the backing storage fully allocated.
 		 * - No other BO uses the global gtt (well contexts, but meh),
-		 *   so we don't really have issues with mutliple objects not
+		 *   so we don't really have issues with multiple objects not
 		 *   fitting due to fragmentation.
 		 * So this is actually safe.
 		 */
 		ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
 		if (ret)
 			goto err;
-		exec_start += i915_gem_obj_ggtt_offset(batch_obj);
+		params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
 	} else
+		params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
+	/* Allocate a request for this batch buffer nice and early. */
+	ret = i915_gem_request_alloc(ring, ctx, ¶ms->request);
+	if (ret)
+		goto err_batch_unpin;
+	ret = i915_gem_request_add_to_client(params->request, file);
+	if (ret)
+		goto err_batch_unpin;
+	/*
+	 * Save assorted stuff away to pass through to *_submission().
+	 * NB: This data should be 'persistent' and not local as it will
+	 * kept around beyond the duration of the IOCTL once the GPU
+	 * scheduler arrives.
+	 */
+	params->dev                     = dev;
+	params->file                    = file;
+	params->ring                    = ring;
+	params->dispatch_flags          = dispatch_flags;
+	params->batch_obj               = batch_obj;
-		exec_start += i915_gem_obj_offset(batch_obj, vm);
+	params->ctx                     = ctx;
-	ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args,
+	ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
 				      &eb->vmas, batch_obj, exec_start, flags);
 err_batch_unpin:
 	/*
 	 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
 	 * batch vma for correctness. For less ugly and less fragility this
 	 * needs to be adjusted to also track the ggtt batch vma properly as
 	 * active.
+	 */
-	 */
+	if (dispatch_flags & I915_DISPATCH_SECURE)
-	if (flags & I915_DISPATCH_SECURE)
+		i915_gem_object_ggtt_unpin(batch_obj);
 		i915_gem_object_ggtt_unpin(batch_obj);
 err:
+	/* the request owns the ref now */
+	i915_gem_context_unreference(ctx);
+	eb_destroy(eb);
+	/*
+	 * If the request was created but not successfully submitted then it
+	 * must be freed again. If it was submitted then it is being tracked
+	 * on the active request list and no clean up is required here.
-	/* the request owns the ref now */
+	 */
-	i915_gem_context_unreference(ctx);
+	if (ret && params->request)
-	eb_destroy(eb);
+		i915_gem_request_cancel(params->request);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_gem_execbuffer.c – Rev 5367 → 6084