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1 | /* |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation |
2 | * Copyright © 2011-2012 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Ben Widawsky |
24 | * Ben Widawsky |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | /* |
28 | /* |
29 | * This file implements HW context support. On gen5+ a HW context consists of an |
29 | * This file implements HW context support. On gen5+ a HW context consists of an |
30 | * opaque GPU object which is referenced at times of context saves and restores. |
30 | * opaque GPU object which is referenced at times of context saves and restores. |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
33 | * something like a context does exist for the media ring, the code only |
33 | * something like a context does exist for the media ring, the code only |
34 | * supports contexts for the render ring. |
34 | * supports contexts for the render ring. |
35 | * |
35 | * |
36 | * In software, there is a distinction between contexts created by the user, |
36 | * In software, there is a distinction between contexts created by the user, |
37 | * and the default HW context. The default HW context is used by GPU clients |
37 | * and the default HW context. The default HW context is used by GPU clients |
38 | * that do not request setup of their own hardware context. The default |
38 | * that do not request setup of their own hardware context. The default |
39 | * context's state is never restored to help prevent programming errors. This |
39 | * context's state is never restored to help prevent programming errors. This |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
41 | * The default context only exists to give the GPU some offset to load as the |
41 | * The default context only exists to give the GPU some offset to load as the |
42 | * current to invoke a save of the context we actually care about. In fact, the |
42 | * current to invoke a save of the context we actually care about. In fact, the |
43 | * code could likely be constructed, albeit in a more complicated fashion, to |
43 | * code could likely be constructed, albeit in a more complicated fashion, to |
44 | * never use the default context, though that limits the driver's ability to |
44 | * never use the default context, though that limits the driver's ability to |
45 | * swap out, and/or destroy other contexts. |
45 | * swap out, and/or destroy other contexts. |
46 | * |
46 | * |
47 | * All other contexts are created as a request by the GPU client. These contexts |
47 | * All other contexts are created as a request by the GPU client. These contexts |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
49 | * potentially query certain state) at any time. The kernel driver makes |
49 | * potentially query certain state) at any time. The kernel driver makes |
50 | * certain that the appropriate commands are inserted. |
50 | * certain that the appropriate commands are inserted. |
51 | * |
51 | * |
52 | * The context life cycle is semi-complicated in that context BOs may live |
52 | * The context life cycle is semi-complicated in that context BOs may live |
53 | * longer than the context itself because of the way the hardware, and object |
53 | * longer than the context itself because of the way the hardware, and object |
54 | * tracking works. Below is a very crude representation of the state machine |
54 | * tracking works. Below is a very crude representation of the state machine |
55 | * describing the context life. |
55 | * describing the context life. |
56 | * refcount pincount active |
56 | * refcount pincount active |
57 | * S0: initial state 0 0 0 |
57 | * S0: initial state 0 0 0 |
58 | * S1: context created 1 0 0 |
58 | * S1: context created 1 0 0 |
59 | * S2: context is currently running 2 1 X |
59 | * S2: context is currently running 2 1 X |
60 | * S3: GPU referenced, but not current 2 0 1 |
60 | * S3: GPU referenced, but not current 2 0 1 |
61 | * S4: context is current, but destroyed 1 1 0 |
61 | * S4: context is current, but destroyed 1 1 0 |
62 | * S5: like S3, but destroyed 1 0 1 |
62 | * S5: like S3, but destroyed 1 0 1 |
63 | * |
63 | * |
64 | * The most common (but not all) transitions: |
64 | * The most common (but not all) transitions: |
65 | * S0->S1: client creates a context |
65 | * S0->S1: client creates a context |
66 | * S1->S2: client submits execbuf with context |
66 | * S1->S2: client submits execbuf with context |
67 | * S2->S3: other clients submits execbuf with context |
67 | * S2->S3: other clients submits execbuf with context |
68 | * S3->S1: context object was retired |
68 | * S3->S1: context object was retired |
69 | * S3->S2: clients submits another execbuf |
69 | * S3->S2: clients submits another execbuf |
70 | * S2->S4: context destroy called with current context |
70 | * S2->S4: context destroy called with current context |
71 | * S3->S5->S0: destroy path |
71 | * S3->S5->S0: destroy path |
72 | * S4->S5->S0: destroy path on current context |
72 | * S4->S5->S0: destroy path on current context |
73 | * |
73 | * |
74 | * There are two confusing terms used above: |
74 | * There are two confusing terms used above: |
75 | * The "current context" means the context which is currently running on the |
75 | * The "current context" means the context which is currently running on the |
76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this |
78 | * offset, but it will on the next context switch. The only way to avoid this |
79 | * is to do a GPU reset. |
79 | * is to do a GPU reset. |
80 | * |
80 | * |
81 | * An "active context' is one which was previously the "current context" and is |
81 | * An "active context' is one which was previously the "current context" and is |
82 | * on the active list waiting for the next context switch to occur. Until this |
82 | * on the active list waiting for the next context switch to occur. Until this |
83 | * happens, the object must remain at the same gtt offset. It is therefore |
83 | * happens, the object must remain at the same gtt offset. It is therefore |
84 | * possible to destroy a context, but it is still active. |
84 | * possible to destroy a context, but it is still active. |
85 | * |
85 | * |
86 | */ |
86 | */ |
87 | 87 | ||
88 | #include |
88 | #include |
89 | #include |
89 | #include |
90 | #include "i915_drv.h" |
90 | #include "i915_drv.h" |
91 | #include "i915_trace.h" |
91 | #include "i915_trace.h" |
92 | 92 | ||
93 | /* This is a HW constraint. The value below is the largest known requirement |
93 | /* This is a HW constraint. The value below is the largest known requirement |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
95 | * part. It should be safe to decrease this, but it's more future proof as is. |
95 | * part. It should be safe to decrease this, but it's more future proof as is. |
96 | */ |
96 | */ |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 |
98 | #define GEN7_CONTEXT_ALIGN 4096 |
99 | 99 | ||
100 | static size_t get_context_alignment(struct drm_device *dev) |
100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { |
101 | { |
102 | if (IS_GEN6(dev)) |
102 | if (IS_GEN6(dev)) |
103 | return GEN6_CONTEXT_ALIGN; |
103 | return GEN6_CONTEXT_ALIGN; |
104 | 104 | ||
105 | return GEN7_CONTEXT_ALIGN; |
105 | return GEN7_CONTEXT_ALIGN; |
106 | } |
106 | } |
107 | 107 | ||
108 | static int get_context_size(struct drm_device *dev) |
108 | static int get_context_size(struct drm_device *dev) |
109 | { |
109 | { |
110 | struct drm_i915_private *dev_priv = dev->dev_private; |
110 | struct drm_i915_private *dev_priv = dev->dev_private; |
111 | int ret; |
111 | int ret; |
112 | u32 reg; |
112 | u32 reg; |
113 | 113 | ||
114 | switch (INTEL_INFO(dev)->gen) { |
114 | switch (INTEL_INFO(dev)->gen) { |
115 | case 6: |
115 | case 6: |
116 | reg = I915_READ(CXT_SIZE); |
116 | reg = I915_READ(CXT_SIZE); |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
118 | break; |
118 | break; |
119 | case 7: |
119 | case 7: |
120 | reg = I915_READ(GEN7_CXT_SIZE); |
120 | reg = I915_READ(GEN7_CXT_SIZE); |
121 | if (IS_HASWELL(dev)) |
121 | if (IS_HASWELL(dev)) |
122 | ret = HSW_CXT_TOTAL_SIZE; |
122 | ret = HSW_CXT_TOTAL_SIZE; |
123 | else |
123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
125 | break; |
125 | break; |
126 | case 8: |
126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; |
127 | ret = GEN8_CXT_TOTAL_SIZE; |
128 | break; |
128 | break; |
129 | default: |
129 | default: |
130 | BUG(); |
130 | BUG(); |
131 | } |
131 | } |
132 | 132 | ||
133 | return ret; |
133 | return ret; |
134 | } |
134 | } |
135 | 135 | ||
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
137 | { |
137 | { |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
139 | struct i915_vma *vma, *next; |
139 | struct i915_vma *vma, *next; |
140 | 140 | ||
141 | if (!ppgtt) |
141 | if (!ppgtt) |
142 | return; |
142 | return; |
143 | 143 | ||
144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
145 | mm_list) { |
145 | mm_list) { |
146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
147 | break; |
147 | break; |
148 | } |
148 | } |
149 | } |
149 | } |
150 | 150 | ||
151 | void i915_gem_context_free(struct kref *ctx_ref) |
151 | void i915_gem_context_free(struct kref *ctx_ref) |
152 | { |
152 | { |
153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
154 | 154 | ||
155 | trace_i915_context_free(ctx); |
155 | trace_i915_context_free(ctx); |
156 | 156 | ||
157 | if (i915.enable_execlists) |
157 | if (i915.enable_execlists) |
158 | intel_lr_context_free(ctx); |
158 | intel_lr_context_free(ctx); |
159 | 159 | ||
160 | /* |
160 | /* |
161 | * This context is going away and we need to remove all VMAs still |
161 | * This context is going away and we need to remove all VMAs still |
162 | * around. This is to handle imported shared objects for which |
162 | * around. This is to handle imported shared objects for which |
163 | * destructor did not run when their handles were closed. |
163 | * destructor did not run when their handles were closed. |
164 | */ |
164 | */ |
165 | i915_gem_context_clean(ctx); |
165 | i915_gem_context_clean(ctx); |
166 | 166 | ||
167 | i915_ppgtt_put(ctx->ppgtt); |
167 | i915_ppgtt_put(ctx->ppgtt); |
168 | 168 | ||
169 | if (ctx->legacy_hw_ctx.rcs_state) |
169 | if (ctx->legacy_hw_ctx.rcs_state) |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
171 | list_del(&ctx->link); |
171 | list_del(&ctx->link); |
172 | kfree(ctx); |
172 | kfree(ctx); |
173 | } |
173 | } |
174 | 174 | ||
175 | struct drm_i915_gem_object * |
175 | struct drm_i915_gem_object * |
176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
177 | { |
177 | { |
178 | struct drm_i915_gem_object *obj; |
178 | struct drm_i915_gem_object *obj; |
179 | int ret; |
179 | int ret; |
180 | 180 | ||
181 | obj = i915_gem_alloc_object(dev, size); |
181 | obj = i915_gem_alloc_object(dev, size); |
182 | if (obj == NULL) |
182 | if (obj == NULL) |
183 | return ERR_PTR(-ENOMEM); |
183 | return ERR_PTR(-ENOMEM); |
184 | 184 | ||
185 | /* |
185 | /* |
186 | * Try to make the context utilize L3 as well as LLC. |
186 | * Try to make the context utilize L3 as well as LLC. |
187 | * |
187 | * |
188 | * On VLV we don't have L3 controls in the PTEs so we |
188 | * On VLV we don't have L3 controls in the PTEs so we |
189 | * shouldn't touch the cache level, especially as that |
189 | * shouldn't touch the cache level, especially as that |
190 | * would make the object snooped which might have a |
190 | * would make the object snooped which might have a |
191 | * negative performance impact. |
191 | * negative performance impact. |
- | 192 | * |
|
- | 193 | * Snooping is required on non-llc platforms in execlist |
|
- | 194 | * mode, but since all GGTT accesses use PAT entry 0 we |
|
- | 195 | * get snooping anyway regardless of cache_level. |
|
- | 196 | * |
|
- | 197 | * This is only applicable for Ivy Bridge devices since |
|
- | 198 | * later platforms don't have L3 control bits in the PTE. |
|
192 | */ |
199 | */ |
193 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { |
200 | if (IS_IVYBRIDGE(dev)) { |
194 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
201 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
195 | /* Failure shouldn't ever happen this early */ |
202 | /* Failure shouldn't ever happen this early */ |
196 | if (WARN_ON(ret)) { |
203 | if (WARN_ON(ret)) { |
197 | drm_gem_object_unreference(&obj->base); |
204 | drm_gem_object_unreference(&obj->base); |
198 | return ERR_PTR(ret); |
205 | return ERR_PTR(ret); |
199 | } |
206 | } |
200 | } |
207 | } |
201 | 208 | ||
202 | return obj; |
209 | return obj; |
203 | } |
210 | } |
204 | 211 | ||
205 | static struct intel_context * |
212 | static struct intel_context * |
206 | __create_hw_context(struct drm_device *dev, |
213 | __create_hw_context(struct drm_device *dev, |
207 | struct drm_i915_file_private *file_priv) |
214 | struct drm_i915_file_private *file_priv) |
208 | { |
215 | { |
209 | struct drm_i915_private *dev_priv = dev->dev_private; |
216 | struct drm_i915_private *dev_priv = dev->dev_private; |
210 | struct intel_context *ctx; |
217 | struct intel_context *ctx; |
211 | int ret; |
218 | int ret; |
212 | 219 | ||
213 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
220 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
214 | if (ctx == NULL) |
221 | if (ctx == NULL) |
215 | return ERR_PTR(-ENOMEM); |
222 | return ERR_PTR(-ENOMEM); |
216 | 223 | ||
217 | kref_init(&ctx->ref); |
224 | kref_init(&ctx->ref); |
218 | list_add_tail(&ctx->link, &dev_priv->context_list); |
225 | list_add_tail(&ctx->link, &dev_priv->context_list); |
219 | ctx->i915 = dev_priv; |
226 | ctx->i915 = dev_priv; |
220 | 227 | ||
221 | if (dev_priv->hw_context_size) { |
228 | if (dev_priv->hw_context_size) { |
222 | struct drm_i915_gem_object *obj = |
229 | struct drm_i915_gem_object *obj = |
223 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
230 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
224 | if (IS_ERR(obj)) { |
231 | if (IS_ERR(obj)) { |
225 | ret = PTR_ERR(obj); |
232 | ret = PTR_ERR(obj); |
226 | goto err_out; |
233 | goto err_out; |
227 | } |
234 | } |
228 | ctx->legacy_hw_ctx.rcs_state = obj; |
235 | ctx->legacy_hw_ctx.rcs_state = obj; |
229 | } |
236 | } |
230 | 237 | ||
231 | /* Default context will never have a file_priv */ |
238 | /* Default context will never have a file_priv */ |
232 | if (file_priv != NULL) { |
239 | if (file_priv != NULL) { |
233 | ret = idr_alloc(&file_priv->context_idr, ctx, |
240 | ret = idr_alloc(&file_priv->context_idr, ctx, |
234 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
241 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
235 | if (ret < 0) |
242 | if (ret < 0) |
236 | goto err_out; |
243 | goto err_out; |
237 | } else |
244 | } else |
238 | ret = DEFAULT_CONTEXT_HANDLE; |
245 | ret = DEFAULT_CONTEXT_HANDLE; |
239 | 246 | ||
240 | ctx->file_priv = file_priv; |
247 | ctx->file_priv = file_priv; |
241 | ctx->user_handle = ret; |
248 | ctx->user_handle = ret; |
242 | /* NB: Mark all slices as needing a remap so that when the context first |
249 | /* NB: Mark all slices as needing a remap so that when the context first |
243 | * loads it will restore whatever remap state already exists. If there |
250 | * loads it will restore whatever remap state already exists. If there |
244 | * is no remap info, it will be a NOP. */ |
251 | * is no remap info, it will be a NOP. */ |
245 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
252 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
246 | 253 | ||
247 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
254 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
248 | 255 | ||
249 | return ctx; |
256 | return ctx; |
250 | 257 | ||
251 | err_out: |
258 | err_out: |
252 | i915_gem_context_unreference(ctx); |
259 | i915_gem_context_unreference(ctx); |
253 | return ERR_PTR(ret); |
260 | return ERR_PTR(ret); |
254 | } |
261 | } |
255 | 262 | ||
256 | /** |
263 | /** |
257 | * The default context needs to exist per ring that uses contexts. It stores the |
264 | * The default context needs to exist per ring that uses contexts. It stores the |
258 | * context state of the GPU for applications that don't utilize HW contexts, as |
265 | * context state of the GPU for applications that don't utilize HW contexts, as |
259 | * well as an idle case. |
266 | * well as an idle case. |
260 | */ |
267 | */ |
261 | static struct intel_context * |
268 | static struct intel_context * |
262 | i915_gem_create_context(struct drm_device *dev, |
269 | i915_gem_create_context(struct drm_device *dev, |
263 | struct drm_i915_file_private *file_priv) |
270 | struct drm_i915_file_private *file_priv) |
264 | { |
271 | { |
265 | const bool is_global_default_ctx = file_priv == NULL; |
272 | const bool is_global_default_ctx = file_priv == NULL; |
266 | struct intel_context *ctx; |
273 | struct intel_context *ctx; |
267 | int ret = 0; |
274 | int ret = 0; |
268 | 275 | ||
269 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
276 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
270 | 277 | ||
271 | ctx = __create_hw_context(dev, file_priv); |
278 | ctx = __create_hw_context(dev, file_priv); |
272 | if (IS_ERR(ctx)) |
279 | if (IS_ERR(ctx)) |
273 | return ctx; |
280 | return ctx; |
274 | 281 | ||
275 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
282 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
276 | /* We may need to do things with the shrinker which |
283 | /* We may need to do things with the shrinker which |
277 | * require us to immediately switch back to the default |
284 | * require us to immediately switch back to the default |
278 | * context. This can cause a problem as pinning the |
285 | * context. This can cause a problem as pinning the |
279 | * default context also requires GTT space which may not |
286 | * default context also requires GTT space which may not |
280 | * be available. To avoid this we always pin the default |
287 | * be available. To avoid this we always pin the default |
281 | * context. |
288 | * context. |
282 | */ |
289 | */ |
283 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
290 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
284 | get_context_alignment(dev), 0); |
291 | get_context_alignment(dev), 0); |
285 | if (ret) { |
292 | if (ret) { |
286 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
293 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
287 | goto err_destroy; |
294 | goto err_destroy; |
288 | } |
295 | } |
289 | } |
296 | } |
290 | 297 | ||
291 | if (USES_FULL_PPGTT(dev)) { |
298 | if (USES_FULL_PPGTT(dev)) { |
292 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
299 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
293 | 300 | ||
294 | if (IS_ERR_OR_NULL(ppgtt)) { |
301 | if (IS_ERR_OR_NULL(ppgtt)) { |
295 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
302 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
296 | PTR_ERR(ppgtt)); |
303 | PTR_ERR(ppgtt)); |
297 | ret = PTR_ERR(ppgtt); |
304 | ret = PTR_ERR(ppgtt); |
298 | goto err_unpin; |
305 | goto err_unpin; |
299 | } |
306 | } |
300 | 307 | ||
301 | ctx->ppgtt = ppgtt; |
308 | ctx->ppgtt = ppgtt; |
302 | } |
309 | } |
303 | 310 | ||
304 | trace_i915_context_create(ctx); |
311 | trace_i915_context_create(ctx); |
305 | 312 | ||
306 | return ctx; |
313 | return ctx; |
307 | 314 | ||
308 | err_unpin: |
315 | err_unpin: |
309 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
316 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
310 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
317 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
311 | err_destroy: |
318 | err_destroy: |
312 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
319 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
313 | i915_gem_context_unreference(ctx); |
320 | i915_gem_context_unreference(ctx); |
314 | return ERR_PTR(ret); |
321 | return ERR_PTR(ret); |
315 | } |
322 | } |
316 | 323 | ||
317 | void i915_gem_context_reset(struct drm_device *dev) |
324 | void i915_gem_context_reset(struct drm_device *dev) |
318 | { |
325 | { |
319 | struct drm_i915_private *dev_priv = dev->dev_private; |
326 | struct drm_i915_private *dev_priv = dev->dev_private; |
320 | int i; |
327 | int i; |
321 | 328 | ||
322 | if (i915.enable_execlists) { |
329 | if (i915.enable_execlists) { |
323 | struct intel_context *ctx; |
330 | struct intel_context *ctx; |
324 | 331 | ||
325 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
332 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
326 | intel_lr_context_reset(dev, ctx); |
333 | intel_lr_context_reset(dev, ctx); |
327 | } |
334 | } |
328 | 335 | ||
329 | return; |
336 | return; |
330 | } |
337 | } |
331 | 338 | ||
332 | for (i = 0; i < I915_NUM_RINGS; i++) { |
339 | for (i = 0; i < I915_NUM_RINGS; i++) { |
333 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
340 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
334 | struct intel_context *lctx = ring->last_context; |
341 | struct intel_context *lctx = ring->last_context; |
335 | 342 | ||
336 | if (lctx) { |
343 | if (lctx) { |
337 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
344 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
338 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); |
345 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); |
339 | 346 | ||
340 | i915_gem_context_unreference(lctx); |
347 | i915_gem_context_unreference(lctx); |
341 | ring->last_context = NULL; |
348 | ring->last_context = NULL; |
342 | } |
349 | } |
343 | 350 | ||
344 | /* Force the GPU state to be reinitialised on enabling */ |
351 | /* Force the GPU state to be reinitialised on enabling */ |
345 | if (ring->default_context) |
352 | if (ring->default_context) |
346 | ring->default_context->legacy_hw_ctx.initialized = false; |
353 | ring->default_context->legacy_hw_ctx.initialized = false; |
347 | } |
354 | } |
348 | } |
355 | } |
349 | 356 | ||
350 | int i915_gem_context_init(struct drm_device *dev) |
357 | int i915_gem_context_init(struct drm_device *dev) |
351 | { |
358 | { |
352 | struct drm_i915_private *dev_priv = dev->dev_private; |
359 | struct drm_i915_private *dev_priv = dev->dev_private; |
353 | struct intel_context *ctx; |
360 | struct intel_context *ctx; |
354 | int i; |
361 | int i; |
355 | 362 | ||
356 | /* Init should only be called once per module load. Eventually the |
363 | /* Init should only be called once per module load. Eventually the |
357 | * restriction on the context_disabled check can be loosened. */ |
364 | * restriction on the context_disabled check can be loosened. */ |
358 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
365 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
359 | return 0; |
366 | return 0; |
360 | 367 | ||
361 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
368 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
362 | if (!i915.enable_execlists) { |
369 | if (!i915.enable_execlists) { |
363 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); |
370 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); |
364 | return -EINVAL; |
371 | return -EINVAL; |
365 | } |
372 | } |
366 | } |
373 | } |
367 | 374 | ||
368 | if (i915.enable_execlists) { |
375 | if (i915.enable_execlists) { |
369 | /* NB: intentionally left blank. We will allocate our own |
376 | /* NB: intentionally left blank. We will allocate our own |
370 | * backing objects as we need them, thank you very much */ |
377 | * backing objects as we need them, thank you very much */ |
371 | dev_priv->hw_context_size = 0; |
378 | dev_priv->hw_context_size = 0; |
372 | } else if (HAS_HW_CONTEXTS(dev)) { |
379 | } else if (HAS_HW_CONTEXTS(dev)) { |
373 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
380 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
374 | if (dev_priv->hw_context_size > (1<<20)) { |
381 | if (dev_priv->hw_context_size > (1<<20)) { |
375 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
382 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
376 | dev_priv->hw_context_size); |
383 | dev_priv->hw_context_size); |
377 | dev_priv->hw_context_size = 0; |
384 | dev_priv->hw_context_size = 0; |
378 | } |
385 | } |
379 | } |
386 | } |
380 | 387 | ||
381 | ctx = i915_gem_create_context(dev, NULL); |
388 | ctx = i915_gem_create_context(dev, NULL); |
382 | if (IS_ERR(ctx)) { |
389 | if (IS_ERR(ctx)) { |
383 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
390 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
384 | PTR_ERR(ctx)); |
391 | PTR_ERR(ctx)); |
385 | return PTR_ERR(ctx); |
392 | return PTR_ERR(ctx); |
386 | } |
393 | } |
387 | 394 | ||
388 | for (i = 0; i < I915_NUM_RINGS; i++) { |
395 | for (i = 0; i < I915_NUM_RINGS; i++) { |
389 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
396 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
390 | 397 | ||
391 | /* NB: RCS will hold a ref for all rings */ |
398 | /* NB: RCS will hold a ref for all rings */ |
392 | ring->default_context = ctx; |
399 | ring->default_context = ctx; |
393 | } |
400 | } |
394 | 401 | ||
395 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
402 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
396 | i915.enable_execlists ? "LR" : |
403 | i915.enable_execlists ? "LR" : |
397 | dev_priv->hw_context_size ? "HW" : "fake"); |
404 | dev_priv->hw_context_size ? "HW" : "fake"); |
398 | return 0; |
405 | return 0; |
399 | } |
406 | } |
400 | 407 | ||
401 | void i915_gem_context_fini(struct drm_device *dev) |
408 | void i915_gem_context_fini(struct drm_device *dev) |
402 | { |
409 | { |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
410 | struct drm_i915_private *dev_priv = dev->dev_private; |
404 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
411 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
405 | int i; |
412 | int i; |
406 | 413 | ||
407 | if (dctx->legacy_hw_ctx.rcs_state) { |
414 | if (dctx->legacy_hw_ctx.rcs_state) { |
408 | /* The only known way to stop the gpu from accessing the hw context is |
415 | /* The only known way to stop the gpu from accessing the hw context is |
409 | * to reset it. Do this as the very last operation to avoid confusing |
416 | * to reset it. Do this as the very last operation to avoid confusing |
410 | * other code, leading to spurious errors. */ |
417 | * other code, leading to spurious errors. */ |
411 | intel_gpu_reset(dev); |
418 | intel_gpu_reset(dev); |
412 | 419 | ||
413 | /* When default context is created and switched to, base object refcount |
420 | /* When default context is created and switched to, base object refcount |
414 | * will be 2 (+1 from object creation and +1 from do_switch()). |
421 | * will be 2 (+1 from object creation and +1 from do_switch()). |
415 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
422 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
416 | * to default context. So we need to unreference the base object once |
423 | * to default context. So we need to unreference the base object once |
417 | * to offset the do_switch part, so that i915_gem_context_unreference() |
424 | * to offset the do_switch part, so that i915_gem_context_unreference() |
418 | * can then free the base object correctly. */ |
425 | * can then free the base object correctly. */ |
419 | WARN_ON(!dev_priv->ring[RCS].last_context); |
426 | WARN_ON(!dev_priv->ring[RCS].last_context); |
420 | if (dev_priv->ring[RCS].last_context == dctx) { |
427 | if (dev_priv->ring[RCS].last_context == dctx) { |
421 | /* Fake switch to NULL context */ |
428 | /* Fake switch to NULL context */ |
422 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
429 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
423 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
430 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
424 | i915_gem_context_unreference(dctx); |
431 | i915_gem_context_unreference(dctx); |
425 | dev_priv->ring[RCS].last_context = NULL; |
432 | dev_priv->ring[RCS].last_context = NULL; |
426 | } |
433 | } |
427 | 434 | ||
428 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
435 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
429 | } |
436 | } |
430 | 437 | ||
431 | for (i = 0; i < I915_NUM_RINGS; i++) { |
438 | for (i = 0; i < I915_NUM_RINGS; i++) { |
432 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
439 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
433 | 440 | ||
434 | if (ring->last_context) |
441 | if (ring->last_context) |
435 | i915_gem_context_unreference(ring->last_context); |
442 | i915_gem_context_unreference(ring->last_context); |
436 | 443 | ||
437 | ring->default_context = NULL; |
444 | ring->default_context = NULL; |
438 | ring->last_context = NULL; |
445 | ring->last_context = NULL; |
439 | } |
446 | } |
440 | 447 | ||
441 | i915_gem_context_unreference(dctx); |
448 | i915_gem_context_unreference(dctx); |
442 | } |
449 | } |
443 | 450 | ||
444 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
451 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
445 | { |
452 | { |
446 | struct intel_engine_cs *ring = req->ring; |
453 | struct intel_engine_cs *ring = req->ring; |
447 | int ret; |
454 | int ret; |
448 | 455 | ||
449 | if (i915.enable_execlists) { |
456 | if (i915.enable_execlists) { |
450 | if (ring->init_context == NULL) |
457 | if (ring->init_context == NULL) |
451 | return 0; |
458 | return 0; |
452 | 459 | ||
453 | ret = ring->init_context(req); |
460 | ret = ring->init_context(req); |
454 | } else |
461 | } else |
455 | ret = i915_switch_context(req); |
462 | ret = i915_switch_context(req); |
456 | 463 | ||
457 | if (ret) { |
464 | if (ret) { |
458 | DRM_ERROR("ring init context: %d\n", ret); |
465 | DRM_ERROR("ring init context: %d\n", ret); |
459 | return ret; |
466 | return ret; |
460 | } |
467 | } |
461 | 468 | ||
462 | return 0; |
469 | return 0; |
463 | } |
470 | } |
464 | 471 | ||
465 | static int context_idr_cleanup(int id, void *p, void *data) |
472 | static int context_idr_cleanup(int id, void *p, void *data) |
466 | { |
473 | { |
467 | struct intel_context *ctx = p; |
474 | struct intel_context *ctx = p; |
468 | 475 | ||
469 | i915_gem_context_unreference(ctx); |
476 | i915_gem_context_unreference(ctx); |
470 | return 0; |
477 | return 0; |
471 | } |
478 | } |
472 | 479 | ||
473 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
480 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
474 | { |
481 | { |
475 | struct drm_i915_file_private *file_priv = file->driver_priv; |
482 | struct drm_i915_file_private *file_priv = file->driver_priv; |
476 | struct intel_context *ctx; |
483 | struct intel_context *ctx; |
477 | 484 | ||
478 | idr_init(&file_priv->context_idr); |
485 | idr_init(&file_priv->context_idr); |
479 | 486 | ||
480 | mutex_lock(&dev->struct_mutex); |
487 | mutex_lock(&dev->struct_mutex); |
481 | ctx = i915_gem_create_context(dev, file_priv); |
488 | ctx = i915_gem_create_context(dev, file_priv); |
482 | mutex_unlock(&dev->struct_mutex); |
489 | mutex_unlock(&dev->struct_mutex); |
483 | 490 | ||
484 | if (IS_ERR(ctx)) { |
491 | if (IS_ERR(ctx)) { |
485 | idr_destroy(&file_priv->context_idr); |
492 | idr_destroy(&file_priv->context_idr); |
486 | return PTR_ERR(ctx); |
493 | return PTR_ERR(ctx); |
487 | } |
494 | } |
488 | 495 | ||
489 | return 0; |
496 | return 0; |
490 | } |
497 | } |
491 | 498 | ||
492 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
499 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
493 | { |
500 | { |
494 | struct drm_i915_file_private *file_priv = file->driver_priv; |
501 | struct drm_i915_file_private *file_priv = file->driver_priv; |
495 | 502 | ||
496 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
503 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
497 | idr_destroy(&file_priv->context_idr); |
504 | idr_destroy(&file_priv->context_idr); |
498 | } |
505 | } |
499 | 506 | ||
500 | struct intel_context * |
507 | struct intel_context * |
501 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
508 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
502 | { |
509 | { |
503 | struct intel_context *ctx; |
510 | struct intel_context *ctx; |
504 | 511 | ||
505 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
512 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
506 | if (!ctx) |
513 | if (!ctx) |
507 | return ERR_PTR(-ENOENT); |
514 | return ERR_PTR(-ENOENT); |
508 | 515 | ||
509 | return ctx; |
516 | return ctx; |
510 | } |
517 | } |
511 | 518 | ||
512 | static inline int |
519 | static inline int |
513 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
520 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
514 | { |
521 | { |
515 | struct intel_engine_cs *ring = req->ring; |
522 | struct intel_engine_cs *ring = req->ring; |
516 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
523 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
517 | const int num_rings = |
524 | const int num_rings = |
518 | /* Use an extended w/a on ivb+ if signalling from other rings */ |
525 | /* Use an extended w/a on ivb+ if signalling from other rings */ |
519 | i915_semaphore_is_enabled(ring->dev) ? |
526 | i915_semaphore_is_enabled(ring->dev) ? |
520 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : |
527 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : |
521 | 0; |
528 | 0; |
522 | int len, i, ret; |
529 | int len, i, ret; |
523 | 530 | ||
524 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
531 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
525 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
532 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
526 | * explicitly, so we rely on the value at ring init, stored in |
533 | * explicitly, so we rely on the value at ring init, stored in |
527 | * itlb_before_ctx_switch. |
534 | * itlb_before_ctx_switch. |
528 | */ |
535 | */ |
529 | if (IS_GEN6(ring->dev)) { |
536 | if (IS_GEN6(ring->dev)) { |
530 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
537 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
531 | if (ret) |
538 | if (ret) |
532 | return ret; |
539 | return ret; |
533 | } |
540 | } |
534 | 541 | ||
535 | /* These flags are for resource streamer on HSW+ */ |
542 | /* These flags are for resource streamer on HSW+ */ |
536 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
543 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
537 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
544 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
538 | else if (INTEL_INFO(ring->dev)->gen < 8) |
545 | else if (INTEL_INFO(ring->dev)->gen < 8) |
539 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
546 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
540 | 547 | ||
541 | 548 | ||
542 | len = 4; |
549 | len = 4; |
543 | if (INTEL_INFO(ring->dev)->gen >= 7) |
550 | if (INTEL_INFO(ring->dev)->gen >= 7) |
544 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); |
551 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); |
545 | 552 | ||
546 | ret = intel_ring_begin(req, len); |
553 | ret = intel_ring_begin(req, len); |
547 | if (ret) |
554 | if (ret) |
548 | return ret; |
555 | return ret; |
549 | 556 | ||
550 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
557 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
551 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
558 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
552 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
559 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
553 | if (num_rings) { |
560 | if (num_rings) { |
554 | struct intel_engine_cs *signaller; |
561 | struct intel_engine_cs *signaller; |
555 | 562 | ||
556 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
563 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
557 | for_each_ring(signaller, to_i915(ring->dev), i) { |
564 | for_each_ring(signaller, to_i915(ring->dev), i) { |
558 | if (signaller == ring) |
565 | if (signaller == ring) |
559 | continue; |
566 | continue; |
560 | 567 | ||
561 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
568 | intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base)); |
562 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
569 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
563 | } |
570 | } |
564 | } |
571 | } |
565 | } |
572 | } |
566 | 573 | ||
567 | intel_ring_emit(ring, MI_NOOP); |
574 | intel_ring_emit(ring, MI_NOOP); |
568 | intel_ring_emit(ring, MI_SET_CONTEXT); |
575 | intel_ring_emit(ring, MI_SET_CONTEXT); |
569 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
576 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
570 | flags); |
577 | flags); |
571 | /* |
578 | /* |
572 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
579 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
573 | * WaMiSetContext_Hang:snb,ivb,vlv |
580 | * WaMiSetContext_Hang:snb,ivb,vlv |
574 | */ |
581 | */ |
575 | intel_ring_emit(ring, MI_NOOP); |
582 | intel_ring_emit(ring, MI_NOOP); |
576 | 583 | ||
577 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
584 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
578 | if (num_rings) { |
585 | if (num_rings) { |
579 | struct intel_engine_cs *signaller; |
586 | struct intel_engine_cs *signaller; |
580 | 587 | ||
581 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
588 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); |
582 | for_each_ring(signaller, to_i915(ring->dev), i) { |
589 | for_each_ring(signaller, to_i915(ring->dev), i) { |
583 | if (signaller == ring) |
590 | if (signaller == ring) |
584 | continue; |
591 | continue; |
585 | 592 | ||
586 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
593 | intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base)); |
587 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
594 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
588 | } |
595 | } |
589 | } |
596 | } |
590 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
597 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
591 | } |
598 | } |
592 | 599 | ||
593 | intel_ring_advance(ring); |
600 | intel_ring_advance(ring); |
594 | 601 | ||
595 | return ret; |
602 | return ret; |
596 | } |
603 | } |
597 | 604 | ||
598 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
605 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
599 | struct intel_context *from, |
606 | struct intel_context *from, |
600 | struct intel_context *to) |
607 | struct intel_context *to) |
601 | { |
608 | { |
602 | if (to->remap_slice) |
609 | if (to->remap_slice) |
603 | return false; |
610 | return false; |
604 | 611 | ||
605 | if (to->ppgtt && from == to && |
612 | if (to->ppgtt && from == to && |
606 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) |
613 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) |
607 | return true; |
614 | return true; |
608 | 615 | ||
609 | return false; |
616 | return false; |
610 | } |
617 | } |
611 | 618 | ||
612 | static bool |
619 | static bool |
613 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) |
620 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) |
614 | { |
621 | { |
615 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
622 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
616 | 623 | ||
617 | if (!to->ppgtt) |
624 | if (!to->ppgtt) |
618 | return false; |
625 | return false; |
619 | 626 | ||
620 | if (INTEL_INFO(ring->dev)->gen < 8) |
627 | if (INTEL_INFO(ring->dev)->gen < 8) |
621 | return true; |
628 | return true; |
622 | 629 | ||
623 | if (ring != &dev_priv->ring[RCS]) |
630 | if (ring != &dev_priv->ring[RCS]) |
624 | return true; |
631 | return true; |
625 | 632 | ||
626 | return false; |
633 | return false; |
627 | } |
634 | } |
628 | 635 | ||
629 | static bool |
636 | static bool |
630 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
637 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
631 | u32 hw_flags) |
638 | u32 hw_flags) |
632 | { |
639 | { |
633 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
640 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
634 | 641 | ||
635 | if (!to->ppgtt) |
642 | if (!to->ppgtt) |
636 | return false; |
643 | return false; |
637 | 644 | ||
638 | if (!IS_GEN8(ring->dev)) |
645 | if (!IS_GEN8(ring->dev)) |
639 | return false; |
646 | return false; |
640 | 647 | ||
641 | if (ring != &dev_priv->ring[RCS]) |
648 | if (ring != &dev_priv->ring[RCS]) |
642 | return false; |
649 | return false; |
643 | 650 | ||
644 | if (hw_flags & MI_RESTORE_INHIBIT) |
651 | if (hw_flags & MI_RESTORE_INHIBIT) |
645 | return true; |
652 | return true; |
646 | 653 | ||
647 | return false; |
654 | return false; |
648 | } |
655 | } |
649 | 656 | ||
650 | static int do_switch(struct drm_i915_gem_request *req) |
657 | static int do_switch(struct drm_i915_gem_request *req) |
651 | { |
658 | { |
652 | struct intel_context *to = req->ctx; |
659 | struct intel_context *to = req->ctx; |
653 | struct intel_engine_cs *ring = req->ring; |
660 | struct intel_engine_cs *ring = req->ring; |
654 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
661 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
655 | struct intel_context *from = ring->last_context; |
662 | struct intel_context *from = ring->last_context; |
656 | u32 hw_flags = 0; |
663 | u32 hw_flags = 0; |
657 | bool uninitialized = false; |
664 | bool uninitialized = false; |
658 | int ret, i; |
665 | int ret, i; |
659 | 666 | ||
660 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
667 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
661 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
668 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
662 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); |
669 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); |
663 | } |
670 | } |
664 | 671 | ||
665 | if (should_skip_switch(ring, from, to)) |
672 | if (should_skip_switch(ring, from, to)) |
666 | return 0; |
673 | return 0; |
667 | 674 | ||
668 | /* Trying to pin first makes error handling easier. */ |
675 | /* Trying to pin first makes error handling easier. */ |
669 | if (ring == &dev_priv->ring[RCS]) { |
676 | if (ring == &dev_priv->ring[RCS]) { |
670 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
677 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
671 | get_context_alignment(ring->dev), 0); |
678 | get_context_alignment(ring->dev), 0); |
672 | if (ret) |
679 | if (ret) |
673 | return ret; |
680 | return ret; |
674 | } |
681 | } |
675 | 682 | ||
676 | /* |
683 | /* |
677 | * Pin can switch back to the default context if we end up calling into |
684 | * Pin can switch back to the default context if we end up calling into |
678 | * evict_everything - as a last ditch gtt defrag effort that also |
685 | * evict_everything - as a last ditch gtt defrag effort that also |
679 | * switches to the default context. Hence we need to reload from here. |
686 | * switches to the default context. Hence we need to reload from here. |
680 | */ |
687 | */ |
681 | from = ring->last_context; |
688 | from = ring->last_context; |
682 | 689 | ||
683 | if (needs_pd_load_pre(ring, to)) { |
690 | if (needs_pd_load_pre(ring, to)) { |
684 | /* Older GENs and non render rings still want the load first, |
691 | /* Older GENs and non render rings still want the load first, |
685 | * "PP_DCLV followed by PP_DIR_BASE register through Load |
692 | * "PP_DCLV followed by PP_DIR_BASE register through Load |
686 | * Register Immediate commands in Ring Buffer before submitting |
693 | * Register Immediate commands in Ring Buffer before submitting |
687 | * a context."*/ |
694 | * a context."*/ |
688 | trace_switch_mm(ring, to); |
695 | trace_switch_mm(ring, to); |
689 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
696 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
690 | if (ret) |
697 | if (ret) |
691 | goto unpin_out; |
698 | goto unpin_out; |
692 | 699 | ||
693 | /* Doing a PD load always reloads the page dirs */ |
700 | /* Doing a PD load always reloads the page dirs */ |
694 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
701 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
695 | } |
702 | } |
696 | 703 | ||
697 | if (ring != &dev_priv->ring[RCS]) { |
704 | if (ring != &dev_priv->ring[RCS]) { |
698 | if (from) |
705 | if (from) |
699 | i915_gem_context_unreference(from); |
706 | i915_gem_context_unreference(from); |
700 | goto done; |
707 | goto done; |
701 | } |
708 | } |
702 | 709 | ||
703 | /* |
710 | /* |
704 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
711 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
705 | * that thanks to write = false in this call and us not setting any gpu |
712 | * that thanks to write = false in this call and us not setting any gpu |
706 | * write domains when putting a context object onto the active list |
713 | * write domains when putting a context object onto the active list |
707 | * (when switching away from it), this won't block. |
714 | * (when switching away from it), this won't block. |
708 | * |
715 | * |
709 | * XXX: We need a real interface to do this instead of trickery. |
716 | * XXX: We need a real interface to do this instead of trickery. |
710 | */ |
717 | */ |
711 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
718 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
712 | if (ret) |
719 | if (ret) |
713 | goto unpin_out; |
720 | goto unpin_out; |
714 | 721 | ||
715 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) { |
722 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) { |
716 | hw_flags |= MI_RESTORE_INHIBIT; |
723 | hw_flags |= MI_RESTORE_INHIBIT; |
717 | /* NB: If we inhibit the restore, the context is not allowed to |
724 | /* NB: If we inhibit the restore, the context is not allowed to |
718 | * die because future work may end up depending on valid address |
725 | * die because future work may end up depending on valid address |
719 | * space. This means we must enforce that a page table load |
726 | * space. This means we must enforce that a page table load |
720 | * occur when this occurs. */ |
727 | * occur when this occurs. */ |
721 | } else if (to->ppgtt && |
728 | } else if (to->ppgtt && |
722 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
729 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
723 | hw_flags |= MI_FORCE_RESTORE; |
730 | hw_flags |= MI_FORCE_RESTORE; |
724 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
731 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
725 | } |
732 | } |
726 | 733 | ||
727 | /* We should never emit switch_mm more than once */ |
734 | /* We should never emit switch_mm more than once */ |
728 | WARN_ON(needs_pd_load_pre(ring, to) && |
735 | WARN_ON(needs_pd_load_pre(ring, to) && |
729 | needs_pd_load_post(ring, to, hw_flags)); |
736 | needs_pd_load_post(ring, to, hw_flags)); |
730 | 737 | ||
731 | ret = mi_set_context(req, hw_flags); |
738 | ret = mi_set_context(req, hw_flags); |
732 | if (ret) |
739 | if (ret) |
733 | goto unpin_out; |
740 | goto unpin_out; |
734 | 741 | ||
735 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
742 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
736 | * setup, and we do not wish to move them. |
743 | * setup, and we do not wish to move them. |
737 | */ |
744 | */ |
738 | if (needs_pd_load_post(ring, to, hw_flags)) { |
745 | if (needs_pd_load_post(ring, to, hw_flags)) { |
739 | trace_switch_mm(ring, to); |
746 | trace_switch_mm(ring, to); |
740 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
747 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
741 | /* The hardware context switch is emitted, but we haven't |
748 | /* The hardware context switch is emitted, but we haven't |
742 | * actually changed the state - so it's probably safe to bail |
749 | * actually changed the state - so it's probably safe to bail |
743 | * here. Still, let the user know something dangerous has |
750 | * here. Still, let the user know something dangerous has |
744 | * happened. |
751 | * happened. |
745 | */ |
752 | */ |
746 | if (ret) { |
753 | if (ret) { |
747 | DRM_ERROR("Failed to change address space on context switch\n"); |
754 | DRM_ERROR("Failed to change address space on context switch\n"); |
748 | goto unpin_out; |
755 | goto unpin_out; |
749 | } |
756 | } |
750 | } |
757 | } |
751 | 758 | ||
752 | for (i = 0; i < MAX_L3_SLICES; i++) { |
759 | for (i = 0; i < MAX_L3_SLICES; i++) { |
753 | if (!(to->remap_slice & (1< |
760 | if (!(to->remap_slice & (1< |
754 | continue; |
761 | continue; |
755 | 762 | ||
756 | ret = i915_gem_l3_remap(req, i); |
763 | ret = i915_gem_l3_remap(req, i); |
757 | /* If it failed, try again next round */ |
764 | /* If it failed, try again next round */ |
758 | if (ret) |
765 | if (ret) |
759 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); |
766 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); |
760 | else |
767 | else |
761 | to->remap_slice &= ~(1< |
768 | to->remap_slice &= ~(1< |
762 | } |
769 | } |
763 | 770 | ||
764 | /* The backing object for the context is done after switching to the |
771 | /* The backing object for the context is done after switching to the |
765 | * *next* context. Therefore we cannot retire the previous context until |
772 | * *next* context. Therefore we cannot retire the previous context until |
766 | * the next context has already started running. In fact, the below code |
773 | * the next context has already started running. In fact, the below code |
767 | * is a bit suboptimal because the retiring can occur simply after the |
774 | * is a bit suboptimal because the retiring can occur simply after the |
768 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
775 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
769 | */ |
776 | */ |
770 | if (from != NULL) { |
777 | if (from != NULL) { |
771 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
778 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
772 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
779 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
773 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
780 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
774 | * whole damn pipeline, we don't need to explicitly mark the |
781 | * whole damn pipeline, we don't need to explicitly mark the |
775 | * object dirty. The only exception is that the context must be |
782 | * object dirty. The only exception is that the context must be |
776 | * correct in case the object gets swapped out. Ideally we'd be |
783 | * correct in case the object gets swapped out. Ideally we'd be |
777 | * able to defer doing this until we know the object would be |
784 | * able to defer doing this until we know the object would be |
778 | * swapped, but there is no way to do that yet. |
785 | * swapped, but there is no way to do that yet. |
779 | */ |
786 | */ |
780 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
787 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
781 | 788 | ||
782 | /* obj is kept alive until the next request by its active ref */ |
789 | /* obj is kept alive until the next request by its active ref */ |
783 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
790 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
784 | i915_gem_context_unreference(from); |
791 | i915_gem_context_unreference(from); |
785 | } |
792 | } |
786 | 793 | ||
787 | uninitialized = !to->legacy_hw_ctx.initialized; |
794 | uninitialized = !to->legacy_hw_ctx.initialized; |
788 | to->legacy_hw_ctx.initialized = true; |
795 | to->legacy_hw_ctx.initialized = true; |
789 | 796 | ||
790 | done: |
797 | done: |
791 | i915_gem_context_reference(to); |
798 | i915_gem_context_reference(to); |
792 | ring->last_context = to; |
799 | ring->last_context = to; |
793 | 800 | ||
794 | if (uninitialized) { |
801 | if (uninitialized) { |
795 | if (ring->init_context) { |
802 | if (ring->init_context) { |
796 | ret = ring->init_context(req); |
803 | ret = ring->init_context(req); |
797 | if (ret) |
804 | if (ret) |
798 | DRM_ERROR("ring init context: %d\n", ret); |
805 | DRM_ERROR("ring init context: %d\n", ret); |
799 | } |
806 | } |
800 | } |
807 | } |
801 | 808 | ||
802 | return 0; |
809 | return 0; |
803 | 810 | ||
804 | unpin_out: |
811 | unpin_out: |
805 | if (ring->id == RCS) |
812 | if (ring->id == RCS) |
806 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
813 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
807 | return ret; |
814 | return ret; |
808 | } |
815 | } |
809 | 816 | ||
810 | /** |
817 | /** |
811 | * i915_switch_context() - perform a GPU context switch. |
818 | * i915_switch_context() - perform a GPU context switch. |
812 | * @req: request for which we'll execute the context switch |
819 | * @req: request for which we'll execute the context switch |
813 | * |
820 | * |
814 | * The context life cycle is simple. The context refcount is incremented and |
821 | * The context life cycle is simple. The context refcount is incremented and |
815 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
822 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
816 | * it will have a refcount > 1. This allows us to destroy the context abstract |
823 | * it will have a refcount > 1. This allows us to destroy the context abstract |
817 | * object while letting the normal object tracking destroy the backing BO. |
824 | * object while letting the normal object tracking destroy the backing BO. |
818 | * |
825 | * |
819 | * This function should not be used in execlists mode. Instead the context is |
826 | * This function should not be used in execlists mode. Instead the context is |
820 | * switched by writing to the ELSP and requests keep a reference to their |
827 | * switched by writing to the ELSP and requests keep a reference to their |
821 | * context. |
828 | * context. |
822 | */ |
829 | */ |
823 | int i915_switch_context(struct drm_i915_gem_request *req) |
830 | int i915_switch_context(struct drm_i915_gem_request *req) |
824 | { |
831 | { |
825 | struct intel_engine_cs *ring = req->ring; |
832 | struct intel_engine_cs *ring = req->ring; |
826 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
833 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
827 | 834 | ||
828 | WARN_ON(i915.enable_execlists); |
835 | WARN_ON(i915.enable_execlists); |
829 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
836 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
830 | 837 | ||
831 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
838 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
832 | if (req->ctx != ring->last_context) { |
839 | if (req->ctx != ring->last_context) { |
833 | i915_gem_context_reference(req->ctx); |
840 | i915_gem_context_reference(req->ctx); |
834 | if (ring->last_context) |
841 | if (ring->last_context) |
835 | i915_gem_context_unreference(ring->last_context); |
842 | i915_gem_context_unreference(ring->last_context); |
836 | ring->last_context = req->ctx; |
843 | ring->last_context = req->ctx; |
837 | } |
844 | } |
838 | return 0; |
845 | return 0; |
839 | } |
846 | } |
840 | 847 | ||
841 | return do_switch(req); |
848 | return do_switch(req); |
842 | } |
849 | } |
843 | 850 | ||
844 | static bool contexts_enabled(struct drm_device *dev) |
851 | static bool contexts_enabled(struct drm_device *dev) |
845 | { |
852 | { |
846 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
853 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
847 | } |
854 | } |
848 | 855 | ||
849 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
856 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
850 | struct drm_file *file) |
857 | struct drm_file *file) |
851 | { |
858 | { |
852 | struct drm_i915_gem_context_create *args = data; |
859 | struct drm_i915_gem_context_create *args = data; |
853 | struct drm_i915_file_private *file_priv = file->driver_priv; |
860 | struct drm_i915_file_private *file_priv = file->driver_priv; |
854 | struct intel_context *ctx; |
861 | struct intel_context *ctx; |
855 | int ret; |
862 | int ret; |
856 | 863 | ||
857 | if (!contexts_enabled(dev)) |
864 | if (!contexts_enabled(dev)) |
858 | return -ENODEV; |
865 | return -ENODEV; |
859 | 866 | ||
860 | ret = i915_mutex_lock_interruptible(dev); |
867 | ret = i915_mutex_lock_interruptible(dev); |
861 | if (ret) |
868 | if (ret) |
862 | return ret; |
869 | return ret; |
863 | 870 | ||
864 | ctx = i915_gem_create_context(dev, file_priv); |
871 | ctx = i915_gem_create_context(dev, file_priv); |
865 | mutex_unlock(&dev->struct_mutex); |
872 | mutex_unlock(&dev->struct_mutex); |
866 | if (IS_ERR(ctx)) |
873 | if (IS_ERR(ctx)) |
867 | return PTR_ERR(ctx); |
874 | return PTR_ERR(ctx); |
868 | 875 | ||
869 | args->ctx_id = ctx->user_handle; |
876 | args->ctx_id = ctx->user_handle; |
870 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
877 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
871 | 878 | ||
872 | return 0; |
879 | return 0; |
873 | } |
880 | } |
874 | 881 | ||
875 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
882 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
876 | struct drm_file *file) |
883 | struct drm_file *file) |
877 | { |
884 | { |
878 | struct drm_i915_gem_context_destroy *args = data; |
885 | struct drm_i915_gem_context_destroy *args = data; |
879 | struct drm_i915_file_private *file_priv = file->driver_priv; |
886 | struct drm_i915_file_private *file_priv = file->driver_priv; |
880 | struct intel_context *ctx; |
887 | struct intel_context *ctx; |
881 | int ret; |
888 | int ret; |
882 | 889 | ||
883 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
890 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
884 | return -ENOENT; |
891 | return -ENOENT; |
885 | 892 | ||
886 | ret = i915_mutex_lock_interruptible(dev); |
893 | ret = i915_mutex_lock_interruptible(dev); |
887 | if (ret) |
894 | if (ret) |
888 | return ret; |
895 | return ret; |
889 | 896 | ||
890 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
897 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
891 | if (IS_ERR(ctx)) { |
898 | if (IS_ERR(ctx)) { |
892 | mutex_unlock(&dev->struct_mutex); |
899 | mutex_unlock(&dev->struct_mutex); |
893 | return PTR_ERR(ctx); |
900 | return PTR_ERR(ctx); |
894 | } |
901 | } |
895 | 902 | ||
896 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
903 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
897 | i915_gem_context_unreference(ctx); |
904 | i915_gem_context_unreference(ctx); |
898 | mutex_unlock(&dev->struct_mutex); |
905 | mutex_unlock(&dev->struct_mutex); |
899 | 906 | ||
900 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
907 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
901 | return 0; |
908 | return 0; |
902 | } |
909 | } |
903 | 910 | ||
904 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
911 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
905 | struct drm_file *file) |
912 | struct drm_file *file) |
906 | { |
913 | { |
907 | struct drm_i915_file_private *file_priv = file->driver_priv; |
914 | struct drm_i915_file_private *file_priv = file->driver_priv; |
908 | struct drm_i915_gem_context_param *args = data; |
915 | struct drm_i915_gem_context_param *args = data; |
909 | struct intel_context *ctx; |
916 | struct intel_context *ctx; |
910 | int ret; |
917 | int ret; |
911 | 918 | ||
912 | ret = i915_mutex_lock_interruptible(dev); |
919 | ret = i915_mutex_lock_interruptible(dev); |
913 | if (ret) |
920 | if (ret) |
914 | return ret; |
921 | return ret; |
915 | 922 | ||
916 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
923 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
917 | if (IS_ERR(ctx)) { |
924 | if (IS_ERR(ctx)) { |
918 | mutex_unlock(&dev->struct_mutex); |
925 | mutex_unlock(&dev->struct_mutex); |
919 | return PTR_ERR(ctx); |
926 | return PTR_ERR(ctx); |
920 | } |
927 | } |
921 | 928 | ||
922 | args->size = 0; |
929 | args->size = 0; |
923 | switch (args->param) { |
930 | switch (args->param) { |
924 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
931 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
925 | args->value = ctx->hang_stats.ban_period_seconds; |
932 | args->value = ctx->hang_stats.ban_period_seconds; |
926 | break; |
933 | break; |
927 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
934 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
928 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
935 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
929 | break; |
936 | break; |
- | 937 | case I915_CONTEXT_PARAM_GTT_SIZE: |
|
- | 938 | if (ctx->ppgtt) |
|
- | 939 | args->value = ctx->ppgtt->base.total; |
|
- | 940 | else if (to_i915(dev)->mm.aliasing_ppgtt) |
|
- | 941 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; |
|
- | 942 | else |
|
- | 943 | args->value = to_i915(dev)->gtt.base.total; |
|
- | 944 | break; |
|
930 | default: |
945 | default: |
931 | ret = -EINVAL; |
946 | ret = -EINVAL; |
932 | break; |
947 | break; |
933 | } |
948 | } |
934 | mutex_unlock(&dev->struct_mutex); |
949 | mutex_unlock(&dev->struct_mutex); |
935 | 950 | ||
936 | return ret; |
951 | return ret; |
937 | } |
952 | } |
938 | 953 | ||
939 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
954 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
940 | struct drm_file *file) |
955 | struct drm_file *file) |
941 | { |
956 | { |
942 | struct drm_i915_file_private *file_priv = file->driver_priv; |
957 | struct drm_i915_file_private *file_priv = file->driver_priv; |
943 | struct drm_i915_gem_context_param *args = data; |
958 | struct drm_i915_gem_context_param *args = data; |
944 | struct intel_context *ctx; |
959 | struct intel_context *ctx; |
945 | int ret; |
960 | int ret; |
946 | 961 | ||
947 | ret = i915_mutex_lock_interruptible(dev); |
962 | ret = i915_mutex_lock_interruptible(dev); |
948 | if (ret) |
963 | if (ret) |
949 | return ret; |
964 | return ret; |
950 | 965 | ||
951 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
966 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
952 | if (IS_ERR(ctx)) { |
967 | if (IS_ERR(ctx)) { |
953 | mutex_unlock(&dev->struct_mutex); |
968 | mutex_unlock(&dev->struct_mutex); |
954 | return PTR_ERR(ctx); |
969 | return PTR_ERR(ctx); |
955 | } |
970 | } |
956 | 971 | ||
957 | switch (args->param) { |
972 | switch (args->param) { |
958 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
973 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
959 | if (args->size) |
974 | if (args->size) |
960 | ret = -EINVAL; |
975 | ret = -EINVAL; |
961 | else if (args->value < ctx->hang_stats.ban_period_seconds) |
976 | else if (args->value < ctx->hang_stats.ban_period_seconds && |
- | 977 | !capable(CAP_SYS_ADMIN)) |
|
962 | ret = -EPERM; |
978 | ret = -EPERM; |
963 | else |
979 | else |
964 | ctx->hang_stats.ban_period_seconds = args->value; |
980 | ctx->hang_stats.ban_period_seconds = args->value; |
965 | break; |
981 | break; |
966 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
982 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
967 | if (args->size) { |
983 | if (args->size) { |
968 | ret = -EINVAL; |
984 | ret = -EINVAL; |
969 | } else { |
985 | } else { |
970 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; |
986 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; |
971 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; |
987 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; |
972 | } |
988 | } |
973 | break; |
989 | break; |
974 | default: |
990 | default: |
975 | ret = -EINVAL; |
991 | ret = -EINVAL; |
976 | break; |
992 | break; |
977 | } |
993 | } |
978 | mutex_unlock(&dev->struct_mutex); |
994 | mutex_unlock(&dev->struct_mutex); |
979 | 995 | ||
980 | return ret; |
996 | return ret; |
981 | }> |
997 | }> |
982 | > |
998 | > |
983 | > |
999 | > |
984 | > |
1000 | > |
985 | >>>>>>20))><20))>>><>>10) |
1001 | >>>>>>20))><20))>>><>>10) |
986 | #define><10) |
1002 | #define><10) |
987 | #define> |
1003 | #define> |