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Rev 6320 Rev 6937
Line 187... Line 187...
187 
	 *
 187 
	 *
188 
	 * On VLV we don't have L3 controls in the PTEs so we
 188 
	 * On VLV we don't have L3 controls in the PTEs so we
189 
	 * shouldn't touch the cache level, especially as that
 189 
	 * shouldn't touch the cache level, especially as that
190 
	 * would make the object snooped which might have a
 190 
	 * would make the object snooped which might have a
191 
	 * negative performance impact.
 191 
	 * negative performance impact.
- 
 
 192 
	 *
- 
 
 193 
	 * Snooping is required on non-llc platforms in execlist
- 
 
 194 
	 * mode, but since all GGTT accesses use PAT entry 0 we
- 
 
 195 
	 * get snooping anyway regardless of cache_level.
- 
 
 196 
	 *
- 
 
 197 
	 * This is only applicable for Ivy Bridge devices since
- 
 
 198 
	 * later platforms don't have L3 control bits in the PTE.
192 
	 */
 199 
	 */
193 
	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
 200 
	if (IS_IVYBRIDGE(dev)) {
194 
		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 201 
		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
195 
		/* Failure shouldn't ever happen this early */
 202 
		/* Failure shouldn't ever happen this early */
196 
		if (WARN_ON(ret)) {
 203 
		if (WARN_ON(ret)) {
197 
			drm_gem_object_unreference(&obj->base);
 204 
			drm_gem_object_unreference(&obj->base);
198 
			return ERR_PTR(ret);
 205 
			return ERR_PTR(ret);
Line 556... Line 563...
556 
			intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
 563 
			intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
557 
			for_each_ring(signaller, to_i915(ring->dev), i) {
 564 
			for_each_ring(signaller, to_i915(ring->dev), i) {
558 
				if (signaller == ring)
 565 
				if (signaller == ring)
559 
					continue;
 566 
					continue;
Line 560... Line 567...
560 
 
 567 
 
561 
				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
 568 
				intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base));
562 
				intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
 569 
				intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
563 
			}
 570 
			}
564 
		}
 571 
		}
Line 581... Line 588...
581 
			intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
 588 
			intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
582 
			for_each_ring(signaller, to_i915(ring->dev), i) {
 589 
			for_each_ring(signaller, to_i915(ring->dev), i) {
583 
				if (signaller == ring)
 590 
				if (signaller == ring)
584 
					continue;
 591 
					continue;
Line 585... Line 592...
585 
 
 592 
 
586 
				intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
 593 
				intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base));
587 
				intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
 594 
				intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
588 
			}
 595 
			}
589 
		}
 596 
		}
590 
		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 597 
		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
Line 925... Line 932...
925 
		args->value = ctx->hang_stats.ban_period_seconds;
 932 
		args->value = ctx->hang_stats.ban_period_seconds;
926 
		break;
 933 
		break;
927 
	case I915_CONTEXT_PARAM_NO_ZEROMAP:
 934 
	case I915_CONTEXT_PARAM_NO_ZEROMAP:
928 
		args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
 935 
		args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
929 
		break;
 936 
		break;
- 
 
 937 
	case I915_CONTEXT_PARAM_GTT_SIZE:
- 
 
 938 
		if (ctx->ppgtt)
- 
 
 939 
			args->value = ctx->ppgtt->base.total;
- 
 
 940 
		else if (to_i915(dev)->mm.aliasing_ppgtt)
- 
 
 941 
			args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
- 
 
 942 
		else
- 
 
 943 
			args->value = to_i915(dev)->gtt.base.total;
- 
 
 944 
		break;
930 
	default:
 945 
	default:
931 
		ret = -EINVAL;
 946 
		ret = -EINVAL;
932 
		break;
 947 
		break;
933 
	}
 948 
	}
934 
	mutex_unlock(&dev->struct_mutex);
 949 
	mutex_unlock(&dev->struct_mutex);
Line 956... Line 971...
956 
 
 971 
 
957 
	switch (args->param) {
 972 
	switch (args->param) {
958 
	case I915_CONTEXT_PARAM_BAN_PERIOD:
 973 
	case I915_CONTEXT_PARAM_BAN_PERIOD:
959 
		if (args->size)
 974 
		if (args->size)
960 
			ret = -EINVAL;
 975 
			ret = -EINVAL;
- 
 
 976 
		else if (args->value < ctx->hang_stats.ban_period_seconds &&
961 
		else if (args->value < ctx->hang_stats.ban_period_seconds)
 977 
			 !capable(CAP_SYS_ADMIN))
962 
			ret = -EPERM;
 978 
			ret = -EPERM;
963 
		else
 979 
		else
964 
			ctx->hang_stats.ban_period_seconds = args->value;
 980 
			ctx->hang_stats.ban_period_seconds = args->value;
965 
		break;
 981 
		break;