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1 | /* |
1 | /* |
2 | * Copyright © 2008 Intel Corporation |
2 | * Copyright © 2008 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "i915_drv.h" |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" |
33 | #include "intel_drv.h" |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | //#include |
36 | //#include |
37 | #include |
37 | #include |
38 | #include |
38 | #include |
39 | 39 | ||
40 | extern int x86_clflush_size; |
40 | extern int x86_clflush_size; |
41 | 41 | ||
42 | #define PROT_READ 0x1 /* page can be read */ |
42 | #define PROT_READ 0x1 /* page can be read */ |
43 | #define PROT_WRITE 0x2 /* page can be written */ |
43 | #define PROT_WRITE 0x2 /* page can be written */ |
44 | #define MAP_SHARED 0x01 /* Share changes */ |
44 | #define MAP_SHARED 0x01 /* Share changes */ |
45 | 45 | ||
46 | #undef mb |
46 | #undef mb |
47 | #undef rmb |
47 | #undef rmb |
48 | #undef wmb |
48 | #undef wmb |
49 | #define mb() asm volatile("mfence") |
49 | #define mb() asm volatile("mfence") |
50 | #define rmb() asm volatile ("lfence") |
50 | #define rmb() asm volatile ("lfence") |
51 | #define wmb() asm volatile ("sfence") |
51 | #define wmb() asm volatile ("sfence") |
52 | 52 | ||
53 | struct drm_i915_gem_object *get_fb_obj(); |
53 | struct drm_i915_gem_object *get_fb_obj(); |
54 | 54 | ||
55 | unsigned long vm_mmap(struct file *file, unsigned long addr, |
55 | unsigned long vm_mmap(struct file *file, unsigned long addr, |
56 | unsigned long len, unsigned long prot, |
56 | unsigned long len, unsigned long prot, |
57 | unsigned long flag, unsigned long offset); |
57 | unsigned long flag, unsigned long offset); |
58 | 58 | ||
59 | static inline void clflush(volatile void *__p) |
59 | static inline void clflush(volatile void *__p) |
60 | { |
60 | { |
61 | asm volatile("clflush %0" : "+m" (*(volatile char*)__p)); |
61 | asm volatile("clflush %0" : "+m" (*(volatile char*)__p)); |
62 | } |
62 | } |
63 | 63 | ||
64 | #define MAX_ERRNO 4095 |
64 | #define MAX_ERRNO 4095 |
65 | 65 | ||
66 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
66 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
67 | 67 | ||
68 | 68 | ||
69 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
69 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
70 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
70 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
71 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
71 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
72 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
72 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
73 | 73 | ||
74 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
74 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
75 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
75 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
76 | bool force); |
76 | bool force); |
77 | static __must_check int |
77 | static __must_check int |
78 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
78 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
79 | struct i915_address_space *vm, |
79 | struct i915_address_space *vm, |
80 | unsigned alignment, |
80 | unsigned alignment, |
81 | bool map_and_fenceable, |
81 | bool map_and_fenceable, |
82 | bool nonblocking); |
82 | bool nonblocking); |
83 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
83 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
84 | struct drm_i915_gem_object *obj, |
84 | struct drm_i915_gem_object *obj, |
85 | struct drm_i915_gem_pwrite *args, |
85 | struct drm_i915_gem_pwrite *args, |
86 | struct drm_file *file); |
86 | struct drm_file *file); |
87 | 87 | ||
88 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
88 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
89 | struct drm_i915_gem_object *obj); |
89 | struct drm_i915_gem_object *obj); |
90 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
90 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
91 | struct drm_i915_fence_reg *fence, |
91 | struct drm_i915_fence_reg *fence, |
92 | bool enable); |
92 | bool enable); |
93 | 93 | ||
94 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
94 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
95 | static long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
95 | static long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
96 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
96 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
97 | 97 | ||
98 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
98 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
99 | enum i915_cache_level level) |
99 | enum i915_cache_level level) |
100 | { |
100 | { |
101 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
101 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
102 | } |
102 | } |
103 | 103 | ||
104 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
104 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
105 | { |
105 | { |
106 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
106 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
107 | return true; |
107 | return true; |
108 | 108 | ||
109 | return obj->pin_display; |
109 | return obj->pin_display; |
110 | } |
110 | } |
111 | 111 | ||
112 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
112 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
113 | { |
113 | { |
114 | if (obj->tiling_mode) |
114 | if (obj->tiling_mode) |
115 | i915_gem_release_mmap(obj); |
115 | i915_gem_release_mmap(obj); |
116 | 116 | ||
117 | /* As we do not have an associated fence register, we will force |
117 | /* As we do not have an associated fence register, we will force |
118 | * a tiling change if we ever need to acquire one. |
118 | * a tiling change if we ever need to acquire one. |
119 | */ |
119 | */ |
120 | obj->fence_dirty = false; |
120 | obj->fence_dirty = false; |
121 | obj->fence_reg = I915_FENCE_REG_NONE; |
121 | obj->fence_reg = I915_FENCE_REG_NONE; |
122 | } |
122 | } |
123 | 123 | ||
124 | /* some bookkeeping */ |
124 | /* some bookkeeping */ |
125 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
125 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
126 | size_t size) |
126 | size_t size) |
127 | { |
127 | { |
128 | spin_lock(&dev_priv->mm.object_stat_lock); |
128 | spin_lock(&dev_priv->mm.object_stat_lock); |
129 | dev_priv->mm.object_count++; |
129 | dev_priv->mm.object_count++; |
130 | dev_priv->mm.object_memory += size; |
130 | dev_priv->mm.object_memory += size; |
131 | spin_unlock(&dev_priv->mm.object_stat_lock); |
131 | spin_unlock(&dev_priv->mm.object_stat_lock); |
132 | } |
132 | } |
133 | 133 | ||
134 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
134 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
135 | size_t size) |
135 | size_t size) |
136 | { |
136 | { |
137 | spin_lock(&dev_priv->mm.object_stat_lock); |
137 | spin_lock(&dev_priv->mm.object_stat_lock); |
138 | dev_priv->mm.object_count--; |
138 | dev_priv->mm.object_count--; |
139 | dev_priv->mm.object_memory -= size; |
139 | dev_priv->mm.object_memory -= size; |
140 | spin_unlock(&dev_priv->mm.object_stat_lock); |
140 | spin_unlock(&dev_priv->mm.object_stat_lock); |
141 | } |
141 | } |
142 | 142 | ||
143 | static int |
143 | static int |
144 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
144 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
145 | { |
145 | { |
146 | int ret; |
146 | int ret; |
147 | 147 | ||
148 | #define EXIT_COND (!i915_reset_in_progress(error)) |
148 | #define EXIT_COND (!i915_reset_in_progress(error)) |
149 | if (EXIT_COND) |
149 | if (EXIT_COND) |
150 | return 0; |
150 | return 0; |
151 | #if 0 |
151 | #if 0 |
152 | /* |
152 | /* |
153 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
153 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
154 | * userspace. If it takes that long something really bad is going on and |
154 | * userspace. If it takes that long something really bad is going on and |
155 | * we should simply try to bail out and fail as gracefully as possible. |
155 | * we should simply try to bail out and fail as gracefully as possible. |
156 | */ |
156 | */ |
157 | ret = wait_event_interruptible_timeout(error->reset_queue, |
157 | ret = wait_event_interruptible_timeout(error->reset_queue, |
158 | EXIT_COND, |
158 | EXIT_COND, |
159 | 10*HZ); |
159 | 10*HZ); |
160 | if (ret == 0) { |
160 | if (ret == 0) { |
161 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
161 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
162 | return -EIO; |
162 | return -EIO; |
163 | } else if (ret < 0) { |
163 | } else if (ret < 0) { |
164 | return ret; |
164 | return ret; |
165 | } |
165 | } |
166 | 166 | ||
167 | #endif |
167 | #endif |
168 | #undef EXIT_COND |
168 | #undef EXIT_COND |
169 | 169 | ||
170 | return 0; |
170 | return 0; |
171 | } |
171 | } |
172 | 172 | ||
173 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
173 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
174 | { |
174 | { |
175 | struct drm_i915_private *dev_priv = dev->dev_private; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; |
176 | int ret; |
176 | int ret; |
177 | 177 | ||
178 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
178 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
179 | if (ret) |
179 | if (ret) |
180 | return ret; |
180 | return ret; |
181 | 181 | ||
182 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
182 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
183 | if (ret) |
183 | if (ret) |
184 | return ret; |
184 | return ret; |
185 | 185 | ||
186 | WARN_ON(i915_verify_lists(dev)); |
186 | WARN_ON(i915_verify_lists(dev)); |
187 | return 0; |
187 | return 0; |
188 | } |
188 | } |
189 | 189 | ||
190 | static inline bool |
190 | static inline bool |
191 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
191 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
192 | { |
192 | { |
193 | return i915_gem_obj_bound_any(obj) && !obj->active; |
193 | return i915_gem_obj_bound_any(obj) && !obj->active; |
194 | } |
194 | } |
195 | 195 | ||
196 | 196 | ||
197 | #if 0 |
197 | #if 0 |
198 | 198 | ||
199 | int |
199 | int |
200 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
200 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
201 | struct drm_file *file) |
201 | struct drm_file *file) |
202 | { |
202 | { |
203 | struct drm_i915_private *dev_priv = dev->dev_private; |
203 | struct drm_i915_private *dev_priv = dev->dev_private; |
204 | struct drm_i915_gem_init *args = data; |
204 | struct drm_i915_gem_init *args = data; |
205 | 205 | ||
206 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
206 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
207 | return -ENODEV; |
207 | return -ENODEV; |
208 | 208 | ||
209 | if (args->gtt_start >= args->gtt_end || |
209 | if (args->gtt_start >= args->gtt_end || |
210 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
210 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
211 | return -EINVAL; |
211 | return -EINVAL; |
212 | 212 | ||
213 | /* GEM with user mode setting was never supported on ilk and later. */ |
213 | /* GEM with user mode setting was never supported on ilk and later. */ |
214 | if (INTEL_INFO(dev)->gen >= 5) |
214 | if (INTEL_INFO(dev)->gen >= 5) |
215 | return -ENODEV; |
215 | return -ENODEV; |
216 | 216 | ||
217 | mutex_lock(&dev->struct_mutex); |
217 | mutex_lock(&dev->struct_mutex); |
218 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
218 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
219 | args->gtt_end); |
219 | args->gtt_end); |
220 | dev_priv->gtt.mappable_end = args->gtt_end; |
220 | dev_priv->gtt.mappable_end = args->gtt_end; |
221 | mutex_unlock(&dev->struct_mutex); |
221 | mutex_unlock(&dev->struct_mutex); |
222 | 222 | ||
223 | return 0; |
223 | return 0; |
224 | } |
224 | } |
225 | #endif |
225 | #endif |
226 | 226 | ||
227 | int |
227 | int |
228 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
228 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
229 | struct drm_file *file) |
229 | struct drm_file *file) |
230 | { |
230 | { |
231 | struct drm_i915_private *dev_priv = dev->dev_private; |
231 | struct drm_i915_private *dev_priv = dev->dev_private; |
232 | struct drm_i915_gem_get_aperture *args = data; |
232 | struct drm_i915_gem_get_aperture *args = data; |
233 | struct drm_i915_gem_object *obj; |
233 | struct drm_i915_gem_object *obj; |
234 | size_t pinned; |
234 | size_t pinned; |
235 | 235 | ||
236 | pinned = 0; |
236 | pinned = 0; |
237 | mutex_lock(&dev->struct_mutex); |
237 | mutex_lock(&dev->struct_mutex); |
238 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
238 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
239 | if (obj->pin_count) |
239 | if (obj->pin_count) |
240 | pinned += i915_gem_obj_ggtt_size(obj); |
240 | pinned += i915_gem_obj_ggtt_size(obj); |
241 | mutex_unlock(&dev->struct_mutex); |
241 | mutex_unlock(&dev->struct_mutex); |
242 | 242 | ||
243 | args->aper_size = dev_priv->gtt.base.total; |
243 | args->aper_size = dev_priv->gtt.base.total; |
244 | args->aper_available_size = args->aper_size - pinned; |
244 | args->aper_available_size = args->aper_size - pinned; |
245 | 245 | ||
246 | return 0; |
246 | return 0; |
247 | } |
247 | } |
248 | 248 | ||
249 | void *i915_gem_object_alloc(struct drm_device *dev) |
249 | void *i915_gem_object_alloc(struct drm_device *dev) |
250 | { |
250 | { |
251 | struct drm_i915_private *dev_priv = dev->dev_private; |
251 | struct drm_i915_private *dev_priv = dev->dev_private; |
252 | return kmalloc(sizeof(struct drm_i915_gem_object), 0); |
252 | return kmalloc(sizeof(struct drm_i915_gem_object), 0); |
253 | } |
253 | } |
254 | 254 | ||
255 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
255 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
256 | { |
256 | { |
257 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
257 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
258 | kfree(obj); |
258 | kfree(obj); |
259 | } |
259 | } |
260 | 260 | ||
261 | static int |
261 | static int |
262 | i915_gem_create(struct drm_file *file, |
262 | i915_gem_create(struct drm_file *file, |
263 | struct drm_device *dev, |
263 | struct drm_device *dev, |
264 | uint64_t size, |
264 | uint64_t size, |
265 | uint32_t *handle_p) |
265 | uint32_t *handle_p) |
266 | { |
266 | { |
267 | struct drm_i915_gem_object *obj; |
267 | struct drm_i915_gem_object *obj; |
268 | int ret; |
268 | int ret; |
269 | u32 handle; |
269 | u32 handle; |
270 | 270 | ||
271 | size = roundup(size, PAGE_SIZE); |
271 | size = roundup(size, PAGE_SIZE); |
272 | if (size == 0) |
272 | if (size == 0) |
273 | return -EINVAL; |
273 | return -EINVAL; |
274 | 274 | ||
275 | /* Allocate the new object */ |
275 | /* Allocate the new object */ |
276 | obj = i915_gem_alloc_object(dev, size); |
276 | obj = i915_gem_alloc_object(dev, size); |
277 | if (obj == NULL) |
277 | if (obj == NULL) |
278 | return -ENOMEM; |
278 | return -ENOMEM; |
279 | 279 | ||
280 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
280 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
281 | /* drop reference from allocate - handle holds it now */ |
281 | /* drop reference from allocate - handle holds it now */ |
282 | drm_gem_object_unreference_unlocked(&obj->base); |
282 | drm_gem_object_unreference_unlocked(&obj->base); |
283 | if (ret) |
283 | if (ret) |
284 | return ret; |
284 | return ret; |
285 | 285 | ||
286 | *handle_p = handle; |
286 | *handle_p = handle; |
287 | return 0; |
287 | return 0; |
288 | } |
288 | } |
289 | 289 | ||
290 | int |
290 | int |
291 | i915_gem_dumb_create(struct drm_file *file, |
291 | i915_gem_dumb_create(struct drm_file *file, |
292 | struct drm_device *dev, |
292 | struct drm_device *dev, |
293 | struct drm_mode_create_dumb *args) |
293 | struct drm_mode_create_dumb *args) |
294 | { |
294 | { |
295 | /* have to work out size/pitch and return them */ |
295 | /* have to work out size/pitch and return them */ |
296 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
296 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
297 | args->size = args->pitch * args->height; |
297 | args->size = args->pitch * args->height; |
298 | return i915_gem_create(file, dev, |
298 | return i915_gem_create(file, dev, |
299 | args->size, &args->handle); |
299 | args->size, &args->handle); |
300 | } |
300 | } |
301 | 301 | ||
302 | /** |
302 | /** |
303 | * Creates a new mm object and returns a handle to it. |
303 | * Creates a new mm object and returns a handle to it. |
304 | */ |
304 | */ |
305 | int |
305 | int |
306 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
306 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
307 | struct drm_file *file) |
307 | struct drm_file *file) |
308 | { |
308 | { |
309 | struct drm_i915_gem_create *args = data; |
309 | struct drm_i915_gem_create *args = data; |
310 | 310 | ||
311 | return i915_gem_create(file, dev, |
311 | return i915_gem_create(file, dev, |
312 | args->size, &args->handle); |
312 | args->size, &args->handle); |
313 | } |
313 | } |
314 | 314 | ||
315 | 315 | ||
316 | #if 0 |
316 | #if 0 |
317 | 317 | ||
318 | static inline int |
318 | static inline int |
319 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
319 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
320 | const char *gpu_vaddr, int gpu_offset, |
320 | const char *gpu_vaddr, int gpu_offset, |
321 | int length) |
321 | int length) |
322 | { |
322 | { |
323 | int ret, cpu_offset = 0; |
323 | int ret, cpu_offset = 0; |
324 | 324 | ||
325 | while (length > 0) { |
325 | while (length > 0) { |
326 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
326 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
327 | int this_length = min(cacheline_end - gpu_offset, length); |
327 | int this_length = min(cacheline_end - gpu_offset, length); |
328 | int swizzled_gpu_offset = gpu_offset ^ 64; |
328 | int swizzled_gpu_offset = gpu_offset ^ 64; |
329 | 329 | ||
330 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
330 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
331 | gpu_vaddr + swizzled_gpu_offset, |
331 | gpu_vaddr + swizzled_gpu_offset, |
332 | this_length); |
332 | this_length); |
333 | if (ret) |
333 | if (ret) |
334 | return ret + length; |
334 | return ret + length; |
335 | 335 | ||
336 | cpu_offset += this_length; |
336 | cpu_offset += this_length; |
337 | gpu_offset += this_length; |
337 | gpu_offset += this_length; |
338 | length -= this_length; |
338 | length -= this_length; |
339 | } |
339 | } |
340 | 340 | ||
341 | return 0; |
341 | return 0; |
342 | } |
342 | } |
343 | 343 | ||
344 | static inline int |
344 | static inline int |
345 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
345 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
346 | const char __user *cpu_vaddr, |
346 | const char __user *cpu_vaddr, |
347 | int length) |
347 | int length) |
348 | { |
348 | { |
349 | int ret, cpu_offset = 0; |
349 | int ret, cpu_offset = 0; |
350 | 350 | ||
351 | while (length > 0) { |
351 | while (length > 0) { |
352 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
352 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
353 | int this_length = min(cacheline_end - gpu_offset, length); |
353 | int this_length = min(cacheline_end - gpu_offset, length); |
354 | int swizzled_gpu_offset = gpu_offset ^ 64; |
354 | int swizzled_gpu_offset = gpu_offset ^ 64; |
355 | 355 | ||
356 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
356 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
357 | cpu_vaddr + cpu_offset, |
357 | cpu_vaddr + cpu_offset, |
358 | this_length); |
358 | this_length); |
359 | if (ret) |
359 | if (ret) |
360 | return ret + length; |
360 | return ret + length; |
361 | 361 | ||
362 | cpu_offset += this_length; |
362 | cpu_offset += this_length; |
363 | gpu_offset += this_length; |
363 | gpu_offset += this_length; |
364 | length -= this_length; |
364 | length -= this_length; |
365 | } |
365 | } |
366 | 366 | ||
367 | return 0; |
367 | return 0; |
368 | } |
368 | } |
369 | 369 | ||
370 | /* Per-page copy function for the shmem pread fastpath. |
370 | /* Per-page copy function for the shmem pread fastpath. |
371 | * Flushes invalid cachelines before reading the target if |
371 | * Flushes invalid cachelines before reading the target if |
372 | * needs_clflush is set. */ |
372 | * needs_clflush is set. */ |
373 | static int |
373 | static int |
374 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
374 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
375 | char __user *user_data, |
375 | char __user *user_data, |
376 | bool page_do_bit17_swizzling, bool needs_clflush) |
376 | bool page_do_bit17_swizzling, bool needs_clflush) |
377 | { |
377 | { |
378 | char *vaddr; |
378 | char *vaddr; |
379 | int ret; |
379 | int ret; |
380 | 380 | ||
381 | if (unlikely(page_do_bit17_swizzling)) |
381 | if (unlikely(page_do_bit17_swizzling)) |
382 | return -EINVAL; |
382 | return -EINVAL; |
383 | 383 | ||
384 | vaddr = kmap_atomic(page); |
384 | vaddr = kmap_atomic(page); |
385 | if (needs_clflush) |
385 | if (needs_clflush) |
386 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
386 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
387 | page_length); |
387 | page_length); |
388 | ret = __copy_to_user_inatomic(user_data, |
388 | ret = __copy_to_user_inatomic(user_data, |
389 | vaddr + shmem_page_offset, |
389 | vaddr + shmem_page_offset, |
390 | page_length); |
390 | page_length); |
391 | kunmap_atomic(vaddr); |
391 | kunmap_atomic(vaddr); |
392 | 392 | ||
393 | return ret ? -EFAULT : 0; |
393 | return ret ? -EFAULT : 0; |
394 | } |
394 | } |
395 | 395 | ||
396 | static void |
396 | static void |
397 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
397 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
398 | bool swizzled) |
398 | bool swizzled) |
399 | { |
399 | { |
400 | if (unlikely(swizzled)) { |
400 | if (unlikely(swizzled)) { |
401 | unsigned long start = (unsigned long) addr; |
401 | unsigned long start = (unsigned long) addr; |
402 | unsigned long end = (unsigned long) addr + length; |
402 | unsigned long end = (unsigned long) addr + length; |
403 | 403 | ||
404 | /* For swizzling simply ensure that we always flush both |
404 | /* For swizzling simply ensure that we always flush both |
405 | * channels. Lame, but simple and it works. Swizzled |
405 | * channels. Lame, but simple and it works. Swizzled |
406 | * pwrite/pread is far from a hotpath - current userspace |
406 | * pwrite/pread is far from a hotpath - current userspace |
407 | * doesn't use it at all. */ |
407 | * doesn't use it at all. */ |
408 | start = round_down(start, 128); |
408 | start = round_down(start, 128); |
409 | end = round_up(end, 128); |
409 | end = round_up(end, 128); |
410 | 410 | ||
411 | drm_clflush_virt_range((void *)start, end - start); |
411 | drm_clflush_virt_range((void *)start, end - start); |
412 | } else { |
412 | } else { |
413 | drm_clflush_virt_range(addr, length); |
413 | drm_clflush_virt_range(addr, length); |
414 | } |
414 | } |
415 | 415 | ||
416 | } |
416 | } |
417 | 417 | ||
418 | /* Only difference to the fast-path function is that this can handle bit17 |
418 | /* Only difference to the fast-path function is that this can handle bit17 |
419 | * and uses non-atomic copy and kmap functions. */ |
419 | * and uses non-atomic copy and kmap functions. */ |
420 | static int |
420 | static int |
421 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
421 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
422 | char __user *user_data, |
422 | char __user *user_data, |
423 | bool page_do_bit17_swizzling, bool needs_clflush) |
423 | bool page_do_bit17_swizzling, bool needs_clflush) |
424 | { |
424 | { |
425 | char *vaddr; |
425 | char *vaddr; |
426 | int ret; |
426 | int ret; |
427 | 427 | ||
428 | vaddr = kmap(page); |
428 | vaddr = kmap(page); |
429 | if (needs_clflush) |
429 | if (needs_clflush) |
430 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
430 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
431 | page_length, |
431 | page_length, |
432 | page_do_bit17_swizzling); |
432 | page_do_bit17_swizzling); |
433 | 433 | ||
434 | if (page_do_bit17_swizzling) |
434 | if (page_do_bit17_swizzling) |
435 | ret = __copy_to_user_swizzled(user_data, |
435 | ret = __copy_to_user_swizzled(user_data, |
436 | vaddr, shmem_page_offset, |
436 | vaddr, shmem_page_offset, |
437 | page_length); |
437 | page_length); |
438 | else |
438 | else |
439 | ret = __copy_to_user(user_data, |
439 | ret = __copy_to_user(user_data, |
440 | vaddr + shmem_page_offset, |
440 | vaddr + shmem_page_offset, |
441 | page_length); |
441 | page_length); |
442 | kunmap(page); |
442 | kunmap(page); |
443 | 443 | ||
444 | return ret ? - EFAULT : 0; |
444 | return ret ? - EFAULT : 0; |
445 | } |
445 | } |
446 | 446 | ||
447 | static int |
447 | static int |
448 | i915_gem_shmem_pread(struct drm_device *dev, |
448 | i915_gem_shmem_pread(struct drm_device *dev, |
449 | struct drm_i915_gem_object *obj, |
449 | struct drm_i915_gem_object *obj, |
450 | struct drm_i915_gem_pread *args, |
450 | struct drm_i915_gem_pread *args, |
451 | struct drm_file *file) |
451 | struct drm_file *file) |
452 | { |
452 | { |
453 | char __user *user_data; |
453 | char __user *user_data; |
454 | ssize_t remain; |
454 | ssize_t remain; |
455 | loff_t offset; |
455 | loff_t offset; |
456 | int shmem_page_offset, page_length, ret = 0; |
456 | int shmem_page_offset, page_length, ret = 0; |
457 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
457 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
458 | int prefaulted = 0; |
458 | int prefaulted = 0; |
459 | int needs_clflush = 0; |
459 | int needs_clflush = 0; |
460 | struct sg_page_iter sg_iter; |
460 | struct sg_page_iter sg_iter; |
461 | 461 | ||
462 | user_data = to_user_ptr(args->data_ptr); |
462 | user_data = to_user_ptr(args->data_ptr); |
463 | remain = args->size; |
463 | remain = args->size; |
464 | 464 | ||
465 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
465 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
466 | 466 | ||
467 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
467 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
468 | /* If we're not in the cpu read domain, set ourself into the gtt |
468 | /* If we're not in the cpu read domain, set ourself into the gtt |
469 | * read domain and manually flush cachelines (if required). This |
469 | * read domain and manually flush cachelines (if required). This |
470 | * optimizes for the case when the gpu will dirty the data |
470 | * optimizes for the case when the gpu will dirty the data |
471 | * anyway again before the next pread happens. */ |
471 | * anyway again before the next pread happens. */ |
472 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
472 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
473 | if (i915_gem_obj_bound_any(obj)) { |
473 | if (i915_gem_obj_bound_any(obj)) { |
474 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
474 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
475 | if (ret) |
475 | if (ret) |
476 | return ret; |
476 | return ret; |
477 | } |
477 | } |
478 | } |
478 | } |
479 | 479 | ||
480 | ret = i915_gem_object_get_pages(obj); |
480 | ret = i915_gem_object_get_pages(obj); |
481 | if (ret) |
481 | if (ret) |
482 | return ret; |
482 | return ret; |
483 | 483 | ||
484 | i915_gem_object_pin_pages(obj); |
484 | i915_gem_object_pin_pages(obj); |
485 | 485 | ||
486 | offset = args->offset; |
486 | offset = args->offset; |
487 | 487 | ||
488 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
488 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
489 | offset >> PAGE_SHIFT) { |
489 | offset >> PAGE_SHIFT) { |
490 | struct page *page = sg_page_iter_page(&sg_iter); |
490 | struct page *page = sg_page_iter_page(&sg_iter); |
491 | 491 | ||
492 | if (remain <= 0) |
492 | if (remain <= 0) |
493 | break; |
493 | break; |
494 | 494 | ||
495 | /* Operation in this page |
495 | /* Operation in this page |
496 | * |
496 | * |
497 | * shmem_page_offset = offset within page in shmem file |
497 | * shmem_page_offset = offset within page in shmem file |
498 | * page_length = bytes to copy for this page |
498 | * page_length = bytes to copy for this page |
499 | */ |
499 | */ |
500 | shmem_page_offset = offset_in_page(offset); |
500 | shmem_page_offset = offset_in_page(offset); |
501 | page_length = remain; |
501 | page_length = remain; |
502 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
502 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
503 | page_length = PAGE_SIZE - shmem_page_offset; |
503 | page_length = PAGE_SIZE - shmem_page_offset; |
504 | 504 | ||
505 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
505 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
506 | (page_to_phys(page) & (1 << 17)) != 0; |
506 | (page_to_phys(page) & (1 << 17)) != 0; |
507 | 507 | ||
508 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
508 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
509 | user_data, page_do_bit17_swizzling, |
509 | user_data, page_do_bit17_swizzling, |
510 | needs_clflush); |
510 | needs_clflush); |
511 | if (ret == 0) |
511 | if (ret == 0) |
512 | goto next_page; |
512 | goto next_page; |
513 | 513 | ||
514 | mutex_unlock(&dev->struct_mutex); |
514 | mutex_unlock(&dev->struct_mutex); |
515 | 515 | ||
516 | if (likely(!i915_prefault_disable) && !prefaulted) { |
516 | if (likely(!i915_prefault_disable) && !prefaulted) { |
517 | ret = fault_in_multipages_writeable(user_data, remain); |
517 | ret = fault_in_multipages_writeable(user_data, remain); |
518 | /* Userspace is tricking us, but we've already clobbered |
518 | /* Userspace is tricking us, but we've already clobbered |
519 | * its pages with the prefault and promised to write the |
519 | * its pages with the prefault and promised to write the |
520 | * data up to the first fault. Hence ignore any errors |
520 | * data up to the first fault. Hence ignore any errors |
521 | * and just continue. */ |
521 | * and just continue. */ |
522 | (void)ret; |
522 | (void)ret; |
523 | prefaulted = 1; |
523 | prefaulted = 1; |
524 | } |
524 | } |
525 | 525 | ||
526 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
526 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
527 | user_data, page_do_bit17_swizzling, |
527 | user_data, page_do_bit17_swizzling, |
528 | needs_clflush); |
528 | needs_clflush); |
529 | 529 | ||
530 | mutex_lock(&dev->struct_mutex); |
530 | mutex_lock(&dev->struct_mutex); |
531 | 531 | ||
532 | next_page: |
532 | next_page: |
533 | mark_page_accessed(page); |
533 | mark_page_accessed(page); |
534 | 534 | ||
535 | if (ret) |
535 | if (ret) |
536 | goto out; |
536 | goto out; |
537 | 537 | ||
538 | remain -= page_length; |
538 | remain -= page_length; |
539 | user_data += page_length; |
539 | user_data += page_length; |
540 | offset += page_length; |
540 | offset += page_length; |
541 | } |
541 | } |
542 | 542 | ||
543 | out: |
543 | out: |
544 | i915_gem_object_unpin_pages(obj); |
544 | i915_gem_object_unpin_pages(obj); |
545 | 545 | ||
546 | return ret; |
546 | return ret; |
547 | } |
547 | } |
548 | 548 | ||
549 | /** |
549 | /** |
550 | * Reads data from the object referenced by handle. |
550 | * Reads data from the object referenced by handle. |
551 | * |
551 | * |
552 | * On error, the contents of *data are undefined. |
552 | * On error, the contents of *data are undefined. |
553 | */ |
553 | */ |
554 | int |
554 | int |
555 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
555 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
556 | struct drm_file *file) |
556 | struct drm_file *file) |
557 | { |
557 | { |
558 | struct drm_i915_gem_pread *args = data; |
558 | struct drm_i915_gem_pread *args = data; |
559 | struct drm_i915_gem_object *obj; |
559 | struct drm_i915_gem_object *obj; |
560 | int ret = 0; |
560 | int ret = 0; |
561 | 561 | ||
562 | if (args->size == 0) |
562 | if (args->size == 0) |
563 | return 0; |
563 | return 0; |
564 | 564 | ||
565 | if (!access_ok(VERIFY_WRITE, |
565 | if (!access_ok(VERIFY_WRITE, |
566 | to_user_ptr(args->data_ptr), |
566 | to_user_ptr(args->data_ptr), |
567 | args->size)) |
567 | args->size)) |
568 | return -EFAULT; |
568 | return -EFAULT; |
569 | 569 | ||
570 | ret = i915_mutex_lock_interruptible(dev); |
570 | ret = i915_mutex_lock_interruptible(dev); |
571 | if (ret) |
571 | if (ret) |
572 | return ret; |
572 | return ret; |
573 | 573 | ||
574 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
574 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
575 | if (&obj->base == NULL) { |
575 | if (&obj->base == NULL) { |
576 | ret = -ENOENT; |
576 | ret = -ENOENT; |
577 | goto unlock; |
577 | goto unlock; |
578 | } |
578 | } |
579 | 579 | ||
580 | /* Bounds check source. */ |
580 | /* Bounds check source. */ |
581 | if (args->offset > obj->base.size || |
581 | if (args->offset > obj->base.size || |
582 | args->size > obj->base.size - args->offset) { |
582 | args->size > obj->base.size - args->offset) { |
583 | ret = -EINVAL; |
583 | ret = -EINVAL; |
584 | goto out; |
584 | goto out; |
585 | } |
585 | } |
586 | 586 | ||
587 | /* prime objects have no backing filp to GEM pread/pwrite |
587 | /* prime objects have no backing filp to GEM pread/pwrite |
588 | * pages from. |
588 | * pages from. |
589 | */ |
589 | */ |
590 | if (!obj->base.filp) { |
590 | if (!obj->base.filp) { |
591 | ret = -EINVAL; |
591 | ret = -EINVAL; |
592 | goto out; |
592 | goto out; |
593 | } |
593 | } |
594 | 594 | ||
595 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
595 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
596 | 596 | ||
597 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
597 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
598 | 598 | ||
599 | out: |
599 | out: |
600 | drm_gem_object_unreference(&obj->base); |
600 | drm_gem_object_unreference(&obj->base); |
601 | unlock: |
601 | unlock: |
602 | mutex_unlock(&dev->struct_mutex); |
602 | mutex_unlock(&dev->struct_mutex); |
603 | return ret; |
603 | return ret; |
604 | } |
604 | } |
605 | 605 | ||
606 | /* This is the fast write path which cannot handle |
606 | /* This is the fast write path which cannot handle |
607 | * page faults in the source data |
607 | * page faults in the source data |
608 | */ |
608 | */ |
609 | 609 | ||
610 | static inline int |
610 | static inline int |
611 | fast_user_write(struct io_mapping *mapping, |
611 | fast_user_write(struct io_mapping *mapping, |
612 | loff_t page_base, int page_offset, |
612 | loff_t page_base, int page_offset, |
613 | char __user *user_data, |
613 | char __user *user_data, |
614 | int length) |
614 | int length) |
615 | { |
615 | { |
616 | void __iomem *vaddr_atomic; |
616 | void __iomem *vaddr_atomic; |
617 | void *vaddr; |
617 | void *vaddr; |
618 | unsigned long unwritten; |
618 | unsigned long unwritten; |
619 | 619 | ||
620 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
620 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
621 | /* We can use the cpu mem copy function because this is X86. */ |
621 | /* We can use the cpu mem copy function because this is X86. */ |
622 | vaddr = (void __force*)vaddr_atomic + page_offset; |
622 | vaddr = (void __force*)vaddr_atomic + page_offset; |
623 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
623 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
624 | user_data, length); |
624 | user_data, length); |
625 | io_mapping_unmap_atomic(vaddr_atomic); |
625 | io_mapping_unmap_atomic(vaddr_atomic); |
626 | return unwritten; |
626 | return unwritten; |
627 | } |
627 | } |
628 | #endif |
628 | #endif |
629 | 629 | ||
630 | #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) |
630 | #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) |
631 | /** |
631 | /** |
632 | * This is the fast pwrite path, where we copy the data directly from the |
632 | * This is the fast pwrite path, where we copy the data directly from the |
633 | * user into the GTT, uncached. |
633 | * user into the GTT, uncached. |
634 | */ |
634 | */ |
635 | static int |
635 | static int |
636 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
636 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
637 | struct drm_i915_gem_object *obj, |
637 | struct drm_i915_gem_object *obj, |
638 | struct drm_i915_gem_pwrite *args, |
638 | struct drm_i915_gem_pwrite *args, |
639 | struct drm_file *file) |
639 | struct drm_file *file) |
640 | { |
640 | { |
641 | drm_i915_private_t *dev_priv = dev->dev_private; |
641 | drm_i915_private_t *dev_priv = dev->dev_private; |
642 | ssize_t remain; |
642 | ssize_t remain; |
643 | loff_t offset, page_base; |
643 | loff_t offset, page_base; |
644 | char __user *user_data; |
644 | char __user *user_data; |
645 | int page_offset, page_length, ret; |
645 | int page_offset, page_length, ret; |
646 | char *vaddr; |
646 | char *vaddr; |
647 | 647 | ||
648 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
648 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
649 | if (ret) |
649 | if (ret) |
650 | goto out; |
650 | goto out; |
651 | 651 | ||
652 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
652 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
653 | if (ret) |
653 | if (ret) |
654 | goto out_unpin; |
654 | goto out_unpin; |
655 | 655 | ||
656 | ret = i915_gem_object_put_fence(obj); |
656 | ret = i915_gem_object_put_fence(obj); |
657 | if (ret) |
657 | if (ret) |
658 | goto out_unpin; |
658 | goto out_unpin; |
659 | 659 | ||
660 | vaddr = AllocKernelSpace(4096); |
660 | vaddr = AllocKernelSpace(4096); |
661 | if(vaddr == NULL) |
661 | if(vaddr == NULL) |
662 | { |
662 | { |
663 | ret = -ENOSPC; |
663 | ret = -ENOSPC; |
664 | goto out_unpin; |
664 | goto out_unpin; |
665 | }; |
665 | }; |
666 | 666 | ||
667 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
667 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
668 | remain = args->size; |
668 | remain = args->size; |
669 | 669 | ||
670 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
670 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
671 | 671 | ||
672 | while (remain > 0) { |
672 | while (remain > 0) { |
673 | /* Operation in this page |
673 | /* Operation in this page |
674 | * |
674 | * |
675 | * page_base = page offset within aperture |
675 | * page_base = page offset within aperture |
676 | * page_offset = offset within page |
676 | * page_offset = offset within page |
677 | * page_length = bytes to copy for this page |
677 | * page_length = bytes to copy for this page |
678 | */ |
678 | */ |
679 | page_base = offset & PAGE_MASK; |
679 | page_base = offset & PAGE_MASK; |
680 | page_offset = offset_in_page(offset); |
680 | page_offset = offset_in_page(offset); |
681 | page_length = remain; |
681 | page_length = remain; |
682 | if ((page_offset + remain) > PAGE_SIZE) |
682 | if ((page_offset + remain) > PAGE_SIZE) |
683 | page_length = PAGE_SIZE - page_offset; |
683 | page_length = PAGE_SIZE - page_offset; |
684 | 684 | ||
685 | MapPage(vaddr, page_base, PG_SW|PG_NOCACHE); |
685 | MapPage(vaddr, dev_priv->gtt.mappable_base+page_base, PG_SW|PG_NOCACHE); |
686 | 686 | ||
687 | memcpy(vaddr+page_offset, user_data, page_length); |
687 | memcpy(vaddr+page_offset, user_data, page_length); |
688 | 688 | ||
689 | remain -= page_length; |
689 | remain -= page_length; |
690 | user_data += page_length; |
690 | user_data += page_length; |
691 | offset += page_length; |
691 | offset += page_length; |
692 | } |
692 | } |
693 | 693 | ||
694 | FreeKernelSpace(vaddr); |
694 | FreeKernelSpace(vaddr); |
695 | 695 | ||
696 | out_unpin: |
696 | out_unpin: |
697 | i915_gem_object_unpin(obj); |
697 | i915_gem_object_unpin(obj); |
698 | out: |
698 | out: |
699 | return ret; |
699 | return ret; |
700 | } |
700 | } |
701 | 701 | ||
702 | /* Per-page copy function for the shmem pwrite fastpath. |
702 | /* Per-page copy function for the shmem pwrite fastpath. |
703 | * Flushes invalid cachelines before writing to the target if |
703 | * Flushes invalid cachelines before writing to the target if |
704 | * needs_clflush_before is set and flushes out any written cachelines after |
704 | * needs_clflush_before is set and flushes out any written cachelines after |
705 | * writing if needs_clflush is set. */ |
705 | * writing if needs_clflush is set. */ |
706 | static int |
706 | static int |
707 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
707 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
708 | char __user *user_data, |
708 | char __user *user_data, |
709 | bool page_do_bit17_swizzling, |
709 | bool page_do_bit17_swizzling, |
710 | bool needs_clflush_before, |
710 | bool needs_clflush_before, |
711 | bool needs_clflush_after) |
711 | bool needs_clflush_after) |
712 | { |
712 | { |
713 | char *vaddr; |
713 | char *vaddr; |
714 | int ret = 0; |
714 | int ret = 0; |
715 | 715 | ||
716 | if (unlikely(page_do_bit17_swizzling)) |
716 | if (unlikely(page_do_bit17_swizzling)) |
717 | return -EINVAL; |
717 | return -EINVAL; |
718 | 718 | ||
719 | vaddr = (char *)MapIoMem((addr_t)page, 4096, PG_SW); |
719 | vaddr = (char *)MapIoMem((addr_t)page, 4096, PG_SW|PG_NOCACHE); |
720 | if (needs_clflush_before) |
720 | if (needs_clflush_before) |
721 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
721 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
722 | page_length); |
722 | page_length); |
723 | memcpy(vaddr + shmem_page_offset, |
723 | memcpy(vaddr + shmem_page_offset, |
724 | user_data, |
724 | user_data, |
725 | page_length); |
725 | page_length); |
726 | if (needs_clflush_after) |
726 | if (needs_clflush_after) |
727 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
727 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
728 | page_length); |
728 | page_length); |
729 | FreeKernelSpace(vaddr); |
729 | FreeKernelSpace(vaddr); |
730 | 730 | ||
731 | return ret ? -EFAULT : 0; |
731 | return ret ? -EFAULT : 0; |
732 | } |
732 | } |
733 | #if 0 |
733 | #if 0 |
734 | 734 | ||
735 | /* Only difference to the fast-path function is that this can handle bit17 |
735 | /* Only difference to the fast-path function is that this can handle bit17 |
736 | * and uses non-atomic copy and kmap functions. */ |
736 | * and uses non-atomic copy and kmap functions. */ |
737 | static int |
737 | static int |
738 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
738 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
739 | char __user *user_data, |
739 | char __user *user_data, |
740 | bool page_do_bit17_swizzling, |
740 | bool page_do_bit17_swizzling, |
741 | bool needs_clflush_before, |
741 | bool needs_clflush_before, |
742 | bool needs_clflush_after) |
742 | bool needs_clflush_after) |
743 | { |
743 | { |
744 | char *vaddr; |
744 | char *vaddr; |
745 | int ret; |
745 | int ret; |
746 | 746 | ||
747 | vaddr = kmap(page); |
747 | vaddr = kmap(page); |
748 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
748 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
749 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
749 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
750 | page_length, |
750 | page_length, |
751 | page_do_bit17_swizzling); |
751 | page_do_bit17_swizzling); |
752 | if (page_do_bit17_swizzling) |
752 | if (page_do_bit17_swizzling) |
753 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
753 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
754 | user_data, |
754 | user_data, |
755 | page_length); |
755 | page_length); |
756 | else |
756 | else |
757 | ret = __copy_from_user(vaddr + shmem_page_offset, |
757 | ret = __copy_from_user(vaddr + shmem_page_offset, |
758 | user_data, |
758 | user_data, |
759 | page_length); |
759 | page_length); |
760 | if (needs_clflush_after) |
760 | if (needs_clflush_after) |
761 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
761 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
762 | page_length, |
762 | page_length, |
763 | page_do_bit17_swizzling); |
763 | page_do_bit17_swizzling); |
764 | kunmap(page); |
764 | kunmap(page); |
765 | 765 | ||
766 | return ret ? -EFAULT : 0; |
766 | return ret ? -EFAULT : 0; |
767 | } |
767 | } |
768 | #endif |
768 | #endif |
769 | 769 | ||
770 | 770 | ||
771 | static int |
771 | static int |
772 | i915_gem_shmem_pwrite(struct drm_device *dev, |
772 | i915_gem_shmem_pwrite(struct drm_device *dev, |
773 | struct drm_i915_gem_object *obj, |
773 | struct drm_i915_gem_object *obj, |
774 | struct drm_i915_gem_pwrite *args, |
774 | struct drm_i915_gem_pwrite *args, |
775 | struct drm_file *file) |
775 | struct drm_file *file) |
776 | { |
776 | { |
777 | ssize_t remain; |
777 | ssize_t remain; |
778 | loff_t offset; |
778 | loff_t offset; |
779 | char __user *user_data; |
779 | char __user *user_data; |
780 | int shmem_page_offset, page_length, ret = 0; |
780 | int shmem_page_offset, page_length, ret = 0; |
781 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
781 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
782 | int hit_slowpath = 0; |
782 | int hit_slowpath = 0; |
783 | int needs_clflush_after = 0; |
783 | int needs_clflush_after = 0; |
784 | int needs_clflush_before = 0; |
784 | int needs_clflush_before = 0; |
785 | struct sg_page_iter sg_iter; |
785 | struct sg_page_iter sg_iter; |
786 | 786 | ||
787 | user_data = to_user_ptr(args->data_ptr); |
787 | user_data = to_user_ptr(args->data_ptr); |
788 | remain = args->size; |
788 | remain = args->size; |
789 | 789 | ||
790 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
790 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
791 | 791 | ||
792 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
792 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
793 | /* If we're not in the cpu write domain, set ourself into the gtt |
793 | /* If we're not in the cpu write domain, set ourself into the gtt |
794 | * write domain and manually flush cachelines (if required). This |
794 | * write domain and manually flush cachelines (if required). This |
795 | * optimizes for the case when the gpu will use the data |
795 | * optimizes for the case when the gpu will use the data |
796 | * right away and we therefore have to clflush anyway. */ |
796 | * right away and we therefore have to clflush anyway. */ |
797 | needs_clflush_after = cpu_write_needs_clflush(obj); |
797 | needs_clflush_after = cpu_write_needs_clflush(obj); |
798 | if (i915_gem_obj_bound_any(obj)) { |
798 | if (i915_gem_obj_bound_any(obj)) { |
799 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
799 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
800 | if (ret) |
800 | if (ret) |
801 | return ret; |
801 | return ret; |
802 | } |
802 | } |
803 | } |
803 | } |
804 | /* Same trick applies to invalidate partially written cachelines read |
804 | /* Same trick applies to invalidate partially written cachelines read |
805 | * before writing. */ |
805 | * before writing. */ |
806 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
806 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
807 | needs_clflush_before = |
807 | needs_clflush_before = |
808 | !cpu_cache_is_coherent(dev, obj->cache_level); |
808 | !cpu_cache_is_coherent(dev, obj->cache_level); |
809 | 809 | ||
810 | ret = i915_gem_object_get_pages(obj); |
810 | ret = i915_gem_object_get_pages(obj); |
811 | if (ret) |
811 | if (ret) |
812 | return ret; |
812 | return ret; |
813 | 813 | ||
814 | i915_gem_object_pin_pages(obj); |
814 | i915_gem_object_pin_pages(obj); |
815 | 815 | ||
816 | offset = args->offset; |
816 | offset = args->offset; |
817 | obj->dirty = 1; |
817 | obj->dirty = 1; |
818 | 818 | ||
819 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
819 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
820 | offset >> PAGE_SHIFT) { |
820 | offset >> PAGE_SHIFT) { |
821 | struct page *page = sg_page_iter_page(&sg_iter); |
821 | struct page *page = sg_page_iter_page(&sg_iter); |
822 | int partial_cacheline_write; |
822 | int partial_cacheline_write; |
823 | 823 | ||
824 | if (remain <= 0) |
824 | if (remain <= 0) |
825 | break; |
825 | break; |
826 | 826 | ||
827 | /* Operation in this page |
827 | /* Operation in this page |
828 | * |
828 | * |
829 | * shmem_page_offset = offset within page in shmem file |
829 | * shmem_page_offset = offset within page in shmem file |
830 | * page_length = bytes to copy for this page |
830 | * page_length = bytes to copy for this page |
831 | */ |
831 | */ |
832 | shmem_page_offset = offset_in_page(offset); |
832 | shmem_page_offset = offset_in_page(offset); |
833 | 833 | ||
834 | page_length = remain; |
834 | page_length = remain; |
835 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
835 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
836 | page_length = PAGE_SIZE - shmem_page_offset; |
836 | page_length = PAGE_SIZE - shmem_page_offset; |
837 | 837 | ||
838 | /* If we don't overwrite a cacheline completely we need to be |
838 | /* If we don't overwrite a cacheline completely we need to be |
839 | * careful to have up-to-date data by first clflushing. Don't |
839 | * careful to have up-to-date data by first clflushing. Don't |
840 | * overcomplicate things and flush the entire patch. */ |
840 | * overcomplicate things and flush the entire patch. */ |
841 | partial_cacheline_write = needs_clflush_before && |
841 | partial_cacheline_write = needs_clflush_before && |
842 | ((shmem_page_offset | page_length) |
842 | ((shmem_page_offset | page_length) |
843 | & (x86_clflush_size - 1)); |
843 | & (x86_clflush_size - 1)); |
844 | 844 | ||
845 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
845 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
846 | (page_to_phys(page) & (1 << 17)) != 0; |
846 | (page_to_phys(page) & (1 << 17)) != 0; |
847 | 847 | ||
848 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
848 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
849 | user_data, page_do_bit17_swizzling, |
849 | user_data, page_do_bit17_swizzling, |
850 | partial_cacheline_write, |
850 | partial_cacheline_write, |
851 | needs_clflush_after); |
851 | needs_clflush_after); |
852 | if (ret == 0) |
852 | if (ret == 0) |
853 | goto next_page; |
853 | goto next_page; |
854 | 854 | ||
855 | hit_slowpath = 1; |
855 | hit_slowpath = 1; |
856 | mutex_unlock(&dev->struct_mutex); |
856 | mutex_unlock(&dev->struct_mutex); |
857 | dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__); |
857 | dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__); |
858 | 858 | ||
859 | // ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
859 | // ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
860 | // user_data, page_do_bit17_swizzling, |
860 | // user_data, page_do_bit17_swizzling, |
861 | // partial_cacheline_write, |
861 | // partial_cacheline_write, |
862 | // needs_clflush_after); |
862 | // needs_clflush_after); |
863 | 863 | ||
864 | mutex_lock(&dev->struct_mutex); |
864 | mutex_lock(&dev->struct_mutex); |
865 | 865 | ||
866 | next_page: |
866 | next_page: |
867 | 867 | ||
868 | if (ret) |
868 | if (ret) |
869 | goto out; |
869 | goto out; |
870 | 870 | ||
871 | remain -= page_length; |
871 | remain -= page_length; |
872 | user_data += page_length; |
872 | user_data += page_length; |
873 | offset += page_length; |
873 | offset += page_length; |
874 | } |
874 | } |
875 | 875 | ||
876 | out: |
876 | out: |
877 | i915_gem_object_unpin_pages(obj); |
877 | i915_gem_object_unpin_pages(obj); |
878 | 878 | ||
879 | if (hit_slowpath) { |
879 | if (hit_slowpath) { |
880 | /* |
880 | /* |
881 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
881 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
882 | * cachelines in-line while writing and the object moved |
882 | * cachelines in-line while writing and the object moved |
883 | * out of the cpu write domain while we've dropped the lock. |
883 | * out of the cpu write domain while we've dropped the lock. |
884 | */ |
884 | */ |
885 | if (!needs_clflush_after && |
885 | if (!needs_clflush_after && |
886 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
886 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
887 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
887 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
888 | i915_gem_chipset_flush(dev); |
888 | i915_gem_chipset_flush(dev); |
889 | } |
889 | } |
890 | } |
890 | } |
891 | 891 | ||
892 | if (needs_clflush_after) |
892 | if (needs_clflush_after) |
893 | i915_gem_chipset_flush(dev); |
893 | i915_gem_chipset_flush(dev); |
894 | 894 | ||
895 | return ret; |
895 | return ret; |
896 | } |
896 | } |
897 | 897 | ||
898 | /** |
898 | /** |
899 | * Writes data to the object referenced by handle. |
899 | * Writes data to the object referenced by handle. |
900 | * |
900 | * |
901 | * On error, the contents of the buffer that were to be modified are undefined. |
901 | * On error, the contents of the buffer that were to be modified are undefined. |
902 | */ |
902 | */ |
903 | int |
903 | int |
904 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
904 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
905 | struct drm_file *file) |
905 | struct drm_file *file) |
906 | { |
906 | { |
907 | struct drm_i915_gem_pwrite *args = data; |
907 | struct drm_i915_gem_pwrite *args = data; |
908 | struct drm_i915_gem_object *obj; |
908 | struct drm_i915_gem_object *obj; |
909 | int ret; |
909 | int ret; |
910 | 910 | ||
911 | if (args->size == 0) |
911 | if (args->size == 0) |
912 | return 0; |
912 | return 0; |
913 | 913 | ||
914 | if(args->handle == -2) |
914 | if(args->handle == -2) |
915 | { |
915 | { |
916 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
916 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
917 | return 0; |
917 | return 0; |
918 | } |
918 | } |
919 | 919 | ||
920 | ret = i915_mutex_lock_interruptible(dev); |
920 | ret = i915_mutex_lock_interruptible(dev); |
921 | if (ret) |
921 | if (ret) |
922 | return ret; |
922 | return ret; |
923 | 923 | ||
924 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
924 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
925 | if (&obj->base == NULL) { |
925 | if (&obj->base == NULL) { |
926 | ret = -ENOENT; |
926 | ret = -ENOENT; |
927 | goto unlock; |
927 | goto unlock; |
928 | } |
928 | } |
929 | 929 | ||
930 | /* Bounds check destination. */ |
930 | /* Bounds check destination. */ |
931 | if (args->offset > obj->base.size || |
931 | if (args->offset > obj->base.size || |
932 | args->size > obj->base.size - args->offset) { |
932 | args->size > obj->base.size - args->offset) { |
933 | ret = -EINVAL; |
933 | ret = -EINVAL; |
934 | goto out; |
934 | goto out; |
935 | } |
935 | } |
936 | 936 | ||
937 | /* prime objects have no backing filp to GEM pread/pwrite |
937 | /* prime objects have no backing filp to GEM pread/pwrite |
938 | * pages from. |
938 | * pages from. |
939 | */ |
939 | */ |
940 | if (!obj->base.filp) { |
940 | if (!obj->base.filp) { |
941 | ret = -EINVAL; |
941 | ret = -EINVAL; |
942 | goto out; |
942 | goto out; |
943 | } |
943 | } |
944 | 944 | ||
945 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
945 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
946 | 946 | ||
947 | ret = -EFAULT; |
947 | ret = -EFAULT; |
948 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
948 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
949 | * it would end up going through the fenced access, and we'll get |
949 | * it would end up going through the fenced access, and we'll get |
950 | * different detiling behavior between reading and writing. |
950 | * different detiling behavior between reading and writing. |
951 | * pread/pwrite currently are reading and writing from the CPU |
951 | * pread/pwrite currently are reading and writing from the CPU |
952 | * perspective, requiring manual detiling by the client. |
952 | * perspective, requiring manual detiling by the client. |
953 | */ |
953 | */ |
954 | // if (obj->phys_obj) { |
954 | // if (obj->phys_obj) { |
955 | // ret = i915_gem_phys_pwrite(dev, obj, args, file); |
955 | // ret = i915_gem_phys_pwrite(dev, obj, args, file); |
956 | // goto out; |
956 | // goto out; |
957 | // } |
957 | // } |
958 | 958 | ||
959 | if (obj->tiling_mode == I915_TILING_NONE && |
959 | if (obj->tiling_mode == I915_TILING_NONE && |
960 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
960 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
961 | cpu_write_needs_clflush(obj)) { |
961 | cpu_write_needs_clflush(obj)) { |
962 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
962 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
963 | /* Note that the gtt paths might fail with non-page-backed user |
963 | /* Note that the gtt paths might fail with non-page-backed user |
964 | * pointers (e.g. gtt mappings when moving data between |
964 | * pointers (e.g. gtt mappings when moving data between |
965 | * textures). Fallback to the shmem path in that case. */ |
965 | * textures). Fallback to the shmem path in that case. */ |
966 | } |
966 | } |
967 | 967 | ||
968 | if (ret == -EFAULT || ret == -ENOSPC) |
968 | if (ret == -EFAULT || ret == -ENOSPC) |
969 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
969 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
970 | 970 | ||
971 | out: |
971 | out: |
972 | drm_gem_object_unreference(&obj->base); |
972 | drm_gem_object_unreference(&obj->base); |
973 | unlock: |
973 | unlock: |
974 | mutex_unlock(&dev->struct_mutex); |
974 | mutex_unlock(&dev->struct_mutex); |
975 | return ret; |
975 | return ret; |
976 | } |
976 | } |
977 | 977 | ||
978 | int |
978 | int |
979 | i915_gem_check_wedge(struct i915_gpu_error *error, |
979 | i915_gem_check_wedge(struct i915_gpu_error *error, |
980 | bool interruptible) |
980 | bool interruptible) |
981 | { |
981 | { |
982 | if (i915_reset_in_progress(error)) { |
982 | if (i915_reset_in_progress(error)) { |
983 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
983 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
984 | * -EIO unconditionally for these. */ |
984 | * -EIO unconditionally for these. */ |
985 | if (!interruptible) |
985 | if (!interruptible) |
986 | return -EIO; |
986 | return -EIO; |
987 | 987 | ||
988 | /* Recovery complete, but the reset failed ... */ |
988 | /* Recovery complete, but the reset failed ... */ |
989 | if (i915_terminally_wedged(error)) |
989 | if (i915_terminally_wedged(error)) |
990 | return -EIO; |
990 | return -EIO; |
991 | 991 | ||
992 | return -EAGAIN; |
992 | return -EAGAIN; |
993 | } |
993 | } |
994 | 994 | ||
995 | return 0; |
995 | return 0; |
996 | } |
996 | } |
997 | 997 | ||
998 | /* |
998 | /* |
999 | * Compare seqno against outstanding lazy request. Emit a request if they are |
999 | * Compare seqno against outstanding lazy request. Emit a request if they are |
1000 | * equal. |
1000 | * equal. |
1001 | */ |
1001 | */ |
1002 | static int |
1002 | static int |
1003 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
1003 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
1004 | { |
1004 | { |
1005 | int ret; |
1005 | int ret; |
1006 | 1006 | ||
1007 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
1007 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
1008 | 1008 | ||
1009 | ret = 0; |
1009 | ret = 0; |
1010 | if (seqno == ring->outstanding_lazy_request) |
1010 | if (seqno == ring->outstanding_lazy_request) |
1011 | ret = i915_add_request(ring, NULL); |
1011 | ret = i915_add_request(ring, NULL); |
1012 | 1012 | ||
1013 | return ret; |
1013 | return ret; |
1014 | } |
1014 | } |
1015 | 1015 | ||
1016 | /** |
1016 | /** |
1017 | * __wait_seqno - wait until execution of seqno has finished |
1017 | * __wait_seqno - wait until execution of seqno has finished |
1018 | * @ring: the ring expected to report seqno |
1018 | * @ring: the ring expected to report seqno |
1019 | * @seqno: duh! |
1019 | * @seqno: duh! |
1020 | * @reset_counter: reset sequence associated with the given seqno |
1020 | * @reset_counter: reset sequence associated with the given seqno |
1021 | * @interruptible: do an interruptible wait (normally yes) |
1021 | * @interruptible: do an interruptible wait (normally yes) |
1022 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
1022 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
1023 | * |
1023 | * |
1024 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1024 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1025 | * values have been read by the caller in an smp safe manner. Where read-side |
1025 | * values have been read by the caller in an smp safe manner. Where read-side |
1026 | * locks are involved, it is sufficient to read the reset_counter before |
1026 | * locks are involved, it is sufficient to read the reset_counter before |
1027 | * unlocking the lock that protects the seqno. For lockless tricks, the |
1027 | * unlocking the lock that protects the seqno. For lockless tricks, the |
1028 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
1028 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
1029 | * inserted. |
1029 | * inserted. |
1030 | * |
1030 | * |
1031 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1031 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1032 | * errno with remaining time filled in timeout argument. |
1032 | * errno with remaining time filled in timeout argument. |
1033 | */ |
1033 | */ |
1034 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
1034 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
1035 | unsigned reset_counter, |
1035 | unsigned reset_counter, |
1036 | bool interruptible, struct timespec *timeout) |
1036 | bool interruptible, struct timespec *timeout) |
1037 | { |
1037 | { |
1038 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1038 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1039 | struct timespec before, now, wait_time={1,0}; |
1039 | struct timespec before, now, wait_time={1,0}; |
1040 | unsigned long timeout_jiffies; |
1040 | unsigned long timeout_jiffies; |
1041 | long end; |
1041 | long end; |
1042 | bool wait_forever = true; |
1042 | bool wait_forever = true; |
1043 | int ret; |
1043 | int ret; |
1044 | 1044 | ||
1045 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1045 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1046 | 1046 | ||
1047 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1047 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1048 | return 0; |
1048 | return 0; |
1049 | 1049 | ||
1050 | trace_i915_gem_request_wait_begin(ring, seqno); |
1050 | trace_i915_gem_request_wait_begin(ring, seqno); |
1051 | 1051 | ||
1052 | if (timeout != NULL) { |
1052 | if (timeout != NULL) { |
1053 | wait_time = *timeout; |
1053 | wait_time = *timeout; |
1054 | wait_forever = false; |
1054 | wait_forever = false; |
1055 | } |
1055 | } |
1056 | 1056 | ||
1057 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
1057 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
1058 | 1058 | ||
1059 | if (WARN_ON(!ring->irq_get(ring))) |
1059 | if (WARN_ON(!ring->irq_get(ring))) |
1060 | return -ENODEV; |
1060 | return -ENODEV; |
1061 | 1061 | ||
1062 | /* Record current time in case interrupted by signal, or wedged * */ |
1062 | /* Record current time in case interrupted by signal, or wedged * */ |
1063 | getrawmonotonic(&before); |
1063 | getrawmonotonic(&before); |
1064 | 1064 | ||
1065 | #define EXIT_COND \ |
1065 | #define EXIT_COND \ |
1066 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
1066 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
1067 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1067 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1068 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
1068 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
1069 | do { |
1069 | do { |
1070 | if (interruptible) |
1070 | if (interruptible) |
1071 | end = wait_event_interruptible_timeout(ring->irq_queue, |
1071 | end = wait_event_interruptible_timeout(ring->irq_queue, |
1072 | EXIT_COND, |
1072 | EXIT_COND, |
1073 | timeout_jiffies); |
1073 | timeout_jiffies); |
1074 | else |
1074 | else |
1075 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
1075 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
1076 | timeout_jiffies); |
1076 | timeout_jiffies); |
1077 | 1077 | ||
1078 | /* We need to check whether any gpu reset happened in between |
1078 | /* We need to check whether any gpu reset happened in between |
1079 | * the caller grabbing the seqno and now ... */ |
1079 | * the caller grabbing the seqno and now ... */ |
1080 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
1080 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
1081 | end = -EAGAIN; |
1081 | end = -EAGAIN; |
1082 | 1082 | ||
1083 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely |
1083 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely |
1084 | * gone. */ |
1084 | * gone. */ |
1085 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1085 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1086 | if (ret) |
1086 | if (ret) |
1087 | end = ret; |
1087 | end = ret; |
1088 | } while (end == 0 && wait_forever); |
1088 | } while (end == 0 && wait_forever); |
1089 | 1089 | ||
1090 | getrawmonotonic(&now); |
1090 | getrawmonotonic(&now); |
1091 | 1091 | ||
1092 | ring->irq_put(ring); |
1092 | ring->irq_put(ring); |
1093 | trace_i915_gem_request_wait_end(ring, seqno); |
1093 | trace_i915_gem_request_wait_end(ring, seqno); |
1094 | #undef EXIT_COND |
1094 | #undef EXIT_COND |
1095 | 1095 | ||
1096 | if (timeout) { |
1096 | if (timeout) { |
1097 | // struct timespec sleep_time = timespec_sub(now, before); |
1097 | // struct timespec sleep_time = timespec_sub(now, before); |
1098 | // *timeout = timespec_sub(*timeout, sleep_time); |
1098 | // *timeout = timespec_sub(*timeout, sleep_time); |
1099 | } |
1099 | } |
1100 | 1100 | ||
1101 | switch (end) { |
1101 | switch (end) { |
1102 | case -EIO: |
1102 | case -EIO: |
1103 | case -EAGAIN: /* Wedged */ |
1103 | case -EAGAIN: /* Wedged */ |
1104 | case -ERESTARTSYS: /* Signal */ |
1104 | case -ERESTARTSYS: /* Signal */ |
1105 | return (int)end; |
1105 | return (int)end; |
1106 | case 0: /* Timeout */ |
1106 | case 0: /* Timeout */ |
1107 | return -ETIME; |
1107 | return -ETIME; |
1108 | default: /* Completed */ |
1108 | default: /* Completed */ |
1109 | WARN_ON(end < 0); /* We're not aware of other errors */ |
1109 | WARN_ON(end < 0); /* We're not aware of other errors */ |
1110 | return 0; |
1110 | return 0; |
1111 | } |
1111 | } |
1112 | } |
1112 | } |
1113 | 1113 | ||
1114 | /** |
1114 | /** |
1115 | * Waits for a sequence number to be signaled, and cleans up the |
1115 | * Waits for a sequence number to be signaled, and cleans up the |
1116 | * request and object lists appropriately for that event. |
1116 | * request and object lists appropriately for that event. |
1117 | */ |
1117 | */ |
1118 | int |
1118 | int |
1119 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
1119 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
1120 | { |
1120 | { |
1121 | struct drm_device *dev = ring->dev; |
1121 | struct drm_device *dev = ring->dev; |
1122 | struct drm_i915_private *dev_priv = dev->dev_private; |
1122 | struct drm_i915_private *dev_priv = dev->dev_private; |
1123 | bool interruptible = dev_priv->mm.interruptible; |
1123 | bool interruptible = dev_priv->mm.interruptible; |
1124 | int ret; |
1124 | int ret; |
1125 | 1125 | ||
1126 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1126 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1127 | BUG_ON(seqno == 0); |
1127 | BUG_ON(seqno == 0); |
1128 | 1128 | ||
1129 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1129 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1130 | if (ret) |
1130 | if (ret) |
1131 | return ret; |
1131 | return ret; |
1132 | 1132 | ||
1133 | ret = i915_gem_check_olr(ring, seqno); |
1133 | ret = i915_gem_check_olr(ring, seqno); |
1134 | if (ret) |
1134 | if (ret) |
1135 | return ret; |
1135 | return ret; |
1136 | 1136 | ||
1137 | return __wait_seqno(ring, seqno, |
1137 | return __wait_seqno(ring, seqno, |
1138 | atomic_read(&dev_priv->gpu_error.reset_counter), |
1138 | atomic_read(&dev_priv->gpu_error.reset_counter), |
1139 | interruptible, NULL); |
1139 | interruptible, NULL); |
1140 | } |
1140 | } |
1141 | 1141 | ||
1142 | static int |
1142 | static int |
1143 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
1143 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
1144 | struct intel_ring_buffer *ring) |
1144 | struct intel_ring_buffer *ring) |
1145 | { |
1145 | { |
1146 | i915_gem_retire_requests_ring(ring); |
1146 | i915_gem_retire_requests_ring(ring); |
1147 | 1147 | ||
1148 | /* Manually manage the write flush as we may have not yet |
1148 | /* Manually manage the write flush as we may have not yet |
1149 | * retired the buffer. |
1149 | * retired the buffer. |
1150 | * |
1150 | * |
1151 | * Note that the last_write_seqno is always the earlier of |
1151 | * Note that the last_write_seqno is always the earlier of |
1152 | * the two (read/write) seqno, so if we haved successfully waited, |
1152 | * the two (read/write) seqno, so if we haved successfully waited, |
1153 | * we know we have passed the last write. |
1153 | * we know we have passed the last write. |
1154 | */ |
1154 | */ |
1155 | obj->last_write_seqno = 0; |
1155 | obj->last_write_seqno = 0; |
1156 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
1156 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
1157 | 1157 | ||
1158 | return 0; |
1158 | return 0; |
1159 | } |
1159 | } |
1160 | 1160 | ||
1161 | /** |
1161 | /** |
1162 | * Ensures that all rendering to the object has completed and the object is |
1162 | * Ensures that all rendering to the object has completed and the object is |
1163 | * safe to unbind from the GTT or access from the CPU. |
1163 | * safe to unbind from the GTT or access from the CPU. |
1164 | */ |
1164 | */ |
1165 | static __must_check int |
1165 | static __must_check int |
1166 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1166 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1167 | bool readonly) |
1167 | bool readonly) |
1168 | { |
1168 | { |
1169 | struct intel_ring_buffer *ring = obj->ring; |
1169 | struct intel_ring_buffer *ring = obj->ring; |
1170 | u32 seqno; |
1170 | u32 seqno; |
1171 | int ret; |
1171 | int ret; |
1172 | 1172 | ||
1173 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1173 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1174 | if (seqno == 0) |
1174 | if (seqno == 0) |
1175 | return 0; |
1175 | return 0; |
1176 | 1176 | ||
1177 | ret = i915_wait_seqno(ring, seqno); |
1177 | ret = i915_wait_seqno(ring, seqno); |
1178 | if (ret) |
1178 | if (ret) |
1179 | return ret; |
1179 | return ret; |
1180 | 1180 | ||
1181 | return i915_gem_object_wait_rendering__tail(obj, ring); |
1181 | return i915_gem_object_wait_rendering__tail(obj, ring); |
1182 | } |
1182 | } |
1183 | 1183 | ||
1184 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1184 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1185 | * as the object state may change during this call. |
1185 | * as the object state may change during this call. |
1186 | */ |
1186 | */ |
1187 | static __must_check int |
1187 | static __must_check int |
1188 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
1188 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
1189 | bool readonly) |
1189 | bool readonly) |
1190 | { |
1190 | { |
1191 | struct drm_device *dev = obj->base.dev; |
1191 | struct drm_device *dev = obj->base.dev; |
1192 | struct drm_i915_private *dev_priv = dev->dev_private; |
1192 | struct drm_i915_private *dev_priv = dev->dev_private; |
1193 | struct intel_ring_buffer *ring = obj->ring; |
1193 | struct intel_ring_buffer *ring = obj->ring; |
1194 | unsigned reset_counter; |
1194 | unsigned reset_counter; |
1195 | u32 seqno; |
1195 | u32 seqno; |
1196 | int ret; |
1196 | int ret; |
1197 | 1197 | ||
1198 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1198 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1199 | BUG_ON(!dev_priv->mm.interruptible); |
1199 | BUG_ON(!dev_priv->mm.interruptible); |
1200 | 1200 | ||
1201 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1201 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1202 | if (seqno == 0) |
1202 | if (seqno == 0) |
1203 | return 0; |
1203 | return 0; |
1204 | 1204 | ||
1205 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
1205 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
1206 | if (ret) |
1206 | if (ret) |
1207 | return ret; |
1207 | return ret; |
1208 | 1208 | ||
1209 | ret = i915_gem_check_olr(ring, seqno); |
1209 | ret = i915_gem_check_olr(ring, seqno); |
1210 | if (ret) |
1210 | if (ret) |
1211 | return ret; |
1211 | return ret; |
1212 | 1212 | ||
1213 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1213 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1214 | mutex_unlock(&dev->struct_mutex); |
1214 | mutex_unlock(&dev->struct_mutex); |
1215 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
1215 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
1216 | mutex_lock(&dev->struct_mutex); |
1216 | mutex_lock(&dev->struct_mutex); |
1217 | if (ret) |
1217 | if (ret) |
1218 | return ret; |
1218 | return ret; |
1219 | 1219 | ||
1220 | return i915_gem_object_wait_rendering__tail(obj, ring); |
1220 | return i915_gem_object_wait_rendering__tail(obj, ring); |
1221 | } |
1221 | } |
1222 | 1222 | ||
1223 | /** |
1223 | /** |
1224 | * Called when user space prepares to use an object with the CPU, either |
1224 | * Called when user space prepares to use an object with the CPU, either |
1225 | * through the mmap ioctl's mapping or a GTT mapping. |
1225 | * through the mmap ioctl's mapping or a GTT mapping. |
1226 | */ |
1226 | */ |
1227 | int |
1227 | int |
1228 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1228 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1229 | struct drm_file *file) |
1229 | struct drm_file *file) |
1230 | { |
1230 | { |
1231 | struct drm_i915_gem_set_domain *args = data; |
1231 | struct drm_i915_gem_set_domain *args = data; |
1232 | struct drm_i915_gem_object *obj; |
1232 | struct drm_i915_gem_object *obj; |
1233 | uint32_t read_domains = args->read_domains; |
1233 | uint32_t read_domains = args->read_domains; |
1234 | uint32_t write_domain = args->write_domain; |
1234 | uint32_t write_domain = args->write_domain; |
1235 | int ret; |
1235 | int ret; |
1236 | 1236 | ||
1237 | 1237 | ||
1238 | if(args->handle == -2) |
1238 | if(args->handle == -2) |
1239 | { |
1239 | { |
1240 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
1240 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
1241 | return 0; |
1241 | return 0; |
1242 | } |
1242 | } |
1243 | 1243 | ||
1244 | /* Only handle setting domains to types used by the CPU. */ |
1244 | /* Only handle setting domains to types used by the CPU. */ |
1245 | if (write_domain & I915_GEM_GPU_DOMAINS) |
1245 | if (write_domain & I915_GEM_GPU_DOMAINS) |
1246 | return -EINVAL; |
1246 | return -EINVAL; |
1247 | 1247 | ||
1248 | if (read_domains & I915_GEM_GPU_DOMAINS) |
1248 | if (read_domains & I915_GEM_GPU_DOMAINS) |
1249 | return -EINVAL; |
1249 | return -EINVAL; |
1250 | 1250 | ||
1251 | /* Having something in the write domain implies it's in the read |
1251 | /* Having something in the write domain implies it's in the read |
1252 | * domain, and only that read domain. Enforce that in the request. |
1252 | * domain, and only that read domain. Enforce that in the request. |
1253 | */ |
1253 | */ |
1254 | if (write_domain != 0 && read_domains != write_domain) |
1254 | if (write_domain != 0 && read_domains != write_domain) |
1255 | return -EINVAL; |
1255 | return -EINVAL; |
1256 | 1256 | ||
1257 | ret = i915_mutex_lock_interruptible(dev); |
1257 | ret = i915_mutex_lock_interruptible(dev); |
1258 | if (ret) |
1258 | if (ret) |
1259 | return ret; |
1259 | return ret; |
1260 | 1260 | ||
1261 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1261 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1262 | if (&obj->base == NULL) { |
1262 | if (&obj->base == NULL) { |
1263 | ret = -ENOENT; |
1263 | ret = -ENOENT; |
1264 | goto unlock; |
1264 | goto unlock; |
1265 | } |
1265 | } |
1266 | 1266 | ||
1267 | /* Try to flush the object off the GPU without holding the lock. |
1267 | /* Try to flush the object off the GPU without holding the lock. |
1268 | * We will repeat the flush holding the lock in the normal manner |
1268 | * We will repeat the flush holding the lock in the normal manner |
1269 | * to catch cases where we are gazumped. |
1269 | * to catch cases where we are gazumped. |
1270 | */ |
1270 | */ |
1271 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
1271 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
1272 | if (ret) |
1272 | if (ret) |
1273 | goto unref; |
1273 | goto unref; |
1274 | 1274 | ||
1275 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1275 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1276 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
1276 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
1277 | 1277 | ||
1278 | /* Silently promote "you're not bound, there was nothing to do" |
1278 | /* Silently promote "you're not bound, there was nothing to do" |
1279 | * to success, since the client was just asking us to |
1279 | * to success, since the client was just asking us to |
1280 | * make sure everything was done. |
1280 | * make sure everything was done. |
1281 | */ |
1281 | */ |
1282 | if (ret == -EINVAL) |
1282 | if (ret == -EINVAL) |
1283 | ret = 0; |
1283 | ret = 0; |
1284 | } else { |
1284 | } else { |
1285 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
1285 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
1286 | } |
1286 | } |
1287 | 1287 | ||
1288 | unref: |
1288 | unref: |
1289 | drm_gem_object_unreference(&obj->base); |
1289 | drm_gem_object_unreference(&obj->base); |
1290 | unlock: |
1290 | unlock: |
1291 | mutex_unlock(&dev->struct_mutex); |
1291 | mutex_unlock(&dev->struct_mutex); |
1292 | return ret; |
1292 | return ret; |
1293 | } |
1293 | } |
1294 | 1294 | ||
1295 | /** |
1295 | /** |
1296 | * Called when user space has done writes to this buffer |
1296 | * Called when user space has done writes to this buffer |
1297 | */ |
1297 | */ |
1298 | int |
1298 | int |
1299 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
1299 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
1300 | struct drm_file *file) |
1300 | struct drm_file *file) |
1301 | { |
1301 | { |
1302 | struct drm_i915_gem_sw_finish *args = data; |
1302 | struct drm_i915_gem_sw_finish *args = data; |
1303 | struct drm_i915_gem_object *obj; |
1303 | struct drm_i915_gem_object *obj; |
1304 | int ret = 0; |
1304 | int ret = 0; |
1305 | 1305 | ||
1306 | if(args->handle == -2) |
1306 | if(args->handle == -2) |
1307 | { |
1307 | { |
1308 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
1308 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
1309 | return 0; |
1309 | return 0; |
1310 | } |
1310 | } |
1311 | 1311 | ||
1312 | ret = i915_mutex_lock_interruptible(dev); |
1312 | ret = i915_mutex_lock_interruptible(dev); |
1313 | if (ret) |
1313 | if (ret) |
1314 | return ret; |
1314 | return ret; |
1315 | 1315 | ||
1316 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1316 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1317 | if (&obj->base == NULL) { |
1317 | if (&obj->base == NULL) { |
1318 | ret = -ENOENT; |
1318 | ret = -ENOENT; |
1319 | goto unlock; |
1319 | goto unlock; |
1320 | } |
1320 | } |
1321 | 1321 | ||
1322 | /* Pinned buffers may be scanout, so flush the cache */ |
1322 | /* Pinned buffers may be scanout, so flush the cache */ |
1323 | if (obj->pin_display) |
1323 | if (obj->pin_display) |
1324 | i915_gem_object_flush_cpu_write_domain(obj, true); |
1324 | i915_gem_object_flush_cpu_write_domain(obj, true); |
1325 | 1325 | ||
1326 | drm_gem_object_unreference(&obj->base); |
1326 | drm_gem_object_unreference(&obj->base); |
1327 | unlock: |
1327 | unlock: |
1328 | mutex_unlock(&dev->struct_mutex); |
1328 | mutex_unlock(&dev->struct_mutex); |
1329 | return ret; |
1329 | return ret; |
1330 | } |
1330 | } |
1331 | 1331 | ||
1332 | /** |
1332 | /** |
1333 | * Maps the contents of an object, returning the address it is mapped |
1333 | * Maps the contents of an object, returning the address it is mapped |
1334 | * into. |
1334 | * into. |
1335 | * |
1335 | * |
1336 | * While the mapping holds a reference on the contents of the object, it doesn't |
1336 | * While the mapping holds a reference on the contents of the object, it doesn't |
1337 | * imply a ref on the object itself. |
1337 | * imply a ref on the object itself. |
1338 | */ |
1338 | */ |
1339 | int |
1339 | int |
1340 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
1340 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
1341 | struct drm_file *file) |
1341 | struct drm_file *file) |
1342 | { |
1342 | { |
1343 | struct drm_i915_gem_mmap *args = data; |
1343 | struct drm_i915_gem_mmap *args = data; |
1344 | struct drm_gem_object *obj; |
1344 | struct drm_gem_object *obj; |
1345 | unsigned long addr = 0; |
1345 | unsigned long addr = 0; |
1346 | 1346 | ||
1347 | if(args->handle == -2) |
1347 | if(args->handle == -2) |
1348 | { |
1348 | { |
1349 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
1349 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
1350 | return 0; |
1350 | return 0; |
1351 | } |
1351 | } |
1352 | 1352 | ||
1353 | obj = drm_gem_object_lookup(dev, file, args->handle); |
1353 | obj = drm_gem_object_lookup(dev, file, args->handle); |
1354 | if (obj == NULL) |
1354 | if (obj == NULL) |
1355 | return -ENOENT; |
1355 | return -ENOENT; |
1356 | 1356 | ||
1357 | /* prime objects have no backing filp to GEM mmap |
1357 | /* prime objects have no backing filp to GEM mmap |
1358 | * pages from. |
1358 | * pages from. |
1359 | */ |
1359 | */ |
1360 | if (!obj->filp) { |
1360 | if (!obj->filp) { |
1361 | drm_gem_object_unreference_unlocked(obj); |
1361 | drm_gem_object_unreference_unlocked(obj); |
1362 | return -EINVAL; |
1362 | return -EINVAL; |
1363 | } |
1363 | } |
1364 | 1364 | ||
1365 | addr = vm_mmap(obj->filp, 0, args->size, |
1365 | addr = vm_mmap(obj->filp, 0, args->size, |
1366 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1366 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1367 | args->offset); |
1367 | args->offset); |
1368 | drm_gem_object_unreference_unlocked(obj); |
1368 | drm_gem_object_unreference_unlocked(obj); |
1369 | if (IS_ERR((void *)addr)) |
1369 | if (IS_ERR((void *)addr)) |
1370 | return addr; |
1370 | return addr; |
1371 | 1371 | ||
1372 | args->addr_ptr = (uint64_t) addr; |
1372 | args->addr_ptr = (uint64_t) addr; |
1373 | 1373 | ||
1374 | return 0; |
1374 | return 0; |
1375 | } |
1375 | } |
1376 | 1376 | ||
1377 | 1377 | ||
1378 | 1378 | ||
1379 | 1379 | ||
1380 | 1380 | ||
1381 | 1381 | ||
1382 | 1382 | ||
1383 | 1383 | ||
1384 | 1384 | ||
1385 | 1385 | ||
1386 | 1386 | ||
1387 | 1387 | ||
1388 | 1388 | ||
1389 | /** |
1389 | /** |
1390 | * i915_gem_release_mmap - remove physical page mappings |
1390 | * i915_gem_release_mmap - remove physical page mappings |
1391 | * @obj: obj in question |
1391 | * @obj: obj in question |
1392 | * |
1392 | * |
1393 | * Preserve the reservation of the mmapping with the DRM core code, but |
1393 | * Preserve the reservation of the mmapping with the DRM core code, but |
1394 | * relinquish ownership of the pages back to the system. |
1394 | * relinquish ownership of the pages back to the system. |
1395 | * |
1395 | * |
1396 | * It is vital that we remove the page mapping if we have mapped a tiled |
1396 | * It is vital that we remove the page mapping if we have mapped a tiled |
1397 | * object through the GTT and then lose the fence register due to |
1397 | * object through the GTT and then lose the fence register due to |
1398 | * resource pressure. Similarly if the object has been moved out of the |
1398 | * resource pressure. Similarly if the object has been moved out of the |
1399 | * aperture, than pages mapped into userspace must be revoked. Removing the |
1399 | * aperture, than pages mapped into userspace must be revoked. Removing the |
1400 | * mapping will then trigger a page fault on the next user access, allowing |
1400 | * mapping will then trigger a page fault on the next user access, allowing |
1401 | * fixup by i915_gem_fault(). |
1401 | * fixup by i915_gem_fault(). |
1402 | */ |
1402 | */ |
1403 | void |
1403 | void |
1404 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
1404 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
1405 | { |
1405 | { |
1406 | if (!obj->fault_mappable) |
1406 | if (!obj->fault_mappable) |
1407 | return; |
1407 | return; |
1408 | 1408 | ||
1409 | // drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
1409 | // drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
1410 | obj->fault_mappable = false; |
1410 | obj->fault_mappable = false; |
1411 | } |
1411 | } |
1412 | 1412 | ||
1413 | uint32_t |
1413 | uint32_t |
1414 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
1414 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
1415 | { |
1415 | { |
1416 | uint32_t gtt_size; |
1416 | uint32_t gtt_size; |
1417 | 1417 | ||
1418 | if (INTEL_INFO(dev)->gen >= 4 || |
1418 | if (INTEL_INFO(dev)->gen >= 4 || |
1419 | tiling_mode == I915_TILING_NONE) |
1419 | tiling_mode == I915_TILING_NONE) |
1420 | return size; |
1420 | return size; |
1421 | 1421 | ||
1422 | /* Previous chips need a power-of-two fence region when tiling */ |
1422 | /* Previous chips need a power-of-two fence region when tiling */ |
1423 | if (INTEL_INFO(dev)->gen == 3) |
1423 | if (INTEL_INFO(dev)->gen == 3) |
1424 | gtt_size = 1024*1024; |
1424 | gtt_size = 1024*1024; |
1425 | else |
1425 | else |
1426 | gtt_size = 512*1024; |
1426 | gtt_size = 512*1024; |
1427 | 1427 | ||
1428 | while (gtt_size < size) |
1428 | while (gtt_size < size) |
1429 | gtt_size <<= 1; |
1429 | gtt_size <<= 1; |
1430 | 1430 | ||
1431 | return gtt_size; |
1431 | return gtt_size; |
1432 | } |
1432 | } |
1433 | 1433 | ||
1434 | /** |
1434 | /** |
1435 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
1435 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
1436 | * @obj: object to check |
1436 | * @obj: object to check |
1437 | * |
1437 | * |
1438 | * Return the required GTT alignment for an object, taking into account |
1438 | * Return the required GTT alignment for an object, taking into account |
1439 | * potential fence register mapping. |
1439 | * potential fence register mapping. |
1440 | */ |
1440 | */ |
1441 | uint32_t |
1441 | uint32_t |
1442 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1442 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1443 | int tiling_mode, bool fenced) |
1443 | int tiling_mode, bool fenced) |
1444 | { |
1444 | { |
1445 | /* |
1445 | /* |
1446 | * Minimum alignment is 4k (GTT page size), but might be greater |
1446 | * Minimum alignment is 4k (GTT page size), but might be greater |
1447 | * if a fence register is needed for the object. |
1447 | * if a fence register is needed for the object. |
1448 | */ |
1448 | */ |
1449 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
1449 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
1450 | tiling_mode == I915_TILING_NONE) |
1450 | tiling_mode == I915_TILING_NONE) |
1451 | return 4096; |
1451 | return 4096; |
1452 | 1452 | ||
1453 | /* |
1453 | /* |
1454 | * Previous chips need to be aligned to the size of the smallest |
1454 | * Previous chips need to be aligned to the size of the smallest |
1455 | * fence register that can contain the object. |
1455 | * fence register that can contain the object. |
1456 | */ |
1456 | */ |
1457 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
1457 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
1458 | } |
1458 | } |
1459 | 1459 | ||
1460 | /** |
1460 | /** |
1461 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
1461 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
1462 | * unfenced object |
1462 | * unfenced object |
1463 | * @dev: the device |
1463 | * @dev: the device |
1464 | * @size: size of the object |
1464 | * @size: size of the object |
1465 | * @tiling_mode: tiling mode of the object |
1465 | * @tiling_mode: tiling mode of the object |
1466 | * |
1466 | * |
1467 | * Return the required GTT alignment for an object, only taking into account |
1467 | * Return the required GTT alignment for an object, only taking into account |
1468 | * unfenced tiled surface requirements. |
1468 | * unfenced tiled surface requirements. |
1469 | */ |
1469 | */ |
1470 | uint32_t |
1470 | uint32_t |
1471 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1471 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1472 | uint32_t size, |
1472 | uint32_t size, |
1473 | int tiling_mode) |
1473 | int tiling_mode) |
1474 | { |
1474 | { |
1475 | /* |
1475 | /* |
1476 | * Minimum alignment is 4k (GTT page size) for sane hw. |
1476 | * Minimum alignment is 4k (GTT page size) for sane hw. |
1477 | */ |
1477 | */ |
1478 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
1478 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
1479 | tiling_mode == I915_TILING_NONE) |
1479 | tiling_mode == I915_TILING_NONE) |
1480 | return 4096; |
1480 | return 4096; |
1481 | 1481 | ||
1482 | /* Previous hardware however needs to be aligned to a power-of-two |
1482 | /* Previous hardware however needs to be aligned to a power-of-two |
1483 | * tile height. The simplest method for determining this is to reuse |
1483 | * tile height. The simplest method for determining this is to reuse |
1484 | * the power-of-tile object size. |
1484 | * the power-of-tile object size. |
1485 | */ |
1485 | */ |
1486 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
1486 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
1487 | } |
1487 | } |
1488 | 1488 | ||
1489 | int |
1489 | int |
1490 | i915_gem_mmap_gtt(struct drm_file *file, |
1490 | i915_gem_mmap_gtt(struct drm_file *file, |
1491 | struct drm_device *dev, |
1491 | struct drm_device *dev, |
1492 | uint32_t handle, |
1492 | uint32_t handle, |
1493 | uint64_t *offset) |
1493 | uint64_t *offset) |
1494 | { |
1494 | { |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
1496 | struct drm_i915_gem_object *obj; |
1496 | struct drm_i915_gem_object *obj; |
1497 | unsigned long pfn; |
1497 | unsigned long pfn; |
1498 | char *mem, *ptr; |
1498 | char *mem, *ptr; |
1499 | int ret; |
1499 | int ret; |
1500 | 1500 | ||
1501 | ret = i915_mutex_lock_interruptible(dev); |
1501 | ret = i915_mutex_lock_interruptible(dev); |
1502 | if (ret) |
1502 | if (ret) |
1503 | return ret; |
1503 | return ret; |
1504 | 1504 | ||
1505 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
1505 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
1506 | if (&obj->base == NULL) { |
1506 | if (&obj->base == NULL) { |
1507 | ret = -ENOENT; |
1507 | ret = -ENOENT; |
1508 | goto unlock; |
1508 | goto unlock; |
1509 | } |
1509 | } |
1510 | 1510 | ||
1511 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
1511 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
1512 | ret = -E2BIG; |
1512 | ret = -E2BIG; |
1513 | goto out; |
1513 | goto out; |
1514 | } |
1514 | } |
1515 | 1515 | ||
1516 | if (obj->madv != I915_MADV_WILLNEED) { |
1516 | if (obj->madv != I915_MADV_WILLNEED) { |
1517 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1517 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1518 | ret = -EINVAL; |
1518 | ret = -EINVAL; |
1519 | goto out; |
1519 | goto out; |
1520 | } |
1520 | } |
1521 | /* Now bind it into the GTT if needed */ |
1521 | /* Now bind it into the GTT if needed */ |
1522 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
1522 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
1523 | if (ret) |
1523 | if (ret) |
1524 | goto out; |
1524 | goto out; |
1525 | 1525 | ||
1526 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
1526 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
1527 | if (ret) |
1527 | if (ret) |
1528 | goto unpin; |
1528 | goto unpin; |
1529 | 1529 | ||
1530 | ret = i915_gem_object_get_fence(obj); |
1530 | ret = i915_gem_object_get_fence(obj); |
1531 | if (ret) |
1531 | if (ret) |
1532 | goto unpin; |
1532 | goto unpin; |
1533 | 1533 | ||
1534 | obj->fault_mappable = true; |
1534 | obj->fault_mappable = true; |
1535 | 1535 | ||
1536 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1536 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1537 | 1537 | ||
1538 | /* Finally, remap it using the new GTT offset */ |
1538 | /* Finally, remap it using the new GTT offset */ |
1539 | 1539 | ||
1540 | mem = UserAlloc(obj->base.size); |
1540 | mem = UserAlloc(obj->base.size); |
1541 | if(unlikely(mem == NULL)) |
1541 | if(unlikely(mem == NULL)) |
1542 | { |
1542 | { |
1543 | ret = -ENOMEM; |
1543 | ret = -ENOMEM; |
1544 | goto unpin; |
1544 | goto unpin; |
1545 | } |
1545 | } |
1546 | 1546 | ||
1547 | for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096) |
1547 | for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096) |
1548 | MapPage(ptr, pfn, PG_SHARED|PG_UW); |
1548 | MapPage(ptr, pfn, PG_SHARED|PG_UW); |
1549 | 1549 | ||
1550 | unpin: |
1550 | unpin: |
1551 | i915_gem_object_unpin(obj); |
1551 | i915_gem_object_unpin(obj); |
1552 | 1552 | ||
1553 | 1553 | ||
1554 | *offset = mem; |
1554 | *offset = mem; |
1555 | 1555 | ||
1556 | out: |
1556 | out: |
1557 | drm_gem_object_unreference(&obj->base); |
1557 | drm_gem_object_unreference(&obj->base); |
1558 | unlock: |
1558 | unlock: |
1559 | mutex_unlock(&dev->struct_mutex); |
1559 | mutex_unlock(&dev->struct_mutex); |
1560 | return ret; |
1560 | return ret; |
1561 | } |
1561 | } |
1562 | 1562 | ||
1563 | /** |
1563 | /** |
1564 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
1564 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
1565 | * @dev: DRM device |
1565 | * @dev: DRM device |
1566 | * @data: GTT mapping ioctl data |
1566 | * @data: GTT mapping ioctl data |
1567 | * @file: GEM object info |
1567 | * @file: GEM object info |
1568 | * |
1568 | * |
1569 | * Simply returns the fake offset to userspace so it can mmap it. |
1569 | * Simply returns the fake offset to userspace so it can mmap it. |
1570 | * The mmap call will end up in drm_gem_mmap(), which will set things |
1570 | * The mmap call will end up in drm_gem_mmap(), which will set things |
1571 | * up so we can get faults in the handler above. |
1571 | * up so we can get faults in the handler above. |
1572 | * |
1572 | * |
1573 | * The fault handler will take care of binding the object into the GTT |
1573 | * The fault handler will take care of binding the object into the GTT |
1574 | * (since it may have been evicted to make room for something), allocating |
1574 | * (since it may have been evicted to make room for something), allocating |
1575 | * a fence register, and mapping the appropriate aperture address into |
1575 | * a fence register, and mapping the appropriate aperture address into |
1576 | * userspace. |
1576 | * userspace. |
1577 | */ |
1577 | */ |
1578 | int |
1578 | int |
1579 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1579 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1580 | struct drm_file *file) |
1580 | struct drm_file *file) |
1581 | { |
1581 | { |
1582 | struct drm_i915_gem_mmap_gtt *args = data; |
1582 | struct drm_i915_gem_mmap_gtt *args = data; |
1583 | 1583 | ||
1584 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1584 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1585 | } |
1585 | } |
1586 | 1586 | ||
1587 | /* Immediately discard the backing storage */ |
1587 | /* Immediately discard the backing storage */ |
1588 | static void |
1588 | static void |
1589 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
1589 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
1590 | { |
1590 | { |
1591 | // struct inode *inode; |
1591 | // struct inode *inode; |
1592 | 1592 | ||
1593 | // i915_gem_object_free_mmap_offset(obj); |
1593 | // i915_gem_object_free_mmap_offset(obj); |
1594 | 1594 | ||
1595 | if (obj->base.filp == NULL) |
1595 | if (obj->base.filp == NULL) |
1596 | return; |
1596 | return; |
1597 | 1597 | ||
1598 | /* Our goal here is to return as much of the memory as |
1598 | /* Our goal here is to return as much of the memory as |
1599 | * is possible back to the system as we are called from OOM. |
1599 | * is possible back to the system as we are called from OOM. |
1600 | * To do this we must instruct the shmfs to drop all of its |
1600 | * To do this we must instruct the shmfs to drop all of its |
1601 | * backing pages, *now*. |
1601 | * backing pages, *now*. |
1602 | */ |
1602 | */ |
1603 | // inode = obj->base.filp->f_path.dentry->d_inode; |
1603 | // inode = obj->base.filp->f_path.dentry->d_inode; |
1604 | // shmem_truncate_range(inode, 0, (loff_t)-1); |
1604 | // shmem_truncate_range(inode, 0, (loff_t)-1); |
1605 | 1605 | ||
1606 | obj->madv = __I915_MADV_PURGED; |
1606 | obj->madv = __I915_MADV_PURGED; |
1607 | } |
1607 | } |
1608 | 1608 | ||
1609 | static inline int |
1609 | static inline int |
1610 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
1610 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
1611 | { |
1611 | { |
1612 | return obj->madv == I915_MADV_DONTNEED; |
1612 | return obj->madv == I915_MADV_DONTNEED; |
1613 | } |
1613 | } |
1614 | 1614 | ||
1615 | static void |
1615 | static void |
1616 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
1616 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
1617 | { |
1617 | { |
1618 | struct sg_page_iter sg_iter; |
1618 | struct sg_page_iter sg_iter; |
1619 | int ret; |
1619 | int ret; |
1620 | 1620 | ||
1621 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
1621 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
1622 | 1622 | ||
1623 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1623 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1624 | if (ret) { |
1624 | if (ret) { |
1625 | /* In the event of a disaster, abandon all caches and |
1625 | /* In the event of a disaster, abandon all caches and |
1626 | * hope for the best. |
1626 | * hope for the best. |
1627 | */ |
1627 | */ |
1628 | WARN_ON(ret != -EIO); |
1628 | WARN_ON(ret != -EIO); |
1629 | i915_gem_clflush_object(obj, true); |
1629 | i915_gem_clflush_object(obj, true); |
1630 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1630 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1631 | } |
1631 | } |
1632 | 1632 | ||
1633 | if (obj->madv == I915_MADV_DONTNEED) |
1633 | if (obj->madv == I915_MADV_DONTNEED) |
1634 | obj->dirty = 0; |
1634 | obj->dirty = 0; |
1635 | 1635 | ||
1636 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
1636 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
1637 | struct page *page = sg_page_iter_page(&sg_iter); |
1637 | struct page *page = sg_page_iter_page(&sg_iter); |
1638 | 1638 | ||
1639 | page_cache_release(page); |
1639 | page_cache_release(page); |
1640 | } |
1640 | } |
1641 | //DRM_DEBUG_KMS("%s release %d pages\n", __FUNCTION__, page_count); |
1641 | //DRM_DEBUG_KMS("%s release %d pages\n", __FUNCTION__, page_count); |
1642 | 1642 | ||
1643 | obj->dirty = 0; |
1643 | obj->dirty = 0; |
1644 | 1644 | ||
1645 | sg_free_table(obj->pages); |
1645 | sg_free_table(obj->pages); |
1646 | kfree(obj->pages); |
1646 | kfree(obj->pages); |
1647 | } |
1647 | } |
1648 | 1648 | ||
1649 | int |
1649 | int |
1650 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1650 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1651 | { |
1651 | { |
1652 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1652 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1653 | 1653 | ||
1654 | if (obj->pages == NULL) |
1654 | if (obj->pages == NULL) |
1655 | return 0; |
1655 | return 0; |
1656 | 1656 | ||
1657 | if (obj->pages_pin_count) |
1657 | if (obj->pages_pin_count) |
1658 | return -EBUSY; |
1658 | return -EBUSY; |
1659 | 1659 | ||
1660 | BUG_ON(i915_gem_obj_bound_any(obj)); |
1660 | BUG_ON(i915_gem_obj_bound_any(obj)); |
1661 | 1661 | ||
1662 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1662 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1663 | * array, hence protect them from being reaped by removing them from gtt |
1663 | * array, hence protect them from being reaped by removing them from gtt |
1664 | * lists early. */ |
1664 | * lists early. */ |
1665 | list_del(&obj->global_list); |
1665 | list_del(&obj->global_list); |
1666 | 1666 | ||
1667 | ops->put_pages(obj); |
1667 | ops->put_pages(obj); |
1668 | obj->pages = NULL; |
1668 | obj->pages = NULL; |
1669 | 1669 | ||
1670 | if (i915_gem_object_is_purgeable(obj)) |
1670 | if (i915_gem_object_is_purgeable(obj)) |
1671 | i915_gem_object_truncate(obj); |
1671 | i915_gem_object_truncate(obj); |
1672 | 1672 | ||
1673 | return 0; |
1673 | return 0; |
1674 | } |
1674 | } |
1675 | 1675 | ||
1676 | 1676 | ||
1677 | 1677 | ||
1678 | 1678 | ||
1679 | 1679 | ||
1680 | 1680 | ||
1681 | 1681 | ||
1682 | 1682 | ||
1683 | static int |
1683 | static int |
1684 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
1684 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
1685 | { |
1685 | { |
1686 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1686 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1687 | int page_count, i; |
1687 | int page_count, i; |
1688 | struct sg_table *st; |
1688 | struct sg_table *st; |
1689 | struct scatterlist *sg; |
1689 | struct scatterlist *sg; |
1690 | struct sg_page_iter sg_iter; |
1690 | struct sg_page_iter sg_iter; |
1691 | struct page *page; |
1691 | struct page *page; |
1692 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
1692 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
1693 | gfp_t gfp; |
1693 | gfp_t gfp; |
1694 | 1694 | ||
1695 | /* Assert that the object is not currently in any GPU domain. As it |
1695 | /* Assert that the object is not currently in any GPU domain. As it |
1696 | * wasn't in the GTT, there shouldn't be any way it could have been in |
1696 | * wasn't in the GTT, there shouldn't be any way it could have been in |
1697 | * a GPU cache |
1697 | * a GPU cache |
1698 | */ |
1698 | */ |
1699 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
1699 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
1700 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
1700 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
1701 | 1701 | ||
1702 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1702 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1703 | if (st == NULL) |
1703 | if (st == NULL) |
1704 | return -ENOMEM; |
1704 | return -ENOMEM; |
1705 | 1705 | ||
1706 | page_count = obj->base.size / PAGE_SIZE; |
1706 | page_count = obj->base.size / PAGE_SIZE; |
1707 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1707 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1708 | kfree(st); |
1708 | kfree(st); |
1709 | FAIL(); |
1709 | FAIL(); |
1710 | return -ENOMEM; |
1710 | return -ENOMEM; |
1711 | } |
1711 | } |
1712 | 1712 | ||
1713 | /* Get the list of pages out of our struct file. They'll be pinned |
1713 | /* Get the list of pages out of our struct file. They'll be pinned |
1714 | * at this point until we release them. |
1714 | * at this point until we release them. |
1715 | * |
1715 | * |
1716 | * Fail silently without starting the shrinker |
1716 | * Fail silently without starting the shrinker |
1717 | */ |
1717 | */ |
1718 | sg = st->sgl; |
1718 | sg = st->sgl; |
1719 | st->nents = 0; |
1719 | st->nents = 0; |
1720 | for (i = 0; i < page_count; i++) { |
1720 | for (i = 0; i < page_count; i++) { |
1721 | page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp); |
1721 | page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp); |
1722 | if (IS_ERR(page)) { |
1722 | if (IS_ERR(page)) { |
1723 | dbgprintf("%s invalid page %p\n", __FUNCTION__, page); |
1723 | dbgprintf("%s invalid page %p\n", __FUNCTION__, page); |
1724 | goto err_pages; |
1724 | goto err_pages; |
1725 | 1725 | ||
1726 | } |
1726 | } |
1727 | 1727 | ||
1728 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1728 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1729 | if (i) |
1729 | if (i) |
1730 | sg = sg_next(sg); |
1730 | sg = sg_next(sg); |
1731 | st->nents++; |
1731 | st->nents++; |
1732 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1732 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1733 | } else { |
1733 | } else { |
1734 | sg->length += PAGE_SIZE; |
1734 | sg->length += PAGE_SIZE; |
1735 | } |
1735 | } |
1736 | last_pfn = page_to_pfn(page); |
1736 | last_pfn = page_to_pfn(page); |
1737 | } |
1737 | } |
1738 | 1738 | ||
1739 | sg_mark_end(sg); |
1739 | sg_mark_end(sg); |
1740 | obj->pages = st; |
1740 | obj->pages = st; |
1741 | 1741 | ||
1742 | return 0; |
1742 | return 0; |
1743 | 1743 | ||
1744 | err_pages: |
1744 | err_pages: |
1745 | sg_mark_end(sg); |
1745 | sg_mark_end(sg); |
1746 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
1746 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
1747 | page_cache_release(sg_page_iter_page(&sg_iter)); |
1747 | page_cache_release(sg_page_iter_page(&sg_iter)); |
1748 | sg_free_table(st); |
1748 | sg_free_table(st); |
1749 | kfree(st); |
1749 | kfree(st); |
1750 | FAIL(); |
1750 | FAIL(); |
1751 | return PTR_ERR(page); |
1751 | return PTR_ERR(page); |
1752 | } |
1752 | } |
1753 | 1753 | ||
1754 | /* Ensure that the associated pages are gathered from the backing storage |
1754 | /* Ensure that the associated pages are gathered from the backing storage |
1755 | * and pinned into our object. i915_gem_object_get_pages() may be called |
1755 | * and pinned into our object. i915_gem_object_get_pages() may be called |
1756 | * multiple times before they are released by a single call to |
1756 | * multiple times before they are released by a single call to |
1757 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
1757 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
1758 | * either as a result of memory pressure (reaping pages under the shrinker) |
1758 | * either as a result of memory pressure (reaping pages under the shrinker) |
1759 | * or as the object is itself released. |
1759 | * or as the object is itself released. |
1760 | */ |
1760 | */ |
1761 | int |
1761 | int |
1762 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
1762 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
1763 | { |
1763 | { |
1764 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1764 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1765 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1765 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1766 | int ret; |
1766 | int ret; |
1767 | 1767 | ||
1768 | if (obj->pages) |
1768 | if (obj->pages) |
1769 | return 0; |
1769 | return 0; |
1770 | 1770 | ||
1771 | BUG_ON(obj->pages_pin_count); |
1771 | BUG_ON(obj->pages_pin_count); |
1772 | 1772 | ||
1773 | ret = ops->get_pages(obj); |
1773 | ret = ops->get_pages(obj); |
1774 | if (ret) |
1774 | if (ret) |
1775 | return ret; |
1775 | return ret; |
1776 | 1776 | ||
1777 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
1777 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
1778 | return 0; |
1778 | return 0; |
1779 | } |
1779 | } |
1780 | 1780 | ||
1781 | void |
1781 | void |
1782 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1782 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1783 | struct intel_ring_buffer *ring) |
1783 | struct intel_ring_buffer *ring) |
1784 | { |
1784 | { |
1785 | struct drm_device *dev = obj->base.dev; |
1785 | struct drm_device *dev = obj->base.dev; |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; |
1787 | u32 seqno = intel_ring_get_seqno(ring); |
1787 | u32 seqno = intel_ring_get_seqno(ring); |
1788 | 1788 | ||
1789 | BUG_ON(ring == NULL); |
1789 | BUG_ON(ring == NULL); |
1790 | if (obj->ring != ring && obj->last_write_seqno) { |
1790 | if (obj->ring != ring && obj->last_write_seqno) { |
1791 | /* Keep the seqno relative to the current ring */ |
1791 | /* Keep the seqno relative to the current ring */ |
1792 | obj->last_write_seqno = seqno; |
1792 | obj->last_write_seqno = seqno; |
1793 | } |
1793 | } |
1794 | obj->ring = ring; |
1794 | obj->ring = ring; |
1795 | 1795 | ||
1796 | /* Add a reference if we're newly entering the active list. */ |
1796 | /* Add a reference if we're newly entering the active list. */ |
1797 | if (!obj->active) { |
1797 | if (!obj->active) { |
1798 | drm_gem_object_reference(&obj->base); |
1798 | drm_gem_object_reference(&obj->base); |
1799 | obj->active = 1; |
1799 | obj->active = 1; |
1800 | } |
1800 | } |
1801 | 1801 | ||
1802 | list_move_tail(&obj->ring_list, &ring->active_list); |
1802 | list_move_tail(&obj->ring_list, &ring->active_list); |
1803 | 1803 | ||
1804 | obj->last_read_seqno = seqno; |
1804 | obj->last_read_seqno = seqno; |
1805 | 1805 | ||
1806 | if (obj->fenced_gpu_access) { |
1806 | if (obj->fenced_gpu_access) { |
1807 | obj->last_fenced_seqno = seqno; |
1807 | obj->last_fenced_seqno = seqno; |
1808 | 1808 | ||
1809 | /* Bump MRU to take account of the delayed flush */ |
1809 | /* Bump MRU to take account of the delayed flush */ |
1810 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
1810 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
1811 | struct drm_i915_fence_reg *reg; |
1811 | struct drm_i915_fence_reg *reg; |
1812 | 1812 | ||
1813 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
1813 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
1814 | list_move_tail(®->lru_list, |
1814 | list_move_tail(®->lru_list, |
1815 | &dev_priv->mm.fence_list); |
1815 | &dev_priv->mm.fence_list); |
1816 | } |
1816 | } |
1817 | } |
1817 | } |
1818 | } |
1818 | } |
1819 | 1819 | ||
1820 | static void |
1820 | static void |
1821 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
1821 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
1822 | { |
1822 | { |
1823 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1823 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1824 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
1824 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
1825 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
1825 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
1826 | 1826 | ||
1827 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
1827 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
1828 | BUG_ON(!obj->active); |
1828 | BUG_ON(!obj->active); |
1829 | 1829 | ||
1830 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
1830 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
1831 | 1831 | ||
1832 | list_del_init(&obj->ring_list); |
1832 | list_del_init(&obj->ring_list); |
1833 | obj->ring = NULL; |
1833 | obj->ring = NULL; |
1834 | 1834 | ||
1835 | obj->last_read_seqno = 0; |
1835 | obj->last_read_seqno = 0; |
1836 | obj->last_write_seqno = 0; |
1836 | obj->last_write_seqno = 0; |
1837 | obj->base.write_domain = 0; |
1837 | obj->base.write_domain = 0; |
1838 | 1838 | ||
1839 | obj->last_fenced_seqno = 0; |
1839 | obj->last_fenced_seqno = 0; |
1840 | obj->fenced_gpu_access = false; |
1840 | obj->fenced_gpu_access = false; |
1841 | 1841 | ||
1842 | obj->active = 0; |
1842 | obj->active = 0; |
1843 | drm_gem_object_unreference(&obj->base); |
1843 | drm_gem_object_unreference(&obj->base); |
1844 | 1844 | ||
1845 | WARN_ON(i915_verify_lists(dev)); |
1845 | WARN_ON(i915_verify_lists(dev)); |
1846 | } |
1846 | } |
1847 | 1847 | ||
1848 | static int |
1848 | static int |
1849 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
1849 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
1850 | { |
1850 | { |
1851 | struct drm_i915_private *dev_priv = dev->dev_private; |
1851 | struct drm_i915_private *dev_priv = dev->dev_private; |
1852 | struct intel_ring_buffer *ring; |
1852 | struct intel_ring_buffer *ring; |
1853 | int ret, i, j; |
1853 | int ret, i, j; |
1854 | 1854 | ||
1855 | /* Carefully retire all requests without writing to the rings */ |
1855 | /* Carefully retire all requests without writing to the rings */ |
1856 | for_each_ring(ring, dev_priv, i) { |
1856 | for_each_ring(ring, dev_priv, i) { |
1857 | ret = intel_ring_idle(ring); |
1857 | ret = intel_ring_idle(ring); |
1858 | if (ret) |
1858 | if (ret) |
1859 | return ret; |
1859 | return ret; |
1860 | } |
1860 | } |
1861 | i915_gem_retire_requests(dev); |
1861 | i915_gem_retire_requests(dev); |
1862 | 1862 | ||
1863 | /* Finally reset hw state */ |
1863 | /* Finally reset hw state */ |
1864 | for_each_ring(ring, dev_priv, i) { |
1864 | for_each_ring(ring, dev_priv, i) { |
1865 | intel_ring_init_seqno(ring, seqno); |
1865 | intel_ring_init_seqno(ring, seqno); |
1866 | 1866 | ||
1867 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1867 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1868 | ring->sync_seqno[j] = 0; |
1868 | ring->sync_seqno[j] = 0; |
1869 | } |
1869 | } |
1870 | 1870 | ||
1871 | return 0; |
1871 | return 0; |
1872 | } |
1872 | } |
1873 | 1873 | ||
1874 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1874 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1875 | { |
1875 | { |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
1877 | int ret; |
1877 | int ret; |
1878 | 1878 | ||
1879 | if (seqno == 0) |
1879 | if (seqno == 0) |
1880 | return -EINVAL; |
1880 | return -EINVAL; |
1881 | 1881 | ||
1882 | /* HWS page needs to be set less than what we |
1882 | /* HWS page needs to be set less than what we |
1883 | * will inject to ring |
1883 | * will inject to ring |
1884 | */ |
1884 | */ |
1885 | ret = i915_gem_init_seqno(dev, seqno - 1); |
1885 | ret = i915_gem_init_seqno(dev, seqno - 1); |
1886 | if (ret) |
1886 | if (ret) |
1887 | return ret; |
1887 | return ret; |
1888 | 1888 | ||
1889 | /* Carefully set the last_seqno value so that wrap |
1889 | /* Carefully set the last_seqno value so that wrap |
1890 | * detection still works |
1890 | * detection still works |
1891 | */ |
1891 | */ |
1892 | dev_priv->next_seqno = seqno; |
1892 | dev_priv->next_seqno = seqno; |
1893 | dev_priv->last_seqno = seqno - 1; |
1893 | dev_priv->last_seqno = seqno - 1; |
1894 | if (dev_priv->last_seqno == 0) |
1894 | if (dev_priv->last_seqno == 0) |
1895 | dev_priv->last_seqno--; |
1895 | dev_priv->last_seqno--; |
1896 | 1896 | ||
1897 | return 0; |
1897 | return 0; |
1898 | } |
1898 | } |
1899 | 1899 | ||
1900 | int |
1900 | int |
1901 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
1901 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
1902 | { |
1902 | { |
1903 | struct drm_i915_private *dev_priv = dev->dev_private; |
1903 | struct drm_i915_private *dev_priv = dev->dev_private; |
1904 | 1904 | ||
1905 | /* reserve 0 for non-seqno */ |
1905 | /* reserve 0 for non-seqno */ |
1906 | if (dev_priv->next_seqno == 0) { |
1906 | if (dev_priv->next_seqno == 0) { |
1907 | int ret = i915_gem_init_seqno(dev, 0); |
1907 | int ret = i915_gem_init_seqno(dev, 0); |
1908 | if (ret) |
1908 | if (ret) |
1909 | return ret; |
1909 | return ret; |
1910 | 1910 | ||
1911 | dev_priv->next_seqno = 1; |
1911 | dev_priv->next_seqno = 1; |
1912 | } |
1912 | } |
1913 | 1913 | ||
1914 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
1914 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
1915 | return 0; |
1915 | return 0; |
1916 | } |
1916 | } |
1917 | 1917 | ||
1918 | int __i915_add_request(struct intel_ring_buffer *ring, |
1918 | int __i915_add_request(struct intel_ring_buffer *ring, |
1919 | struct drm_file *file, |
1919 | struct drm_file *file, |
1920 | struct drm_i915_gem_object *obj, |
1920 | struct drm_i915_gem_object *obj, |
1921 | u32 *out_seqno) |
1921 | u32 *out_seqno) |
1922 | { |
1922 | { |
1923 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1923 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1924 | struct drm_i915_gem_request *request; |
1924 | struct drm_i915_gem_request *request; |
1925 | u32 request_ring_position, request_start; |
1925 | u32 request_ring_position, request_start; |
1926 | int was_empty; |
1926 | int was_empty; |
1927 | int ret; |
1927 | int ret; |
1928 | 1928 | ||
1929 | request_start = intel_ring_get_tail(ring); |
1929 | request_start = intel_ring_get_tail(ring); |
1930 | /* |
1930 | /* |
1931 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
1931 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
1932 | * after having emitted the batchbuffer command. Hence we need to fix |
1932 | * after having emitted the batchbuffer command. Hence we need to fix |
1933 | * things up similar to emitting the lazy request. The difference here |
1933 | * things up similar to emitting the lazy request. The difference here |
1934 | * is that the flush _must_ happen before the next request, no matter |
1934 | * is that the flush _must_ happen before the next request, no matter |
1935 | * what. |
1935 | * what. |
1936 | */ |
1936 | */ |
1937 | ret = intel_ring_flush_all_caches(ring); |
1937 | ret = intel_ring_flush_all_caches(ring); |
1938 | if (ret) |
1938 | if (ret) |
1939 | return ret; |
1939 | return ret; |
1940 | 1940 | ||
1941 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1941 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1942 | if (request == NULL) |
1942 | if (request == NULL) |
1943 | return -ENOMEM; |
1943 | return -ENOMEM; |
1944 | 1944 | ||
1945 | 1945 | ||
1946 | /* Record the position of the start of the request so that |
1946 | /* Record the position of the start of the request so that |
1947 | * should we detect the updated seqno part-way through the |
1947 | * should we detect the updated seqno part-way through the |
1948 | * GPU processing the request, we never over-estimate the |
1948 | * GPU processing the request, we never over-estimate the |
1949 | * position of the head. |
1949 | * position of the head. |
1950 | */ |
1950 | */ |
1951 | request_ring_position = intel_ring_get_tail(ring); |
1951 | request_ring_position = intel_ring_get_tail(ring); |
1952 | 1952 | ||
1953 | ret = ring->add_request(ring); |
1953 | ret = ring->add_request(ring); |
1954 | if (ret) { |
1954 | if (ret) { |
1955 | kfree(request); |
1955 | kfree(request); |
1956 | return ret; |
1956 | return ret; |
1957 | } |
1957 | } |
1958 | 1958 | ||
1959 | request->seqno = intel_ring_get_seqno(ring); |
1959 | request->seqno = intel_ring_get_seqno(ring); |
1960 | request->ring = ring; |
1960 | request->ring = ring; |
1961 | request->head = request_start; |
1961 | request->head = request_start; |
1962 | request->tail = request_ring_position; |
1962 | request->tail = request_ring_position; |
1963 | request->ctx = ring->last_context; |
1963 | request->ctx = ring->last_context; |
1964 | request->batch_obj = obj; |
1964 | request->batch_obj = obj; |
1965 | 1965 | ||
1966 | /* Whilst this request exists, batch_obj will be on the |
1966 | /* Whilst this request exists, batch_obj will be on the |
1967 | * active_list, and so will hold the active reference. Only when this |
1967 | * active_list, and so will hold the active reference. Only when this |
1968 | * request is retired will the the batch_obj be moved onto the |
1968 | * request is retired will the the batch_obj be moved onto the |
1969 | * inactive_list and lose its active reference. Hence we do not need |
1969 | * inactive_list and lose its active reference. Hence we do not need |
1970 | * to explicitly hold another reference here. |
1970 | * to explicitly hold another reference here. |
1971 | */ |
1971 | */ |
1972 | 1972 | ||
1973 | if (request->ctx) |
1973 | if (request->ctx) |
1974 | i915_gem_context_reference(request->ctx); |
1974 | i915_gem_context_reference(request->ctx); |
1975 | 1975 | ||
1976 | request->emitted_jiffies = GetTimerTicks(); |
1976 | request->emitted_jiffies = GetTimerTicks(); |
1977 | was_empty = list_empty(&ring->request_list); |
1977 | was_empty = list_empty(&ring->request_list); |
1978 | list_add_tail(&request->list, &ring->request_list); |
1978 | list_add_tail(&request->list, &ring->request_list); |
1979 | request->file_priv = NULL; |
1979 | request->file_priv = NULL; |
1980 | 1980 | ||
1981 | if (file) { |
1981 | if (file) { |
1982 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1982 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1983 | 1983 | ||
1984 | spin_lock(&file_priv->mm.lock); |
1984 | spin_lock(&file_priv->mm.lock); |
1985 | request->file_priv = file_priv; |
1985 | request->file_priv = file_priv; |
1986 | list_add_tail(&request->client_list, |
1986 | list_add_tail(&request->client_list, |
1987 | &file_priv->mm.request_list); |
1987 | &file_priv->mm.request_list); |
1988 | spin_unlock(&file_priv->mm.lock); |
1988 | spin_unlock(&file_priv->mm.lock); |
1989 | } |
1989 | } |
1990 | 1990 | ||
1991 | trace_i915_gem_request_add(ring, request->seqno); |
1991 | trace_i915_gem_request_add(ring, request->seqno); |
1992 | ring->outstanding_lazy_request = 0; |
1992 | ring->outstanding_lazy_request = 0; |
1993 | 1993 | ||
1994 | if (!dev_priv->ums.mm_suspended) { |
1994 | if (!dev_priv->ums.mm_suspended) { |
1995 | // i915_queue_hangcheck(ring->dev); |
1995 | // i915_queue_hangcheck(ring->dev); |
1996 | 1996 | ||
1997 | if (was_empty) { |
1997 | if (was_empty) { |
1998 | queue_delayed_work(dev_priv->wq, |
1998 | queue_delayed_work(dev_priv->wq, |
1999 | &dev_priv->mm.retire_work, |
1999 | &dev_priv->mm.retire_work, |
2000 | round_jiffies_up_relative(HZ)); |
2000 | round_jiffies_up_relative(HZ)); |
2001 | intel_mark_busy(dev_priv->dev); |
2001 | intel_mark_busy(dev_priv->dev); |
2002 | } |
2002 | } |
2003 | } |
2003 | } |
2004 | 2004 | ||
2005 | if (out_seqno) |
2005 | if (out_seqno) |
2006 | *out_seqno = request->seqno; |
2006 | *out_seqno = request->seqno; |
2007 | return 0; |
2007 | return 0; |
2008 | } |
2008 | } |
2009 | 2009 | ||
2010 | static inline void |
2010 | static inline void |
2011 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
2011 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
2012 | { |
2012 | { |
2013 | struct drm_i915_file_private *file_priv = request->file_priv; |
2013 | struct drm_i915_file_private *file_priv = request->file_priv; |
2014 | 2014 | ||
2015 | if (!file_priv) |
2015 | if (!file_priv) |
2016 | return; |
2016 | return; |
2017 | 2017 | ||
2018 | spin_lock(&file_priv->mm.lock); |
2018 | spin_lock(&file_priv->mm.lock); |
2019 | if (request->file_priv) { |
2019 | if (request->file_priv) { |
2020 | list_del(&request->client_list); |
2020 | list_del(&request->client_list); |
2021 | request->file_priv = NULL; |
2021 | request->file_priv = NULL; |
2022 | } |
2022 | } |
2023 | spin_unlock(&file_priv->mm.lock); |
2023 | spin_unlock(&file_priv->mm.lock); |
2024 | } |
2024 | } |
2025 | 2025 | ||
2026 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2026 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2027 | struct i915_address_space *vm) |
2027 | struct i915_address_space *vm) |
2028 | { |
2028 | { |
2029 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2029 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2030 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) |
2030 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) |
2031 | return true; |
2031 | return true; |
2032 | 2032 | ||
2033 | return false; |
2033 | return false; |
2034 | } |
2034 | } |
2035 | 2035 | ||
2036 | static bool i915_head_inside_request(const u32 acthd_unmasked, |
2036 | static bool i915_head_inside_request(const u32 acthd_unmasked, |
2037 | const u32 request_start, |
2037 | const u32 request_start, |
2038 | const u32 request_end) |
2038 | const u32 request_end) |
2039 | { |
2039 | { |
2040 | const u32 acthd = acthd_unmasked & HEAD_ADDR; |
2040 | const u32 acthd = acthd_unmasked & HEAD_ADDR; |
2041 | 2041 | ||
2042 | if (request_start < request_end) { |
2042 | if (request_start < request_end) { |
2043 | if (acthd >= request_start && acthd < request_end) |
2043 | if (acthd >= request_start && acthd < request_end) |
2044 | return true; |
2044 | return true; |
2045 | } else if (request_start > request_end) { |
2045 | } else if (request_start > request_end) { |
2046 | if (acthd >= request_start || acthd < request_end) |
2046 | if (acthd >= request_start || acthd < request_end) |
2047 | return true; |
2047 | return true; |
2048 | } |
2048 | } |
2049 | 2049 | ||
2050 | return false; |
2050 | return false; |
2051 | } |
2051 | } |
2052 | 2052 | ||
2053 | static struct i915_address_space * |
2053 | static struct i915_address_space * |
2054 | request_to_vm(struct drm_i915_gem_request *request) |
2054 | request_to_vm(struct drm_i915_gem_request *request) |
2055 | { |
2055 | { |
2056 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; |
2056 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; |
2057 | struct i915_address_space *vm; |
2057 | struct i915_address_space *vm; |
2058 | 2058 | ||
2059 | vm = &dev_priv->gtt.base; |
2059 | vm = &dev_priv->gtt.base; |
2060 | 2060 | ||
2061 | return vm; |
2061 | return vm; |
2062 | } |
2062 | } |
2063 | 2063 | ||
2064 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2064 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2065 | const u32 acthd, bool *inside) |
2065 | const u32 acthd, bool *inside) |
2066 | { |
2066 | { |
2067 | /* There is a possibility that unmasked head address |
2067 | /* There is a possibility that unmasked head address |
2068 | * pointing inside the ring, matches the batch_obj address range. |
2068 | * pointing inside the ring, matches the batch_obj address range. |
2069 | * However this is extremely unlikely. |
2069 | * However this is extremely unlikely. |
2070 | */ |
2070 | */ |
2071 | if (request->batch_obj) { |
2071 | if (request->batch_obj) { |
2072 | if (i915_head_inside_object(acthd, request->batch_obj, |
2072 | if (i915_head_inside_object(acthd, request->batch_obj, |
2073 | request_to_vm(request))) { |
2073 | request_to_vm(request))) { |
2074 | *inside = true; |
2074 | *inside = true; |
2075 | return true; |
2075 | return true; |
2076 | } |
2076 | } |
2077 | } |
2077 | } |
2078 | 2078 | ||
2079 | if (i915_head_inside_request(acthd, request->head, request->tail)) { |
2079 | if (i915_head_inside_request(acthd, request->head, request->tail)) { |
2080 | *inside = false; |
2080 | *inside = false; |
2081 | return true; |
2081 | return true; |
2082 | } |
2082 | } |
2083 | 2083 | ||
2084 | return false; |
2084 | return false; |
2085 | } |
2085 | } |
2086 | 2086 | ||
2087 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2087 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2088 | struct drm_i915_gem_request *request, |
2088 | struct drm_i915_gem_request *request, |
2089 | u32 acthd) |
2089 | u32 acthd) |
2090 | { |
2090 | { |
2091 | struct i915_ctx_hang_stats *hs = NULL; |
2091 | struct i915_ctx_hang_stats *hs = NULL; |
2092 | bool inside, guilty; |
2092 | bool inside, guilty; |
2093 | unsigned long offset = 0; |
2093 | unsigned long offset = 0; |
2094 | 2094 | ||
2095 | /* Innocent until proven guilty */ |
2095 | /* Innocent until proven guilty */ |
2096 | guilty = false; |
2096 | guilty = false; |
2097 | 2097 | ||
2098 | if (request->batch_obj) |
2098 | if (request->batch_obj) |
2099 | offset = i915_gem_obj_offset(request->batch_obj, |
2099 | offset = i915_gem_obj_offset(request->batch_obj, |
2100 | request_to_vm(request)); |
2100 | request_to_vm(request)); |
2101 | 2101 | ||
2102 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
2102 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
2103 | i915_request_guilty(request, acthd, &inside)) { |
2103 | i915_request_guilty(request, acthd, &inside)) { |
2104 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
2104 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
2105 | ring->name, |
2105 | ring->name, |
2106 | inside ? "inside" : "flushing", |
2106 | inside ? "inside" : "flushing", |
2107 | offset, |
2107 | offset, |
2108 | request->ctx ? request->ctx->id : 0, |
2108 | request->ctx ? request->ctx->id : 0, |
2109 | acthd); |
2109 | acthd); |
2110 | 2110 | ||
2111 | guilty = true; |
2111 | guilty = true; |
2112 | } |
2112 | } |
2113 | 2113 | ||
2114 | /* If contexts are disabled or this is the default context, use |
2114 | /* If contexts are disabled or this is the default context, use |
2115 | * file_priv->reset_state |
2115 | * file_priv->reset_state |
2116 | */ |
2116 | */ |
2117 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) |
2117 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) |
2118 | hs = &request->ctx->hang_stats; |
2118 | hs = &request->ctx->hang_stats; |
2119 | else if (request->file_priv) |
2119 | else if (request->file_priv) |
2120 | hs = &request->file_priv->hang_stats; |
2120 | hs = &request->file_priv->hang_stats; |
2121 | 2121 | ||
2122 | if (hs) { |
2122 | if (hs) { |
2123 | if (guilty) |
2123 | if (guilty) |
2124 | hs->batch_active++; |
2124 | hs->batch_active++; |
2125 | else |
2125 | else |
2126 | hs->batch_pending++; |
2126 | hs->batch_pending++; |
2127 | } |
2127 | } |
2128 | } |
2128 | } |
2129 | 2129 | ||
2130 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2130 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2131 | { |
2131 | { |
2132 | list_del(&request->list); |
2132 | list_del(&request->list); |
2133 | i915_gem_request_remove_from_client(request); |
2133 | i915_gem_request_remove_from_client(request); |
2134 | 2134 | ||
2135 | if (request->ctx) |
2135 | if (request->ctx) |
2136 | i915_gem_context_unreference(request->ctx); |
2136 | i915_gem_context_unreference(request->ctx); |
2137 | 2137 | ||
2138 | kfree(request); |
2138 | kfree(request); |
2139 | } |
2139 | } |
2140 | 2140 | ||
2141 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2141 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2142 | struct intel_ring_buffer *ring) |
2142 | struct intel_ring_buffer *ring) |
2143 | { |
2143 | { |
2144 | u32 completed_seqno; |
2144 | u32 completed_seqno; |
2145 | u32 acthd; |
2145 | u32 acthd; |
2146 | 2146 | ||
2147 | acthd = intel_ring_get_active_head(ring); |
2147 | acthd = intel_ring_get_active_head(ring); |
2148 | completed_seqno = ring->get_seqno(ring, false); |
2148 | completed_seqno = ring->get_seqno(ring, false); |
2149 | 2149 | ||
2150 | while (!list_empty(&ring->request_list)) { |
2150 | while (!list_empty(&ring->request_list)) { |
2151 | struct drm_i915_gem_request *request; |
2151 | struct drm_i915_gem_request *request; |
2152 | 2152 | ||
2153 | request = list_first_entry(&ring->request_list, |
2153 | request = list_first_entry(&ring->request_list, |
2154 | struct drm_i915_gem_request, |
2154 | struct drm_i915_gem_request, |
2155 | list); |
2155 | list); |
2156 | 2156 | ||
2157 | if (request->seqno > completed_seqno) |
2157 | if (request->seqno > completed_seqno) |
2158 | i915_set_reset_status(ring, request, acthd); |
2158 | i915_set_reset_status(ring, request, acthd); |
2159 | 2159 | ||
2160 | i915_gem_free_request(request); |
2160 | i915_gem_free_request(request); |
2161 | } |
2161 | } |
2162 | 2162 | ||
2163 | while (!list_empty(&ring->active_list)) { |
2163 | while (!list_empty(&ring->active_list)) { |
2164 | struct drm_i915_gem_object *obj; |
2164 | struct drm_i915_gem_object *obj; |
2165 | 2165 | ||
2166 | obj = list_first_entry(&ring->active_list, |
2166 | obj = list_first_entry(&ring->active_list, |
2167 | struct drm_i915_gem_object, |
2167 | struct drm_i915_gem_object, |
2168 | ring_list); |
2168 | ring_list); |
2169 | 2169 | ||
2170 | i915_gem_object_move_to_inactive(obj); |
2170 | i915_gem_object_move_to_inactive(obj); |
2171 | } |
2171 | } |
2172 | } |
2172 | } |
2173 | 2173 | ||
2174 | void i915_gem_restore_fences(struct drm_device *dev) |
2174 | void i915_gem_restore_fences(struct drm_device *dev) |
2175 | { |
2175 | { |
2176 | struct drm_i915_private *dev_priv = dev->dev_private; |
2176 | struct drm_i915_private *dev_priv = dev->dev_private; |
2177 | int i; |
2177 | int i; |
2178 | 2178 | ||
2179 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
2179 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
2180 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
2180 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
2181 | 2181 | ||
2182 | /* |
2182 | /* |
2183 | * Commit delayed tiling changes if we have an object still |
2183 | * Commit delayed tiling changes if we have an object still |
2184 | * attached to the fence, otherwise just clear the fence. |
2184 | * attached to the fence, otherwise just clear the fence. |
2185 | */ |
2185 | */ |
2186 | if (reg->obj) { |
2186 | if (reg->obj) { |
2187 | i915_gem_object_update_fence(reg->obj, reg, |
2187 | i915_gem_object_update_fence(reg->obj, reg, |
2188 | reg->obj->tiling_mode); |
2188 | reg->obj->tiling_mode); |
2189 | } else { |
2189 | } else { |
2190 | i915_gem_write_fence(dev, i, NULL); |
2190 | i915_gem_write_fence(dev, i, NULL); |
2191 | } |
2191 | } |
2192 | } |
2192 | } |
2193 | } |
2193 | } |
2194 | 2194 | ||
2195 | void i915_gem_reset(struct drm_device *dev) |
2195 | void i915_gem_reset(struct drm_device *dev) |
2196 | { |
2196 | { |
2197 | struct drm_i915_private *dev_priv = dev->dev_private; |
2197 | struct drm_i915_private *dev_priv = dev->dev_private; |
2198 | struct intel_ring_buffer *ring; |
2198 | struct intel_ring_buffer *ring; |
2199 | int i; |
2199 | int i; |
2200 | 2200 | ||
2201 | for_each_ring(ring, dev_priv, i) |
2201 | for_each_ring(ring, dev_priv, i) |
2202 | i915_gem_reset_ring_lists(dev_priv, ring); |
2202 | i915_gem_reset_ring_lists(dev_priv, ring); |
2203 | 2203 | ||
2204 | i915_gem_restore_fences(dev); |
2204 | i915_gem_restore_fences(dev); |
2205 | } |
2205 | } |
2206 | 2206 | ||
2207 | /** |
2207 | /** |
2208 | * This function clears the request list as sequence numbers are passed. |
2208 | * This function clears the request list as sequence numbers are passed. |
2209 | */ |
2209 | */ |
2210 | void |
2210 | void |
2211 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
2211 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
2212 | { |
2212 | { |
2213 | uint32_t seqno; |
2213 | uint32_t seqno; |
2214 | 2214 | ||
2215 | if (list_empty(&ring->request_list)) |
2215 | if (list_empty(&ring->request_list)) |
2216 | return; |
2216 | return; |
2217 | 2217 | ||
2218 | WARN_ON(i915_verify_lists(ring->dev)); |
2218 | WARN_ON(i915_verify_lists(ring->dev)); |
2219 | 2219 | ||
2220 | seqno = ring->get_seqno(ring, true); |
2220 | seqno = ring->get_seqno(ring, true); |
2221 | 2221 | ||
2222 | while (!list_empty(&ring->request_list)) { |
2222 | while (!list_empty(&ring->request_list)) { |
2223 | struct drm_i915_gem_request *request; |
2223 | struct drm_i915_gem_request *request; |
2224 | 2224 | ||
2225 | request = list_first_entry(&ring->request_list, |
2225 | request = list_first_entry(&ring->request_list, |
2226 | struct drm_i915_gem_request, |
2226 | struct drm_i915_gem_request, |
2227 | list); |
2227 | list); |
2228 | 2228 | ||
2229 | if (!i915_seqno_passed(seqno, request->seqno)) |
2229 | if (!i915_seqno_passed(seqno, request->seqno)) |
2230 | break; |
2230 | break; |
2231 | 2231 | ||
2232 | trace_i915_gem_request_retire(ring, request->seqno); |
2232 | trace_i915_gem_request_retire(ring, request->seqno); |
2233 | /* We know the GPU must have read the request to have |
2233 | /* We know the GPU must have read the request to have |
2234 | * sent us the seqno + interrupt, so use the position |
2234 | * sent us the seqno + interrupt, so use the position |
2235 | * of tail of the request to update the last known position |
2235 | * of tail of the request to update the last known position |
2236 | * of the GPU head. |
2236 | * of the GPU head. |
2237 | */ |
2237 | */ |
2238 | ring->last_retired_head = request->tail; |
2238 | ring->last_retired_head = request->tail; |
2239 | 2239 | ||
2240 | i915_gem_free_request(request); |
2240 | i915_gem_free_request(request); |
2241 | } |
2241 | } |
2242 | 2242 | ||
2243 | /* Move any buffers on the active list that are no longer referenced |
2243 | /* Move any buffers on the active list that are no longer referenced |
2244 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
2244 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
2245 | */ |
2245 | */ |
2246 | while (!list_empty(&ring->active_list)) { |
2246 | while (!list_empty(&ring->active_list)) { |
2247 | struct drm_i915_gem_object *obj; |
2247 | struct drm_i915_gem_object *obj; |
2248 | 2248 | ||
2249 | obj = list_first_entry(&ring->active_list, |
2249 | obj = list_first_entry(&ring->active_list, |
2250 | struct drm_i915_gem_object, |
2250 | struct drm_i915_gem_object, |
2251 | ring_list); |
2251 | ring_list); |
2252 | 2252 | ||
2253 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
2253 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
2254 | break; |
2254 | break; |
2255 | 2255 | ||
2256 | i915_gem_object_move_to_inactive(obj); |
2256 | i915_gem_object_move_to_inactive(obj); |
2257 | } |
2257 | } |
2258 | 2258 | ||
2259 | if (unlikely(ring->trace_irq_seqno && |
2259 | if (unlikely(ring->trace_irq_seqno && |
2260 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
2260 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
2261 | ring->irq_put(ring); |
2261 | ring->irq_put(ring); |
2262 | ring->trace_irq_seqno = 0; |
2262 | ring->trace_irq_seqno = 0; |
2263 | } |
2263 | } |
2264 | 2264 | ||
2265 | WARN_ON(i915_verify_lists(ring->dev)); |
2265 | WARN_ON(i915_verify_lists(ring->dev)); |
2266 | } |
2266 | } |
2267 | 2267 | ||
2268 | void |
2268 | void |
2269 | i915_gem_retire_requests(struct drm_device *dev) |
2269 | i915_gem_retire_requests(struct drm_device *dev) |
2270 | { |
2270 | { |
2271 | drm_i915_private_t *dev_priv = dev->dev_private; |
2271 | drm_i915_private_t *dev_priv = dev->dev_private; |
2272 | struct intel_ring_buffer *ring; |
2272 | struct intel_ring_buffer *ring; |
2273 | int i; |
2273 | int i; |
2274 | 2274 | ||
2275 | for_each_ring(ring, dev_priv, i) |
2275 | for_each_ring(ring, dev_priv, i) |
2276 | i915_gem_retire_requests_ring(ring); |
2276 | i915_gem_retire_requests_ring(ring); |
2277 | } |
2277 | } |
2278 | 2278 | ||
2279 | static void |
2279 | static void |
2280 | i915_gem_retire_work_handler(struct work_struct *work) |
2280 | i915_gem_retire_work_handler(struct work_struct *work) |
2281 | { |
2281 | { |
2282 | drm_i915_private_t *dev_priv; |
2282 | drm_i915_private_t *dev_priv; |
2283 | struct drm_device *dev; |
2283 | struct drm_device *dev; |
2284 | struct intel_ring_buffer *ring; |
2284 | struct intel_ring_buffer *ring; |
2285 | bool idle; |
2285 | bool idle; |
2286 | int i; |
2286 | int i; |
2287 | 2287 | ||
2288 | dev_priv = container_of(work, drm_i915_private_t, |
2288 | dev_priv = container_of(work, drm_i915_private_t, |
2289 | mm.retire_work.work); |
2289 | mm.retire_work.work); |
2290 | dev = dev_priv->dev; |
2290 | dev = dev_priv->dev; |
2291 | 2291 | ||
2292 | /* Come back later if the device is busy... */ |
2292 | /* Come back later if the device is busy... */ |
2293 | if (!mutex_trylock(&dev->struct_mutex)) { |
2293 | if (!mutex_trylock(&dev->struct_mutex)) { |
2294 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2294 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2295 | round_jiffies_up_relative(HZ)); |
2295 | round_jiffies_up_relative(HZ)); |
2296 | return; |
2296 | return; |
2297 | } |
2297 | } |
2298 | 2298 | ||
2299 | i915_gem_retire_requests(dev); |
2299 | i915_gem_retire_requests(dev); |
2300 | 2300 | ||
2301 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2301 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2302 | * objects indefinitely. |
2302 | * objects indefinitely. |
2303 | */ |
2303 | */ |
2304 | idle = true; |
2304 | idle = true; |
2305 | for_each_ring(ring, dev_priv, i) { |
2305 | for_each_ring(ring, dev_priv, i) { |
2306 | if (ring->gpu_caches_dirty) |
2306 | if (ring->gpu_caches_dirty) |
2307 | i915_add_request(ring, NULL); |
2307 | i915_add_request(ring, NULL); |
2308 | 2308 | ||
2309 | idle &= list_empty(&ring->request_list); |
2309 | idle &= list_empty(&ring->request_list); |
2310 | } |
2310 | } |
2311 | 2311 | ||
2312 | if (!dev_priv->ums.mm_suspended && !idle) |
2312 | if (!dev_priv->ums.mm_suspended && !idle) |
2313 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2313 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2314 | round_jiffies_up_relative(HZ)); |
2314 | round_jiffies_up_relative(HZ)); |
2315 | if (idle) |
2315 | if (idle) |
2316 | intel_mark_idle(dev); |
2316 | intel_mark_idle(dev); |
2317 | 2317 | ||
2318 | mutex_unlock(&dev->struct_mutex); |
2318 | mutex_unlock(&dev->struct_mutex); |
2319 | } |
2319 | } |
2320 | 2320 | ||
2321 | /** |
2321 | /** |
2322 | * Ensures that an object will eventually get non-busy by flushing any required |
2322 | * Ensures that an object will eventually get non-busy by flushing any required |
2323 | * write domains, emitting any outstanding lazy request and retiring and |
2323 | * write domains, emitting any outstanding lazy request and retiring and |
2324 | * completed requests. |
2324 | * completed requests. |
2325 | */ |
2325 | */ |
2326 | static int |
2326 | static int |
2327 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
2327 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
2328 | { |
2328 | { |
2329 | int ret; |
2329 | int ret; |
2330 | 2330 | ||
2331 | if (obj->active) { |
2331 | if (obj->active) { |
2332 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
2332 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
2333 | if (ret) |
2333 | if (ret) |
2334 | return ret; |
2334 | return ret; |
2335 | 2335 | ||
2336 | i915_gem_retire_requests_ring(obj->ring); |
2336 | i915_gem_retire_requests_ring(obj->ring); |
2337 | } |
2337 | } |
2338 | 2338 | ||
2339 | return 0; |
2339 | return 0; |
2340 | } |
2340 | } |
2341 | 2341 | ||
2342 | /** |
2342 | /** |
2343 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
2343 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
2344 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
2344 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
2345 | * |
2345 | * |
2346 | * Returns 0 if successful, else an error is returned with the remaining time in |
2346 | * Returns 0 if successful, else an error is returned with the remaining time in |
2347 | * the timeout parameter. |
2347 | * the timeout parameter. |
2348 | * -ETIME: object is still busy after timeout |
2348 | * -ETIME: object is still busy after timeout |
2349 | * -ERESTARTSYS: signal interrupted the wait |
2349 | * -ERESTARTSYS: signal interrupted the wait |
2350 | * -ENONENT: object doesn't exist |
2350 | * -ENONENT: object doesn't exist |
2351 | * Also possible, but rare: |
2351 | * Also possible, but rare: |
2352 | * -EAGAIN: GPU wedged |
2352 | * -EAGAIN: GPU wedged |
2353 | * -ENOMEM: damn |
2353 | * -ENOMEM: damn |
2354 | * -ENODEV: Internal IRQ fail |
2354 | * -ENODEV: Internal IRQ fail |
2355 | * -E?: The add request failed |
2355 | * -E?: The add request failed |
2356 | * |
2356 | * |
2357 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
2357 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
2358 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
2358 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
2359 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
2359 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
2360 | * without holding struct_mutex the object may become re-busied before this |
2360 | * without holding struct_mutex the object may become re-busied before this |
2361 | * function completes. A similar but shorter * race condition exists in the busy |
2361 | * function completes. A similar but shorter * race condition exists in the busy |
2362 | * ioctl |
2362 | * ioctl |
2363 | */ |
2363 | */ |
2364 | int |
2364 | int |
2365 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
2365 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
2366 | { |
2366 | { |
2367 | drm_i915_private_t *dev_priv = dev->dev_private; |
2367 | drm_i915_private_t *dev_priv = dev->dev_private; |
2368 | struct drm_i915_gem_wait *args = data; |
2368 | struct drm_i915_gem_wait *args = data; |
2369 | struct drm_i915_gem_object *obj; |
2369 | struct drm_i915_gem_object *obj; |
2370 | struct intel_ring_buffer *ring = NULL; |
2370 | struct intel_ring_buffer *ring = NULL; |
2371 | struct timespec timeout_stack, *timeout = NULL; |
2371 | struct timespec timeout_stack, *timeout = NULL; |
2372 | unsigned reset_counter; |
2372 | unsigned reset_counter; |
2373 | u32 seqno = 0; |
2373 | u32 seqno = 0; |
2374 | int ret = 0; |
2374 | int ret = 0; |
2375 | 2375 | ||
2376 | if (args->timeout_ns >= 0) { |
2376 | if (args->timeout_ns >= 0) { |
2377 | timeout_stack = ns_to_timespec(args->timeout_ns); |
2377 | timeout_stack = ns_to_timespec(args->timeout_ns); |
2378 | timeout = &timeout_stack; |
2378 | timeout = &timeout_stack; |
2379 | } |
2379 | } |
2380 | 2380 | ||
2381 | ret = i915_mutex_lock_interruptible(dev); |
2381 | ret = i915_mutex_lock_interruptible(dev); |
2382 | if (ret) |
2382 | if (ret) |
2383 | return ret; |
2383 | return ret; |
2384 | 2384 | ||
2385 | if(args->bo_handle == -2) |
2385 | if(args->bo_handle == -2) |
2386 | { |
2386 | { |
2387 | obj = get_fb_obj(); |
2387 | obj = get_fb_obj(); |
2388 | drm_gem_object_reference(&obj->base); |
2388 | drm_gem_object_reference(&obj->base); |
2389 | } |
2389 | } |
2390 | else |
2390 | else |
2391 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
2391 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
2392 | if (&obj->base == NULL) { |
2392 | if (&obj->base == NULL) { |
2393 | mutex_unlock(&dev->struct_mutex); |
2393 | mutex_unlock(&dev->struct_mutex); |
2394 | return -ENOENT; |
2394 | return -ENOENT; |
2395 | } |
2395 | } |
2396 | 2396 | ||
2397 | /* Need to make sure the object gets inactive eventually. */ |
2397 | /* Need to make sure the object gets inactive eventually. */ |
2398 | ret = i915_gem_object_flush_active(obj); |
2398 | ret = i915_gem_object_flush_active(obj); |
2399 | if (ret) |
2399 | if (ret) |
2400 | goto out; |
2400 | goto out; |
2401 | 2401 | ||
2402 | if (obj->active) { |
2402 | if (obj->active) { |
2403 | seqno = obj->last_read_seqno; |
2403 | seqno = obj->last_read_seqno; |
2404 | ring = obj->ring; |
2404 | ring = obj->ring; |
2405 | } |
2405 | } |
2406 | 2406 | ||
2407 | if (seqno == 0) |
2407 | if (seqno == 0) |
2408 | goto out; |
2408 | goto out; |
2409 | 2409 | ||
2410 | /* Do this after OLR check to make sure we make forward progress polling |
2410 | /* Do this after OLR check to make sure we make forward progress polling |
2411 | * on this IOCTL with a 0 timeout (like busy ioctl) |
2411 | * on this IOCTL with a 0 timeout (like busy ioctl) |
2412 | */ |
2412 | */ |
2413 | if (!args->timeout_ns) { |
2413 | if (!args->timeout_ns) { |
2414 | ret = -ETIME; |
2414 | ret = -ETIME; |
2415 | goto out; |
2415 | goto out; |
2416 | } |
2416 | } |
2417 | 2417 | ||
2418 | drm_gem_object_unreference(&obj->base); |
2418 | drm_gem_object_unreference(&obj->base); |
2419 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
2419 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
2420 | mutex_unlock(&dev->struct_mutex); |
2420 | mutex_unlock(&dev->struct_mutex); |
2421 | 2421 | ||
2422 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
2422 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
2423 | if (timeout) |
2423 | if (timeout) |
2424 | args->timeout_ns = timespec_to_ns(timeout); |
2424 | args->timeout_ns = timespec_to_ns(timeout); |
2425 | return ret; |
2425 | return ret; |
2426 | 2426 | ||
2427 | out: |
2427 | out: |
2428 | drm_gem_object_unreference(&obj->base); |
2428 | drm_gem_object_unreference(&obj->base); |
2429 | mutex_unlock(&dev->struct_mutex); |
2429 | mutex_unlock(&dev->struct_mutex); |
2430 | return ret; |
2430 | return ret; |
2431 | } |
2431 | } |
2432 | 2432 | ||
2433 | /** |
2433 | /** |
2434 | * i915_gem_object_sync - sync an object to a ring. |
2434 | * i915_gem_object_sync - sync an object to a ring. |
2435 | * |
2435 | * |
2436 | * @obj: object which may be in use on another ring. |
2436 | * @obj: object which may be in use on another ring. |
2437 | * @to: ring we wish to use the object on. May be NULL. |
2437 | * @to: ring we wish to use the object on. May be NULL. |
2438 | * |
2438 | * |
2439 | * This code is meant to abstract object synchronization with the GPU. |
2439 | * This code is meant to abstract object synchronization with the GPU. |
2440 | * Calling with NULL implies synchronizing the object with the CPU |
2440 | * Calling with NULL implies synchronizing the object with the CPU |
2441 | * rather than a particular GPU ring. |
2441 | * rather than a particular GPU ring. |
2442 | * |
2442 | * |
2443 | * Returns 0 if successful, else propagates up the lower layer error. |
2443 | * Returns 0 if successful, else propagates up the lower layer error. |
2444 | */ |
2444 | */ |
2445 | int |
2445 | int |
2446 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2446 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2447 | struct intel_ring_buffer *to) |
2447 | struct intel_ring_buffer *to) |
2448 | { |
2448 | { |
2449 | struct intel_ring_buffer *from = obj->ring; |
2449 | struct intel_ring_buffer *from = obj->ring; |
2450 | u32 seqno; |
2450 | u32 seqno; |
2451 | int ret, idx; |
2451 | int ret, idx; |
2452 | 2452 | ||
2453 | if (from == NULL || to == from) |
2453 | if (from == NULL || to == from) |
2454 | return 0; |
2454 | return 0; |
2455 | 2455 | ||
2456 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2456 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2457 | return i915_gem_object_wait_rendering(obj, false); |
2457 | return i915_gem_object_wait_rendering(obj, false); |
2458 | 2458 | ||
2459 | idx = intel_ring_sync_index(from, to); |
2459 | idx = intel_ring_sync_index(from, to); |
2460 | 2460 | ||
2461 | seqno = obj->last_read_seqno; |
2461 | seqno = obj->last_read_seqno; |
2462 | if (seqno <= from->sync_seqno[idx]) |
2462 | if (seqno <= from->sync_seqno[idx]) |
2463 | return 0; |
2463 | return 0; |
2464 | 2464 | ||
2465 | ret = i915_gem_check_olr(obj->ring, seqno); |
2465 | ret = i915_gem_check_olr(obj->ring, seqno); |
2466 | if (ret) |
2466 | if (ret) |
2467 | return ret; |
2467 | return ret; |
2468 | 2468 | ||
2469 | ret = to->sync_to(to, from, seqno); |
2469 | ret = to->sync_to(to, from, seqno); |
2470 | if (!ret) |
2470 | if (!ret) |
2471 | /* We use last_read_seqno because sync_to() |
2471 | /* We use last_read_seqno because sync_to() |
2472 | * might have just caused seqno wrap under |
2472 | * might have just caused seqno wrap under |
2473 | * the radar. |
2473 | * the radar. |
2474 | */ |
2474 | */ |
2475 | from->sync_seqno[idx] = obj->last_read_seqno; |
2475 | from->sync_seqno[idx] = obj->last_read_seqno; |
2476 | 2476 | ||
2477 | return ret; |
2477 | return ret; |
2478 | } |
2478 | } |
2479 | 2479 | ||
2480 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2480 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2481 | { |
2481 | { |
2482 | u32 old_write_domain, old_read_domains; |
2482 | u32 old_write_domain, old_read_domains; |
2483 | 2483 | ||
2484 | /* Force a pagefault for domain tracking on next user access */ |
2484 | /* Force a pagefault for domain tracking on next user access */ |
2485 | // i915_gem_release_mmap(obj); |
2485 | // i915_gem_release_mmap(obj); |
2486 | 2486 | ||
2487 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2487 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2488 | return; |
2488 | return; |
2489 | 2489 | ||
2490 | /* Wait for any direct GTT access to complete */ |
2490 | /* Wait for any direct GTT access to complete */ |
2491 | mb(); |
2491 | mb(); |
2492 | 2492 | ||
2493 | old_read_domains = obj->base.read_domains; |
2493 | old_read_domains = obj->base.read_domains; |
2494 | old_write_domain = obj->base.write_domain; |
2494 | old_write_domain = obj->base.write_domain; |
2495 | 2495 | ||
2496 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
2496 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
2497 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
2497 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
2498 | 2498 | ||
2499 | trace_i915_gem_object_change_domain(obj, |
2499 | trace_i915_gem_object_change_domain(obj, |
2500 | old_read_domains, |
2500 | old_read_domains, |
2501 | old_write_domain); |
2501 | old_write_domain); |
2502 | } |
2502 | } |
2503 | 2503 | ||
2504 | int i915_vma_unbind(struct i915_vma *vma) |
2504 | int i915_vma_unbind(struct i915_vma *vma) |
2505 | { |
2505 | { |
2506 | struct drm_i915_gem_object *obj = vma->obj; |
2506 | struct drm_i915_gem_object *obj = vma->obj; |
2507 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
2507 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
2508 | int ret; |
2508 | int ret; |
2509 | 2509 | ||
2510 | if(obj == get_fb_obj()) |
2510 | if(obj == get_fb_obj()) |
2511 | return 0; |
2511 | return 0; |
2512 | 2512 | ||
2513 | if (list_empty(&vma->vma_link)) |
2513 | if (list_empty(&vma->vma_link)) |
2514 | return 0; |
2514 | return 0; |
2515 | 2515 | ||
2516 | if (!drm_mm_node_allocated(&vma->node)) |
2516 | if (!drm_mm_node_allocated(&vma->node)) |
2517 | goto destroy; |
2517 | goto destroy; |
2518 | 2518 | ||
2519 | if (obj->pin_count) |
2519 | if (obj->pin_count) |
2520 | return -EBUSY; |
2520 | return -EBUSY; |
2521 | 2521 | ||
2522 | BUG_ON(obj->pages == NULL); |
2522 | BUG_ON(obj->pages == NULL); |
2523 | 2523 | ||
2524 | ret = i915_gem_object_finish_gpu(obj); |
2524 | ret = i915_gem_object_finish_gpu(obj); |
2525 | if (ret) |
2525 | if (ret) |
2526 | return ret; |
2526 | return ret; |
2527 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2527 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2528 | * should be safe and we need to cleanup or else we might |
2528 | * should be safe and we need to cleanup or else we might |
2529 | * cause memory corruption through use-after-free. |
2529 | * cause memory corruption through use-after-free. |
2530 | */ |
2530 | */ |
2531 | 2531 | ||
2532 | i915_gem_object_finish_gtt(obj); |
2532 | i915_gem_object_finish_gtt(obj); |
2533 | 2533 | ||
2534 | /* release the fence reg _after_ flushing */ |
2534 | /* release the fence reg _after_ flushing */ |
2535 | ret = i915_gem_object_put_fence(obj); |
2535 | ret = i915_gem_object_put_fence(obj); |
2536 | if (ret) |
2536 | if (ret) |
2537 | return ret; |
2537 | return ret; |
2538 | 2538 | ||
2539 | trace_i915_vma_unbind(vma); |
2539 | trace_i915_vma_unbind(vma); |
2540 | 2540 | ||
2541 | if (obj->has_global_gtt_mapping) |
2541 | if (obj->has_global_gtt_mapping) |
2542 | i915_gem_gtt_unbind_object(obj); |
2542 | i915_gem_gtt_unbind_object(obj); |
2543 | if (obj->has_aliasing_ppgtt_mapping) { |
2543 | if (obj->has_aliasing_ppgtt_mapping) { |
2544 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
2544 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
2545 | obj->has_aliasing_ppgtt_mapping = 0; |
2545 | obj->has_aliasing_ppgtt_mapping = 0; |
2546 | } |
2546 | } |
2547 | i915_gem_gtt_finish_object(obj); |
2547 | i915_gem_gtt_finish_object(obj); |
2548 | i915_gem_object_unpin_pages(obj); |
2548 | i915_gem_object_unpin_pages(obj); |
2549 | 2549 | ||
2550 | list_del(&vma->mm_list); |
2550 | list_del(&vma->mm_list); |
2551 | /* Avoid an unnecessary call to unbind on rebind. */ |
2551 | /* Avoid an unnecessary call to unbind on rebind. */ |
2552 | if (i915_is_ggtt(vma->vm)) |
2552 | if (i915_is_ggtt(vma->vm)) |
2553 | obj->map_and_fenceable = true; |
2553 | obj->map_and_fenceable = true; |
2554 | 2554 | ||
2555 | drm_mm_remove_node(&vma->node); |
2555 | drm_mm_remove_node(&vma->node); |
2556 | 2556 | ||
2557 | destroy: |
2557 | destroy: |
2558 | i915_gem_vma_destroy(vma); |
2558 | i915_gem_vma_destroy(vma); |
2559 | 2559 | ||
2560 | /* Since the unbound list is global, only move to that list if |
2560 | /* Since the unbound list is global, only move to that list if |
2561 | * no more VMAs exist. |
2561 | * no more VMAs exist. |
2562 | * NB: Until we have real VMAs there will only ever be one */ |
2562 | * NB: Until we have real VMAs there will only ever be one */ |
2563 | WARN_ON(!list_empty(&obj->vma_list)); |
2563 | WARN_ON(!list_empty(&obj->vma_list)); |
2564 | if (list_empty(&obj->vma_list)) |
2564 | if (list_empty(&obj->vma_list)) |
2565 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
2565 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
2566 | 2566 | ||
2567 | return 0; |
2567 | return 0; |
2568 | } |
2568 | } |
2569 | 2569 | ||
2570 | /** |
2570 | /** |
2571 | * Unbinds an object from the global GTT aperture. |
2571 | * Unbinds an object from the global GTT aperture. |
2572 | */ |
2572 | */ |
2573 | int |
2573 | int |
2574 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
2574 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
2575 | { |
2575 | { |
2576 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2576 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2577 | struct i915_address_space *ggtt = &dev_priv->gtt.base; |
2577 | struct i915_address_space *ggtt = &dev_priv->gtt.base; |
2578 | 2578 | ||
2579 | if (!i915_gem_obj_ggtt_bound(obj)) |
2579 | if (!i915_gem_obj_ggtt_bound(obj)) |
2580 | return 0; |
2580 | return 0; |
2581 | 2581 | ||
2582 | if (obj->pin_count) |
2582 | if (obj->pin_count) |
2583 | return -EBUSY; |
2583 | return -EBUSY; |
2584 | 2584 | ||
2585 | BUG_ON(obj->pages == NULL); |
2585 | BUG_ON(obj->pages == NULL); |
2586 | 2586 | ||
2587 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); |
2587 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); |
2588 | } |
2588 | } |
2589 | 2589 | ||
2590 | int i915_gpu_idle(struct drm_device *dev) |
2590 | int i915_gpu_idle(struct drm_device *dev) |
2591 | { |
2591 | { |
2592 | drm_i915_private_t *dev_priv = dev->dev_private; |
2592 | drm_i915_private_t *dev_priv = dev->dev_private; |
2593 | struct intel_ring_buffer *ring; |
2593 | struct intel_ring_buffer *ring; |
2594 | int ret, i; |
2594 | int ret, i; |
2595 | 2595 | ||
2596 | /* Flush everything onto the inactive list. */ |
2596 | /* Flush everything onto the inactive list. */ |
2597 | for_each_ring(ring, dev_priv, i) { |
2597 | for_each_ring(ring, dev_priv, i) { |
2598 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2598 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2599 | if (ret) |
2599 | if (ret) |
2600 | return ret; |
2600 | return ret; |
2601 | 2601 | ||
2602 | ret = intel_ring_idle(ring); |
2602 | ret = intel_ring_idle(ring); |
2603 | if (ret) |
2603 | if (ret) |
2604 | return ret; |
2604 | return ret; |
2605 | } |
2605 | } |
2606 | 2606 | ||
2607 | return 0; |
2607 | return 0; |
2608 | } |
2608 | } |
2609 | 2609 | ||
2610 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2610 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2611 | struct drm_i915_gem_object *obj) |
2611 | struct drm_i915_gem_object *obj) |
2612 | { |
2612 | { |
2613 | drm_i915_private_t *dev_priv = dev->dev_private; |
2613 | drm_i915_private_t *dev_priv = dev->dev_private; |
2614 | int fence_reg; |
2614 | int fence_reg; |
2615 | int fence_pitch_shift; |
2615 | int fence_pitch_shift; |
2616 | 2616 | ||
2617 | if (INTEL_INFO(dev)->gen >= 6) { |
2617 | if (INTEL_INFO(dev)->gen >= 6) { |
2618 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
2618 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
2619 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2619 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2620 | } else { |
2620 | } else { |
2621 | fence_reg = FENCE_REG_965_0; |
2621 | fence_reg = FENCE_REG_965_0; |
2622 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
2622 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
2623 | } |
2623 | } |
2624 | 2624 | ||
2625 | fence_reg += reg * 8; |
2625 | fence_reg += reg * 8; |
2626 | 2626 | ||
2627 | /* To w/a incoherency with non-atomic 64-bit register updates, |
2627 | /* To w/a incoherency with non-atomic 64-bit register updates, |
2628 | * we split the 64-bit update into two 32-bit writes. In order |
2628 | * we split the 64-bit update into two 32-bit writes. In order |
2629 | * for a partial fence not to be evaluated between writes, we |
2629 | * for a partial fence not to be evaluated between writes, we |
2630 | * precede the update with write to turn off the fence register, |
2630 | * precede the update with write to turn off the fence register, |
2631 | * and only enable the fence as the last step. |
2631 | * and only enable the fence as the last step. |
2632 | * |
2632 | * |
2633 | * For extra levels of paranoia, we make sure each step lands |
2633 | * For extra levels of paranoia, we make sure each step lands |
2634 | * before applying the next step. |
2634 | * before applying the next step. |
2635 | */ |
2635 | */ |
2636 | I915_WRITE(fence_reg, 0); |
2636 | I915_WRITE(fence_reg, 0); |
2637 | POSTING_READ(fence_reg); |
2637 | POSTING_READ(fence_reg); |
2638 | 2638 | ||
2639 | if (obj) { |
2639 | if (obj) { |
2640 | u32 size = i915_gem_obj_ggtt_size(obj); |
2640 | u32 size = i915_gem_obj_ggtt_size(obj); |
2641 | uint64_t val; |
2641 | uint64_t val; |
2642 | 2642 | ||
2643 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
2643 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
2644 | 0xfffff000) << 32; |
2644 | 0xfffff000) << 32; |
2645 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
2645 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
2646 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
2646 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
2647 | if (obj->tiling_mode == I915_TILING_Y) |
2647 | if (obj->tiling_mode == I915_TILING_Y) |
2648 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2648 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2649 | val |= I965_FENCE_REG_VALID; |
2649 | val |= I965_FENCE_REG_VALID; |
2650 | 2650 | ||
2651 | I915_WRITE(fence_reg + 4, val >> 32); |
2651 | I915_WRITE(fence_reg + 4, val >> 32); |
2652 | POSTING_READ(fence_reg + 4); |
2652 | POSTING_READ(fence_reg + 4); |
2653 | 2653 | ||
2654 | I915_WRITE(fence_reg + 0, val); |
2654 | I915_WRITE(fence_reg + 0, val); |
2655 | 2655 | ||
2656 | dbgprintf("%s val %x%x\n",__FUNCTION__, (int)(val >> 32), (int)val); |
2656 | dbgprintf("%s val %x%x\n",__FUNCTION__, (int)(val >> 32), (int)val); |
2657 | 2657 | ||
2658 | POSTING_READ(fence_reg); |
2658 | POSTING_READ(fence_reg); |
2659 | } else { |
2659 | } else { |
2660 | I915_WRITE(fence_reg + 4, 0); |
2660 | I915_WRITE(fence_reg + 4, 0); |
2661 | POSTING_READ(fence_reg + 4); |
2661 | POSTING_READ(fence_reg + 4); |
2662 | } |
2662 | } |
2663 | } |
2663 | } |
2664 | 2664 | ||
2665 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2665 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2666 | struct drm_i915_gem_object *obj) |
2666 | struct drm_i915_gem_object *obj) |
2667 | { |
2667 | { |
2668 | drm_i915_private_t *dev_priv = dev->dev_private; |
2668 | drm_i915_private_t *dev_priv = dev->dev_private; |
2669 | u32 val; |
2669 | u32 val; |
2670 | 2670 | ||
2671 | if (obj) { |
2671 | if (obj) { |
2672 | u32 size = i915_gem_obj_ggtt_size(obj); |
2672 | u32 size = i915_gem_obj_ggtt_size(obj); |
2673 | int pitch_val; |
2673 | int pitch_val; |
2674 | int tile_width; |
2674 | int tile_width; |
2675 | 2675 | ||
2676 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
2676 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
2677 | (size & -size) != size || |
2677 | (size & -size) != size || |
2678 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2678 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2679 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
2679 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
2680 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
2680 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
2681 | 2681 | ||
2682 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2682 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2683 | tile_width = 128; |
2683 | tile_width = 128; |
2684 | else |
2684 | else |
2685 | tile_width = 512; |
2685 | tile_width = 512; |
2686 | 2686 | ||
2687 | /* Note: pitch better be a power of two tile widths */ |
2687 | /* Note: pitch better be a power of two tile widths */ |
2688 | pitch_val = obj->stride / tile_width; |
2688 | pitch_val = obj->stride / tile_width; |
2689 | pitch_val = ffs(pitch_val) - 1; |
2689 | pitch_val = ffs(pitch_val) - 1; |
2690 | 2690 | ||
2691 | val = i915_gem_obj_ggtt_offset(obj); |
2691 | val = i915_gem_obj_ggtt_offset(obj); |
2692 | if (obj->tiling_mode == I915_TILING_Y) |
2692 | if (obj->tiling_mode == I915_TILING_Y) |
2693 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2693 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2694 | val |= I915_FENCE_SIZE_BITS(size); |
2694 | val |= I915_FENCE_SIZE_BITS(size); |
2695 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2695 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2696 | val |= I830_FENCE_REG_VALID; |
2696 | val |= I830_FENCE_REG_VALID; |
2697 | } else |
2697 | } else |
2698 | val = 0; |
2698 | val = 0; |
2699 | 2699 | ||
2700 | if (reg < 8) |
2700 | if (reg < 8) |
2701 | reg = FENCE_REG_830_0 + reg * 4; |
2701 | reg = FENCE_REG_830_0 + reg * 4; |
2702 | else |
2702 | else |
2703 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
2703 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
2704 | 2704 | ||
2705 | I915_WRITE(reg, val); |
2705 | I915_WRITE(reg, val); |
2706 | POSTING_READ(reg); |
2706 | POSTING_READ(reg); |
2707 | } |
2707 | } |
2708 | 2708 | ||
2709 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2709 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2710 | struct drm_i915_gem_object *obj) |
2710 | struct drm_i915_gem_object *obj) |
2711 | { |
2711 | { |
2712 | drm_i915_private_t *dev_priv = dev->dev_private; |
2712 | drm_i915_private_t *dev_priv = dev->dev_private; |
2713 | uint32_t val; |
2713 | uint32_t val; |
2714 | 2714 | ||
2715 | if (obj) { |
2715 | if (obj) { |
2716 | u32 size = i915_gem_obj_ggtt_size(obj); |
2716 | u32 size = i915_gem_obj_ggtt_size(obj); |
2717 | uint32_t pitch_val; |
2717 | uint32_t pitch_val; |
2718 | 2718 | ||
2719 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
2719 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
2720 | (size & -size) != size || |
2720 | (size & -size) != size || |
2721 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2721 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2722 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
2722 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
2723 | i915_gem_obj_ggtt_offset(obj), size); |
2723 | i915_gem_obj_ggtt_offset(obj), size); |
2724 | 2724 | ||
2725 | pitch_val = obj->stride / 128; |
2725 | pitch_val = obj->stride / 128; |
2726 | pitch_val = ffs(pitch_val) - 1; |
2726 | pitch_val = ffs(pitch_val) - 1; |
2727 | 2727 | ||
2728 | val = i915_gem_obj_ggtt_offset(obj); |
2728 | val = i915_gem_obj_ggtt_offset(obj); |
2729 | if (obj->tiling_mode == I915_TILING_Y) |
2729 | if (obj->tiling_mode == I915_TILING_Y) |
2730 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2730 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2731 | val |= I830_FENCE_SIZE_BITS(size); |
2731 | val |= I830_FENCE_SIZE_BITS(size); |
2732 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2732 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2733 | val |= I830_FENCE_REG_VALID; |
2733 | val |= I830_FENCE_REG_VALID; |
2734 | } else |
2734 | } else |
2735 | val = 0; |
2735 | val = 0; |
2736 | 2736 | ||
2737 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2737 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2738 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
2738 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
2739 | } |
2739 | } |
2740 | 2740 | ||
2741 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2741 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2742 | { |
2742 | { |
2743 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
2743 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
2744 | } |
2744 | } |
2745 | 2745 | ||
2746 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2746 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2747 | struct drm_i915_gem_object *obj) |
2747 | struct drm_i915_gem_object *obj) |
2748 | { |
2748 | { |
2749 | struct drm_i915_private *dev_priv = dev->dev_private; |
2749 | struct drm_i915_private *dev_priv = dev->dev_private; |
2750 | 2750 | ||
2751 | /* Ensure that all CPU reads are completed before installing a fence |
2751 | /* Ensure that all CPU reads are completed before installing a fence |
2752 | * and all writes before removing the fence. |
2752 | * and all writes before removing the fence. |
2753 | */ |
2753 | */ |
2754 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
2754 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
2755 | mb(); |
2755 | mb(); |
2756 | 2756 | ||
2757 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2757 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2758 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
2758 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
2759 | obj->stride, obj->tiling_mode); |
2759 | obj->stride, obj->tiling_mode); |
2760 | 2760 | ||
2761 | switch (INTEL_INFO(dev)->gen) { |
2761 | switch (INTEL_INFO(dev)->gen) { |
2762 | case 7: |
2762 | case 7: |
2763 | case 6: |
2763 | case 6: |
2764 | case 5: |
2764 | case 5: |
2765 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
2765 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
2766 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
2766 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
2767 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
2767 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
2768 | default: BUG(); |
2768 | default: BUG(); |
2769 | } |
2769 | } |
2770 | 2770 | ||
2771 | /* And similarly be paranoid that no direct access to this region |
2771 | /* And similarly be paranoid that no direct access to this region |
2772 | * is reordered to before the fence is installed. |
2772 | * is reordered to before the fence is installed. |
2773 | */ |
2773 | */ |
2774 | if (i915_gem_object_needs_mb(obj)) |
2774 | if (i915_gem_object_needs_mb(obj)) |
2775 | mb(); |
2775 | mb(); |
2776 | } |
2776 | } |
2777 | 2777 | ||
2778 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2778 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2779 | struct drm_i915_fence_reg *fence) |
2779 | struct drm_i915_fence_reg *fence) |
2780 | { |
2780 | { |
2781 | return fence - dev_priv->fence_regs; |
2781 | return fence - dev_priv->fence_regs; |
2782 | } |
2782 | } |
2783 | 2783 | ||
2784 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2784 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2785 | struct drm_i915_fence_reg *fence, |
2785 | struct drm_i915_fence_reg *fence, |
2786 | bool enable) |
2786 | bool enable) |
2787 | { |
2787 | { |
2788 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2788 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2789 | int reg = fence_number(dev_priv, fence); |
2789 | int reg = fence_number(dev_priv, fence); |
2790 | 2790 | ||
2791 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
2791 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
2792 | 2792 | ||
2793 | if (enable) { |
2793 | if (enable) { |
2794 | obj->fence_reg = reg; |
2794 | obj->fence_reg = reg; |
2795 | fence->obj = obj; |
2795 | fence->obj = obj; |
2796 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
2796 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
2797 | } else { |
2797 | } else { |
2798 | obj->fence_reg = I915_FENCE_REG_NONE; |
2798 | obj->fence_reg = I915_FENCE_REG_NONE; |
2799 | fence->obj = NULL; |
2799 | fence->obj = NULL; |
2800 | list_del_init(&fence->lru_list); |
2800 | list_del_init(&fence->lru_list); |
2801 | } |
2801 | } |
2802 | obj->fence_dirty = false; |
2802 | obj->fence_dirty = false; |
2803 | } |
2803 | } |
2804 | 2804 | ||
2805 | static int |
2805 | static int |
2806 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
2806 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
2807 | { |
2807 | { |
2808 | if (obj->last_fenced_seqno) { |
2808 | if (obj->last_fenced_seqno) { |
2809 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
2809 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
2810 | if (ret) |
2810 | if (ret) |
2811 | return ret; |
2811 | return ret; |
2812 | 2812 | ||
2813 | obj->last_fenced_seqno = 0; |
2813 | obj->last_fenced_seqno = 0; |
2814 | } |
2814 | } |
2815 | 2815 | ||
2816 | obj->fenced_gpu_access = false; |
2816 | obj->fenced_gpu_access = false; |
2817 | return 0; |
2817 | return 0; |
2818 | } |
2818 | } |
2819 | 2819 | ||
2820 | int |
2820 | int |
2821 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
2821 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
2822 | { |
2822 | { |
2823 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2823 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2824 | struct drm_i915_fence_reg *fence; |
2824 | struct drm_i915_fence_reg *fence; |
2825 | int ret; |
2825 | int ret; |
2826 | 2826 | ||
2827 | ret = i915_gem_object_wait_fence(obj); |
2827 | ret = i915_gem_object_wait_fence(obj); |
2828 | if (ret) |
2828 | if (ret) |
2829 | return ret; |
2829 | return ret; |
2830 | 2830 | ||
2831 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2831 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2832 | return 0; |
2832 | return 0; |
2833 | 2833 | ||
2834 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2834 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2835 | 2835 | ||
2836 | i915_gem_object_fence_lost(obj); |
2836 | i915_gem_object_fence_lost(obj); |
2837 | i915_gem_object_update_fence(obj, fence, false); |
2837 | i915_gem_object_update_fence(obj, fence, false); |
2838 | 2838 | ||
2839 | return 0; |
2839 | return 0; |
2840 | } |
2840 | } |
2841 | 2841 | ||
2842 | static struct drm_i915_fence_reg * |
2842 | static struct drm_i915_fence_reg * |
2843 | i915_find_fence_reg(struct drm_device *dev) |
2843 | i915_find_fence_reg(struct drm_device *dev) |
2844 | { |
2844 | { |
2845 | struct drm_i915_private *dev_priv = dev->dev_private; |
2845 | struct drm_i915_private *dev_priv = dev->dev_private; |
2846 | struct drm_i915_fence_reg *reg, *avail; |
2846 | struct drm_i915_fence_reg *reg, *avail; |
2847 | int i; |
2847 | int i; |
2848 | 2848 | ||
2849 | /* First try to find a free reg */ |
2849 | /* First try to find a free reg */ |
2850 | avail = NULL; |
2850 | avail = NULL; |
2851 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2851 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2852 | reg = &dev_priv->fence_regs[i]; |
2852 | reg = &dev_priv->fence_regs[i]; |
2853 | if (!reg->obj) |
2853 | if (!reg->obj) |
2854 | return reg; |
2854 | return reg; |
2855 | 2855 | ||
2856 | if (!reg->pin_count) |
2856 | if (!reg->pin_count) |
2857 | avail = reg; |
2857 | avail = reg; |
2858 | } |
2858 | } |
2859 | 2859 | ||
2860 | if (avail == NULL) |
2860 | if (avail == NULL) |
2861 | return NULL; |
2861 | return NULL; |
2862 | 2862 | ||
2863 | /* None available, try to steal one or wait for a user to finish */ |
2863 | /* None available, try to steal one or wait for a user to finish */ |
2864 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
2864 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
2865 | if (reg->pin_count) |
2865 | if (reg->pin_count) |
2866 | continue; |
2866 | continue; |
2867 | 2867 | ||
2868 | return reg; |
2868 | return reg; |
2869 | } |
2869 | } |
2870 | 2870 | ||
2871 | return NULL; |
2871 | return NULL; |
2872 | } |
2872 | } |
2873 | 2873 | ||
2874 | /** |
2874 | /** |
2875 | * i915_gem_object_get_fence - set up fencing for an object |
2875 | * i915_gem_object_get_fence - set up fencing for an object |
2876 | * @obj: object to map through a fence reg |
2876 | * @obj: object to map through a fence reg |
2877 | * |
2877 | * |
2878 | * When mapping objects through the GTT, userspace wants to be able to write |
2878 | * When mapping objects through the GTT, userspace wants to be able to write |
2879 | * to them without having to worry about swizzling if the object is tiled. |
2879 | * to them without having to worry about swizzling if the object is tiled. |
2880 | * This function walks the fence regs looking for a free one for @obj, |
2880 | * This function walks the fence regs looking for a free one for @obj, |
2881 | * stealing one if it can't find any. |
2881 | * stealing one if it can't find any. |
2882 | * |
2882 | * |
2883 | * It then sets up the reg based on the object's properties: address, pitch |
2883 | * It then sets up the reg based on the object's properties: address, pitch |
2884 | * and tiling format. |
2884 | * and tiling format. |
2885 | * |
2885 | * |
2886 | * For an untiled surface, this removes any existing fence. |
2886 | * For an untiled surface, this removes any existing fence. |
2887 | */ |
2887 | */ |
2888 | int |
2888 | int |
2889 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
2889 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
2890 | { |
2890 | { |
2891 | struct drm_device *dev = obj->base.dev; |
2891 | struct drm_device *dev = obj->base.dev; |
2892 | struct drm_i915_private *dev_priv = dev->dev_private; |
2892 | struct drm_i915_private *dev_priv = dev->dev_private; |
2893 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
2893 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
2894 | struct drm_i915_fence_reg *reg; |
2894 | struct drm_i915_fence_reg *reg; |
2895 | int ret; |
2895 | int ret; |
2896 | 2896 | ||
2897 | /* Have we updated the tiling parameters upon the object and so |
2897 | /* Have we updated the tiling parameters upon the object and so |
2898 | * will need to serialise the write to the associated fence register? |
2898 | * will need to serialise the write to the associated fence register? |
2899 | */ |
2899 | */ |
2900 | if (obj->fence_dirty) { |
2900 | if (obj->fence_dirty) { |
2901 | ret = i915_gem_object_wait_fence(obj); |
2901 | ret = i915_gem_object_wait_fence(obj); |
2902 | if (ret) |
2902 | if (ret) |
2903 | return ret; |
2903 | return ret; |
2904 | } |
2904 | } |
2905 | 2905 | ||
2906 | /* Just update our place in the LRU if our fence is getting reused. */ |
2906 | /* Just update our place in the LRU if our fence is getting reused. */ |
2907 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2907 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2908 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
2908 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
2909 | if (!obj->fence_dirty) { |
2909 | if (!obj->fence_dirty) { |
2910 | list_move_tail(®->lru_list, |
2910 | list_move_tail(®->lru_list, |
2911 | &dev_priv->mm.fence_list); |
2911 | &dev_priv->mm.fence_list); |
2912 | return 0; |
2912 | return 0; |
2913 | } |
2913 | } |
2914 | } else if (enable) { |
2914 | } else if (enable) { |
2915 | reg = i915_find_fence_reg(dev); |
2915 | reg = i915_find_fence_reg(dev); |
2916 | if (reg == NULL) |
2916 | if (reg == NULL) |
2917 | return -EDEADLK; |
2917 | return -EDEADLK; |
2918 | 2918 | ||
2919 | if (reg->obj) { |
2919 | if (reg->obj) { |
2920 | struct drm_i915_gem_object *old = reg->obj; |
2920 | struct drm_i915_gem_object *old = reg->obj; |
2921 | 2921 | ||
2922 | ret = i915_gem_object_wait_fence(old); |
2922 | ret = i915_gem_object_wait_fence(old); |
2923 | if (ret) |
2923 | if (ret) |
2924 | return ret; |
2924 | return ret; |
2925 | 2925 | ||
2926 | i915_gem_object_fence_lost(old); |
2926 | i915_gem_object_fence_lost(old); |
2927 | } |
2927 | } |
2928 | } else |
2928 | } else |
2929 | return 0; |
2929 | return 0; |
2930 | 2930 | ||
2931 | i915_gem_object_update_fence(obj, reg, enable); |
2931 | i915_gem_object_update_fence(obj, reg, enable); |
2932 | 2932 | ||
2933 | return 0; |
2933 | return 0; |
2934 | } |
2934 | } |
2935 | 2935 | ||
2936 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2936 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2937 | struct drm_mm_node *gtt_space, |
2937 | struct drm_mm_node *gtt_space, |
2938 | unsigned long cache_level) |
2938 | unsigned long cache_level) |
2939 | { |
2939 | { |
2940 | struct drm_mm_node *other; |
2940 | struct drm_mm_node *other; |
2941 | 2941 | ||
2942 | /* On non-LLC machines we have to be careful when putting differing |
2942 | /* On non-LLC machines we have to be careful when putting differing |
2943 | * types of snoopable memory together to avoid the prefetcher |
2943 | * types of snoopable memory together to avoid the prefetcher |
2944 | * crossing memory domains and dying. |
2944 | * crossing memory domains and dying. |
2945 | */ |
2945 | */ |
2946 | if (HAS_LLC(dev)) |
2946 | if (HAS_LLC(dev)) |
2947 | return true; |
2947 | return true; |
2948 | 2948 | ||
2949 | if (!drm_mm_node_allocated(gtt_space)) |
2949 | if (!drm_mm_node_allocated(gtt_space)) |
2950 | return true; |
2950 | return true; |
2951 | 2951 | ||
2952 | if (list_empty(>t_space->node_list)) |
2952 | if (list_empty(>t_space->node_list)) |
2953 | return true; |
2953 | return true; |
2954 | 2954 | ||
2955 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
2955 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
2956 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
2956 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
2957 | return false; |
2957 | return false; |
2958 | 2958 | ||
2959 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
2959 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
2960 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
2960 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
2961 | return false; |
2961 | return false; |
2962 | 2962 | ||
2963 | return true; |
2963 | return true; |
2964 | } |
2964 | } |
2965 | 2965 | ||
2966 | static void i915_gem_verify_gtt(struct drm_device *dev) |
2966 | static void i915_gem_verify_gtt(struct drm_device *dev) |
2967 | { |
2967 | { |
2968 | #if WATCH_GTT |
2968 | #if WATCH_GTT |
2969 | struct drm_i915_private *dev_priv = dev->dev_private; |
2969 | struct drm_i915_private *dev_priv = dev->dev_private; |
2970 | struct drm_i915_gem_object *obj; |
2970 | struct drm_i915_gem_object *obj; |
2971 | int err = 0; |
2971 | int err = 0; |
2972 | 2972 | ||
2973 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
2973 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
2974 | if (obj->gtt_space == NULL) { |
2974 | if (obj->gtt_space == NULL) { |
2975 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
2975 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
2976 | err++; |
2976 | err++; |
2977 | continue; |
2977 | continue; |
2978 | } |
2978 | } |
2979 | 2979 | ||
2980 | if (obj->cache_level != obj->gtt_space->color) { |
2980 | if (obj->cache_level != obj->gtt_space->color) { |
2981 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
2981 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
2982 | i915_gem_obj_ggtt_offset(obj), |
2982 | i915_gem_obj_ggtt_offset(obj), |
2983 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
2983 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
2984 | obj->cache_level, |
2984 | obj->cache_level, |
2985 | obj->gtt_space->color); |
2985 | obj->gtt_space->color); |
2986 | err++; |
2986 | err++; |
2987 | continue; |
2987 | continue; |
2988 | } |
2988 | } |
2989 | 2989 | ||
2990 | if (!i915_gem_valid_gtt_space(dev, |
2990 | if (!i915_gem_valid_gtt_space(dev, |
2991 | obj->gtt_space, |
2991 | obj->gtt_space, |
2992 | obj->cache_level)) { |
2992 | obj->cache_level)) { |
2993 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
2993 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
2994 | i915_gem_obj_ggtt_offset(obj), |
2994 | i915_gem_obj_ggtt_offset(obj), |
2995 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
2995 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
2996 | obj->cache_level); |
2996 | obj->cache_level); |
2997 | err++; |
2997 | err++; |
2998 | continue; |
2998 | continue; |
2999 | } |
2999 | } |
3000 | } |
3000 | } |
3001 | 3001 | ||
3002 | WARN_ON(err); |
3002 | WARN_ON(err); |
3003 | #endif |
3003 | #endif |
3004 | } |
3004 | } |
3005 | 3005 | ||
3006 | /** |
3006 | /** |
3007 | * Finds free space in the GTT aperture and binds the object there. |
3007 | * Finds free space in the GTT aperture and binds the object there. |
3008 | */ |
3008 | */ |
3009 | static int |
3009 | static int |
3010 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3010 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3011 | struct i915_address_space *vm, |
3011 | struct i915_address_space *vm, |
3012 | unsigned alignment, |
3012 | unsigned alignment, |
3013 | bool map_and_fenceable, |
3013 | bool map_and_fenceable, |
3014 | bool nonblocking) |
3014 | bool nonblocking) |
3015 | { |
3015 | { |
3016 | struct drm_device *dev = obj->base.dev; |
3016 | struct drm_device *dev = obj->base.dev; |
3017 | drm_i915_private_t *dev_priv = dev->dev_private; |
3017 | drm_i915_private_t *dev_priv = dev->dev_private; |
3018 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
3018 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
3019 | size_t gtt_max = |
3019 | size_t gtt_max = |
3020 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; |
3020 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; |
3021 | struct i915_vma *vma; |
3021 | struct i915_vma *vma; |
3022 | int ret; |
3022 | int ret; |
3023 | 3023 | ||
3024 | fence_size = i915_gem_get_gtt_size(dev, |
3024 | fence_size = i915_gem_get_gtt_size(dev, |
3025 | obj->base.size, |
3025 | obj->base.size, |
3026 | obj->tiling_mode); |
3026 | obj->tiling_mode); |
3027 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
3027 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
3028 | obj->base.size, |
3028 | obj->base.size, |
3029 | obj->tiling_mode, true); |
3029 | obj->tiling_mode, true); |
3030 | unfenced_alignment = |
3030 | unfenced_alignment = |
3031 | i915_gem_get_gtt_alignment(dev, |
3031 | i915_gem_get_gtt_alignment(dev, |
3032 | obj->base.size, |
3032 | obj->base.size, |
3033 | obj->tiling_mode, false); |
3033 | obj->tiling_mode, false); |
3034 | 3034 | ||
3035 | if (alignment == 0) |
3035 | if (alignment == 0) |
3036 | alignment = map_and_fenceable ? fence_alignment : |
3036 | alignment = map_and_fenceable ? fence_alignment : |
3037 | unfenced_alignment; |
3037 | unfenced_alignment; |
3038 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
3038 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
3039 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3039 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3040 | return -EINVAL; |
3040 | return -EINVAL; |
3041 | } |
3041 | } |
3042 | 3042 | ||
3043 | size = map_and_fenceable ? fence_size : obj->base.size; |
3043 | size = map_and_fenceable ? fence_size : obj->base.size; |
3044 | 3044 | ||
3045 | /* If the object is bigger than the entire aperture, reject it early |
3045 | /* If the object is bigger than the entire aperture, reject it early |
3046 | * before evicting everything in a vain attempt to find space. |
3046 | * before evicting everything in a vain attempt to find space. |
3047 | */ |
3047 | */ |
3048 | if (obj->base.size > gtt_max) { |
3048 | if (obj->base.size > gtt_max) { |
3049 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
3049 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
3050 | obj->base.size, |
3050 | obj->base.size, |
3051 | map_and_fenceable ? "mappable" : "total", |
3051 | map_and_fenceable ? "mappable" : "total", |
3052 | gtt_max); |
3052 | gtt_max); |
3053 | return -E2BIG; |
3053 | return -E2BIG; |
3054 | } |
3054 | } |
3055 | 3055 | ||
3056 | ret = i915_gem_object_get_pages(obj); |
3056 | ret = i915_gem_object_get_pages(obj); |
3057 | if (ret) |
3057 | if (ret) |
3058 | return ret; |
3058 | return ret; |
3059 | 3059 | ||
3060 | i915_gem_object_pin_pages(obj); |
3060 | i915_gem_object_pin_pages(obj); |
3061 | 3061 | ||
3062 | BUG_ON(!i915_is_ggtt(vm)); |
3062 | BUG_ON(!i915_is_ggtt(vm)); |
3063 | 3063 | ||
3064 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
3064 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
3065 | if (IS_ERR(vma)) { |
3065 | if (IS_ERR(vma)) { |
3066 | ret = PTR_ERR(vma); |
3066 | ret = PTR_ERR(vma); |
3067 | goto err_unpin; |
3067 | goto err_unpin; |
3068 | } |
3068 | } |
3069 | 3069 | ||
3070 | /* For now we only ever use 1 vma per object */ |
3070 | /* For now we only ever use 1 vma per object */ |
3071 | WARN_ON(!list_is_singular(&obj->vma_list)); |
3071 | WARN_ON(!list_is_singular(&obj->vma_list)); |
3072 | 3072 | ||
3073 | search_free: |
3073 | search_free: |
3074 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3074 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3075 | size, alignment, |
3075 | size, alignment, |
3076 | obj->cache_level, 0, gtt_max, |
3076 | obj->cache_level, 0, gtt_max, |
3077 | DRM_MM_SEARCH_DEFAULT); |
3077 | DRM_MM_SEARCH_DEFAULT); |
3078 | if (ret) { |
3078 | if (ret) { |
3079 | 3079 | ||
3080 | goto err_free_vma; |
3080 | goto err_free_vma; |
3081 | } |
3081 | } |
3082 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
3082 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
3083 | obj->cache_level))) { |
3083 | obj->cache_level))) { |
3084 | ret = -EINVAL; |
3084 | ret = -EINVAL; |
3085 | goto err_remove_node; |
3085 | goto err_remove_node; |
3086 | } |
3086 | } |
3087 | 3087 | ||
3088 | ret = i915_gem_gtt_prepare_object(obj); |
3088 | ret = i915_gem_gtt_prepare_object(obj); |
3089 | if (ret) |
3089 | if (ret) |
3090 | goto err_remove_node; |
3090 | goto err_remove_node; |
3091 | 3091 | ||
3092 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
3092 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
3093 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
3093 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
3094 | 3094 | ||
3095 | if (i915_is_ggtt(vm)) { |
3095 | if (i915_is_ggtt(vm)) { |
3096 | bool mappable, fenceable; |
3096 | bool mappable, fenceable; |
3097 | 3097 | ||
3098 | fenceable = (vma->node.size == fence_size && |
3098 | fenceable = (vma->node.size == fence_size && |
3099 | (vma->node.start & (fence_alignment - 1)) == 0); |
3099 | (vma->node.start & (fence_alignment - 1)) == 0); |
3100 | 3100 | ||
3101 | mappable = (vma->node.start + obj->base.size <= |
3101 | mappable = (vma->node.start + obj->base.size <= |
3102 | dev_priv->gtt.mappable_end); |
3102 | dev_priv->gtt.mappable_end); |
3103 | 3103 | ||
3104 | obj->map_and_fenceable = mappable && fenceable; |
3104 | obj->map_and_fenceable = mappable && fenceable; |
3105 | } |
3105 | } |
3106 | 3106 | ||
3107 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
3107 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
3108 | 3108 | ||
3109 | trace_i915_vma_bind(vma, map_and_fenceable); |
3109 | trace_i915_vma_bind(vma, map_and_fenceable); |
3110 | i915_gem_verify_gtt(dev); |
3110 | i915_gem_verify_gtt(dev); |
3111 | return 0; |
3111 | return 0; |
3112 | 3112 | ||
3113 | err_remove_node: |
3113 | err_remove_node: |
3114 | drm_mm_remove_node(&vma->node); |
3114 | drm_mm_remove_node(&vma->node); |
3115 | err_free_vma: |
3115 | err_free_vma: |
3116 | i915_gem_vma_destroy(vma); |
3116 | i915_gem_vma_destroy(vma); |
3117 | err_unpin: |
3117 | err_unpin: |
3118 | i915_gem_object_unpin_pages(obj); |
3118 | i915_gem_object_unpin_pages(obj); |
3119 | return ret; |
3119 | return ret; |
3120 | } |
3120 | } |
3121 | 3121 | ||
3122 | bool |
3122 | bool |
3123 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3123 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3124 | bool force) |
3124 | bool force) |
3125 | { |
3125 | { |
3126 | /* If we don't have a page list set up, then we're not pinned |
3126 | /* If we don't have a page list set up, then we're not pinned |
3127 | * to GPU, and we can ignore the cache flush because it'll happen |
3127 | * to GPU, and we can ignore the cache flush because it'll happen |
3128 | * again at bind time. |
3128 | * again at bind time. |
3129 | */ |
3129 | */ |
3130 | if (obj->pages == NULL) |
3130 | if (obj->pages == NULL) |
3131 | return false; |
3131 | return false; |
3132 | 3132 | ||
3133 | /* |
3133 | /* |
3134 | * Stolen memory is always coherent with the GPU as it is explicitly |
3134 | * Stolen memory is always coherent with the GPU as it is explicitly |
3135 | * marked as wc by the system, or the system is cache-coherent. |
3135 | * marked as wc by the system, or the system is cache-coherent. |
3136 | */ |
3136 | */ |
3137 | if (obj->stolen) |
3137 | if (obj->stolen) |
3138 | return false; |
3138 | return false; |
3139 | 3139 | ||
3140 | /* If the GPU is snooping the contents of the CPU cache, |
3140 | /* If the GPU is snooping the contents of the CPU cache, |
3141 | * we do not need to manually clear the CPU cache lines. However, |
3141 | * we do not need to manually clear the CPU cache lines. However, |
3142 | * the caches are only snooped when the render cache is |
3142 | * the caches are only snooped when the render cache is |
3143 | * flushed/invalidated. As we always have to emit invalidations |
3143 | * flushed/invalidated. As we always have to emit invalidations |
3144 | * and flushes when moving into and out of the RENDER domain, correct |
3144 | * and flushes when moving into and out of the RENDER domain, correct |
3145 | * snooping behaviour occurs naturally as the result of our domain |
3145 | * snooping behaviour occurs naturally as the result of our domain |
3146 | * tracking. |
3146 | * tracking. |
3147 | */ |
3147 | */ |
3148 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
3148 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
3149 | return false; |
3149 | return false; |
3150 | 3150 | ||
3151 | trace_i915_gem_object_clflush(obj); |
3151 | trace_i915_gem_object_clflush(obj); |
3152 | drm_clflush_sg(obj->pages); |
3152 | drm_clflush_sg(obj->pages); |
3153 | 3153 | ||
3154 | return true; |
3154 | return true; |
3155 | } |
3155 | } |
3156 | 3156 | ||
3157 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3157 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3158 | static void |
3158 | static void |
3159 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
3159 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
3160 | { |
3160 | { |
3161 | uint32_t old_write_domain; |
3161 | uint32_t old_write_domain; |
3162 | 3162 | ||
3163 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
3163 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
3164 | return; |
3164 | return; |
3165 | 3165 | ||
3166 | /* No actual flushing is required for the GTT write domain. Writes |
3166 | /* No actual flushing is required for the GTT write domain. Writes |
3167 | * to it immediately go to main memory as far as we know, so there's |
3167 | * to it immediately go to main memory as far as we know, so there's |
3168 | * no chipset flush. It also doesn't land in render cache. |
3168 | * no chipset flush. It also doesn't land in render cache. |
3169 | * |
3169 | * |
3170 | * However, we do have to enforce the order so that all writes through |
3170 | * However, we do have to enforce the order so that all writes through |
3171 | * the GTT land before any writes to the device, such as updates to |
3171 | * the GTT land before any writes to the device, such as updates to |
3172 | * the GATT itself. |
3172 | * the GATT itself. |
3173 | */ |
3173 | */ |
3174 | wmb(); |
3174 | wmb(); |
3175 | 3175 | ||
3176 | old_write_domain = obj->base.write_domain; |
3176 | old_write_domain = obj->base.write_domain; |
3177 | obj->base.write_domain = 0; |
3177 | obj->base.write_domain = 0; |
3178 | 3178 | ||
3179 | trace_i915_gem_object_change_domain(obj, |
3179 | trace_i915_gem_object_change_domain(obj, |
3180 | obj->base.read_domains, |
3180 | obj->base.read_domains, |
3181 | old_write_domain); |
3181 | old_write_domain); |
3182 | } |
3182 | } |
3183 | 3183 | ||
3184 | /** Flushes the CPU write domain for the object if it's dirty. */ |
3184 | /** Flushes the CPU write domain for the object if it's dirty. */ |
3185 | static void |
3185 | static void |
3186 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3186 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3187 | bool force) |
3187 | bool force) |
3188 | { |
3188 | { |
3189 | uint32_t old_write_domain; |
3189 | uint32_t old_write_domain; |
3190 | 3190 | ||
3191 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
3191 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
3192 | return; |
3192 | return; |
3193 | 3193 | ||
3194 | if (i915_gem_clflush_object(obj, force)) |
3194 | if (i915_gem_clflush_object(obj, force)) |
3195 | i915_gem_chipset_flush(obj->base.dev); |
3195 | i915_gem_chipset_flush(obj->base.dev); |
3196 | 3196 | ||
3197 | old_write_domain = obj->base.write_domain; |
3197 | old_write_domain = obj->base.write_domain; |
3198 | obj->base.write_domain = 0; |
3198 | obj->base.write_domain = 0; |
3199 | 3199 | ||
3200 | trace_i915_gem_object_change_domain(obj, |
3200 | trace_i915_gem_object_change_domain(obj, |
3201 | obj->base.read_domains, |
3201 | obj->base.read_domains, |
3202 | old_write_domain); |
3202 | old_write_domain); |
3203 | } |
3203 | } |
3204 | 3204 | ||
3205 | /** |
3205 | /** |
3206 | * Moves a single object to the GTT read, and possibly write domain. |
3206 | * Moves a single object to the GTT read, and possibly write domain. |
3207 | * |
3207 | * |
3208 | * This function returns when the move is complete, including waiting on |
3208 | * This function returns when the move is complete, including waiting on |
3209 | * flushes to occur. |
3209 | * flushes to occur. |
3210 | */ |
3210 | */ |
3211 | int |
3211 | int |
3212 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
3212 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
3213 | { |
3213 | { |
3214 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
3214 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
3215 | uint32_t old_write_domain, old_read_domains; |
3215 | uint32_t old_write_domain, old_read_domains; |
3216 | int ret; |
3216 | int ret; |
3217 | 3217 | ||
3218 | /* Not valid to be called on unbound objects. */ |
3218 | /* Not valid to be called on unbound objects. */ |
3219 | if (!i915_gem_obj_bound_any(obj)) |
3219 | if (!i915_gem_obj_bound_any(obj)) |
3220 | return -EINVAL; |
3220 | return -EINVAL; |
3221 | 3221 | ||
3222 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3222 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3223 | return 0; |
3223 | return 0; |
3224 | 3224 | ||
3225 | ret = i915_gem_object_wait_rendering(obj, !write); |
3225 | ret = i915_gem_object_wait_rendering(obj, !write); |
3226 | if (ret) |
3226 | if (ret) |
3227 | return ret; |
3227 | return ret; |
3228 | 3228 | ||
3229 | i915_gem_object_flush_cpu_write_domain(obj, false); |
3229 | i915_gem_object_flush_cpu_write_domain(obj, false); |
3230 | 3230 | ||
3231 | /* Serialise direct access to this object with the barriers for |
3231 | /* Serialise direct access to this object with the barriers for |
3232 | * coherent writes from the GPU, by effectively invalidating the |
3232 | * coherent writes from the GPU, by effectively invalidating the |
3233 | * GTT domain upon first access. |
3233 | * GTT domain upon first access. |
3234 | */ |
3234 | */ |
3235 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3235 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3236 | mb(); |
3236 | mb(); |
3237 | 3237 | ||
3238 | old_write_domain = obj->base.write_domain; |
3238 | old_write_domain = obj->base.write_domain; |
3239 | old_read_domains = obj->base.read_domains; |
3239 | old_read_domains = obj->base.read_domains; |
3240 | 3240 | ||
3241 | /* It should now be out of any other write domains, and we can update |
3241 | /* It should now be out of any other write domains, and we can update |
3242 | * the domain values for our changes. |
3242 | * the domain values for our changes. |
3243 | */ |
3243 | */ |
3244 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3244 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3245 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3245 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3246 | if (write) { |
3246 | if (write) { |
3247 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3247 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3248 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
3248 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
3249 | obj->dirty = 1; |
3249 | obj->dirty = 1; |
3250 | } |
3250 | } |
3251 | 3251 | ||
3252 | trace_i915_gem_object_change_domain(obj, |
3252 | trace_i915_gem_object_change_domain(obj, |
3253 | old_read_domains, |
3253 | old_read_domains, |
3254 | old_write_domain); |
3254 | old_write_domain); |
3255 | 3255 | ||
3256 | /* And bump the LRU for this access */ |
3256 | /* And bump the LRU for this access */ |
3257 | if (i915_gem_object_is_inactive(obj)) { |
3257 | if (i915_gem_object_is_inactive(obj)) { |
3258 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
3258 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
3259 | &dev_priv->gtt.base); |
3259 | &dev_priv->gtt.base); |
3260 | if (vma) |
3260 | if (vma) |
3261 | list_move_tail(&vma->mm_list, |
3261 | list_move_tail(&vma->mm_list, |
3262 | &dev_priv->gtt.base.inactive_list); |
3262 | &dev_priv->gtt.base.inactive_list); |
3263 | 3263 | ||
3264 | } |
3264 | } |
3265 | 3265 | ||
3266 | return 0; |
3266 | return 0; |
3267 | } |
3267 | } |
3268 | 3268 | ||
3269 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3269 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3270 | enum i915_cache_level cache_level) |
3270 | enum i915_cache_level cache_level) |
3271 | { |
3271 | { |
3272 | struct drm_device *dev = obj->base.dev; |
3272 | struct drm_device *dev = obj->base.dev; |
3273 | drm_i915_private_t *dev_priv = dev->dev_private; |
3273 | drm_i915_private_t *dev_priv = dev->dev_private; |
3274 | struct i915_vma *vma; |
3274 | struct i915_vma *vma; |
3275 | int ret; |
3275 | int ret; |
3276 | 3276 | ||
3277 | if (obj->cache_level == cache_level) |
3277 | if (obj->cache_level == cache_level) |
3278 | return 0; |
3278 | return 0; |
3279 | 3279 | ||
3280 | if (obj->pin_count) { |
3280 | if (obj->pin_count) { |
3281 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3281 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3282 | return -EBUSY; |
3282 | return -EBUSY; |
3283 | } |
3283 | } |
3284 | 3284 | ||
3285 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3285 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3286 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
3286 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
3287 | ret = i915_vma_unbind(vma); |
3287 | ret = i915_vma_unbind(vma); |
3288 | if (ret) |
3288 | if (ret) |
3289 | return ret; |
3289 | return ret; |
3290 | 3290 | ||
3291 | break; |
3291 | break; |
3292 | } |
3292 | } |
3293 | } |
3293 | } |
3294 | 3294 | ||
3295 | if (i915_gem_obj_bound_any(obj)) { |
3295 | if (i915_gem_obj_bound_any(obj)) { |
3296 | ret = i915_gem_object_finish_gpu(obj); |
3296 | ret = i915_gem_object_finish_gpu(obj); |
3297 | if (ret) |
3297 | if (ret) |
3298 | return ret; |
3298 | return ret; |
3299 | 3299 | ||
3300 | i915_gem_object_finish_gtt(obj); |
3300 | i915_gem_object_finish_gtt(obj); |
3301 | 3301 | ||
3302 | /* Before SandyBridge, you could not use tiling or fence |
3302 | /* Before SandyBridge, you could not use tiling or fence |
3303 | * registers with snooped memory, so relinquish any fences |
3303 | * registers with snooped memory, so relinquish any fences |
3304 | * currently pointing to our region in the aperture. |
3304 | * currently pointing to our region in the aperture. |
3305 | */ |
3305 | */ |
3306 | if (INTEL_INFO(dev)->gen < 6) { |
3306 | if (INTEL_INFO(dev)->gen < 6) { |
3307 | ret = i915_gem_object_put_fence(obj); |
3307 | ret = i915_gem_object_put_fence(obj); |
3308 | if (ret) |
3308 | if (ret) |
3309 | return ret; |
3309 | return ret; |
3310 | } |
3310 | } |
3311 | 3311 | ||
3312 | if (obj->has_global_gtt_mapping) |
3312 | if (obj->has_global_gtt_mapping) |
3313 | i915_gem_gtt_bind_object(obj, cache_level); |
3313 | i915_gem_gtt_bind_object(obj, cache_level); |
3314 | if (obj->has_aliasing_ppgtt_mapping) |
3314 | if (obj->has_aliasing_ppgtt_mapping) |
3315 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
3315 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
3316 | obj, cache_level); |
3316 | obj, cache_level); |
3317 | } |
3317 | } |
3318 | 3318 | ||
3319 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3319 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3320 | vma->node.color = cache_level; |
3320 | vma->node.color = cache_level; |
3321 | obj->cache_level = cache_level; |
3321 | obj->cache_level = cache_level; |
3322 | 3322 | ||
3323 | if (cpu_write_needs_clflush(obj)) { |
3323 | if (cpu_write_needs_clflush(obj)) { |
3324 | u32 old_read_domains, old_write_domain; |
3324 | u32 old_read_domains, old_write_domain; |
3325 | 3325 | ||
3326 | /* If we're coming from LLC cached, then we haven't |
3326 | /* If we're coming from LLC cached, then we haven't |
3327 | * actually been tracking whether the data is in the |
3327 | * actually been tracking whether the data is in the |
3328 | * CPU cache or not, since we only allow one bit set |
3328 | * CPU cache or not, since we only allow one bit set |
3329 | * in obj->write_domain and have been skipping the clflushes. |
3329 | * in obj->write_domain and have been skipping the clflushes. |
3330 | * Just set it to the CPU cache for now. |
3330 | * Just set it to the CPU cache for now. |
3331 | */ |
3331 | */ |
3332 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
3332 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
3333 | 3333 | ||
3334 | old_read_domains = obj->base.read_domains; |
3334 | old_read_domains = obj->base.read_domains; |
3335 | old_write_domain = obj->base.write_domain; |
3335 | old_write_domain = obj->base.write_domain; |
3336 | 3336 | ||
3337 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3337 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3338 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3338 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3339 | 3339 | ||
3340 | trace_i915_gem_object_change_domain(obj, |
3340 | trace_i915_gem_object_change_domain(obj, |
3341 | old_read_domains, |
3341 | old_read_domains, |
3342 | old_write_domain); |
3342 | old_write_domain); |
3343 | } |
3343 | } |
3344 | 3344 | ||
3345 | i915_gem_verify_gtt(dev); |
3345 | i915_gem_verify_gtt(dev); |
3346 | return 0; |
3346 | return 0; |
3347 | } |
3347 | } |
3348 | 3348 | ||
3349 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3349 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3350 | struct drm_file *file) |
3350 | struct drm_file *file) |
3351 | { |
3351 | { |
3352 | struct drm_i915_gem_caching *args = data; |
3352 | struct drm_i915_gem_caching *args = data; |
3353 | struct drm_i915_gem_object *obj; |
3353 | struct drm_i915_gem_object *obj; |
3354 | int ret; |
3354 | int ret; |
3355 | 3355 | ||
3356 | if(args->handle == -2) |
3356 | if(args->handle == -2) |
3357 | { |
3357 | { |
3358 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
3358 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
3359 | return 0; |
3359 | return 0; |
3360 | } |
3360 | } |
3361 | 3361 | ||
3362 | ret = i915_mutex_lock_interruptible(dev); |
3362 | ret = i915_mutex_lock_interruptible(dev); |
3363 | if (ret) |
3363 | if (ret) |
3364 | return ret; |
3364 | return ret; |
3365 | 3365 | ||
3366 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3366 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3367 | if (&obj->base == NULL) { |
3367 | if (&obj->base == NULL) { |
3368 | ret = -ENOENT; |
3368 | ret = -ENOENT; |
3369 | goto unlock; |
3369 | goto unlock; |
3370 | } |
3370 | } |
3371 | 3371 | ||
3372 | switch (obj->cache_level) { |
3372 | switch (obj->cache_level) { |
3373 | case I915_CACHE_LLC: |
3373 | case I915_CACHE_LLC: |
3374 | case I915_CACHE_L3_LLC: |
3374 | case I915_CACHE_L3_LLC: |
3375 | args->caching = I915_CACHING_CACHED; |
3375 | args->caching = I915_CACHING_CACHED; |
3376 | break; |
3376 | break; |
3377 | 3377 | ||
3378 | case I915_CACHE_WT: |
3378 | case I915_CACHE_WT: |
3379 | args->caching = I915_CACHING_DISPLAY; |
3379 | args->caching = I915_CACHING_DISPLAY; |
3380 | break; |
3380 | break; |
3381 | 3381 | ||
3382 | default: |
3382 | default: |
3383 | args->caching = I915_CACHING_NONE; |
3383 | args->caching = I915_CACHING_NONE; |
3384 | break; |
3384 | break; |
3385 | } |
3385 | } |
3386 | 3386 | ||
3387 | drm_gem_object_unreference(&obj->base); |
3387 | drm_gem_object_unreference(&obj->base); |
3388 | unlock: |
3388 | unlock: |
3389 | mutex_unlock(&dev->struct_mutex); |
3389 | mutex_unlock(&dev->struct_mutex); |
3390 | return ret; |
3390 | return ret; |
3391 | } |
3391 | } |
3392 | 3392 | ||
3393 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3393 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3394 | struct drm_file *file) |
3394 | struct drm_file *file) |
3395 | { |
3395 | { |
3396 | struct drm_i915_gem_caching *args = data; |
3396 | struct drm_i915_gem_caching *args = data; |
3397 | struct drm_i915_gem_object *obj; |
3397 | struct drm_i915_gem_object *obj; |
3398 | enum i915_cache_level level; |
3398 | enum i915_cache_level level; |
3399 | int ret; |
3399 | int ret; |
3400 | 3400 | ||
3401 | if(args->handle == -2) |
3401 | if(args->handle == -2) |
3402 | { |
3402 | { |
3403 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
3403 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
3404 | return 0; |
3404 | return 0; |
3405 | } |
3405 | } |
3406 | 3406 | ||
3407 | switch (args->caching) { |
3407 | switch (args->caching) { |
3408 | case I915_CACHING_NONE: |
3408 | case I915_CACHING_NONE: |
3409 | level = I915_CACHE_NONE; |
3409 | level = I915_CACHE_NONE; |
3410 | break; |
3410 | break; |
3411 | case I915_CACHING_CACHED: |
3411 | case I915_CACHING_CACHED: |
3412 | level = I915_CACHE_LLC; |
3412 | level = I915_CACHE_LLC; |
3413 | break; |
3413 | break; |
3414 | case I915_CACHING_DISPLAY: |
3414 | case I915_CACHING_DISPLAY: |
3415 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
3415 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
3416 | break; |
3416 | break; |
3417 | default: |
3417 | default: |
3418 | return -EINVAL; |
3418 | return -EINVAL; |
3419 | } |
3419 | } |
3420 | 3420 | ||
3421 | ret = i915_mutex_lock_interruptible(dev); |
3421 | ret = i915_mutex_lock_interruptible(dev); |
3422 | if (ret) |
3422 | if (ret) |
3423 | return ret; |
3423 | return ret; |
3424 | 3424 | ||
3425 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3425 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3426 | if (&obj->base == NULL) { |
3426 | if (&obj->base == NULL) { |
3427 | ret = -ENOENT; |
3427 | ret = -ENOENT; |
3428 | goto unlock; |
3428 | goto unlock; |
3429 | } |
3429 | } |
3430 | 3430 | ||
3431 | ret = i915_gem_object_set_cache_level(obj, level); |
3431 | ret = i915_gem_object_set_cache_level(obj, level); |
3432 | 3432 | ||
3433 | drm_gem_object_unreference(&obj->base); |
3433 | drm_gem_object_unreference(&obj->base); |
3434 | unlock: |
3434 | unlock: |
3435 | mutex_unlock(&dev->struct_mutex); |
3435 | mutex_unlock(&dev->struct_mutex); |
3436 | return ret; |
3436 | return ret; |
3437 | } |
3437 | } |
3438 | 3438 | ||
3439 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3439 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3440 | { |
3440 | { |
3441 | /* There are 3 sources that pin objects: |
3441 | /* There are 3 sources that pin objects: |
3442 | * 1. The display engine (scanouts, sprites, cursors); |
3442 | * 1. The display engine (scanouts, sprites, cursors); |
3443 | * 2. Reservations for execbuffer; |
3443 | * 2. Reservations for execbuffer; |
3444 | * 3. The user. |
3444 | * 3. The user. |
3445 | * |
3445 | * |
3446 | * We can ignore reservations as we hold the struct_mutex and |
3446 | * We can ignore reservations as we hold the struct_mutex and |
3447 | * are only called outside of the reservation path. The user |
3447 | * are only called outside of the reservation path. The user |
3448 | * can only increment pin_count once, and so if after |
3448 | * can only increment pin_count once, and so if after |
3449 | * subtracting the potential reference by the user, any pin_count |
3449 | * subtracting the potential reference by the user, any pin_count |
3450 | * remains, it must be due to another use by the display engine. |
3450 | * remains, it must be due to another use by the display engine. |
3451 | */ |
3451 | */ |
3452 | return obj->pin_count - !!obj->user_pin_count; |
3452 | return obj->pin_count - !!obj->user_pin_count; |
3453 | } |
3453 | } |
3454 | 3454 | ||
3455 | /* |
3455 | /* |
3456 | * Prepare buffer for display plane (scanout, cursors, etc). |
3456 | * Prepare buffer for display plane (scanout, cursors, etc). |
3457 | * Can be called from an uninterruptible phase (modesetting) and allows |
3457 | * Can be called from an uninterruptible phase (modesetting) and allows |
3458 | * any flushes to be pipelined (for pageflips). |
3458 | * any flushes to be pipelined (for pageflips). |
3459 | */ |
3459 | */ |
3460 | int |
3460 | int |
3461 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3461 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3462 | u32 alignment, |
3462 | u32 alignment, |
3463 | struct intel_ring_buffer *pipelined) |
3463 | struct intel_ring_buffer *pipelined) |
3464 | { |
3464 | { |
3465 | u32 old_read_domains, old_write_domain; |
3465 | u32 old_read_domains, old_write_domain; |
3466 | int ret; |
3466 | int ret; |
3467 | 3467 | ||
3468 | if (pipelined != obj->ring) { |
3468 | if (pipelined != obj->ring) { |
3469 | ret = i915_gem_object_sync(obj, pipelined); |
3469 | ret = i915_gem_object_sync(obj, pipelined); |
3470 | if (ret) |
3470 | if (ret) |
3471 | return ret; |
3471 | return ret; |
3472 | } |
3472 | } |
3473 | 3473 | ||
3474 | /* Mark the pin_display early so that we account for the |
3474 | /* Mark the pin_display early so that we account for the |
3475 | * display coherency whilst setting up the cache domains. |
3475 | * display coherency whilst setting up the cache domains. |
3476 | */ |
3476 | */ |
3477 | obj->pin_display = true; |
3477 | obj->pin_display = true; |
3478 | 3478 | ||
3479 | /* The display engine is not coherent with the LLC cache on gen6. As |
3479 | /* The display engine is not coherent with the LLC cache on gen6. As |
3480 | * a result, we make sure that the pinning that is about to occur is |
3480 | * a result, we make sure that the pinning that is about to occur is |
3481 | * done with uncached PTEs. This is lowest common denominator for all |
3481 | * done with uncached PTEs. This is lowest common denominator for all |
3482 | * chipsets. |
3482 | * chipsets. |
3483 | * |
3483 | * |
3484 | * However for gen6+, we could do better by using the GFDT bit instead |
3484 | * However for gen6+, we could do better by using the GFDT bit instead |
3485 | * of uncaching, which would allow us to flush all the LLC-cached data |
3485 | * of uncaching, which would allow us to flush all the LLC-cached data |
3486 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
3486 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
3487 | */ |
3487 | */ |
3488 | ret = i915_gem_object_set_cache_level(obj, |
3488 | ret = i915_gem_object_set_cache_level(obj, |
3489 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
3489 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
3490 | if (ret) |
3490 | if (ret) |
3491 | goto err_unpin_display; |
3491 | goto err_unpin_display; |
3492 | 3492 | ||
3493 | /* As the user may map the buffer once pinned in the display plane |
3493 | /* As the user may map the buffer once pinned in the display plane |
3494 | * (e.g. libkms for the bootup splash), we have to ensure that we |
3494 | * (e.g. libkms for the bootup splash), we have to ensure that we |
3495 | * always use map_and_fenceable for all scanout buffers. |
3495 | * always use map_and_fenceable for all scanout buffers. |
3496 | */ |
3496 | */ |
3497 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
3497 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
3498 | if (ret) |
3498 | if (ret) |
3499 | goto err_unpin_display; |
3499 | goto err_unpin_display; |
3500 | 3500 | ||
3501 | i915_gem_object_flush_cpu_write_domain(obj, true); |
3501 | i915_gem_object_flush_cpu_write_domain(obj, true); |
3502 | 3502 | ||
3503 | old_write_domain = obj->base.write_domain; |
3503 | old_write_domain = obj->base.write_domain; |
3504 | old_read_domains = obj->base.read_domains; |
3504 | old_read_domains = obj->base.read_domains; |
3505 | 3505 | ||
3506 | /* It should now be out of any other write domains, and we can update |
3506 | /* It should now be out of any other write domains, and we can update |
3507 | * the domain values for our changes. |
3507 | * the domain values for our changes. |
3508 | */ |
3508 | */ |
3509 | obj->base.write_domain = 0; |
3509 | obj->base.write_domain = 0; |
3510 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3510 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3511 | 3511 | ||
3512 | trace_i915_gem_object_change_domain(obj, |
3512 | trace_i915_gem_object_change_domain(obj, |
3513 | old_read_domains, |
3513 | old_read_domains, |
3514 | old_write_domain); |
3514 | old_write_domain); |
3515 | 3515 | ||
3516 | return 0; |
3516 | return 0; |
3517 | 3517 | ||
3518 | err_unpin_display: |
3518 | err_unpin_display: |
3519 | obj->pin_display = is_pin_display(obj); |
3519 | obj->pin_display = is_pin_display(obj); |
3520 | return ret; |
3520 | return ret; |
3521 | } |
3521 | } |
3522 | 3522 | ||
3523 | void |
3523 | void |
3524 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
3524 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
3525 | { |
3525 | { |
3526 | i915_gem_object_unpin(obj); |
3526 | i915_gem_object_unpin(obj); |
3527 | obj->pin_display = is_pin_display(obj); |
3527 | obj->pin_display = is_pin_display(obj); |
3528 | } |
3528 | } |
3529 | 3529 | ||
3530 | int |
3530 | int |
3531 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
3531 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
3532 | { |
3532 | { |
3533 | int ret; |
3533 | int ret; |
3534 | 3534 | ||
3535 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
3535 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
3536 | return 0; |
3536 | return 0; |
3537 | 3537 | ||
3538 | ret = i915_gem_object_wait_rendering(obj, false); |
3538 | ret = i915_gem_object_wait_rendering(obj, false); |
3539 | if (ret) |
3539 | if (ret) |
3540 | return ret; |
3540 | return ret; |
3541 | 3541 | ||
3542 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3542 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3543 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
3543 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
3544 | return 0; |
3544 | return 0; |
3545 | } |
3545 | } |
3546 | 3546 | ||
3547 | /** |
3547 | /** |
3548 | * Moves a single object to the CPU read, and possibly write domain. |
3548 | * Moves a single object to the CPU read, and possibly write domain. |
3549 | * |
3549 | * |
3550 | * This function returns when the move is complete, including waiting on |
3550 | * This function returns when the move is complete, including waiting on |
3551 | * flushes to occur. |
3551 | * flushes to occur. |
3552 | */ |
3552 | */ |
3553 | int |
3553 | int |
3554 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
3554 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
3555 | { |
3555 | { |
3556 | uint32_t old_write_domain, old_read_domains; |
3556 | uint32_t old_write_domain, old_read_domains; |
3557 | int ret; |
3557 | int ret; |
3558 | 3558 | ||
3559 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3559 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3560 | return 0; |
3560 | return 0; |
3561 | 3561 | ||
3562 | ret = i915_gem_object_wait_rendering(obj, !write); |
3562 | ret = i915_gem_object_wait_rendering(obj, !write); |
3563 | if (ret) |
3563 | if (ret) |
3564 | return ret; |
3564 | return ret; |
3565 | 3565 | ||
3566 | i915_gem_object_flush_gtt_write_domain(obj); |
3566 | i915_gem_object_flush_gtt_write_domain(obj); |
3567 | 3567 | ||
3568 | old_write_domain = obj->base.write_domain; |
3568 | old_write_domain = obj->base.write_domain; |
3569 | old_read_domains = obj->base.read_domains; |
3569 | old_read_domains = obj->base.read_domains; |
3570 | 3570 | ||
3571 | /* Flush the CPU cache if it's still invalid. */ |
3571 | /* Flush the CPU cache if it's still invalid. */ |
3572 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
3572 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
3573 | i915_gem_clflush_object(obj, false); |
3573 | i915_gem_clflush_object(obj, false); |
3574 | 3574 | ||
3575 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
3575 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
3576 | } |
3576 | } |
3577 | 3577 | ||
3578 | /* It should now be out of any other write domains, and we can update |
3578 | /* It should now be out of any other write domains, and we can update |
3579 | * the domain values for our changes. |
3579 | * the domain values for our changes. |
3580 | */ |
3580 | */ |
3581 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3581 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3582 | 3582 | ||
3583 | /* If we're writing through the CPU, then the GPU read domains will |
3583 | /* If we're writing through the CPU, then the GPU read domains will |
3584 | * need to be invalidated at next use. |
3584 | * need to be invalidated at next use. |
3585 | */ |
3585 | */ |
3586 | if (write) { |
3586 | if (write) { |
3587 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3587 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3588 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3588 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3589 | } |
3589 | } |
3590 | 3590 | ||
3591 | trace_i915_gem_object_change_domain(obj, |
3591 | trace_i915_gem_object_change_domain(obj, |
3592 | old_read_domains, |
3592 | old_read_domains, |
3593 | old_write_domain); |
3593 | old_write_domain); |
3594 | 3594 | ||
3595 | return 0; |
3595 | return 0; |
3596 | } |
3596 | } |
3597 | 3597 | ||
3598 | /* Throttle our rendering by waiting until the ring has completed our requests |
3598 | /* Throttle our rendering by waiting until the ring has completed our requests |
3599 | * emitted over 20 msec ago. |
3599 | * emitted over 20 msec ago. |
3600 | * |
3600 | * |
3601 | * Note that if we were to use the current jiffies each time around the loop, |
3601 | * Note that if we were to use the current jiffies each time around the loop, |
3602 | * we wouldn't escape the function with any frames outstanding if the time to |
3602 | * we wouldn't escape the function with any frames outstanding if the time to |
3603 | * render a frame was over 20ms. |
3603 | * render a frame was over 20ms. |
3604 | * |
3604 | * |
3605 | * This should get us reasonable parallelism between CPU and GPU but also |
3605 | * This should get us reasonable parallelism between CPU and GPU but also |
3606 | * relatively low latency when blocking on a particular request to finish. |
3606 | * relatively low latency when blocking on a particular request to finish. |
3607 | */ |
3607 | */ |
3608 | static int |
3608 | static int |
3609 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
3609 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
3610 | { |
3610 | { |
3611 | struct drm_i915_private *dev_priv = dev->dev_private; |
3611 | struct drm_i915_private *dev_priv = dev->dev_private; |
3612 | struct drm_i915_file_private *file_priv = file->driver_priv; |
3612 | struct drm_i915_file_private *file_priv = file->driver_priv; |
3613 | unsigned long recent_enough = GetTimerTicks() - msecs_to_jiffies(20); |
3613 | unsigned long recent_enough = GetTimerTicks() - msecs_to_jiffies(20); |
3614 | struct drm_i915_gem_request *request; |
3614 | struct drm_i915_gem_request *request; |
3615 | struct intel_ring_buffer *ring = NULL; |
3615 | struct intel_ring_buffer *ring = NULL; |
3616 | unsigned reset_counter; |
3616 | unsigned reset_counter; |
3617 | u32 seqno = 0; |
3617 | u32 seqno = 0; |
3618 | int ret; |
3618 | int ret; |
3619 | 3619 | ||
3620 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3620 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3621 | if (ret) |
3621 | if (ret) |
3622 | return ret; |
3622 | return ret; |
3623 | 3623 | ||
3624 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
3624 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
3625 | if (ret) |
3625 | if (ret) |
3626 | return ret; |
3626 | return ret; |
3627 | 3627 | ||
3628 | spin_lock(&file_priv->mm.lock); |
3628 | spin_lock(&file_priv->mm.lock); |
3629 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
3629 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
3630 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3630 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3631 | break; |
3631 | break; |
3632 | 3632 | ||
3633 | ring = request->ring; |
3633 | ring = request->ring; |
3634 | seqno = request->seqno; |
3634 | seqno = request->seqno; |
3635 | } |
3635 | } |
3636 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3636 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3637 | spin_unlock(&file_priv->mm.lock); |
3637 | spin_unlock(&file_priv->mm.lock); |
3638 | 3638 | ||
3639 | if (seqno == 0) |
3639 | if (seqno == 0) |
3640 | return 0; |
3640 | return 0; |
3641 | 3641 | ||
3642 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3642 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3643 | if (ret == 0) |
3643 | if (ret == 0) |
3644 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
3644 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
3645 | 3645 | ||
3646 | return ret; |
3646 | return ret; |
3647 | } |
3647 | } |
3648 | 3648 | ||
3649 | int |
3649 | int |
3650 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3650 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3651 | struct i915_address_space *vm, |
3651 | struct i915_address_space *vm, |
3652 | uint32_t alignment, |
3652 | uint32_t alignment, |
3653 | bool map_and_fenceable, |
3653 | bool map_and_fenceable, |
3654 | bool nonblocking) |
3654 | bool nonblocking) |
3655 | { |
3655 | { |
3656 | struct i915_vma *vma; |
3656 | struct i915_vma *vma; |
3657 | int ret; |
3657 | int ret; |
3658 | 3658 | ||
3659 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3659 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3660 | return -EBUSY; |
3660 | return -EBUSY; |
3661 | 3661 | ||
3662 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3662 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3663 | 3663 | ||
3664 | vma = i915_gem_obj_to_vma(obj, vm); |
3664 | vma = i915_gem_obj_to_vma(obj, vm); |
3665 | 3665 | ||
3666 | if (vma) { |
3666 | if (vma) { |
3667 | if ((alignment && |
3667 | if ((alignment && |
3668 | vma->node.start & (alignment - 1)) || |
3668 | vma->node.start & (alignment - 1)) || |
3669 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3669 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3670 | WARN(obj->pin_count, |
3670 | WARN(obj->pin_count, |
3671 | "bo is already pinned with incorrect alignment:" |
3671 | "bo is already pinned with incorrect alignment:" |
3672 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
3672 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
3673 | " obj->map_and_fenceable=%d\n", |
3673 | " obj->map_and_fenceable=%d\n", |
3674 | i915_gem_obj_offset(obj, vm), alignment, |
3674 | i915_gem_obj_offset(obj, vm), alignment, |
3675 | map_and_fenceable, |
3675 | map_and_fenceable, |
3676 | obj->map_and_fenceable); |
3676 | obj->map_and_fenceable); |
3677 | ret = i915_vma_unbind(vma); |
3677 | ret = i915_vma_unbind(vma); |
3678 | if (ret) |
3678 | if (ret) |
3679 | return ret; |
3679 | return ret; |
3680 | } |
3680 | } |
3681 | } |
3681 | } |
3682 | 3682 | ||
3683 | if (!i915_gem_obj_bound(obj, vm)) { |
3683 | if (!i915_gem_obj_bound(obj, vm)) { |
3684 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3684 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3685 | 3685 | ||
3686 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3686 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3687 | map_and_fenceable, |
3687 | map_and_fenceable, |
3688 | nonblocking); |
3688 | nonblocking); |
3689 | if (ret) |
3689 | if (ret) |
3690 | return ret; |
3690 | return ret; |
3691 | 3691 | ||
3692 | if (!dev_priv->mm.aliasing_ppgtt) |
3692 | if (!dev_priv->mm.aliasing_ppgtt) |
3693 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
3693 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
3694 | } |
3694 | } |
3695 | 3695 | ||
3696 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3696 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3697 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
3697 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
3698 | 3698 | ||
3699 | obj->pin_count++; |
3699 | obj->pin_count++; |
3700 | obj->pin_mappable |= map_and_fenceable; |
3700 | obj->pin_mappable |= map_and_fenceable; |
3701 | 3701 | ||
3702 | return 0; |
3702 | return 0; |
3703 | } |
3703 | } |
3704 | 3704 | ||
3705 | void |
3705 | void |
3706 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
3706 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
3707 | { |
3707 | { |
3708 | BUG_ON(obj->pin_count == 0); |
3708 | BUG_ON(obj->pin_count == 0); |
3709 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
3709 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
3710 | 3710 | ||
3711 | if (--obj->pin_count == 0) |
3711 | if (--obj->pin_count == 0) |
3712 | obj->pin_mappable = false; |
3712 | obj->pin_mappable = false; |
3713 | } |
3713 | } |
3714 | 3714 | ||
3715 | int |
3715 | int |
3716 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
3716 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
3717 | struct drm_file *file) |
3717 | struct drm_file *file) |
3718 | { |
3718 | { |
3719 | struct drm_i915_gem_pin *args = data; |
3719 | struct drm_i915_gem_pin *args = data; |
3720 | struct drm_i915_gem_object *obj; |
3720 | struct drm_i915_gem_object *obj; |
3721 | int ret; |
3721 | int ret; |
3722 | 3722 | ||
3723 | if(args->handle == -2) |
3723 | if(args->handle == -2) |
3724 | { |
3724 | { |
3725 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
3725 | printf("%s handle %d\n", __FUNCTION__, args->handle); |
3726 | return 0; |
3726 | return 0; |
3727 | } |
3727 | } |
3728 | 3728 | ||
3729 | ret = i915_mutex_lock_interruptible(dev); |
3729 | ret = i915_mutex_lock_interruptible(dev); |
3730 | if (ret) |
3730 | if (ret) |
3731 | return ret; |
3731 | return ret; |
3732 | 3732 | ||
3733 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3733 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3734 | if (&obj->base == NULL) { |
3734 | if (&obj->base == NULL) { |
3735 | ret = -ENOENT; |
3735 | ret = -ENOENT; |
3736 | goto unlock; |
3736 | goto unlock; |
3737 | } |
3737 | } |
3738 | 3738 | ||
3739 | if (obj->madv != I915_MADV_WILLNEED) { |
3739 | if (obj->madv != I915_MADV_WILLNEED) { |
3740 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
3740 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
3741 | ret = -EINVAL; |
3741 | ret = -EINVAL; |
3742 | goto out; |
3742 | goto out; |
3743 | } |
3743 | } |
3744 | 3744 | ||
3745 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
3745 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
3746 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3746 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3747 | args->handle); |
3747 | args->handle); |
3748 | ret = -EINVAL; |
3748 | ret = -EINVAL; |
3749 | goto out; |
3749 | goto out; |
3750 | } |
3750 | } |
3751 | 3751 | ||
3752 | if (obj->user_pin_count == 0) { |
3752 | if (obj->user_pin_count == 0) { |
3753 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
3753 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
3754 | if (ret) |
3754 | if (ret) |
3755 | goto out; |
3755 | goto out; |
3756 | } |
3756 | } |
3757 | 3757 | ||
3758 | obj->user_pin_count++; |
3758 | obj->user_pin_count++; |
3759 | obj->pin_filp = file; |
3759 | obj->pin_filp = file; |
3760 | 3760 | ||
3761 | args->offset = i915_gem_obj_ggtt_offset(obj); |
3761 | args->offset = i915_gem_obj_ggtt_offset(obj); |
3762 | out: |
3762 | out: |
3763 | drm_gem_object_unreference(&obj->base); |
3763 | drm_gem_object_unreference(&obj->base); |
3764 | unlock: |
3764 | unlock: |
3765 | mutex_unlock(&dev->struct_mutex); |
3765 | mutex_unlock(&dev->struct_mutex); |
3766 | return ret; |
3766 | return ret; |
3767 | } |
3767 | } |
3768 | 3768 | ||
3769 | int |
3769 | int |
3770 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
3770 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
3771 | struct drm_file *file) |
3771 | struct drm_file *file) |
3772 | { |
3772 | { |
3773 | struct drm_i915_gem_pin *args = data; |
3773 | struct drm_i915_gem_pin *args = data; |
3774 | struct drm_i915_gem_object *obj; |
3774 | struct drm_i915_gem_object *obj; |
3775 | int ret; |
3775 | int ret; |
3776 | 3776 | ||
3777 | ret = i915_mutex_lock_interruptible(dev); |
3777 | ret = i915_mutex_lock_interruptible(dev); |
3778 | if (ret) |
3778 | if (ret) |
3779 | return ret; |
3779 | return ret; |
3780 | 3780 | ||
3781 | if(args->handle == -2) |
3781 | if(args->handle == -2) |
3782 | { |
3782 | { |
3783 | obj = get_fb_obj(); |
3783 | obj = get_fb_obj(); |
3784 | drm_gem_object_reference(&obj->base); |
3784 | drm_gem_object_reference(&obj->base); |
3785 | } |
3785 | } |
3786 | else |
3786 | else |
3787 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3787 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3788 | if (&obj->base == NULL) { |
3788 | if (&obj->base == NULL) { |
3789 | ret = -ENOENT; |
3789 | ret = -ENOENT; |
3790 | goto unlock; |
3790 | goto unlock; |
3791 | } |
3791 | } |
3792 | 3792 | ||
3793 | if (obj->pin_filp != file) { |
3793 | if (obj->pin_filp != file) { |
3794 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3794 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3795 | args->handle); |
3795 | args->handle); |
3796 | ret = -EINVAL; |
3796 | ret = -EINVAL; |
3797 | goto out; |
3797 | goto out; |
3798 | } |
3798 | } |
3799 | obj->user_pin_count--; |
3799 | obj->user_pin_count--; |
3800 | if (obj->user_pin_count == 0) { |
3800 | if (obj->user_pin_count == 0) { |
3801 | obj->pin_filp = NULL; |
3801 | obj->pin_filp = NULL; |
3802 | i915_gem_object_unpin(obj); |
3802 | i915_gem_object_unpin(obj); |
3803 | } |
3803 | } |
3804 | 3804 | ||
3805 | out: |
3805 | out: |
3806 | drm_gem_object_unreference(&obj->base); |
3806 | drm_gem_object_unreference(&obj->base); |
3807 | unlock: |
3807 | unlock: |
3808 | mutex_unlock(&dev->struct_mutex); |
3808 | mutex_unlock(&dev->struct_mutex); |
3809 | return ret; |
3809 | return ret; |
3810 | } |
3810 | } |
3811 | 3811 | ||
3812 | int |
3812 | int |
3813 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3813 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3814 | struct drm_file *file) |
3814 | struct drm_file *file) |
3815 | { |
3815 | { |
3816 | struct drm_i915_gem_busy *args = data; |
3816 | struct drm_i915_gem_busy *args = data; |
3817 | struct drm_i915_gem_object *obj; |
3817 | struct drm_i915_gem_object *obj; |
3818 | int ret; |
3818 | int ret; |
3819 | 3819 | ||
3820 | ret = i915_mutex_lock_interruptible(dev); |
3820 | ret = i915_mutex_lock_interruptible(dev); |
3821 | if (ret) |
3821 | if (ret) |
3822 | return ret; |
3822 | return ret; |
3823 | 3823 | ||
3824 | if(args->handle == -2) |
3824 | if(args->handle == -2) |
3825 | { |
3825 | { |
3826 | obj = get_fb_obj(); |
3826 | obj = get_fb_obj(); |
3827 | drm_gem_object_reference(&obj->base); |
3827 | drm_gem_object_reference(&obj->base); |
3828 | } |
3828 | } |
3829 | else |
3829 | else |
3830 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3830 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3831 | if (&obj->base == NULL) { |
3831 | if (&obj->base == NULL) { |
3832 | ret = -ENOENT; |
3832 | ret = -ENOENT; |
3833 | goto unlock; |
3833 | goto unlock; |
3834 | } |
3834 | } |
3835 | 3835 | ||
3836 | /* Count all active objects as busy, even if they are currently not used |
3836 | /* Count all active objects as busy, even if they are currently not used |
3837 | * by the gpu. Users of this interface expect objects to eventually |
3837 | * by the gpu. Users of this interface expect objects to eventually |
3838 | * become non-busy without any further actions, therefore emit any |
3838 | * become non-busy without any further actions, therefore emit any |
3839 | * necessary flushes here. |
3839 | * necessary flushes here. |
3840 | */ |
3840 | */ |
3841 | ret = i915_gem_object_flush_active(obj); |
3841 | ret = i915_gem_object_flush_active(obj); |
3842 | 3842 | ||
3843 | args->busy = obj->active; |
3843 | args->busy = obj->active; |
3844 | if (obj->ring) { |
3844 | if (obj->ring) { |
3845 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
3845 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
3846 | args->busy |= intel_ring_flag(obj->ring) << 16; |
3846 | args->busy |= intel_ring_flag(obj->ring) << 16; |
3847 | } |
3847 | } |
3848 | 3848 | ||
3849 | drm_gem_object_unreference(&obj->base); |
3849 | drm_gem_object_unreference(&obj->base); |
3850 | unlock: |
3850 | unlock: |
3851 | mutex_unlock(&dev->struct_mutex); |
3851 | mutex_unlock(&dev->struct_mutex); |
3852 | return ret; |
3852 | return ret; |
3853 | } |
3853 | } |
3854 | 3854 | ||
3855 | int |
3855 | int |
3856 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3856 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3857 | struct drm_file *file_priv) |
3857 | struct drm_file *file_priv) |
3858 | { |
3858 | { |
3859 | return i915_gem_ring_throttle(dev, file_priv); |
3859 | return i915_gem_ring_throttle(dev, file_priv); |
3860 | } |
3860 | } |
3861 | 3861 | ||
3862 | #if 0 |
3862 | #if 0 |
3863 | 3863 | ||
3864 | int |
3864 | int |
3865 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3865 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3866 | struct drm_file *file_priv) |
3866 | struct drm_file *file_priv) |
3867 | { |
3867 | { |
3868 | struct drm_i915_gem_madvise *args = data; |
3868 | struct drm_i915_gem_madvise *args = data; |
3869 | struct drm_i915_gem_object *obj; |
3869 | struct drm_i915_gem_object *obj; |
3870 | int ret; |
3870 | int ret; |
3871 | 3871 | ||
3872 | switch (args->madv) { |
3872 | switch (args->madv) { |
3873 | case I915_MADV_DONTNEED: |
3873 | case I915_MADV_DONTNEED: |
3874 | case I915_MADV_WILLNEED: |
3874 | case I915_MADV_WILLNEED: |
3875 | break; |
3875 | break; |
3876 | default: |
3876 | default: |
3877 | return -EINVAL; |
3877 | return -EINVAL; |
3878 | } |
3878 | } |
3879 | 3879 | ||
3880 | ret = i915_mutex_lock_interruptible(dev); |
3880 | ret = i915_mutex_lock_interruptible(dev); |
3881 | if (ret) |
3881 | if (ret) |
3882 | return ret; |
3882 | return ret; |
3883 | 3883 | ||
3884 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3884 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3885 | if (&obj->base == NULL) { |
3885 | if (&obj->base == NULL) { |
3886 | ret = -ENOENT; |
3886 | ret = -ENOENT; |
3887 | goto unlock; |
3887 | goto unlock; |
3888 | } |
3888 | } |
3889 | 3889 | ||
3890 | if (obj->pin_count) { |
3890 | if (obj->pin_count) { |
3891 | ret = -EINVAL; |
3891 | ret = -EINVAL; |
3892 | goto out; |
3892 | goto out; |
3893 | } |
3893 | } |
3894 | 3894 | ||
3895 | if (obj->madv != __I915_MADV_PURGED) |
3895 | if (obj->madv != __I915_MADV_PURGED) |
3896 | obj->madv = args->madv; |
3896 | obj->madv = args->madv; |
3897 | 3897 | ||
3898 | /* if the object is no longer attached, discard its backing storage */ |
3898 | /* if the object is no longer attached, discard its backing storage */ |
3899 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
3899 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
3900 | i915_gem_object_truncate(obj); |
3900 | i915_gem_object_truncate(obj); |
3901 | 3901 | ||
3902 | args->retained = obj->madv != __I915_MADV_PURGED; |
3902 | args->retained = obj->madv != __I915_MADV_PURGED; |
3903 | 3903 | ||
3904 | out: |
3904 | out: |
3905 | drm_gem_object_unreference(&obj->base); |
3905 | drm_gem_object_unreference(&obj->base); |
3906 | unlock: |
3906 | unlock: |
3907 | mutex_unlock(&dev->struct_mutex); |
3907 | mutex_unlock(&dev->struct_mutex); |
3908 | return ret; |
3908 | return ret; |
3909 | } |
3909 | } |
3910 | #endif |
3910 | #endif |
3911 | 3911 | ||
3912 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3912 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3913 | const struct drm_i915_gem_object_ops *ops) |
3913 | const struct drm_i915_gem_object_ops *ops) |
3914 | { |
3914 | { |
3915 | INIT_LIST_HEAD(&obj->global_list); |
3915 | INIT_LIST_HEAD(&obj->global_list); |
3916 | INIT_LIST_HEAD(&obj->ring_list); |
3916 | INIT_LIST_HEAD(&obj->ring_list); |
3917 | INIT_LIST_HEAD(&obj->exec_list); |
3917 | INIT_LIST_HEAD(&obj->exec_list); |
3918 | INIT_LIST_HEAD(&obj->obj_exec_link); |
3918 | INIT_LIST_HEAD(&obj->obj_exec_link); |
3919 | INIT_LIST_HEAD(&obj->vma_list); |
3919 | INIT_LIST_HEAD(&obj->vma_list); |
3920 | 3920 | ||
3921 | obj->ops = ops; |
3921 | obj->ops = ops; |
3922 | 3922 | ||
3923 | obj->fence_reg = I915_FENCE_REG_NONE; |
3923 | obj->fence_reg = I915_FENCE_REG_NONE; |
3924 | obj->madv = I915_MADV_WILLNEED; |
3924 | obj->madv = I915_MADV_WILLNEED; |
3925 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3925 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3926 | obj->map_and_fenceable = true; |
3926 | obj->map_and_fenceable = true; |
3927 | 3927 | ||
3928 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
3928 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
3929 | } |
3929 | } |
3930 | 3930 | ||
3931 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3931 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3932 | .get_pages = i915_gem_object_get_pages_gtt, |
3932 | .get_pages = i915_gem_object_get_pages_gtt, |
3933 | .put_pages = i915_gem_object_put_pages_gtt, |
3933 | .put_pages = i915_gem_object_put_pages_gtt, |
3934 | }; |
3934 | }; |
3935 | 3935 | ||
3936 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3936 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3937 | size_t size) |
3937 | size_t size) |
3938 | { |
3938 | { |
3939 | struct drm_i915_gem_object *obj; |
3939 | struct drm_i915_gem_object *obj; |
3940 | struct address_space *mapping; |
3940 | struct address_space *mapping; |
3941 | gfp_t mask; |
3941 | gfp_t mask; |
3942 | 3942 | ||
3943 | obj = i915_gem_object_alloc(dev); |
3943 | obj = i915_gem_object_alloc(dev); |
3944 | if (obj == NULL) |
3944 | if (obj == NULL) |
3945 | return NULL; |
3945 | return NULL; |
3946 | 3946 | ||
3947 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3947 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3948 | i915_gem_object_free(obj); |
3948 | i915_gem_object_free(obj); |
3949 | return NULL; |
3949 | return NULL; |
3950 | } |
3950 | } |
3951 | 3951 | ||
3952 | 3952 | ||
3953 | i915_gem_object_init(obj, &i915_gem_object_ops); |
3953 | i915_gem_object_init(obj, &i915_gem_object_ops); |
3954 | 3954 | ||
3955 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3955 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3956 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3956 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3957 | 3957 | ||
3958 | if (HAS_LLC(dev)) { |
3958 | if (HAS_LLC(dev)) { |
3959 | /* On some devices, we can have the GPU use the LLC (the CPU |
3959 | /* On some devices, we can have the GPU use the LLC (the CPU |
3960 | * cache) for about a 10% performance improvement |
3960 | * cache) for about a 10% performance improvement |
3961 | * compared to uncached. Graphics requests other than |
3961 | * compared to uncached. Graphics requests other than |
3962 | * display scanout are coherent with the CPU in |
3962 | * display scanout are coherent with the CPU in |
3963 | * accessing this cache. This means in this mode we |
3963 | * accessing this cache. This means in this mode we |
3964 | * don't need to clflush on the CPU side, and on the |
3964 | * don't need to clflush on the CPU side, and on the |
3965 | * GPU side we only need to flush internal caches to |
3965 | * GPU side we only need to flush internal caches to |
3966 | * get data visible to the CPU. |
3966 | * get data visible to the CPU. |
3967 | * |
3967 | * |
3968 | * However, we maintain the display planes as UC, and so |
3968 | * However, we maintain the display planes as UC, and so |
3969 | * need to rebind when first used as such. |
3969 | * need to rebind when first used as such. |
3970 | */ |
3970 | */ |
3971 | obj->cache_level = I915_CACHE_LLC; |
3971 | obj->cache_level = I915_CACHE_LLC; |
3972 | } else |
3972 | } else |
3973 | obj->cache_level = I915_CACHE_NONE; |
3973 | obj->cache_level = I915_CACHE_NONE; |
3974 | 3974 | ||
3975 | return obj; |
3975 | return obj; |
3976 | } |
3976 | } |
3977 | 3977 | ||
3978 | int i915_gem_init_object(struct drm_gem_object *obj) |
3978 | int i915_gem_init_object(struct drm_gem_object *obj) |
3979 | { |
3979 | { |
3980 | BUG(); |
3980 | BUG(); |
3981 | 3981 | ||
3982 | return 0; |
3982 | return 0; |
3983 | } |
3983 | } |
3984 | 3984 | ||
3985 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
3985 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
3986 | { |
3986 | { |
3987 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3987 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3988 | struct drm_device *dev = obj->base.dev; |
3988 | struct drm_device *dev = obj->base.dev; |
3989 | drm_i915_private_t *dev_priv = dev->dev_private; |
3989 | drm_i915_private_t *dev_priv = dev->dev_private; |
3990 | struct i915_vma *vma, *next; |
3990 | struct i915_vma *vma, *next; |
3991 | 3991 | ||
3992 | trace_i915_gem_object_destroy(obj); |
3992 | trace_i915_gem_object_destroy(obj); |
3993 | 3993 | ||
3994 | 3994 | ||
3995 | obj->pin_count = 0; |
3995 | obj->pin_count = 0; |
3996 | /* NB: 0 or 1 elements */ |
3996 | /* NB: 0 or 1 elements */ |
3997 | WARN_ON(!list_empty(&obj->vma_list) && |
3997 | WARN_ON(!list_empty(&obj->vma_list) && |
3998 | !list_is_singular(&obj->vma_list)); |
3998 | !list_is_singular(&obj->vma_list)); |
3999 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3999 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4000 | int ret = i915_vma_unbind(vma); |
4000 | int ret = i915_vma_unbind(vma); |
4001 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4001 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4002 | bool was_interruptible; |
4002 | bool was_interruptible; |
4003 | 4003 | ||
4004 | was_interruptible = dev_priv->mm.interruptible; |
4004 | was_interruptible = dev_priv->mm.interruptible; |
4005 | dev_priv->mm.interruptible = false; |
4005 | dev_priv->mm.interruptible = false; |
4006 | 4006 | ||
4007 | WARN_ON(i915_vma_unbind(vma)); |
4007 | WARN_ON(i915_vma_unbind(vma)); |
4008 | 4008 | ||
4009 | dev_priv->mm.interruptible = was_interruptible; |
4009 | dev_priv->mm.interruptible = was_interruptible; |
4010 | } |
4010 | } |
4011 | } |
4011 | } |
4012 | 4012 | ||
4013 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4013 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4014 | * before progressing. */ |
4014 | * before progressing. */ |
4015 | if (obj->stolen) |
4015 | if (obj->stolen) |
4016 | i915_gem_object_unpin_pages(obj); |
4016 | i915_gem_object_unpin_pages(obj); |
4017 | 4017 | ||
4018 | if (WARN_ON(obj->pages_pin_count)) |
4018 | if (WARN_ON(obj->pages_pin_count)) |
4019 | obj->pages_pin_count = 0; |
4019 | obj->pages_pin_count = 0; |
4020 | i915_gem_object_put_pages(obj); |
4020 | i915_gem_object_put_pages(obj); |
4021 | // i915_gem_object_free_mmap_offset(obj); |
4021 | // i915_gem_object_free_mmap_offset(obj); |
4022 | i915_gem_object_release_stolen(obj); |
4022 | i915_gem_object_release_stolen(obj); |
4023 | 4023 | ||
4024 | BUG_ON(obj->pages); |
4024 | BUG_ON(obj->pages); |
4025 | 4025 | ||
4026 | 4026 | ||
4027 | if(obj->base.filp != NULL) |
4027 | if(obj->base.filp != NULL) |
4028 | { |
4028 | { |
4029 | // printf("filp %p\n", obj->base.filp); |
4029 | // printf("filp %p\n", obj->base.filp); |
4030 | shmem_file_delete(obj->base.filp); |
4030 | shmem_file_delete(obj->base.filp); |
4031 | } |
4031 | } |
4032 | 4032 | ||
4033 | drm_gem_object_release(&obj->base); |
4033 | drm_gem_object_release(&obj->base); |
4034 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
4034 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
4035 | 4035 | ||
4036 | kfree(obj->bit_17); |
4036 | kfree(obj->bit_17); |
4037 | i915_gem_object_free(obj); |
4037 | i915_gem_object_free(obj); |
4038 | } |
4038 | } |
4039 | 4039 | ||
4040 | struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj, |
4040 | struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj, |
4041 | struct i915_address_space *vm) |
4041 | struct i915_address_space *vm) |
4042 | { |
4042 | { |
4043 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
4043 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
4044 | if (vma == NULL) |
4044 | if (vma == NULL) |
4045 | return ERR_PTR(-ENOMEM); |
4045 | return ERR_PTR(-ENOMEM); |
4046 | 4046 | ||
4047 | INIT_LIST_HEAD(&vma->vma_link); |
4047 | INIT_LIST_HEAD(&vma->vma_link); |
4048 | INIT_LIST_HEAD(&vma->mm_list); |
4048 | INIT_LIST_HEAD(&vma->mm_list); |
4049 | INIT_LIST_HEAD(&vma->exec_list); |
4049 | INIT_LIST_HEAD(&vma->exec_list); |
4050 | vma->vm = vm; |
4050 | vma->vm = vm; |
4051 | vma->obj = obj; |
4051 | vma->obj = obj; |
4052 | 4052 | ||
4053 | /* Keep GGTT vmas first to make debug easier */ |
4053 | /* Keep GGTT vmas first to make debug easier */ |
4054 | if (i915_is_ggtt(vm)) |
4054 | if (i915_is_ggtt(vm)) |
4055 | list_add(&vma->vma_link, &obj->vma_list); |
4055 | list_add(&vma->vma_link, &obj->vma_list); |
4056 | else |
4056 | else |
4057 | list_add_tail(&vma->vma_link, &obj->vma_list); |
4057 | list_add_tail(&vma->vma_link, &obj->vma_list); |
4058 | 4058 | ||
4059 | return vma; |
4059 | return vma; |
4060 | } |
4060 | } |
4061 | 4061 | ||
4062 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4062 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4063 | { |
4063 | { |
4064 | WARN_ON(vma->node.allocated); |
4064 | WARN_ON(vma->node.allocated); |
4065 | list_del(&vma->vma_link); |
4065 | list_del(&vma->vma_link); |
4066 | kfree(vma); |
4066 | kfree(vma); |
4067 | } |
4067 | } |
4068 | 4068 | ||
4069 | #if 0 |
4069 | #if 0 |
4070 | int |
4070 | int |
4071 | i915_gem_idle(struct drm_device *dev) |
4071 | i915_gem_idle(struct drm_device *dev) |
4072 | { |
4072 | { |
4073 | drm_i915_private_t *dev_priv = dev->dev_private; |
4073 | drm_i915_private_t *dev_priv = dev->dev_private; |
4074 | int ret; |
4074 | int ret; |
4075 | 4075 | ||
4076 | if (dev_priv->ums.mm_suspended) { |
4076 | if (dev_priv->ums.mm_suspended) { |
4077 | mutex_unlock(&dev->struct_mutex); |
4077 | mutex_unlock(&dev->struct_mutex); |
4078 | return 0; |
4078 | return 0; |
4079 | } |
4079 | } |
4080 | 4080 | ||
4081 | ret = i915_gpu_idle(dev); |
4081 | ret = i915_gpu_idle(dev); |
4082 | if (ret) { |
4082 | if (ret) { |
4083 | mutex_unlock(&dev->struct_mutex); |
4083 | mutex_unlock(&dev->struct_mutex); |
4084 | return ret; |
4084 | return ret; |
4085 | } |
4085 | } |
4086 | i915_gem_retire_requests(dev); |
4086 | i915_gem_retire_requests(dev); |
4087 | 4087 | ||
4088 | /* Under UMS, be paranoid and evict. */ |
4088 | /* Under UMS, be paranoid and evict. */ |
4089 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4089 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4090 | i915_gem_evict_everything(dev); |
4090 | i915_gem_evict_everything(dev); |
4091 | 4091 | ||
4092 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
4092 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
4093 | 4093 | ||
4094 | i915_kernel_lost_context(dev); |
4094 | i915_kernel_lost_context(dev); |
4095 | i915_gem_cleanup_ringbuffer(dev); |
4095 | i915_gem_cleanup_ringbuffer(dev); |
4096 | 4096 | ||
4097 | /* Cancel the retire work handler, which should be idle now. */ |
4097 | /* Cancel the retire work handler, which should be idle now. */ |
4098 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
4098 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
4099 | 4099 | ||
4100 | return 0; |
4100 | return 0; |
4101 | } |
4101 | } |
4102 | #endif |
4102 | #endif |
4103 | 4103 | ||
4104 | void i915_gem_l3_remap(struct drm_device *dev) |
4104 | void i915_gem_l3_remap(struct drm_device *dev) |
4105 | { |
4105 | { |
4106 | drm_i915_private_t *dev_priv = dev->dev_private; |
4106 | drm_i915_private_t *dev_priv = dev->dev_private; |
4107 | u32 misccpctl; |
4107 | u32 misccpctl; |
4108 | int i; |
4108 | int i; |
4109 | 4109 | ||
4110 | if (!HAS_L3_GPU_CACHE(dev)) |
4110 | if (!HAS_L3_GPU_CACHE(dev)) |
4111 | return; |
4111 | return; |
4112 | 4112 | ||
4113 | if (!dev_priv->l3_parity.remap_info) |
4113 | if (!dev_priv->l3_parity.remap_info) |
4114 | return; |
4114 | return; |
4115 | 4115 | ||
4116 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
4116 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
4117 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
4117 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
4118 | POSTING_READ(GEN7_MISCCPCTL); |
4118 | POSTING_READ(GEN7_MISCCPCTL); |
4119 | 4119 | ||
4120 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
4120 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
4121 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
4121 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
4122 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
4122 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
4123 | DRM_DEBUG("0x%x was already programmed to %x\n", |
4123 | DRM_DEBUG("0x%x was already programmed to %x\n", |
4124 | GEN7_L3LOG_BASE + i, remap); |
4124 | GEN7_L3LOG_BASE + i, remap); |
4125 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
4125 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
4126 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
4126 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
4127 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
4127 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
4128 | } |
4128 | } |
4129 | 4129 | ||
4130 | /* Make sure all the writes land before disabling dop clock gating */ |
4130 | /* Make sure all the writes land before disabling dop clock gating */ |
4131 | POSTING_READ(GEN7_L3LOG_BASE); |
4131 | POSTING_READ(GEN7_L3LOG_BASE); |
4132 | 4132 | ||
4133 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
4133 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
4134 | } |
4134 | } |
4135 | 4135 | ||
4136 | void i915_gem_init_swizzling(struct drm_device *dev) |
4136 | void i915_gem_init_swizzling(struct drm_device *dev) |
4137 | { |
4137 | { |
4138 | drm_i915_private_t *dev_priv = dev->dev_private; |
4138 | drm_i915_private_t *dev_priv = dev->dev_private; |
4139 | 4139 | ||
4140 | if (INTEL_INFO(dev)->gen < 5 || |
4140 | if (INTEL_INFO(dev)->gen < 5 || |
4141 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4141 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4142 | return; |
4142 | return; |
4143 | 4143 | ||
4144 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
4144 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
4145 | DISP_TILE_SURFACE_SWIZZLING); |
4145 | DISP_TILE_SURFACE_SWIZZLING); |
4146 | 4146 | ||
4147 | if (IS_GEN5(dev)) |
4147 | if (IS_GEN5(dev)) |
4148 | return; |
4148 | return; |
4149 | 4149 | ||
4150 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4150 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4151 | if (IS_GEN6(dev)) |
4151 | if (IS_GEN6(dev)) |
4152 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
4152 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
4153 | else if (IS_GEN7(dev)) |
4153 | else if (IS_GEN7(dev)) |
4154 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
4154 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
4155 | else |
4155 | else |
4156 | BUG(); |
4156 | BUG(); |
4157 | } |
4157 | } |
4158 | 4158 | ||
4159 | static bool |
4159 | static bool |
4160 | intel_enable_blt(struct drm_device *dev) |
4160 | intel_enable_blt(struct drm_device *dev) |
4161 | { |
4161 | { |
4162 | if (!HAS_BLT(dev)) |
4162 | if (!HAS_BLT(dev)) |
4163 | return false; |
4163 | return false; |
4164 | 4164 | ||
4165 | /* The blitter was dysfunctional on early prototypes */ |
4165 | /* The blitter was dysfunctional on early prototypes */ |
4166 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
4166 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
4167 | DRM_INFO("BLT not supported on this pre-production hardware;" |
4167 | DRM_INFO("BLT not supported on this pre-production hardware;" |
4168 | " graphics performance will be degraded.\n"); |
4168 | " graphics performance will be degraded.\n"); |
4169 | return false; |
4169 | return false; |
4170 | } |
4170 | } |
4171 | 4171 | ||
4172 | return true; |
4172 | return true; |
4173 | } |
4173 | } |
4174 | 4174 | ||
4175 | static int i915_gem_init_rings(struct drm_device *dev) |
4175 | static int i915_gem_init_rings(struct drm_device *dev) |
4176 | { |
4176 | { |
4177 | struct drm_i915_private *dev_priv = dev->dev_private; |
4177 | struct drm_i915_private *dev_priv = dev->dev_private; |
4178 | int ret; |
4178 | int ret; |
4179 | 4179 | ||
4180 | ret = intel_init_render_ring_buffer(dev); |
4180 | ret = intel_init_render_ring_buffer(dev); |
4181 | if (ret) |
4181 | if (ret) |
4182 | return ret; |
4182 | return ret; |
4183 | 4183 | ||
4184 | if (HAS_BSD(dev)) { |
4184 | if (HAS_BSD(dev)) { |
4185 | ret = intel_init_bsd_ring_buffer(dev); |
4185 | ret = intel_init_bsd_ring_buffer(dev); |
4186 | if (ret) |
4186 | if (ret) |
4187 | goto cleanup_render_ring; |
4187 | goto cleanup_render_ring; |
4188 | } |
4188 | } |
4189 | 4189 | ||
4190 | if (intel_enable_blt(dev)) { |
4190 | if (intel_enable_blt(dev)) { |
4191 | ret = intel_init_blt_ring_buffer(dev); |
4191 | ret = intel_init_blt_ring_buffer(dev); |
4192 | if (ret) |
4192 | if (ret) |
4193 | goto cleanup_bsd_ring; |
4193 | goto cleanup_bsd_ring; |
4194 | } |
4194 | } |
4195 | 4195 | ||
4196 | if (HAS_VEBOX(dev)) { |
4196 | if (HAS_VEBOX(dev)) { |
4197 | ret = intel_init_vebox_ring_buffer(dev); |
4197 | ret = intel_init_vebox_ring_buffer(dev); |
4198 | if (ret) |
4198 | if (ret) |
4199 | goto cleanup_blt_ring; |
4199 | goto cleanup_blt_ring; |
4200 | } |
4200 | } |
4201 | 4201 | ||
4202 | 4202 | ||
4203 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4203 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4204 | if (ret) |
4204 | if (ret) |
4205 | goto cleanup_vebox_ring; |
4205 | goto cleanup_vebox_ring; |
4206 | 4206 | ||
4207 | return 0; |
4207 | return 0; |
4208 | 4208 | ||
4209 | cleanup_vebox_ring: |
4209 | cleanup_vebox_ring: |
4210 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
4210 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
4211 | cleanup_blt_ring: |
4211 | cleanup_blt_ring: |
4212 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
4212 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
4213 | cleanup_bsd_ring: |
4213 | cleanup_bsd_ring: |
4214 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
4214 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
4215 | cleanup_render_ring: |
4215 | cleanup_render_ring: |
4216 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
4216 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
4217 | 4217 | ||
4218 | return ret; |
4218 | return ret; |
4219 | } |
4219 | } |
4220 | 4220 | ||
4221 | int |
4221 | int |
4222 | i915_gem_init_hw(struct drm_device *dev) |
4222 | i915_gem_init_hw(struct drm_device *dev) |
4223 | { |
4223 | { |
4224 | drm_i915_private_t *dev_priv = dev->dev_private; |
4224 | drm_i915_private_t *dev_priv = dev->dev_private; |
4225 | int ret; |
4225 | int ret; |
4226 | 4226 | ||
4227 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
4227 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
4228 | return -EIO; |
4228 | return -EIO; |
4229 | 4229 | ||
4230 | if (dev_priv->ellc_size) |
4230 | if (dev_priv->ellc_size) |
4231 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4231 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4232 | 4232 | ||
4233 | if (HAS_PCH_NOP(dev)) { |
4233 | if (HAS_PCH_NOP(dev)) { |
4234 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4234 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4235 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
4235 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
4236 | I915_WRITE(GEN7_MSG_CTL, temp); |
4236 | I915_WRITE(GEN7_MSG_CTL, temp); |
4237 | } |
4237 | } |
4238 | 4238 | ||
4239 | i915_gem_l3_remap(dev); |
4239 | i915_gem_l3_remap(dev); |
4240 | 4240 | ||
4241 | i915_gem_init_swizzling(dev); |
4241 | i915_gem_init_swizzling(dev); |
4242 | 4242 | ||
4243 | ret = i915_gem_init_rings(dev); |
4243 | ret = i915_gem_init_rings(dev); |
4244 | if (ret) |
4244 | if (ret) |
4245 | return ret; |
4245 | return ret; |
4246 | 4246 | ||
4247 | /* |
4247 | /* |
4248 | * XXX: There was some w/a described somewhere suggesting loading |
4248 | * XXX: There was some w/a described somewhere suggesting loading |
4249 | * contexts before PPGTT. |
4249 | * contexts before PPGTT. |
4250 | */ |
4250 | */ |
4251 | i915_gem_context_init(dev); |
4251 | i915_gem_context_init(dev); |
4252 | if (dev_priv->mm.aliasing_ppgtt) { |
4252 | if (dev_priv->mm.aliasing_ppgtt) { |
4253 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); |
4253 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); |
4254 | if (ret) { |
4254 | if (ret) { |
4255 | i915_gem_cleanup_aliasing_ppgtt(dev); |
4255 | i915_gem_cleanup_aliasing_ppgtt(dev); |
4256 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); |
4256 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); |
4257 | } |
4257 | } |
4258 | } |
4258 | } |
4259 | 4259 | ||
4260 | return 0; |
4260 | return 0; |
4261 | } |
4261 | } |
4262 | 4262 | ||
4263 | int i915_gem_init(struct drm_device *dev) |
4263 | int i915_gem_init(struct drm_device *dev) |
4264 | { |
4264 | { |
4265 | struct drm_i915_private *dev_priv = dev->dev_private; |
4265 | struct drm_i915_private *dev_priv = dev->dev_private; |
4266 | int ret; |
4266 | int ret; |
4267 | 4267 | ||
4268 | mutex_lock(&dev->struct_mutex); |
4268 | mutex_lock(&dev->struct_mutex); |
4269 | 4269 | ||
4270 | if (IS_VALLEYVIEW(dev)) { |
4270 | if (IS_VALLEYVIEW(dev)) { |
4271 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
4271 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
4272 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); |
4272 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); |
4273 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) |
4273 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) |
4274 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4274 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4275 | } |
4275 | } |
4276 | 4276 | ||
4277 | i915_gem_init_global_gtt(dev); |
4277 | i915_gem_init_global_gtt(dev); |
4278 | 4278 | ||
4279 | ret = i915_gem_init_hw(dev); |
4279 | ret = i915_gem_init_hw(dev); |
4280 | mutex_unlock(&dev->struct_mutex); |
4280 | mutex_unlock(&dev->struct_mutex); |
4281 | if (ret) { |
4281 | if (ret) { |
4282 | i915_gem_cleanup_aliasing_ppgtt(dev); |
4282 | i915_gem_cleanup_aliasing_ppgtt(dev); |
4283 | return ret; |
4283 | return ret; |
4284 | } |
4284 | } |
4285 | 4285 | ||
4286 | 4286 | ||
4287 | return 0; |
4287 | return 0; |
4288 | } |
4288 | } |
4289 | 4289 | ||
4290 | void |
4290 | void |
4291 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
4291 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
4292 | { |
4292 | { |
4293 | drm_i915_private_t *dev_priv = dev->dev_private; |
4293 | drm_i915_private_t *dev_priv = dev->dev_private; |
4294 | struct intel_ring_buffer *ring; |
4294 | struct intel_ring_buffer *ring; |
4295 | int i; |
4295 | int i; |
4296 | 4296 | ||
4297 | for_each_ring(ring, dev_priv, i) |
4297 | for_each_ring(ring, dev_priv, i) |
4298 | intel_cleanup_ring_buffer(ring); |
4298 | intel_cleanup_ring_buffer(ring); |
4299 | } |
4299 | } |
4300 | 4300 | ||
4301 | #if 0 |
4301 | #if 0 |
4302 | 4302 | ||
4303 | int |
4303 | int |
4304 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
4304 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
4305 | struct drm_file *file_priv) |
4305 | struct drm_file *file_priv) |
4306 | { |
4306 | { |
4307 | struct drm_i915_private *dev_priv = dev->dev_private; |
4307 | struct drm_i915_private *dev_priv = dev->dev_private; |
4308 | int ret; |
4308 | int ret; |
4309 | 4309 | ||
4310 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4310 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4311 | return 0; |
4311 | return 0; |
4312 | 4312 | ||
4313 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
4313 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
4314 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
4314 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
4315 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
4315 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
4316 | } |
4316 | } |
4317 | 4317 | ||
4318 | mutex_lock(&dev->struct_mutex); |
4318 | mutex_lock(&dev->struct_mutex); |
4319 | dev_priv->ums.mm_suspended = 0; |
4319 | dev_priv->ums.mm_suspended = 0; |
4320 | 4320 | ||
4321 | ret = i915_gem_init_hw(dev); |
4321 | ret = i915_gem_init_hw(dev); |
4322 | if (ret != 0) { |
4322 | if (ret != 0) { |
4323 | mutex_unlock(&dev->struct_mutex); |
4323 | mutex_unlock(&dev->struct_mutex); |
4324 | return ret; |
4324 | return ret; |
4325 | } |
4325 | } |
4326 | 4326 | ||
4327 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
4327 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
4328 | mutex_unlock(&dev->struct_mutex); |
4328 | mutex_unlock(&dev->struct_mutex); |
4329 | 4329 | ||
4330 | ret = drm_irq_install(dev); |
4330 | ret = drm_irq_install(dev); |
4331 | if (ret) |
4331 | if (ret) |
4332 | goto cleanup_ringbuffer; |
4332 | goto cleanup_ringbuffer; |
4333 | 4333 | ||
4334 | return 0; |
4334 | return 0; |
4335 | 4335 | ||
4336 | cleanup_ringbuffer: |
4336 | cleanup_ringbuffer: |
4337 | mutex_lock(&dev->struct_mutex); |
4337 | mutex_lock(&dev->struct_mutex); |
4338 | i915_gem_cleanup_ringbuffer(dev); |
4338 | i915_gem_cleanup_ringbuffer(dev); |
4339 | dev_priv->ums.mm_suspended = 1; |
4339 | dev_priv->ums.mm_suspended = 1; |
4340 | mutex_unlock(&dev->struct_mutex); |
4340 | mutex_unlock(&dev->struct_mutex); |
4341 | 4341 | ||
4342 | return ret; |
4342 | return ret; |
4343 | } |
4343 | } |
4344 | 4344 | ||
4345 | int |
4345 | int |
4346 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
4346 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
4347 | struct drm_file *file_priv) |
4347 | struct drm_file *file_priv) |
4348 | { |
4348 | { |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
4350 | int ret; |
4350 | int ret; |
4351 | 4351 | ||
4352 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4352 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4353 | return 0; |
4353 | return 0; |
4354 | 4354 | ||
4355 | drm_irq_uninstall(dev); |
4355 | drm_irq_uninstall(dev); |
4356 | 4356 | ||
4357 | mutex_lock(&dev->struct_mutex); |
4357 | mutex_lock(&dev->struct_mutex); |
4358 | ret = i915_gem_idle(dev); |
4358 | ret = i915_gem_idle(dev); |
4359 | 4359 | ||
4360 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4360 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4361 | * We need to replace this with a semaphore, or something. |
4361 | * We need to replace this with a semaphore, or something. |
4362 | * And not confound ums.mm_suspended! |
4362 | * And not confound ums.mm_suspended! |
4363 | */ |
4363 | */ |
4364 | if (ret != 0) |
4364 | if (ret != 0) |
4365 | dev_priv->ums.mm_suspended = 1; |
4365 | dev_priv->ums.mm_suspended = 1; |
4366 | mutex_unlock(&dev->struct_mutex); |
4366 | mutex_unlock(&dev->struct_mutex); |
4367 | 4367 | ||
4368 | return ret; |
4368 | return ret; |
4369 | } |
4369 | } |
4370 | 4370 | ||
4371 | void |
4371 | void |
4372 | i915_gem_lastclose(struct drm_device *dev) |
4372 | i915_gem_lastclose(struct drm_device *dev) |
4373 | { |
4373 | { |
4374 | int ret; |
4374 | int ret; |
4375 | 4375 | ||
4376 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4376 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4377 | return; |
4377 | return; |
4378 | 4378 | ||
4379 | mutex_lock(&dev->struct_mutex); |
4379 | mutex_lock(&dev->struct_mutex); |
4380 | ret = i915_gem_idle(dev); |
4380 | ret = i915_gem_idle(dev); |
4381 | if (ret) |
4381 | if (ret) |
4382 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
4382 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
4383 | mutex_unlock(&dev->struct_mutex); |
4383 | mutex_unlock(&dev->struct_mutex); |
4384 | } |
4384 | } |
4385 | #endif |
4385 | #endif |
4386 | 4386 | ||
4387 | static void |
4387 | static void |
4388 | init_ring_lists(struct intel_ring_buffer *ring) |
4388 | init_ring_lists(struct intel_ring_buffer *ring) |
4389 | { |
4389 | { |
4390 | INIT_LIST_HEAD(&ring->active_list); |
4390 | INIT_LIST_HEAD(&ring->active_list); |
4391 | INIT_LIST_HEAD(&ring->request_list); |
4391 | INIT_LIST_HEAD(&ring->request_list); |
4392 | } |
4392 | } |
4393 | 4393 | ||
4394 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4394 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4395 | struct i915_address_space *vm) |
4395 | struct i915_address_space *vm) |
4396 | { |
4396 | { |
4397 | vm->dev = dev_priv->dev; |
4397 | vm->dev = dev_priv->dev; |
4398 | INIT_LIST_HEAD(&vm->active_list); |
4398 | INIT_LIST_HEAD(&vm->active_list); |
4399 | INIT_LIST_HEAD(&vm->inactive_list); |
4399 | INIT_LIST_HEAD(&vm->inactive_list); |
4400 | INIT_LIST_HEAD(&vm->global_link); |
4400 | INIT_LIST_HEAD(&vm->global_link); |
4401 | list_add(&vm->global_link, &dev_priv->vm_list); |
4401 | list_add(&vm->global_link, &dev_priv->vm_list); |
4402 | } |
4402 | } |
4403 | 4403 | ||
4404 | void |
4404 | void |
4405 | i915_gem_load(struct drm_device *dev) |
4405 | i915_gem_load(struct drm_device *dev) |
4406 | { |
4406 | { |
4407 | drm_i915_private_t *dev_priv = dev->dev_private; |
4407 | drm_i915_private_t *dev_priv = dev->dev_private; |
4408 | int i; |
4408 | int i; |
4409 | 4409 | ||
4410 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4410 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4411 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
4411 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
4412 | 4412 | ||
4413 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4413 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4414 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
4414 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
4415 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4415 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4416 | for (i = 0; i < I915_NUM_RINGS; i++) |
4416 | for (i = 0; i < I915_NUM_RINGS; i++) |
4417 | init_ring_lists(&dev_priv->ring[i]); |
4417 | init_ring_lists(&dev_priv->ring[i]); |
4418 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
4418 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
4419 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
4419 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
4420 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4420 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4421 | i915_gem_retire_work_handler); |
4421 | i915_gem_retire_work_handler); |
4422 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
4422 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
4423 | 4423 | ||
4424 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4424 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4425 | if (IS_GEN3(dev)) { |
4425 | if (IS_GEN3(dev)) { |
4426 | I915_WRITE(MI_ARB_STATE, |
4426 | I915_WRITE(MI_ARB_STATE, |
4427 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
4427 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
4428 | } |
4428 | } |
4429 | 4429 | ||
4430 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4430 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4431 | 4431 | ||
4432 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4432 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4433 | dev_priv->num_fence_regs = 32; |
4433 | dev_priv->num_fence_regs = 32; |
4434 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4434 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4435 | dev_priv->num_fence_regs = 16; |
4435 | dev_priv->num_fence_regs = 16; |
4436 | else |
4436 | else |
4437 | dev_priv->num_fence_regs = 8; |
4437 | dev_priv->num_fence_regs = 8; |
4438 | 4438 | ||
4439 | /* Initialize fence registers to zero */ |
4439 | /* Initialize fence registers to zero */ |
4440 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4440 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4441 | i915_gem_restore_fences(dev); |
4441 | i915_gem_restore_fences(dev); |
4442 | 4442 | ||
4443 | i915_gem_detect_bit_6_swizzle(dev); |
4443 | i915_gem_detect_bit_6_swizzle(dev); |
4444 | 4444 | ||
4445 | dev_priv->mm.interruptible = true; |
4445 | dev_priv->mm.interruptible = true; |
4446 | 4446 | ||
4447 | } |
4447 | } |
4448 | 4448 | ||
4449 | #if 0 |
4449 | #if 0 |
4450 | /* |
4450 | /* |
4451 | * Create a physically contiguous memory object for this object |
4451 | * Create a physically contiguous memory object for this object |
4452 | * e.g. for cursor + overlay regs |
4452 | * e.g. for cursor + overlay regs |
4453 | */ |
4453 | */ |
4454 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4454 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4455 | int id, int size, int align) |
4455 | int id, int size, int align) |
4456 | { |
4456 | { |
4457 | drm_i915_private_t *dev_priv = dev->dev_private; |
4457 | drm_i915_private_t *dev_priv = dev->dev_private; |
4458 | struct drm_i915_gem_phys_object *phys_obj; |
4458 | struct drm_i915_gem_phys_object *phys_obj; |
4459 | int ret; |
4459 | int ret; |
4460 | 4460 | ||
4461 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
4461 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
4462 | return 0; |
4462 | return 0; |
4463 | 4463 | ||
4464 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
4464 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
4465 | if (!phys_obj) |
4465 | if (!phys_obj) |
4466 | return -ENOMEM; |
4466 | return -ENOMEM; |
4467 | 4467 | ||
4468 | phys_obj->id = id; |
4468 | phys_obj->id = id; |
4469 | 4469 | ||
4470 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
4470 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
4471 | if (!phys_obj->handle) { |
4471 | if (!phys_obj->handle) { |
4472 | ret = -ENOMEM; |
4472 | ret = -ENOMEM; |
4473 | goto kfree_obj; |
4473 | goto kfree_obj; |
4474 | } |
4474 | } |
4475 | #ifdef CONFIG_X86 |
4475 | #ifdef CONFIG_X86 |
4476 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
4476 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
4477 | #endif |
4477 | #endif |
4478 | 4478 | ||
4479 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
4479 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
4480 | 4480 | ||
4481 | return 0; |
4481 | return 0; |
4482 | kfree_obj: |
4482 | kfree_obj: |
4483 | kfree(phys_obj); |
4483 | kfree(phys_obj); |
4484 | return ret; |
4484 | return ret; |
4485 | } |
4485 | } |
4486 | 4486 | ||
4487 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
4487 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
4488 | { |
4488 | { |
4489 | drm_i915_private_t *dev_priv = dev->dev_private; |
4489 | drm_i915_private_t *dev_priv = dev->dev_private; |
4490 | struct drm_i915_gem_phys_object *phys_obj; |
4490 | struct drm_i915_gem_phys_object *phys_obj; |
4491 | 4491 | ||
4492 | if (!dev_priv->mm.phys_objs[id - 1]) |
4492 | if (!dev_priv->mm.phys_objs[id - 1]) |
4493 | return; |
4493 | return; |
4494 | 4494 | ||
4495 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4495 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4496 | if (phys_obj->cur_obj) { |
4496 | if (phys_obj->cur_obj) { |
4497 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
4497 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
4498 | } |
4498 | } |
4499 | 4499 | ||
4500 | #ifdef CONFIG_X86 |
4500 | #ifdef CONFIG_X86 |
4501 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
4501 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
4502 | #endif |
4502 | #endif |
4503 | drm_pci_free(dev, phys_obj->handle); |
4503 | drm_pci_free(dev, phys_obj->handle); |
4504 | kfree(phys_obj); |
4504 | kfree(phys_obj); |
4505 | dev_priv->mm.phys_objs[id - 1] = NULL; |
4505 | dev_priv->mm.phys_objs[id - 1] = NULL; |
4506 | } |
4506 | } |
4507 | 4507 | ||
4508 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
4508 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
4509 | { |
4509 | { |
4510 | int i; |
4510 | int i; |
4511 | 4511 | ||
4512 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
4512 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
4513 | i915_gem_free_phys_object(dev, i); |
4513 | i915_gem_free_phys_object(dev, i); |
4514 | } |
4514 | } |
4515 | 4515 | ||
4516 | void i915_gem_detach_phys_object(struct drm_device *dev, |
4516 | void i915_gem_detach_phys_object(struct drm_device *dev, |
4517 | struct drm_i915_gem_object *obj) |
4517 | struct drm_i915_gem_object *obj) |
4518 | { |
4518 | { |
4519 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
4519 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
4520 | char *vaddr; |
4520 | char *vaddr; |
4521 | int i; |
4521 | int i; |
4522 | int page_count; |
4522 | int page_count; |
4523 | 4523 | ||
4524 | if (!obj->phys_obj) |
4524 | if (!obj->phys_obj) |
4525 | return; |
4525 | return; |
4526 | vaddr = obj->phys_obj->handle->vaddr; |
4526 | vaddr = obj->phys_obj->handle->vaddr; |
4527 | 4527 | ||
4528 | page_count = obj->base.size / PAGE_SIZE; |
4528 | page_count = obj->base.size / PAGE_SIZE; |
4529 | for (i = 0; i < page_count; i++) { |
4529 | for (i = 0; i < page_count; i++) { |
4530 | struct page *page = shmem_read_mapping_page(mapping, i); |
4530 | struct page *page = shmem_read_mapping_page(mapping, i); |
4531 | if (!IS_ERR(page)) { |
4531 | if (!IS_ERR(page)) { |
4532 | char *dst = kmap_atomic(page); |
4532 | char *dst = kmap_atomic(page); |
4533 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
4533 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
4534 | kunmap_atomic(dst); |
4534 | kunmap_atomic(dst); |
4535 | 4535 | ||
4536 | drm_clflush_pages(&page, 1); |
4536 | drm_clflush_pages(&page, 1); |
4537 | 4537 | ||
4538 | set_page_dirty(page); |
4538 | set_page_dirty(page); |
4539 | mark_page_accessed(page); |
4539 | mark_page_accessed(page); |
4540 | page_cache_release(page); |
4540 | page_cache_release(page); |
4541 | } |
4541 | } |
4542 | } |
4542 | } |
4543 | i915_gem_chipset_flush(dev); |
4543 | i915_gem_chipset_flush(dev); |
4544 | 4544 | ||
4545 | obj->phys_obj->cur_obj = NULL; |
4545 | obj->phys_obj->cur_obj = NULL; |
4546 | obj->phys_obj = NULL; |
4546 | obj->phys_obj = NULL; |
4547 | } |
4547 | } |
4548 | 4548 | ||
4549 | int |
4549 | int |
4550 | i915_gem_attach_phys_object(struct drm_device *dev, |
4550 | i915_gem_attach_phys_object(struct drm_device *dev, |
4551 | struct drm_i915_gem_object *obj, |
4551 | struct drm_i915_gem_object *obj, |
4552 | int id, |
4552 | int id, |
4553 | int align) |
4553 | int align) |
4554 | { |
4554 | { |
4555 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
4555 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
4556 | drm_i915_private_t *dev_priv = dev->dev_private; |
4556 | drm_i915_private_t *dev_priv = dev->dev_private; |
4557 | int ret = 0; |
4557 | int ret = 0; |
4558 | int page_count; |
4558 | int page_count; |
4559 | int i; |
4559 | int i; |
4560 | 4560 | ||
4561 | if (id > I915_MAX_PHYS_OBJECT) |
4561 | if (id > I915_MAX_PHYS_OBJECT) |
4562 | return -EINVAL; |
4562 | return -EINVAL; |
4563 | 4563 | ||
4564 | if (obj->phys_obj) { |
4564 | if (obj->phys_obj) { |
4565 | if (obj->phys_obj->id == id) |
4565 | if (obj->phys_obj->id == id) |
4566 | return 0; |
4566 | return 0; |
4567 | i915_gem_detach_phys_object(dev, obj); |
4567 | i915_gem_detach_phys_object(dev, obj); |
4568 | } |
4568 | } |
4569 | 4569 | ||
4570 | /* create a new object */ |
4570 | /* create a new object */ |
4571 | if (!dev_priv->mm.phys_objs[id - 1]) { |
4571 | if (!dev_priv->mm.phys_objs[id - 1]) { |
4572 | ret = i915_gem_init_phys_object(dev, id, |
4572 | ret = i915_gem_init_phys_object(dev, id, |
4573 | obj->base.size, align); |
4573 | obj->base.size, align); |
4574 | if (ret) { |
4574 | if (ret) { |
4575 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4575 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4576 | id, obj->base.size); |
4576 | id, obj->base.size); |
4577 | return ret; |
4577 | return ret; |
4578 | } |
4578 | } |
4579 | } |
4579 | } |
4580 | 4580 | ||
4581 | /* bind to the object */ |
4581 | /* bind to the object */ |
4582 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4582 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4583 | obj->phys_obj->cur_obj = obj; |
4583 | obj->phys_obj->cur_obj = obj; |
4584 | 4584 | ||
4585 | page_count = obj->base.size / PAGE_SIZE; |
4585 | page_count = obj->base.size / PAGE_SIZE; |
4586 | 4586 | ||
4587 | for (i = 0; i < page_count; i++) { |
4587 | for (i = 0; i < page_count; i++) { |
4588 | struct page *page; |
4588 | struct page *page; |
4589 | char *dst, *src; |
4589 | char *dst, *src; |
4590 | 4590 | ||
4591 | page = shmem_read_mapping_page(mapping, i); |
4591 | page = shmem_read_mapping_page(mapping, i); |
4592 | if (IS_ERR(page)) |
4592 | if (IS_ERR(page)) |
4593 | return PTR_ERR(page); |
4593 | return PTR_ERR(page); |
4594 | 4594 | ||
4595 | src = kmap_atomic(page); |
4595 | src = kmap_atomic(page); |
4596 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4596 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4597 | memcpy(dst, src, PAGE_SIZE); |
4597 | memcpy(dst, src, PAGE_SIZE); |
4598 | kunmap_atomic(src); |
4598 | kunmap_atomic(src); |
4599 | 4599 | ||
4600 | mark_page_accessed(page); |
4600 | mark_page_accessed(page); |
4601 | page_cache_release(page); |
4601 | page_cache_release(page); |
4602 | } |
4602 | } |
4603 | 4603 | ||
4604 | return 0; |
4604 | return 0; |
4605 | } |
4605 | } |
4606 | 4606 | ||
4607 | static int |
4607 | static int |
4608 | i915_gem_phys_pwrite(struct drm_device *dev, |
4608 | i915_gem_phys_pwrite(struct drm_device *dev, |
4609 | struct drm_i915_gem_object *obj, |
4609 | struct drm_i915_gem_object *obj, |
4610 | struct drm_i915_gem_pwrite *args, |
4610 | struct drm_i915_gem_pwrite *args, |
4611 | struct drm_file *file_priv) |
4611 | struct drm_file *file_priv) |
4612 | { |
4612 | { |
4613 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
4613 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
4614 | char __user *user_data = to_user_ptr(args->data_ptr); |
4614 | char __user *user_data = to_user_ptr(args->data_ptr); |
4615 | 4615 | ||
4616 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4616 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4617 | unsigned long unwritten; |
4617 | unsigned long unwritten; |
4618 | 4618 | ||
4619 | /* The physical object once assigned is fixed for the lifetime |
4619 | /* The physical object once assigned is fixed for the lifetime |
4620 | * of the obj, so we can safely drop the lock and continue |
4620 | * of the obj, so we can safely drop the lock and continue |
4621 | * to access vaddr. |
4621 | * to access vaddr. |
4622 | */ |
4622 | */ |
4623 | mutex_unlock(&dev->struct_mutex); |
4623 | mutex_unlock(&dev->struct_mutex); |
4624 | unwritten = copy_from_user(vaddr, user_data, args->size); |
4624 | unwritten = copy_from_user(vaddr, user_data, args->size); |
4625 | mutex_lock(&dev->struct_mutex); |
4625 | mutex_lock(&dev->struct_mutex); |
4626 | if (unwritten) |
4626 | if (unwritten) |
4627 | return -EFAULT; |
4627 | return -EFAULT; |
4628 | } |
4628 | } |
4629 | 4629 | ||
4630 | i915_gem_chipset_flush(dev); |
4630 | i915_gem_chipset_flush(dev); |
4631 | return 0; |
4631 | return 0; |
4632 | } |
4632 | } |
4633 | 4633 | ||
4634 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
4634 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
4635 | { |
4635 | { |
4636 | struct drm_i915_file_private *file_priv = file->driver_priv; |
4636 | struct drm_i915_file_private *file_priv = file->driver_priv; |
4637 | 4637 | ||
4638 | /* Clean up our request list when the client is going away, so that |
4638 | /* Clean up our request list when the client is going away, so that |
4639 | * later retire_requests won't dereference our soon-to-be-gone |
4639 | * later retire_requests won't dereference our soon-to-be-gone |
4640 | * file_priv. |
4640 | * file_priv. |
4641 | */ |
4641 | */ |
4642 | spin_lock(&file_priv->mm.lock); |
4642 | spin_lock(&file_priv->mm.lock); |
4643 | while (!list_empty(&file_priv->mm.request_list)) { |
4643 | while (!list_empty(&file_priv->mm.request_list)) { |
4644 | struct drm_i915_gem_request *request; |
4644 | struct drm_i915_gem_request *request; |
4645 | 4645 | ||
4646 | request = list_first_entry(&file_priv->mm.request_list, |
4646 | request = list_first_entry(&file_priv->mm.request_list, |
4647 | struct drm_i915_gem_request, |
4647 | struct drm_i915_gem_request, |
4648 | client_list); |
4648 | client_list); |
4649 | list_del(&request->client_list); |
4649 | list_del(&request->client_list); |
4650 | request->file_priv = NULL; |
4650 | request->file_priv = NULL; |
4651 | } |
4651 | } |
4652 | spin_unlock(&file_priv->mm.lock); |
4652 | spin_unlock(&file_priv->mm.lock); |
4653 | } |
4653 | } |
4654 | #endif |
4654 | #endif |
4655 | 4655 | ||
4656 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4656 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4657 | { |
4657 | { |
4658 | if (!mutex_is_locked(mutex)) |
4658 | if (!mutex_is_locked(mutex)) |
4659 | return false; |
4659 | return false; |
4660 | 4660 | ||
4661 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
4661 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
4662 | return mutex->owner == task; |
4662 | return mutex->owner == task; |
4663 | #else |
4663 | #else |
4664 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
4664 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
4665 | return false; |
4665 | return false; |
4666 | #endif |
4666 | #endif |
4667 | } |
4667 | } |
4668 | 4668 | ||
4669 | /* All the new VM stuff */ |
4669 | /* All the new VM stuff */ |
4670 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4670 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4671 | struct i915_address_space *vm) |
4671 | struct i915_address_space *vm) |
4672 | { |
4672 | { |
4673 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4673 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4674 | struct i915_vma *vma; |
4674 | struct i915_vma *vma; |
4675 | 4675 | ||
4676 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) |
4676 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) |
4677 | vm = &dev_priv->gtt.base; |
4677 | vm = &dev_priv->gtt.base; |
4678 | 4678 | ||
4679 | BUG_ON(list_empty(&o->vma_list)); |
4679 | BUG_ON(list_empty(&o->vma_list)); |
4680 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
4680 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
4681 | if (vma->vm == vm) |
4681 | if (vma->vm == vm) |
4682 | return vma->node.start; |
4682 | return vma->node.start; |
4683 | 4683 | ||
4684 | } |
4684 | } |
4685 | return 0; //-1; |
4685 | return 0; //-1; |
4686 | } |
4686 | } |
4687 | 4687 | ||
4688 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
4688 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
4689 | struct i915_address_space *vm) |
4689 | struct i915_address_space *vm) |
4690 | { |
4690 | { |
4691 | struct i915_vma *vma; |
4691 | struct i915_vma *vma; |
4692 | 4692 | ||
4693 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4693 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4694 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
4694 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
4695 | return true; |
4695 | return true; |
4696 | 4696 | ||
4697 | return false; |
4697 | return false; |
4698 | } |
4698 | } |
4699 | 4699 | ||
4700 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
4700 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
4701 | { |
4701 | { |
4702 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4702 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4703 | struct i915_address_space *vm; |
4703 | struct i915_address_space *vm; |
4704 | 4704 | ||
4705 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) |
4705 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) |
4706 | if (i915_gem_obj_bound(o, vm)) |
4706 | if (i915_gem_obj_bound(o, vm)) |
4707 | return true; |
4707 | return true; |
4708 | 4708 | ||
4709 | return false; |
4709 | return false; |
4710 | } |
4710 | } |
4711 | 4711 | ||
4712 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
4712 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
4713 | struct i915_address_space *vm) |
4713 | struct i915_address_space *vm) |
4714 | { |
4714 | { |
4715 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4715 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4716 | struct i915_vma *vma; |
4716 | struct i915_vma *vma; |
4717 | 4717 | ||
4718 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) |
4718 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) |
4719 | vm = &dev_priv->gtt.base; |
4719 | vm = &dev_priv->gtt.base; |
4720 | 4720 | ||
4721 | BUG_ON(list_empty(&o->vma_list)); |
4721 | BUG_ON(list_empty(&o->vma_list)); |
4722 | 4722 | ||
4723 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4723 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4724 | if (vma->vm == vm) |
4724 | if (vma->vm == vm) |
4725 | return vma->node.size; |
4725 | return vma->node.size; |
4726 | 4726 | ||
4727 | return 0; |
4727 | return 0; |
4728 | } |
4728 | } |
4729 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4729 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4730 | struct i915_address_space *vm) |
4730 | struct i915_address_space *vm) |
4731 | { |
4731 | { |
4732 | struct i915_vma *vma; |
4732 | struct i915_vma *vma; |
4733 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
4733 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
4734 | if (vma->vm == vm) |
4734 | if (vma->vm == vm) |
4735 | return vma; |
4735 | return vma; |
4736 | 4736 | ||
4737 | return NULL; |
4737 | return NULL; |
4738 | } |
4738 | } |
4739 | 4739 | ||
4740 | struct i915_vma * |
4740 | struct i915_vma * |
4741 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
4741 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
4742 | struct i915_address_space *vm) |
4742 | struct i915_address_space *vm) |
4743 | { |
4743 | { |
4744 | struct i915_vma *vma; |
4744 | struct i915_vma *vma; |
4745 | 4745 | ||
4746 | vma = i915_gem_obj_to_vma(obj, vm); |
4746 | vma = i915_gem_obj_to_vma(obj, vm); |
4747 | if (!vma) |
4747 | if (!vma) |
4748 | vma = i915_gem_vma_create(obj, vm); |
4748 | vma = i915_gem_vma_create(obj, vm); |
4749 | 4749 | ||
4750 | return vma; |
4750 | return vma; |
4751 | }>>=>>>>>>>><>>= |
4751 | }>>=>>>>>>>><>>= |
4752 | >>><>><>>><>><>><>><>><>=>>>>>>>>>=><=>>>><>=>><>=>>6)><6)>6) |
4752 | >>><>><>>><>><>><>><>><>=>>>>>>>>>=><=>>>><>=>><>=>>6)><6)>6) |
4753 | #define><6) |
4753 | #define><6) |
4754 | #define>6)><6)>6) |
4754 | #define>6)><6)>6) |
4755 | #define><6) |
4755 | #define><6) |
4756 | #define> |
4756 | #define> |