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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
/*
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#ifndef _I915_DRV_H_
#define _I915_DRV_H_
 
#include "i915_reg.h"
#include "intel_bios.h"
#include "intel_ringbuffer.h"
//#include 
//#include 
//#include 
//#include 
 
#include 
 
/* General customization:
 */
 
#define I915_TILING_NONE    0
 
 
#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."
 
#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
#define DRIVER_DATE		"20080730"
 
enum pipe {
	PIPE_A = 0,
	PIPE_B,
	PIPE_C,
	I915_MAX_PIPES
};
#define pipe_name(p) ((p) + 'A')
 
enum plane {
	PLANE_A = 0,
	PLANE_B,
	PLANE_C,
};
#define plane_name(p) ((p) + 'A')
 
#define I915_GEM_GPU_DOMAINS	(~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 
#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
 
/* Interface history:
 *
 * 1.1: Original.
 * 1.2: Add Power Management
 * 1.3: Add vblank support
 * 1.4: Fix cmdbuffer path, add heap destroy
 * 1.5: Add vblank pipe configuration
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
 */
#define DRIVER_MAJOR		1
#define DRIVER_MINOR		6
#define DRIVER_PATCHLEVEL	0
 
#define WATCH_COHERENCY	0
#define WATCH_LISTS	0
 
#define I915_GEM_PHYS_CURSOR_0 1
#define I915_GEM_PHYS_CURSOR_1 2
#define I915_GEM_PHYS_OVERLAY_REGS 3
#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 
struct mem_block {
	struct mem_block *next;
	struct mem_block *prev;
	int start;
	int size;
	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
};
 
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;
 
struct intel_opregion {
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
	struct opregion_asle *asle;
	void *vbt;
	u32 __iomem *lid_state;
};
#define OPREGION_SIZE            (8*1024)
 
struct intel_overlay;
struct intel_overlay_error_state;
 
 
#define I915_FENCE_REG_NONE -1
 
struct drm_i915_fence_reg {
	struct list_head lru_list;
	struct drm_i915_gem_object *obj;
	uint32_t setup_seqno;
};
 
struct sdvo_device_mapping {
	u8 initialized;
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
	u8 i2c_pin;
	u8 i2c_speed;
	u8 ddc_pin;
};
 
struct intel_display_error_state;
 
struct drm_i915_error_state {
	u32 eir;
	u32 pgtbl_er;
	u32 pipestat[I915_MAX_PIPES];
	u32 ipeir;
	u32 ipehr;
	u32 instdone;
	u32 acthd;
	u32 error; /* gen6+ */
	u32 bcs_acthd; /* gen6+ blt engine */
	u32 bcs_ipehr;
	u32 bcs_ipeir;
	u32 bcs_instdone;
	u32 bcs_seqno;
	u32 vcs_acthd; /* gen6+ bsd engine */
	u32 vcs_ipehr;
	u32 vcs_ipeir;
	u32 vcs_instdone;
	u32 vcs_seqno;
	u32 instpm;
	u32 instps;
	u32 instdone1;
	u32 seqno;
	u64 bbaddr;
	u64 fence[16];
	struct timeval time;
	struct drm_i915_error_object {
		int page_count;
		u32 gtt_offset;
		u32 *pages[0];
	} *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 seqno;
		u32 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:5;
		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 ring:4;
		u32 cache_level:2;
	} *active_bo, *pinned_bo;
	u32 active_bo_count, pinned_bo_count;
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
};
 
struct drm_i915_display_funcs {
	void (*dpms)(struct drm_crtc *crtc, int mode);
	bool (*fbc_enabled)(struct drm_device *dev);
	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
	void (*disable_fbc)(struct drm_device *dev);
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
	void (*update_wm)(struct drm_device *dev);
	int (*crtc_mode_set)(struct drm_crtc *crtc,
			     struct drm_display_mode *mode,
			     struct drm_display_mode *adjusted_mode,
			     int x, int y,
			     struct drm_framebuffer *old_fb);
	void (*fdi_link_train)(struct drm_crtc *crtc);
	void (*init_clock_gating)(struct drm_device *dev);
	void (*init_pch_clock_gating)(struct drm_device *dev);
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj);
	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			    int x, int y);
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
};
 
struct intel_device_info {
	u8 gen;
	u8 is_mobile : 1;
	u8 is_i85x : 1;
	u8 is_i915g : 1;
	u8 is_i945gm : 1;
	u8 is_g33 : 1;
	u8 need_gfx_hws : 1;
	u8 is_g4x : 1;
	u8 is_pineview : 1;
	u8 is_broadwater : 1;
	u8 is_crestline : 1;
	u8 is_ivybridge : 1;
	u8 has_fbc : 1;
	u8 has_pipe_cxsr : 1;
	u8 has_hotplug : 1;
	u8 cursor_needs_physical : 1;
	u8 has_overlay : 1;
	u8 overlay_needs_physical : 1;
	u8 supports_tv : 1;
	u8 has_bsd_ring : 1;
	u8 has_blt_ring : 1;
};
 
enum no_fbc_reason {
	FBC_NO_OUTPUT, /* no outputs enabled to compress */
	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
	FBC_MODE_TOO_LARGE, /* mode too large for compression */
	FBC_BAD_PLANE, /* fbc not supported on plane */
	FBC_NOT_TILED, /* buffer not tiled */
	FBC_MULTIPLE_PIPES, /* more than one pipe active */
	FBC_MODULE_PARAM,
};
 
enum intel_pch {
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
};
 
#define QUIRK_PIPEA_FORCE (1<<0)
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
 
struct intel_fbdev;
struct intel_fbc_work;
 
 
typedef struct drm_i915_private {
	struct drm_device *dev;
 
	const struct intel_device_info *info;
 
	int has_gem;
	int relative_constants_mode;
 
	void __iomem *regs;
	u32 gt_fifo_count;
 
    struct intel_gmbus {
        struct i2c_adapter adapter;
        struct i2c_adapter *force_bit;
        u32 reg0;
    } *gmbus;
 
	struct pci_dev *bridge_dev;
    struct intel_ring_buffer ring[I915_NUM_RINGS];
	uint32_t next_seqno;
 
    drm_dma_handle_t *status_page_dmah;
//   uint32_t counter;
//   drm_local_map_t hws_map;
//   struct drm_i915_gem_object *pwrctx;
//   struct drm_i915_gem_object *renderctx;
 
//   struct resource mch_res;
 
	unsigned int cpp;
	int back_offset;
	int front_offset;
	int current_page;
	int page_flipping;
 
	atomic_t irq_received;
 
	/* protects the irq masks */
	spinlock_t irq_lock;
	/** Cached value of IMR to avoid reads in updating the bitfield */
	u32 pipestat[2];
	u32 irq_mask;
	u32 gt_irq_mask;
	u32 pch_irq_mask;
 
	u32 hotplug_supported_mask;
//   struct work_struct hotplug_work;
 
	int tex_lru_log_granularity;
	int allow_batchbuffer;
	struct mem_block *agp_heap;
	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
	int vblank_pipe;
	int num_pipe;
 
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
//   struct timer_list hangcheck_timer;
	int hangcheck_count;
	uint32_t last_acthd;
	uint32_t last_instdone;
	uint32_t last_instdone1;
 
	unsigned long cfb_size;
	unsigned int cfb_fb;
	enum plane cfb_plane;
	int cfb_y;
//   struct intel_fbc_work *fbc_work;
 
    struct intel_opregion opregion;
 
	/* overlay */
//   struct intel_overlay *overlay;
 
	/* LVDS info */
	int backlight_level;  /* restore backlight to this value */
	bool backlight_enabled;
	struct drm_display_mode *panel_fixed_mode;
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 
	/* Feature bits from the VBIOS */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	int lvds_ssc_freq;
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
 
		bool initialized;
		bool support;
		int bpp;
        struct edp_power_seq pps;
	} edp;
	bool no_aux_handshake;
 
//   struct notifier_block lid_notifier;
 
	int crt_ddc_pin;
    struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
	unsigned int fsb_freq, mem_freq, is_ddr3;
 
	spinlock_t error_lock;
//   struct drm_i915_error_state *first_error;
//   struct work_struct error_work;
//   struct completion error_completion;
//   struct workqueue_struct *wq;
 
	/* Display functions */
    struct drm_i915_display_funcs display;
 
	/* PCH chipset type */
	enum intel_pch pch_type;
 
	unsigned long quirks;
 
	/* Register state */
	bool modeset_on_lid;
	u8 saveLBB;
	u32 saveDSPACNTR;
	u32 saveDSPBCNTR;
	u32 saveDSPARB;
	u32 saveHWS;
	u32 savePIPEACONF;
	u32 savePIPEBCONF;
	u32 savePIPEASRC;
	u32 savePIPEBSRC;
	u32 saveFPA0;
	u32 saveFPA1;
	u32 saveDPLL_A;
	u32 saveDPLL_A_MD;
	u32 saveHTOTAL_A;
	u32 saveHBLANK_A;
	u32 saveHSYNC_A;
	u32 saveVTOTAL_A;
	u32 saveVBLANK_A;
	u32 saveVSYNC_A;
	u32 saveBCLRPAT_A;
	u32 saveTRANSACONF;
	u32 saveTRANS_HTOTAL_A;
	u32 saveTRANS_HBLANK_A;
	u32 saveTRANS_HSYNC_A;
	u32 saveTRANS_VTOTAL_A;
	u32 saveTRANS_VBLANK_A;
	u32 saveTRANS_VSYNC_A;
	u32 savePIPEASTAT;
	u32 saveDSPASTRIDE;
	u32 saveDSPASIZE;
	u32 saveDSPAPOS;
	u32 saveDSPAADDR;
	u32 saveDSPASURF;
	u32 saveDSPATILEOFF;
	u32 savePFIT_PGM_RATIOS;
	u32 saveBLC_HIST_CTL;
	u32 saveBLC_PWM_CTL;
	u32 saveBLC_PWM_CTL2;
	u32 saveBLC_CPU_PWM_CTL;
	u32 saveBLC_CPU_PWM_CTL2;
	u32 saveFPB0;
	u32 saveFPB1;
	u32 saveDPLL_B;
	u32 saveDPLL_B_MD;
	u32 saveHTOTAL_B;
	u32 saveHBLANK_B;
	u32 saveHSYNC_B;
	u32 saveVTOTAL_B;
	u32 saveVBLANK_B;
	u32 saveVSYNC_B;
	u32 saveBCLRPAT_B;
	u32 saveTRANSBCONF;
	u32 saveTRANS_HTOTAL_B;
	u32 saveTRANS_HBLANK_B;
	u32 saveTRANS_HSYNC_B;
	u32 saveTRANS_VTOTAL_B;
	u32 saveTRANS_VBLANK_B;
	u32 saveTRANS_VSYNC_B;
	u32 savePIPEBSTAT;
	u32 saveDSPBSTRIDE;
	u32 saveDSPBSIZE;
	u32 saveDSPBPOS;
	u32 saveDSPBADDR;
	u32 saveDSPBSURF;
	u32 saveDSPBTILEOFF;
	u32 saveVGA0;
	u32 saveVGA1;
	u32 saveVGA_PD;
	u32 saveVGACNTRL;
	u32 saveADPA;
	u32 saveLVDS;
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
	u32 saveDVOA;
	u32 saveDVOB;
	u32 saveDVOC;
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
	u32 savePP_DIVISOR;
	u32 savePFIT_CONTROL;
	u32 save_palette_a[256];
	u32 save_palette_b[256];
	u32 saveDPFC_CB_BASE;
	u32 saveFBC_CFB_BASE;
	u32 saveFBC_LL_BASE;
	u32 saveFBC_CONTROL;
	u32 saveFBC_CONTROL2;
	u32 saveIER;
	u32 saveIIR;
	u32 saveIMR;
	u32 saveDEIER;
	u32 saveDEIMR;
	u32 saveGTIER;
	u32 saveGTIMR;
	u32 saveFDI_RXA_IMR;
	u32 saveFDI_RXB_IMR;
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
	u8 saveMSR;
	u8 saveSR[8];
	u8 saveGR[25];
	u8 saveAR_INDEX;
	u8 saveAR[21];
	u8 saveDACMASK;
	u8 saveCR[37];
	uint64_t saveFENCE[16];
	u32 saveCURACNTR;
	u32 saveCURAPOS;
	u32 saveCURABASE;
	u32 saveCURBCNTR;
	u32 saveCURBPOS;
	u32 saveCURBBASE;
	u32 saveCURSIZE;
	u32 saveDP_B;
	u32 saveDP_C;
	u32 saveDP_D;
	u32 savePIPEA_GMCH_DATA_M;
	u32 savePIPEB_GMCH_DATA_M;
	u32 savePIPEA_GMCH_DATA_N;
	u32 savePIPEB_GMCH_DATA_N;
	u32 savePIPEA_DP_LINK_M;
	u32 savePIPEB_DP_LINK_M;
	u32 savePIPEA_DP_LINK_N;
	u32 savePIPEB_DP_LINK_N;
	u32 saveFDI_RXA_CTL;
	u32 saveFDI_TXA_CTL;
	u32 saveFDI_RXB_CTL;
	u32 saveFDI_TXB_CTL;
	u32 savePFA_CTL_1;
	u32 savePFB_CTL_1;
	u32 savePFA_WIN_SZ;
	u32 savePFB_WIN_SZ;
	u32 savePFA_WIN_POS;
	u32 savePFB_WIN_POS;
	u32 savePCH_DREF_CONTROL;
	u32 saveDISP_ARB_CTL;
	u32 savePIPEA_DATA_M1;
	u32 savePIPEA_DATA_N1;
	u32 savePIPEA_LINK_M1;
	u32 savePIPEA_LINK_N1;
	u32 savePIPEB_DATA_M1;
	u32 savePIPEB_DATA_N1;
	u32 savePIPEB_LINK_M1;
	u32 savePIPEB_LINK_N1;
	u32 saveMCHBAR_RENDER_STANDBY;
	u32 savePCH_PORT_HOTPLUG;
 
	struct {
		/** Bridge to intel-gtt-ko */
		const struct intel_gtt *gtt;
		/** Memory allocator for GTT stolen memory */
//       struct drm_mm stolen;
		/** Memory allocator for GTT */
//       struct drm_mm gtt_space;
		/** List of all objects in gtt_space. Used to restore gtt
		 * mappings on resume */
		struct list_head gtt_list;
 
		/** Usable portion of the GTT for GEM */
		unsigned long gtt_start;
		unsigned long gtt_mappable_end;
		unsigned long gtt_end;
 
//       struct io_mapping *gtt_mapping;
		int gtt_mtrr;
 
//       struct shrinker inactive_shrinker;
 
		/**
		 * List of objects currently involved in rendering.
		 *
		 * Includes buffers having the contents of their GPU caches
		 * flushed, not necessarily primitives.  last_rendering_seqno
		 * represents when the rendering involved will be completed.
		 *
		 * A reference is held on the buffer while on this list.
		 */
		struct list_head active_list;
 
		/**
		 * List of objects which are not in the ringbuffer but which
		 * still have a write_domain which needs to be flushed before
		 * unbinding.
		 *
		 * last_rendering_seqno is 0 while an object is in this list.
		 *
		 * A reference is held on the buffer while on this list.
		 */
		struct list_head flushing_list;
 
		/**
		 * LRU list of objects which are not in the ringbuffer and
		 * are ready to unbind, but are still in the GTT.
		 *
		 * last_rendering_seqno is 0 while an object is in this list.
		 *
		 * A reference is not held on the buffer while on this list,
		 * as merely being GTT-bound shouldn't prevent its being
		 * freed, and we'll pull it off the list in the free path.
		 */
		struct list_head inactive_list;
 
		/**
		 * LRU list of objects which are not in the ringbuffer but
		 * are still pinned in the GTT.
		 */
		struct list_head pinned_list;
 
		/** LRU list of objects with fence regs on them. */
		struct list_head fence_list;
 
		/**
		 * List of objects currently pending being freed.
		 *
		 * These objects are no longer in use, but due to a signal
		 * we were prevented from freeing them at the appointed time.
		 */
		struct list_head deferred_free_list;
 
		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
//       struct delayed_work retire_work;
 
		/**
		 * Are we in a non-interruptible section of code like
		 * modesetting?
		 */
		bool interruptible;
 
		/**
		 * Flag if the X Server, and thus DRM, is not currently in
		 * control of the device.
		 *
		 * This is set between LeaveVT and EnterVT.  It needs to be
		 * replaced with a semaphore.  It also needs to be
		 * transitioned away from for kernel modesetting.
		 */
		int suspended;
 
		/**
		 * Flag if the hardware appears to be wedged.
		 *
		 * This is set when attempts to idle the device timeout.
		 * It prevents command submission from occurring and makes
		 * every pending request fail
		 */
		atomic_t wedged;
 
		/** Bit 6 swizzling required for X tiling */
		uint32_t bit_6_swizzle_x;
		/** Bit 6 swizzling required for Y tiling */
		uint32_t bit_6_swizzle_y;
 
		/* storage for physical objects */
//       struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 
		/* accounting, useful for userland debugging */
		size_t gtt_total;
		size_t mappable_gtt_total;
		size_t object_memory;
		u32 object_count;
	} mm;
    struct sdvo_device_mapping sdvo_mappings[2];
	/* indicate whether the LVDS_BORDER should be enabled or not */
	unsigned int lvds_border_bits;
	/* Panel fitter placement and size for Ironlake+ */
	u32 pch_pf_pos, pch_pf_size;
	int panel_t3, panel_t12;
 
    struct drm_crtc *plane_to_crtc_mapping[2];
    struct drm_crtc *pipe_to_crtc_mapping[2];
//   wait_queue_head_t pending_flip_queue;
	bool flip_pending_is_done;
 
	/* Reclocking support */
	bool render_reclock_avail;
	bool lvds_downclock_avail;
	/* indicates the reduced downclock for LVDS*/
	int lvds_downclock;
//   struct work_struct idle_work;
//   struct timer_list idle_timer;
	bool busy;
	u16 orig_clock;
	int child_dev_num;
    struct child_device_config *child_dev;
    struct drm_connector *int_lvds_connector;
    struct drm_connector *int_edp_connector;
 
	bool mchbar_need_disable;
 
//   struct work_struct rps_work;
	spinlock_t rps_lock;
	u32 pm_iir;
 
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;
 
	u64 last_count1;
	unsigned long last_time1;
	u64 last_count2;
//   struct timespec last_time2;
	unsigned long gfx_power;
	int c_m;
	int r_t;
	u8 corr;
	spinlock_t *mchdev_lock;
 
//   enum no_fbc_reason no_fbc_reason;
 
//   struct drm_mm_node *compressed_fb;
//   struct drm_mm_node *compressed_llb;
 
	unsigned long last_gpu_reset;
 
	/* list of fbdev register on this device */
//   struct intel_fbdev *fbdev;
 
//   struct backlight_device *backlight;
 
//   struct drm_property *broadcast_rgb_property;
//   struct drm_property *force_audio_property;
 
	atomic_t forcewake_count;
} drm_i915_private_t;
 
enum i915_cache_level {
	I915_CACHE_NONE,
	I915_CACHE_LLC,
	I915_CACHE_LLC_MLC, /* gen6+ */
};
 
struct drm_i915_gem_object {
    struct drm_gem_object base;
 
    /** Current space allocated to this object in the GTT, if any. */
    struct drm_mm_node *gtt_space;
    struct list_head gtt_list;
 
    /** This object's place on the active/flushing/inactive lists */
    struct list_head ring_list;
    struct list_head mm_list;
    /** This object's place on GPU write list */
    struct list_head gpu_write_list;
    /** This object's place in the batchbuffer or on the eviction list */
    struct list_head exec_list;
 
    /**
     * This is set if the object is on the active or flushing lists
     * (has pending rendering), and is not set if it's on inactive (ready
     * to be unbound).
     */
    unsigned int active : 1;
 
    /**
     * This is set if the object has been written to since last bound
     * to the GTT
     */
    unsigned int dirty : 1;
 
    /**
     * This is set if the object has been written to since the last
     * GPU flush.
     */
    unsigned int pending_gpu_write : 1;
 
    /**
     * Fence register bits (if any) for this object.  Will be set
     * as needed when mapped into the GTT.
     * Protected by dev->struct_mutex.
     *
     * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
     */
    signed int fence_reg : 5;
 
    /**
     * Advice: are the backing pages purgeable?
     */
    unsigned int madv : 2;
 
    /**
     * Current tiling mode for the object.
     */
    unsigned int tiling_mode : 2;
    unsigned int tiling_changed : 1;
 
    /** How many users have pinned this object in GTT space. The following
     * users can each hold at most one reference: pwrite/pread, pin_ioctl
     * (via user_pin_count), execbuffer (objects are not allowed multiple
     * times for the same batchbuffer), and the framebuffer code. When
     * switching/pageflipping, the framebuffer code has at most two buffers
     * pinned per crtc.
     *
     * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
     * bits with absolutely no headroom. So use 4 bits. */
    unsigned int pin_count : 4;
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 
    /**
     * Is the object at the current location in the gtt mappable and
     * fenceable? Used to avoid costly recalculations.
     */
    unsigned int map_and_fenceable : 1;
 
    /**
     * Whether the current gtt mapping needs to be mappable (and isn't just
     * mappable by accident). Track pin and fault separate for a more
     * accurate mappable working set.
     */
    unsigned int fault_mappable : 1;
    unsigned int pin_mappable : 1;
 
    /*
     * Is the GPU currently using a fence to access this buffer,
     */
    unsigned int pending_fenced_gpu_access:1;
    unsigned int fenced_gpu_access:1;
 
    unsigned int cache_level:2;
 
    struct page **pages;
 
    /**
     * DMAR support
     */
    struct scatterlist *sg_list;
    int num_sg;
 
    /**
     * Used for performing relocations during execbuffer insertion.
     */
    struct hlist_node exec_node;
    unsigned long exec_handle;
    struct drm_i915_gem_exec_object2 *exec_entry;
 
    /**
     * Current offset of the object in GTT space.
     *
     * This is the same as gtt_space->start
     */
    uint32_t gtt_offset;
 
    /** Breadcrumb of last rendering to the buffer. */
    uint32_t last_rendering_seqno;
    struct intel_ring_buffer *ring;
 
    /** Breadcrumb of last fenced GPU access to the buffer. */
    uint32_t last_fenced_seqno;
    struct intel_ring_buffer *last_fenced_ring;
 
    /** Current tiling stride for the object, if it's tiled. */
    uint32_t stride;
 
    /** Record of address bit 17 of each page at last unbind. */
    unsigned long *bit_17;
 
 
    /**
     * If present, while GEM_DOMAIN_CPU is in the read domain this array
     * flags which individual pages are valid.
     */
    uint8_t *page_cpu_valid;
 
    /** User space pin count and filp owning the pin */
    uint32_t user_pin_count;
    struct drm_file *pin_filp;
 
    /** for phy allocated objects */
    struct drm_i915_gem_phys_object *phys_obj;
 
    /**
     * Number of crtcs where this object is currently the fb, but
     * will be page flipped away on the next vblank.  When it
     * reaches 0, dev_priv->pending_flip_queue will be woken up.
     */
    atomic_t pending_flip;
};
 
 
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
 * By keeping this list, we can avoid having to do questionable
 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 * an emission time with seqnos for tracking how far ahead of the GPU we are.
 */
struct drm_i915_gem_request {
	/** On Which ring this request was generated */
	struct intel_ring_buffer *ring;
 
	/** GEM sequence number associated with this request. */
	uint32_t seqno;
 
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;
 
	/** global list entry for this request */
	struct list_head list;
 
	struct drm_i915_file_private *file_priv;
	/** file_priv list entry for this request */
	struct list_head client_list;
};
 
struct drm_i915_file_private {
	struct {
//       struct spinlock lock;
		struct list_head request_list;
	} mm;
};
 
#define INTEL_INFO(dev)	(((struct drm_i915_private *) (dev)->dev_private)->info)
 
#define IS_I830(dev)		((dev)->pci_device == 0x3577)
#define IS_845G(dev)		((dev)->pci_device == 0x2562)
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
#define IS_I865G(dev)		((dev)->pci_device == 0x2572)
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
#define IS_I915GM(dev)		((dev)->pci_device == 0x2592)
#define IS_I945G(dev)		((dev)->pci_device == 0x2772)
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
#define IS_GM45(dev)		((dev)->pci_device == 0x2A42)
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
#define IS_PINEVIEW_G(dev)	((dev)->pci_device == 0xa001)
#define IS_PINEVIEW_M(dev)	((dev)->pci_device == 0xa011)
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
 
#define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
 
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
/* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 
#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 
//#include "i915_trace.h"
 
extern int i915_max_ioctl;
extern unsigned int i915_fbpercrtc;
extern int i915_panel_ignore_lid;
extern unsigned int i915_powersave;
extern unsigned int i915_semaphores;
extern unsigned int i915_lvds_downclock;
extern unsigned int i915_panel_use_ssc;
extern int i915_vbt_sdvo_panel_type;
extern unsigned int i915_enable_rc6;
extern unsigned int i915_enable_fbc;
extern bool i915_enable_hangcheck;
 
extern int i915_resume(struct drm_device *dev);
extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 
				/* i915_dma.c */
extern void i915_kernel_lost_context(struct drm_device * dev);
extern int i915_driver_load(struct drm_device *, unsigned long flags);
extern int i915_driver_unload(struct drm_device *);
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
extern void i915_driver_lastclose(struct drm_device * dev);
extern void i915_driver_preclose(struct drm_device *dev,
				 struct drm_file *file_priv);
extern void i915_driver_postclose(struct drm_device *dev,
				  struct drm_file *file_priv);
extern int i915_driver_device_is_agp(struct drm_device * dev);
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
extern int i915_emit_box(struct drm_device *dev,
			 struct drm_clip_rect *box,
			 int DR1, int DR4);
extern int i915_reset(struct drm_device *dev, u8 flags);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
 
 
/* i915_irq.c */
void i915_hangcheck_elapsed(unsigned long data);
void i915_handle_error(struct drm_device *dev, bool wedged);
extern int i915_irq_emit(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_irq_wait(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
 
extern void intel_irq_init(struct drm_device *dev);
 
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
 
void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 
void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 
void intel_enable_asle (struct drm_device *dev);
 
#ifdef CONFIG_DEBUG_FS
extern void i915_destroy_error_state(struct drm_device *dev);
#else
#define i915_destroy_error_state(x)
#endif
 
 
/* i915_mem.c */
extern int i915_mem_alloc(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
extern int i915_mem_free(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_mem_init_heap(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
				 struct drm_file *file_priv);
extern void i915_mem_takedown(struct mem_block **heap);
extern void i915_mem_release(struct drm_device * dev,
			     struct drm_file *file_priv, struct mem_block *heap);
/* i915_gem.c */
int i915_gem_init_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv);
int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
void i915_gem_load(struct drm_device *dev);
int i915_gem_init_object(struct drm_gem_object *obj);
int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
				     uint32_t invalidate_domains,
				     uint32_t flush_domains);
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
void i915_gem_free_object(struct drm_gem_object *obj);
int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
				     uint32_t alignment,
				     bool map_and_fenceable);
void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
void i915_gem_lastclose(struct drm_device *dev);
 
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
				    struct intel_ring_buffer *ring,
				    u32 seqno);
 
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
			  uint32_t handle);
/**
 * Returns true if seq1 is later than seq2.
 */
//static inline bool
//i915_seqno_passed(uint32_t seq1, uint32_t seq2)
//{
//   return (int32_t)(seq1 - seq2) >= 0;
//}
 
//static inline u32
//i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
//{
//   drm_i915_private_t *dev_priv = ring->dev->dev_private;
//   return ring->outstanding_lazy_request = dev_priv->next_seqno;
//}
 
/*
void i915_gem_retire_requests(struct drm_device *dev);
void i915_gem_reset(struct drm_device *dev);
void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
					    uint32_t read_domains,
					    uint32_t write_domain);
int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
void i915_gem_do_init(struct drm_device *dev,
		      unsigned long start,
		      unsigned long mappable_end,
		      unsigned long end);
int __must_check i915_gpu_idle(struct drm_device *dev);
int __must_check i915_gem_idle(struct drm_device *dev);
int __must_check i915_add_request(struct intel_ring_buffer *ring,
				  struct drm_file *file,
				  struct drm_i915_gem_request *request);
int __must_check i915_wait_request(struct intel_ring_buffer *ring,
				   uint32_t seqno);
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
				     struct intel_ring_buffer *pipelined);
int i915_gem_attach_phys_object(struct drm_device *dev,
				struct drm_i915_gem_object *obj,
				int id,
				int align);
void i915_gem_detach_phys_object(struct drm_device *dev,
				 struct drm_i915_gem_object *obj);
void i915_gem_free_all_phys_object(struct drm_device *dev);
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 
uint32_t
i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
				    uint32_t size,
				    int tiling_mode);
 
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);
*/
 
/* i915_gem_gtt.c */
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
				enum i915_cache_level cache_level);
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
 
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
					  unsigned alignment, bool mappable);
int __must_check i915_gem_evict_everything(struct drm_device *dev,
					   bool purgeable_only);
int __must_check i915_gem_evict_inactive(struct drm_device *dev,
					 bool purgeable_only);
 
/* i915_gem_tiling.c */
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
 
/* i915_gem_debug.c */
void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
			  const char *where, uint32_t mark);
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
#else
#define i915_verify_lists(dev) 0
#endif
void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
				     int handle);
void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
			  const char *where, uint32_t mark);
 
/* i915_debugfs.c */
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
 
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
 
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
 
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
 
//extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
//{
//   return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
//}
 
extern void intel_i2c_reset(struct drm_device *dev);
 
/* intel_opregion.c */
extern int intel_opregion_setup(struct drm_device *dev);
#ifdef CONFIG_ACPI
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
extern void intel_opregion_asle_intr(struct drm_device *dev);
extern void intel_opregion_gse_intr(struct drm_device *dev);
extern void intel_opregion_enable_asle(struct drm_device *dev);
#else
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
#endif
 
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */
 
/* modesetting */
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
extern bool intel_fbc_enabled(struct drm_device *dev);
extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void ironlake_enable_rc6(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
extern void intel_detect_pch (struct drm_device *dev);
extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 
/* overlay */
#ifdef CONFIG_DEBUG_FS
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
 
extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
extern void intel_display_print_error_state(struct seq_file *m,
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
#endif
 
#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
 
#define BEGIN_LP_RING(n) \
	intel_ring_begin(LP_RING(dev_priv), (n))
 
#define OUT_RING(x) \
	intel_ring_emit(LP_RING(dev_priv), x)
 
#define ADVANCE_LP_RING() \
	intel_ring_advance(LP_RING(dev_priv))
 
/**
 * Lock test for when it's just for synchronization of ring access.
 *
 * In that case, we don't need to do it when GEM is initialized as nobody else
 * has access to the ring.
 */
#define RING_LOCK_TEST_WITH_RETURN(dev, file) do {			\
	if (LP_RING(dev->dev_private)->obj == NULL)			\
		LOCK_TEST_WITH_RETURN(dev, file);			\
} while (0)
 
/* On SNB platform, before reading ring registers forcewake bit
 * must be set to prevent GT core from power down and stale values being
 * returned.
 */
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
 
/* We give fast paths for the really cool registers */
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
	(((dev_priv)->info->gen >= 6) && \
	((reg) < 0x40000) && \
	((reg) != FORCEWAKE))
 
#define __i915_read(x, y) \
static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
	u##x val = 0; \
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		gen6_gt_force_wake_get(dev_priv); \
		val = read##y(dev_priv->regs + reg); \
		gen6_gt_force_wake_put(dev_priv); \
	} else { \
		val = read##y(dev_priv->regs + reg); \
	} \
/*   trace_i915_reg_rw(false, reg, val, sizeof(val)); */\
	return val; \
}
 
__i915_read(8, b)
__i915_read(16, w)
__i915_read(32, l)
__i915_read(64, q)
#undef __i915_read
 
#define __i915_write(x, y) \
static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
/*   trace_i915_reg_rw(true, reg, val, sizeof(val));*/ \
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
		__gen6_gt_wait_for_fifo(dev_priv); \
	} \
	write##y(val, dev_priv->regs + reg); \
}
__i915_write(8, b)
__i915_write(16, w)
__i915_write(32, l)
__i915_write(64, q)
#undef __i915_write
 
#define I915_READ8(reg)		i915_read8(dev_priv, (reg))
#define I915_WRITE8(reg, val)	i915_write8(dev_priv, (reg), (val))
 
#define I915_READ16(reg)	i915_read16(dev_priv, (reg))
#define I915_WRITE16(reg, val)	i915_write16(dev_priv, (reg), (val))
#define I915_READ16_NOTRACE(reg)	readw(dev_priv->regs + (reg))
#define I915_WRITE16_NOTRACE(reg, val)	writew(val, dev_priv->regs + (reg))
 
#define I915_READ(reg)		i915_read32(dev_priv, (reg))
#define I915_WRITE(reg, val)	i915_write32(dev_priv, (reg), (val))
#define I915_READ_NOTRACE(reg)		readl(dev_priv->regs + (reg))
#define I915_WRITE_NOTRACE(reg, val)	writel(val, dev_priv->regs + (reg))
 
#define I915_WRITE64(reg, val)	i915_write64(dev_priv, (reg), (val))
#define I915_READ64(reg)	i915_read64(dev_priv, (reg))
 
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
 
 
#endif
 
struct>
 
struct>
#define>
#define>

Rev 2326	Rev 2327
1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
2	*/	2	*/
3	/*	3	/*
4	*	4	*
5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6	* All Rights Reserved.	6	* All Rights Reserved.
7	*	7	*
8	* Permission is hereby granted, free of charge, to any person obtaining a	8	* Permission is hereby granted, free of charge, to any person obtaining a
9	* copy of this software and associated documentation files (the	9	* copy of this software and associated documentation files (the
10	* "Software"), to deal in the Software without restriction, including	10	* "Software"), to deal in the Software without restriction, including
11	* without limitation the rights to use, copy, modify, merge, publish,	11	* without limitation the rights to use, copy, modify, merge, publish,
12	* distribute, sub license, and/or sell copies of the Software, and to	12	* distribute, sub license, and/or sell copies of the Software, and to
13	* permit persons to whom the Software is furnished to do so, subject to	13	* permit persons to whom the Software is furnished to do so, subject to
14	* the following conditions:	14	* the following conditions:
15	*	15	*
16	* The above copyright notice and this permission notice (including the	16	* The above copyright notice and this permission notice (including the
17	* next paragraph) shall be included in all copies or substantial portions	17	* next paragraph) shall be included in all copies or substantial portions
18	* of the Software.	18	* of the Software.
19	*	19	*
20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27	*	27	*
28	*/	28	*/
29		29
30	#ifndef _I915_DRV_H_	30	#ifndef _I915_DRV_H_
31	#define _I915_DRV_H_	31	#define _I915_DRV_H_
32		32
33	#include "i915_reg.h"	33	#include "i915_reg.h"
34	//#include "intel_bios.h"	34	#include "intel_bios.h"
35	#include "intel_ringbuffer.h"	35	#include "intel_ringbuffer.h"
36	//#include	36	//#include
37	//#include	37	//#include
38	//#include	38	//#include
39	//#include	39	//#include
40		40
41	#include	41	#include
42		42
43	/* General customization:	43	/* General customization:
44	*/	44	*/
-		45
-		46	#define I915_TILING_NONE 0
-		47
45		48
46	#define DRIVER_AUTHOR "Tungsten Graphics, Inc."	49	#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
47		50
48	#define DRIVER_NAME "i915"	51	#define DRIVER_NAME "i915"
49	#define DRIVER_DESC "Intel Graphics"	52	#define DRIVER_DESC "Intel Graphics"
50	#define DRIVER_DATE "20080730"	53	#define DRIVER_DATE "20080730"
51		54
52	enum pipe {	55	enum pipe {
53	PIPE_A = 0,	56	PIPE_A = 0,
54	PIPE_B,	57	PIPE_B,
55	PIPE_C,	58	PIPE_C,
56	I915_MAX_PIPES	59	I915_MAX_PIPES
57	};	60	};
58	#define pipe_name(p) ((p) + 'A')	61	#define pipe_name(p) ((p) + 'A')
59		62
60	enum plane {	63	enum plane {
61	PLANE_A = 0,	64	PLANE_A = 0,
62	PLANE_B,	65	PLANE_B,
63	PLANE_C,	66	PLANE_C,
64	};	67	};
65	#define plane_name(p) ((p) + 'A')	68	#define plane_name(p) ((p) + 'A')
66		69
67	#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU \| I915_GEM_DOMAIN_GTT))	70	#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU \| I915_GEM_DOMAIN_GTT))
68		71
69	#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)	72	#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
70		73
71	/* Interface history:	74	/* Interface history:
72	*	75	*
73	* 1.1: Original.	76	* 1.1: Original.
74	* 1.2: Add Power Management	77	* 1.2: Add Power Management
75	* 1.3: Add vblank support	78	* 1.3: Add vblank support
76	* 1.4: Fix cmdbuffer path, add heap destroy	79	* 1.4: Fix cmdbuffer path, add heap destroy
77	* 1.5: Add vblank pipe configuration	80	* 1.5: Add vblank pipe configuration
78	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank	81	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
79	* - Support vertical blank on secondary display pipe	82	* - Support vertical blank on secondary display pipe
80	*/	83	*/
81	#define DRIVER_MAJOR 1	84	#define DRIVER_MAJOR 1
82	#define DRIVER_MINOR 6	85	#define DRIVER_MINOR 6
83	#define DRIVER_PATCHLEVEL 0	86	#define DRIVER_PATCHLEVEL 0
84		87
85	#define WATCH_COHERENCY 0	88	#define WATCH_COHERENCY 0
86	#define WATCH_LISTS 0	89	#define WATCH_LISTS 0
87		90
88	#define I915_GEM_PHYS_CURSOR_0 1	91	#define I915_GEM_PHYS_CURSOR_0 1
89	#define I915_GEM_PHYS_CURSOR_1 2	92	#define I915_GEM_PHYS_CURSOR_1 2
90	#define I915_GEM_PHYS_OVERLAY_REGS 3	93	#define I915_GEM_PHYS_OVERLAY_REGS 3
91	#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)	94	#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
92		95
93	struct mem_block {	96	struct mem_block {
94	struct mem_block *next;	97	struct mem_block *next;
95	struct mem_block *prev;	98	struct mem_block *prev;
96	int start;	99	int start;
97	int size;	100	int size;
98	struct drm_file file_priv; / NULL: free, -1: heap, other: real files */	101	struct drm_file file_priv; / NULL: free, -1: heap, other: real files */
99	};	102	};
100		103
101	struct opregion_header;	104	struct opregion_header;
102	struct opregion_acpi;	105	struct opregion_acpi;
103	struct opregion_swsci;	106	struct opregion_swsci;
104	struct opregion_asle;	107	struct opregion_asle;
105		108
106	struct intel_opregion {	109	struct intel_opregion {
107	struct opregion_header *header;	110	struct opregion_header *header;
108	struct opregion_acpi *acpi;	111	struct opregion_acpi *acpi;
109	struct opregion_swsci *swsci;	112	struct opregion_swsci *swsci;
110	struct opregion_asle *asle;	113	struct opregion_asle *asle;
111	void *vbt;	114	void *vbt;
112	u32 __iomem *lid_state;	115	u32 __iomem *lid_state;
113	};	116	};
114	#define OPREGION_SIZE (8*1024)	117	#define OPREGION_SIZE (8*1024)
115		118
116	struct intel_overlay;	119	struct intel_overlay;
117	struct intel_overlay_error_state;	120	struct intel_overlay_error_state;
118		121
119		122
120	#define I915_FENCE_REG_NONE -1	123	#define I915_FENCE_REG_NONE -1
121		124
122	struct drm_i915_fence_reg {	125	struct drm_i915_fence_reg {
123	struct list_head lru_list;	126	struct list_head lru_list;
124	struct drm_i915_gem_object *obj;	127	struct drm_i915_gem_object *obj;
125	uint32_t setup_seqno;	128	uint32_t setup_seqno;
126	};	129	};
127		130
128	struct sdvo_device_mapping {	131	struct sdvo_device_mapping {
129	u8 initialized;	132	u8 initialized;
130	u8 dvo_port;	133	u8 dvo_port;
131	u8 slave_addr;	134	u8 slave_addr;
132	u8 dvo_wiring;	135	u8 dvo_wiring;
133	u8 i2c_pin;	136	u8 i2c_pin;
134	u8 i2c_speed;	137	u8 i2c_speed;
135	u8 ddc_pin;	138	u8 ddc_pin;
136	};	139	};
137		140
138	struct intel_display_error_state;	141	struct intel_display_error_state;
139		142
140	struct drm_i915_error_state {	143	struct drm_i915_error_state {
141	u32 eir;	144	u32 eir;
142	u32 pgtbl_er;	145	u32 pgtbl_er;
143	u32 pipestat[I915_MAX_PIPES];	146	u32 pipestat[I915_MAX_PIPES];
144	u32 ipeir;	147	u32 ipeir;
145	u32 ipehr;	148	u32 ipehr;
146	u32 instdone;	149	u32 instdone;
147	u32 acthd;	150	u32 acthd;
148	u32 error; /* gen6+ */	151	u32 error; /* gen6+ */
149	u32 bcs_acthd; /* gen6+ blt engine */	152	u32 bcs_acthd; /* gen6+ blt engine */
150	u32 bcs_ipehr;	153	u32 bcs_ipehr;
151	u32 bcs_ipeir;	154	u32 bcs_ipeir;
152	u32 bcs_instdone;	155	u32 bcs_instdone;
153	u32 bcs_seqno;	156	u32 bcs_seqno;
154	u32 vcs_acthd; /* gen6+ bsd engine */	157	u32 vcs_acthd; /* gen6+ bsd engine */
155	u32 vcs_ipehr;	158	u32 vcs_ipehr;
156	u32 vcs_ipeir;	159	u32 vcs_ipeir;
157	u32 vcs_instdone;	160	u32 vcs_instdone;
158	u32 vcs_seqno;	161	u32 vcs_seqno;
159	u32 instpm;	162	u32 instpm;
160	u32 instps;	163	u32 instps;
161	u32 instdone1;	164	u32 instdone1;
162	u32 seqno;	165	u32 seqno;
163	u64 bbaddr;	166	u64 bbaddr;
164	u64 fence[16];	167	u64 fence[16];
165	struct timeval time;	168	struct timeval time;
166	struct drm_i915_error_object {	169	struct drm_i915_error_object {
167	int page_count;	170	int page_count;
168	u32 gtt_offset;	171	u32 gtt_offset;
169	u32 *pages[0];	172	u32 *pages[0];
170	} ringbuffer[I915_NUM_RINGS], batchbuffer[I915_NUM_RINGS];	173	} ringbuffer[I915_NUM_RINGS], batchbuffer[I915_NUM_RINGS];
171	struct drm_i915_error_buffer {	174	struct drm_i915_error_buffer {
172	u32 size;	175	u32 size;
173	u32 name;	176	u32 name;
174	u32 seqno;	177	u32 seqno;
175	u32 gtt_offset;	178	u32 gtt_offset;
176	u32 read_domains;	179	u32 read_domains;
177	u32 write_domain;	180	u32 write_domain;
178	s32 fence_reg:5;	181	s32 fence_reg:5;
179	s32 pinned:2;	182	s32 pinned:2;
180	u32 tiling:2;	183	u32 tiling:2;
181	u32 dirty:1;	184	u32 dirty:1;
182	u32 purgeable:1;	185	u32 purgeable:1;
183	u32 ring:4;	186	u32 ring:4;
184	u32 cache_level:2;	187	u32 cache_level:2;
185	} active_bo, pinned_bo;	188	} active_bo, pinned_bo;
186	u32 active_bo_count, pinned_bo_count;	189	u32 active_bo_count, pinned_bo_count;
187	struct intel_overlay_error_state *overlay;	190	struct intel_overlay_error_state *overlay;
188	struct intel_display_error_state *display;	191	struct intel_display_error_state *display;
189	};	192	};
190		193
191	struct drm_i915_display_funcs {	194	struct drm_i915_display_funcs {
192	void (dpms)(struct drm_crtc crtc, int mode);	195	void (dpms)(struct drm_crtc crtc, int mode);
193	bool (fbc_enabled)(struct drm_device dev);	196	bool (fbc_enabled)(struct drm_device dev);
194	void (enable_fbc)(struct drm_crtc crtc, unsigned long interval);	197	void (enable_fbc)(struct drm_crtc crtc, unsigned long interval);
195	void (disable_fbc)(struct drm_device dev);	198	void (disable_fbc)(struct drm_device dev);
196	int (get_display_clock_speed)(struct drm_device dev);	199	int (get_display_clock_speed)(struct drm_device dev);
197	int (get_fifo_size)(struct drm_device dev, int plane);	200	int (get_fifo_size)(struct drm_device dev, int plane);
198	void (update_wm)(struct drm_device dev);	201	void (update_wm)(struct drm_device dev);
199	int (crtc_mode_set)(struct drm_crtc crtc,	202	int (crtc_mode_set)(struct drm_crtc crtc,
200	struct drm_display_mode *mode,	203	struct drm_display_mode *mode,
201	struct drm_display_mode *adjusted_mode,	204	struct drm_display_mode *adjusted_mode,
202	int x, int y,	205	int x, int y,
203	struct drm_framebuffer *old_fb);	206	struct drm_framebuffer *old_fb);
204	void (fdi_link_train)(struct drm_crtc crtc);	207	void (fdi_link_train)(struct drm_crtc crtc);
205	void (init_clock_gating)(struct drm_device dev);	208	void (init_clock_gating)(struct drm_device dev);
206	void (init_pch_clock_gating)(struct drm_device dev);	209	void (init_pch_clock_gating)(struct drm_device dev);
207	int (queue_flip)(struct drm_device dev, struct drm_crtc *crtc,	210	int (queue_flip)(struct drm_device dev, struct drm_crtc *crtc,
208	struct drm_framebuffer *fb,	211	struct drm_framebuffer *fb,
209	struct drm_i915_gem_object *obj);	212	struct drm_i915_gem_object *obj);
210	int (update_plane)(struct drm_crtc crtc, struct drm_framebuffer *fb,	213	int (update_plane)(struct drm_crtc crtc, struct drm_framebuffer *fb,
211	int x, int y);	214	int x, int y);
212	/* clock updates for mode set */	215	/* clock updates for mode set */
213	/* cursor updates */	216	/* cursor updates */
214	/* render clock increase/decrease */	217	/* render clock increase/decrease */
215	/* display clock increase/decrease */	218	/* display clock increase/decrease */
216	/* pll clock increase/decrease */	219	/* pll clock increase/decrease */
217	};	220	};
218		221
219	struct intel_device_info {	222	struct intel_device_info {
220	u8 gen;	223	u8 gen;
221	u8 is_mobile : 1;	224	u8 is_mobile : 1;
222	u8 is_i85x : 1;	225	u8 is_i85x : 1;
223	u8 is_i915g : 1;	226	u8 is_i915g : 1;
224	u8 is_i945gm : 1;	227	u8 is_i945gm : 1;
225	u8 is_g33 : 1;	228	u8 is_g33 : 1;
226	u8 need_gfx_hws : 1;	229	u8 need_gfx_hws : 1;
227	u8 is_g4x : 1;	230	u8 is_g4x : 1;
228	u8 is_pineview : 1;	231	u8 is_pineview : 1;
229	u8 is_broadwater : 1;	232	u8 is_broadwater : 1;
230	u8 is_crestline : 1;	233	u8 is_crestline : 1;
231	u8 is_ivybridge : 1;	234	u8 is_ivybridge : 1;
232	u8 has_fbc : 1;	235	u8 has_fbc : 1;
233	u8 has_pipe_cxsr : 1;	236	u8 has_pipe_cxsr : 1;
234	u8 has_hotplug : 1;	237	u8 has_hotplug : 1;
235	u8 cursor_needs_physical : 1;	238	u8 cursor_needs_physical : 1;
236	u8 has_overlay : 1;	239	u8 has_overlay : 1;
237	u8 overlay_needs_physical : 1;	240	u8 overlay_needs_physical : 1;
238	u8 supports_tv : 1;	241	u8 supports_tv : 1;
239	u8 has_bsd_ring : 1;	242	u8 has_bsd_ring : 1;
240	u8 has_blt_ring : 1;	243	u8 has_blt_ring : 1;
241	};	244	};
242		245
243	enum no_fbc_reason {	246	enum no_fbc_reason {
244	FBC_NO_OUTPUT, /* no outputs enabled to compress */	247	FBC_NO_OUTPUT, /* no outputs enabled to compress */
245	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */	248	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
246	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */	249	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
247	FBC_MODE_TOO_LARGE, /* mode too large for compression */	250	FBC_MODE_TOO_LARGE, /* mode too large for compression */
248	FBC_BAD_PLANE, /* fbc not supported on plane */	251	FBC_BAD_PLANE, /* fbc not supported on plane */
249	FBC_NOT_TILED, /* buffer not tiled */	252	FBC_NOT_TILED, /* buffer not tiled */
250	FBC_MULTIPLE_PIPES, /* more than one pipe active */	253	FBC_MULTIPLE_PIPES, /* more than one pipe active */
251	FBC_MODULE_PARAM,	254	FBC_MODULE_PARAM,
252	};	255	};
253		256
254	enum intel_pch {	257	enum intel_pch {
255	PCH_IBX, /* Ibexpeak PCH */	258	PCH_IBX, /* Ibexpeak PCH */
256	PCH_CPT, /* Cougarpoint PCH */	259	PCH_CPT, /* Cougarpoint PCH */
257	};	260	};
258		261
259	#define QUIRK_PIPEA_FORCE (1<<0)	262	#define QUIRK_PIPEA_FORCE (1<<0)
260	#define QUIRK_LVDS_SSC_DISABLE (1<<1)	263	#define QUIRK_LVDS_SSC_DISABLE (1<<1)
261		264
262	struct intel_fbdev;	265	struct intel_fbdev;
263	struct intel_fbc_work;	266	struct intel_fbc_work;
264		267
265		268
266	typedef struct drm_i915_private {	269	typedef struct drm_i915_private {
267	struct drm_device *dev;	270	struct drm_device *dev;
268		271
269	const struct intel_device_info *info;	272	const struct intel_device_info *info;
270		273
271	int has_gem;	274	int has_gem;
272	int relative_constants_mode;	275	int relative_constants_mode;
273		276
274	void __iomem *regs;	277	void __iomem *regs;
275	u32 gt_fifo_count;	278	u32 gt_fifo_count;
276		279
277	struct intel_gmbus {	280	struct intel_gmbus {
278	struct i2c_adapter adapter;	281	struct i2c_adapter adapter;
279	struct i2c_adapter *force_bit;	282	struct i2c_adapter *force_bit;
280	u32 reg0;	283	u32 reg0;
281	} *gmbus;	284	} *gmbus;
282		285
283	struct pci_dev *bridge_dev;	286	struct pci_dev *bridge_dev;
284	struct intel_ring_buffer ring[I915_NUM_RINGS];	287	struct intel_ring_buffer ring[I915_NUM_RINGS];
285	uint32_t next_seqno;	288	uint32_t next_seqno;
286		289
287	drm_dma_handle_t *status_page_dmah;	290	drm_dma_handle_t *status_page_dmah;
288	// uint32_t counter;	291	// uint32_t counter;
289	// drm_local_map_t hws_map;	292	// drm_local_map_t hws_map;
290	// struct drm_i915_gem_object *pwrctx;	293	// struct drm_i915_gem_object *pwrctx;
291	// struct drm_i915_gem_object *renderctx;	294	// struct drm_i915_gem_object *renderctx;
292		295
293	// struct resource mch_res;	296	// struct resource mch_res;
294		297
295	unsigned int cpp;	298	unsigned int cpp;
296	int back_offset;	299	int back_offset;
297	int front_offset;	300	int front_offset;
298	int current_page;	301	int current_page;
299	int page_flipping;	302	int page_flipping;
300		303
301	atomic_t irq_received;	304	atomic_t irq_received;
302		305
303	/* protects the irq masks */	306	/* protects the irq masks */
304	spinlock_t irq_lock;	307	spinlock_t irq_lock;
305	/** Cached value of IMR to avoid reads in updating the bitfield */	308	/** Cached value of IMR to avoid reads in updating the bitfield */
306	u32 pipestat[2];	309	u32 pipestat[2];
307	u32 irq_mask;	310	u32 irq_mask;
308	u32 gt_irq_mask;	311	u32 gt_irq_mask;
309	u32 pch_irq_mask;	312	u32 pch_irq_mask;
310		313
311	u32 hotplug_supported_mask;	314	u32 hotplug_supported_mask;
312	// struct work_struct hotplug_work;	315	// struct work_struct hotplug_work;
313		316
314	int tex_lru_log_granularity;	317	int tex_lru_log_granularity;
315	int allow_batchbuffer;	318	int allow_batchbuffer;
316	struct mem_block *agp_heap;	319	struct mem_block *agp_heap;
317	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;	320	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
318	int vblank_pipe;	321	int vblank_pipe;
319	int num_pipe;	322	int num_pipe;
320		323
321	/* For hangcheck timer */	324	/* For hangcheck timer */
322	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */	325	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
323	// struct timer_list hangcheck_timer;	326	// struct timer_list hangcheck_timer;
324	int hangcheck_count;	327	int hangcheck_count;
325	uint32_t last_acthd;	328	uint32_t last_acthd;
326	uint32_t last_instdone;	329	uint32_t last_instdone;
327	uint32_t last_instdone1;	330	uint32_t last_instdone1;
328		331
329	unsigned long cfb_size;	332	unsigned long cfb_size;
330	unsigned int cfb_fb;	333	unsigned int cfb_fb;
331	enum plane cfb_plane;	334	enum plane cfb_plane;
332	int cfb_y;	335	int cfb_y;
333	// struct intel_fbc_work *fbc_work;	336	// struct intel_fbc_work *fbc_work;
334		337
335	// struct intel_opregion opregion;	338	struct intel_opregion opregion;
336		339
337	/* overlay */	340	/* overlay */
338	// struct intel_overlay *overlay;	341	// struct intel_overlay *overlay;
339		342
340	/* LVDS info */	343	/* LVDS info */
341	int backlight_level; /* restore backlight to this value */	344	int backlight_level; /* restore backlight to this value */
342	bool backlight_enabled;	345	bool backlight_enabled;
343	struct drm_display_mode *panel_fixed_mode;	346	struct drm_display_mode *panel_fixed_mode;
344	struct drm_display_mode lfp_lvds_vbt_mode; / if any */	347	struct drm_display_mode lfp_lvds_vbt_mode; / if any */
345	struct drm_display_mode sdvo_lvds_vbt_mode; / if any */	348	struct drm_display_mode sdvo_lvds_vbt_mode; / if any */
346		349
347	/* Feature bits from the VBIOS */	350	/* Feature bits from the VBIOS */
348	unsigned int int_tv_support:1;	351	unsigned int int_tv_support:1;
349	unsigned int lvds_dither:1;	352	unsigned int lvds_dither:1;
350	unsigned int lvds_vbt:1;	353	unsigned int lvds_vbt:1;
351	unsigned int int_crt_support:1;	354	unsigned int int_crt_support:1;
352	unsigned int lvds_use_ssc:1;	355	unsigned int lvds_use_ssc:1;
353	int lvds_ssc_freq;	356	int lvds_ssc_freq;
354	struct {	357	struct {
355	int rate;	358	int rate;
356	int lanes;	359	int lanes;
357	int preemphasis;	360	int preemphasis;
358	int vswing;	361	int vswing;
359		362
360	bool initialized;	363	bool initialized;
361	bool support;	364	bool support;
362	int bpp;	365	int bpp;
363	// struct edp_power_seq pps;	366	struct edp_power_seq pps;
364	} edp;	367	} edp;
365	bool no_aux_handshake;	368	bool no_aux_handshake;
366		369
367	// struct notifier_block lid_notifier;	370	// struct notifier_block lid_notifier;
368		371
369	int crt_ddc_pin;	372	int crt_ddc_pin;
370	struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */	373	struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
371	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */	374	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
372	int num_fence_regs; /* 8 on pre-965, 16 otherwise */	375	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
373		376
374	unsigned int fsb_freq, mem_freq, is_ddr3;	377	unsigned int fsb_freq, mem_freq, is_ddr3;
375		378
376	spinlock_t error_lock;	379	spinlock_t error_lock;
377	// struct drm_i915_error_state *first_error;	380	// struct drm_i915_error_state *first_error;
378	// struct work_struct error_work;	381	// struct work_struct error_work;
379	// struct completion error_completion;	382	// struct completion error_completion;
380	// struct workqueue_struct *wq;	383	// struct workqueue_struct *wq;
381		384
382	/* Display functions */	385	/* Display functions */
383	// struct drm_i915_display_funcs display;	386	struct drm_i915_display_funcs display;
384		387
385	/* PCH chipset type */	388	/* PCH chipset type */
386	enum intel_pch pch_type;	389	enum intel_pch pch_type;
387		390
388	unsigned long quirks;	391	unsigned long quirks;
389		392
390	/* Register state */	393	/* Register state */
391	bool modeset_on_lid;	394	bool modeset_on_lid;
392	u8 saveLBB;	395	u8 saveLBB;
393	u32 saveDSPACNTR;	396	u32 saveDSPACNTR;
394	u32 saveDSPBCNTR;	397	u32 saveDSPBCNTR;
395	u32 saveDSPARB;	398	u32 saveDSPARB;
396	u32 saveHWS;	399	u32 saveHWS;
397	u32 savePIPEACONF;	400	u32 savePIPEACONF;
398	u32 savePIPEBCONF;	401	u32 savePIPEBCONF;
399	u32 savePIPEASRC;	402	u32 savePIPEASRC;
400	u32 savePIPEBSRC;	403	u32 savePIPEBSRC;
401	u32 saveFPA0;	404	u32 saveFPA0;
402	u32 saveFPA1;	405	u32 saveFPA1;
403	u32 saveDPLL_A;	406	u32 saveDPLL_A;
404	u32 saveDPLL_A_MD;	407	u32 saveDPLL_A_MD;
405	u32 saveHTOTAL_A;	408	u32 saveHTOTAL_A;
406	u32 saveHBLANK_A;	409	u32 saveHBLANK_A;
407	u32 saveHSYNC_A;	410	u32 saveHSYNC_A;
408	u32 saveVTOTAL_A;	411	u32 saveVTOTAL_A;
409	u32 saveVBLANK_A;	412	u32 saveVBLANK_A;
410	u32 saveVSYNC_A;	413	u32 saveVSYNC_A;
411	u32 saveBCLRPAT_A;	414	u32 saveBCLRPAT_A;
412	u32 saveTRANSACONF;	415	u32 saveTRANSACONF;
413	u32 saveTRANS_HTOTAL_A;	416	u32 saveTRANS_HTOTAL_A;
414	u32 saveTRANS_HBLANK_A;	417	u32 saveTRANS_HBLANK_A;
415	u32 saveTRANS_HSYNC_A;	418	u32 saveTRANS_HSYNC_A;
416	u32 saveTRANS_VTOTAL_A;	419	u32 saveTRANS_VTOTAL_A;
417	u32 saveTRANS_VBLANK_A;	420	u32 saveTRANS_VBLANK_A;
418	u32 saveTRANS_VSYNC_A;	421	u32 saveTRANS_VSYNC_A;
419	u32 savePIPEASTAT;	422	u32 savePIPEASTAT;
420	u32 saveDSPASTRIDE;	423	u32 saveDSPASTRIDE;
421	u32 saveDSPASIZE;	424	u32 saveDSPASIZE;
422	u32 saveDSPAPOS;	425	u32 saveDSPAPOS;
423	u32 saveDSPAADDR;	426	u32 saveDSPAADDR;
424	u32 saveDSPASURF;	427	u32 saveDSPASURF;
425	u32 saveDSPATILEOFF;	428	u32 saveDSPATILEOFF;
426	u32 savePFIT_PGM_RATIOS;	429	u32 savePFIT_PGM_RATIOS;
427	u32 saveBLC_HIST_CTL;	430	u32 saveBLC_HIST_CTL;
428	u32 saveBLC_PWM_CTL;	431	u32 saveBLC_PWM_CTL;
429	u32 saveBLC_PWM_CTL2;	432	u32 saveBLC_PWM_CTL2;
430	u32 saveBLC_CPU_PWM_CTL;	433	u32 saveBLC_CPU_PWM_CTL;
431	u32 saveBLC_CPU_PWM_CTL2;	434	u32 saveBLC_CPU_PWM_CTL2;
432	u32 saveFPB0;	435	u32 saveFPB0;
433	u32 saveFPB1;	436	u32 saveFPB1;
434	u32 saveDPLL_B;	437	u32 saveDPLL_B;
435	u32 saveDPLL_B_MD;	438	u32 saveDPLL_B_MD;
436	u32 saveHTOTAL_B;	439	u32 saveHTOTAL_B;
437	u32 saveHBLANK_B;	440	u32 saveHBLANK_B;
438	u32 saveHSYNC_B;	441	u32 saveHSYNC_B;
439	u32 saveVTOTAL_B;	442	u32 saveVTOTAL_B;
440	u32 saveVBLANK_B;	443	u32 saveVBLANK_B;
441	u32 saveVSYNC_B;	444	u32 saveVSYNC_B;
442	u32 saveBCLRPAT_B;	445	u32 saveBCLRPAT_B;
443	u32 saveTRANSBCONF;	446	u32 saveTRANSBCONF;
444	u32 saveTRANS_HTOTAL_B;	447	u32 saveTRANS_HTOTAL_B;
445	u32 saveTRANS_HBLANK_B;	448	u32 saveTRANS_HBLANK_B;
446	u32 saveTRANS_HSYNC_B;	449	u32 saveTRANS_HSYNC_B;
447	u32 saveTRANS_VTOTAL_B;	450	u32 saveTRANS_VTOTAL_B;
448	u32 saveTRANS_VBLANK_B;	451	u32 saveTRANS_VBLANK_B;
449	u32 saveTRANS_VSYNC_B;	452	u32 saveTRANS_VSYNC_B;
450	u32 savePIPEBSTAT;	453	u32 savePIPEBSTAT;
451	u32 saveDSPBSTRIDE;	454	u32 saveDSPBSTRIDE;
452	u32 saveDSPBSIZE;	455	u32 saveDSPBSIZE;
453	u32 saveDSPBPOS;	456	u32 saveDSPBPOS;
454	u32 saveDSPBADDR;	457	u32 saveDSPBADDR;
455	u32 saveDSPBSURF;	458	u32 saveDSPBSURF;
456	u32 saveDSPBTILEOFF;	459	u32 saveDSPBTILEOFF;
457	u32 saveVGA0;	460	u32 saveVGA0;
458	u32 saveVGA1;	461	u32 saveVGA1;
459	u32 saveVGA_PD;	462	u32 saveVGA_PD;
460	u32 saveVGACNTRL;	463	u32 saveVGACNTRL;
461	u32 saveADPA;	464	u32 saveADPA;
462	u32 saveLVDS;	465	u32 saveLVDS;
463	u32 savePP_ON_DELAYS;	466	u32 savePP_ON_DELAYS;
464	u32 savePP_OFF_DELAYS;	467	u32 savePP_OFF_DELAYS;
465	u32 saveDVOA;	468	u32 saveDVOA;
466	u32 saveDVOB;	469	u32 saveDVOB;
467	u32 saveDVOC;	470	u32 saveDVOC;
468	u32 savePP_ON;	471	u32 savePP_ON;
469	u32 savePP_OFF;	472	u32 savePP_OFF;
470	u32 savePP_CONTROL;	473	u32 savePP_CONTROL;
471	u32 savePP_DIVISOR;	474	u32 savePP_DIVISOR;
472	u32 savePFIT_CONTROL;	475	u32 savePFIT_CONTROL;
473	u32 save_palette_a[256];	476	u32 save_palette_a[256];
474	u32 save_palette_b[256];	477	u32 save_palette_b[256];
475	u32 saveDPFC_CB_BASE;	478	u32 saveDPFC_CB_BASE;
476	u32 saveFBC_CFB_BASE;	479	u32 saveFBC_CFB_BASE;
477	u32 saveFBC_LL_BASE;	480	u32 saveFBC_LL_BASE;
478	u32 saveFBC_CONTROL;	481	u32 saveFBC_CONTROL;
479	u32 saveFBC_CONTROL2;	482	u32 saveFBC_CONTROL2;
480	u32 saveIER;	483	u32 saveIER;
481	u32 saveIIR;	484	u32 saveIIR;
482	u32 saveIMR;	485	u32 saveIMR;
483	u32 saveDEIER;	486	u32 saveDEIER;
484	u32 saveDEIMR;	487	u32 saveDEIMR;
485	u32 saveGTIER;	488	u32 saveGTIER;
486	u32 saveGTIMR;	489	u32 saveGTIMR;
487	u32 saveFDI_RXA_IMR;	490	u32 saveFDI_RXA_IMR;
488	u32 saveFDI_RXB_IMR;	491	u32 saveFDI_RXB_IMR;
489	u32 saveCACHE_MODE_0;	492	u32 saveCACHE_MODE_0;
490	u32 saveMI_ARB_STATE;	493	u32 saveMI_ARB_STATE;
491	u32 saveSWF0[16];	494	u32 saveSWF0[16];
492	u32 saveSWF1[16];	495	u32 saveSWF1[16];
493	u32 saveSWF2[3];	496	u32 saveSWF2[3];
494	u8 saveMSR;	497	u8 saveMSR;
495	u8 saveSR[8];	498	u8 saveSR[8];
496	u8 saveGR[25];	499	u8 saveGR[25];
497	u8 saveAR_INDEX;	500	u8 saveAR_INDEX;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_drv.h – Rev 2326 → 2327