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Line 31... Line 31...
31 
#include
31 
#include
32 
#include
32 
#include
33 
#include "i915_drv.h"
 33 
#include "i915_drv.h"
34 
#include "intel_drv.h"
 34 
#include "intel_drv.h"
Line 35... Line -...
35 
 
 - 
 
36 
 
 35 
 
37 
#include
36 
#include
38 
#include
37 
#include
39 
#include
38 
#include
40 
#include
39 
#include
Line 382... Line 381...
382 
     * underneath. This is a requirement from virtualization team.
 381 
     * underneath. This is a requirement from virtualization team.
383 
     */
 382 
     */
384 
    pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 383 
    pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
385 
    if (pch) {
 384 
    if (pch) {
386 
        if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 385 
        if (pch->vendor == PCI_VENDOR_ID_INTEL) {
387 
            int id;
 386 
			unsigned short id;
388 
            id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 387 
            id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
- 
 
 388 
			dev_priv->pch_id = id;
Line 389... Line 389...
389 
 
 389 
 
390 
            if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 390 
            if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
391 
                dev_priv->pch_type = PCH_IBX;
 391 
                dev_priv->pch_type = PCH_IBX;
392 
				dev_priv->num_pch_pll = 2;
 392 
				dev_priv->num_pch_pll = 2;
- 
 
 393 
                DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
393 
                DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 394 
				WARN_ON(!IS_GEN5(dev));
394 
            } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 395 
            } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
395 
                dev_priv->pch_type = PCH_CPT;
 396 
                dev_priv->pch_type = PCH_CPT;
396 
				dev_priv->num_pch_pll = 2;
 397 
				dev_priv->num_pch_pll = 2;
- 
 
 398 
                DRM_DEBUG_KMS("Found CougarPoint PCH\n");
397 
                DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 399 
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
398 
            } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 400 
            } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
399 
                /* PantherPoint is CPT compatible */
 401 
                /* PantherPoint is CPT compatible */
400 
                dev_priv->pch_type = PCH_CPT;
 402 
                dev_priv->pch_type = PCH_CPT;
401 
				dev_priv->num_pch_pll = 2;
 403 
				dev_priv->num_pch_pll = 2;
- 
 
 404 
                DRM_DEBUG_KMS("Found PatherPoint PCH\n");
402 
                DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 405 
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
403 
			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 406 
			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
404 
				dev_priv->pch_type = PCH_LPT;
 407 
				dev_priv->pch_type = PCH_LPT;
405 
				dev_priv->num_pch_pll = 0;
 408 
				dev_priv->num_pch_pll = 0;
- 
 
 409 
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
- 
 
 410 
				WARN_ON(!IS_HASWELL(dev));
- 
 
 411 
			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
- 
 
 412 
				dev_priv->pch_type = PCH_LPT;
- 
 
 413 
				dev_priv->num_pch_pll = 0;
- 
 
 414 
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
406 
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 415 
				WARN_ON(!IS_HASWELL(dev));
407 
            }
 416 
            }
408 
			BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 417 
			BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
409 
        }
 418 
        }
410 
    }
 419 
    }
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447 
    };
 456 
    };
Line 448... Line 457...
448 
 
 457 
 
449 
    struct intel_device_info *intel_info =
 458 
    struct intel_device_info *intel_info =
Line 450... Line 459...
450 
        (struct intel_device_info *) ent->driver_data;
 459 
        (struct intel_device_info *) ent->driver_data;
451 
 
 460 
 
452 
    if (intel_info->is_haswell || intel_info->is_valleyview)
 461 
	if (intel_info->is_valleyview)
453 
        if(!i915_preliminary_hw_support) {
 462 
        if(!i915_preliminary_hw_support) {
454 
            DRM_ERROR("Preliminary hardware support disabled\n");
 463 
            DRM_ERROR("Preliminary hardware support disabled\n");
Line 471... Line 480...
471 
}
 480 
}
Line 472... Line 481...
472 
 
 481 
 
473 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
 482 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
474 
{
 483 
{
- 
 
 484 
    struct drm_device *dev;
- 
 
 485 
    static struct drm_driver driver;
475 
    struct drm_device *dev;
 486 
 
Line 476... Line 487...
476 
    int ret;
 487 
    int ret;
477 
 
 488 
 
478 
    dev = kzalloc(sizeof(*dev), 0);
 489 
    dev = kzalloc(sizeof(*dev), 0);
Line 501... Line 512...
501 
 
 512 
 
502 
    spin_lock_init(&dev->count_lock);
 513 
    spin_lock_init(&dev->count_lock);
503 
    mutex_init(&dev->struct_mutex);
 514 
    mutex_init(&dev->struct_mutex);
Line -... Line 515...
- 
 
 515 
    mutex_init(&dev->ctxlist_mutex);
- 
 
 516 
 
504 
    mutex_init(&dev->ctxlist_mutex);
 517 
    dev->driver = &driver;
Line 505... Line 518...
505 
 
 518 
 
506 
    ret = i915_driver_load(dev, ent->driver_data );
 519 
    ret = i915_driver_load(dev, ent->driver_data );
Line 607... Line 620...
607 
		return false;
 620 
		return false;
Line 608... Line 621...
608 
 
 621 
 
609 
	if (reg == GEN6_GDRST)
 622 
	if (reg == GEN6_GDRST)
Line -... Line 623...
- 
 
 623 
		return false;
- 
 
 624 
 
- 
 
 625 
	switch (reg) {
- 
 
 626 
	case _3D_CHICKEN3:
- 
 
 627 
	case IVB_CHICKEN3:
- 
 
 628 
	case GEN7_COMMON_SLICE_CHICKEN1:
- 
 
 629 
	case GEN7_L3CNTLREG1:
- 
 
 630 
	case GEN7_L3_CHICKEN_MODE_REGISTER:
- 
 
 631 
	case GEN7_ROW_CHICKEN2:
- 
 
 632 
	case GEN7_L3SQCREG4:
- 
 
 633 
	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
- 
 
 634 
	case GEN7_HALF_SLICE_CHICKEN1:
- 
 
 635 
	case GEN6_MBCTL:
- 
 
 636 
	case GEN6_UCGCTL2:
- 
 
 637 
		return false;
- 
 
 638 
	default:
- 
 
 639 
		break;
610 
		return false;
 640 
	}
611 
 
 641 
 
Line -... Line 642...
- 
 
 642 
	return true;
- 
 
 643 
}
- 
 
 644 
 
- 
 
 645 
static void
- 
 
 646 
ilk_dummy_write(struct drm_i915_private *dev_priv)
- 
 
 647 
{
- 
 
 648 
	/* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
- 
 
 649 
	 * chip from rc6 before touching it for real. MI_MODE is masked, hence
- 
 
 650 
	 * harmless to write 0 into. */
612 
	return true;
 651 
	I915_WRITE_NOTRACE(MI_MODE, 0);
613 
}
 652 
}
614 
 
 653 
 
- 
 
 654 
#define __i915_read(x, y) \
- 
 
 655 
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
615 
#define __i915_read(x, y) \
 656 
	u##x val = 0; \
616 
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 657 
	if (IS_GEN5(dev_priv->dev)) \
617 
	u##x val = 0; \
 658 
		ilk_dummy_write(dev_priv); \
618 
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 659 
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
619 
		unsigned long irqflags; \
 660 
		unsigned long irqflags; \
Line 643... Line 684...
643 
	u32 __fifo_ret = 0; \
 684 
	u32 __fifo_ret = 0; \
644 
	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 685 
	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
645 
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 686 
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
646 
		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 687 
		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
647 
	} \
 688 
	} \
- 
 
 689 
	if (IS_GEN5(dev_priv->dev)) \
- 
 
 690 
		ilk_dummy_write(dev_priv); \
- 
 
 691 
	if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
- 
 
 692 
		DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
- 
 
 693 
		I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
- 
 
 694 
	} \
648 
	if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
 695 
	if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
649 
		write##y(val, dev_priv->regs + reg + 0x180000);		\
 696 
		write##y(val, dev_priv->regs + reg + 0x180000);		\
650 
	} else {							\
 697 
	} else {							\
651 
	write##y(val, dev_priv->regs + reg); \
 698 
	write##y(val, dev_priv->regs + reg); \
652 
	}								\
 699 
	}								\