Rev 2352 | Rev 3037 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2352 | Rev 3031 | ||
---|---|---|---|
Line 26... | Line 26... | ||
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * |
27 | * |
28 | */ |
28 | */ |
Line 29... | Line 29... | ||
29 | 29 | ||
30 | //#include |
30 | //#include |
31 | #include "drmP.h" |
- | |
32 | #include "drm.h" |
31 | #include |
33 | #include "i915_drm.h" |
32 | #include |
34 | #include "i915_drv.h" |
33 | #include "i915_drv.h" |
Line 35... | Line 34... | ||
35 | #include "intel_drv.h" |
34 | #include "intel_drv.h" |
36 | 35 | ||
37 | 36 | ||
38 | #include |
37 | #include |
39 | #include |
38 | #include |
Line -... | Line 39... | ||
- | 39 | #include |
|
- | 40 | #include |
|
40 | #include |
41 | #include |
Line 41... | Line 42... | ||
41 | #include |
42 | |
Line 42... | Line 43... | ||
42 | #include |
43 | #include |
Line 43... | Line 44... | ||
43 | 44 | ||
Line -... | Line 45... | ||
- | 45 | #include |
|
- | 46 | ||
- | 47 | #define __read_mostly |
|
- | 48 | ||
- | 49 | int init_display_kms(struct drm_device *dev); |
|
- | 50 | ||
44 | #include |
51 | struct drm_device *main_device; |
- | 52 | ||
- | 53 | static int i915_modeset __read_mostly = 1; |
|
- | 54 | MODULE_PARM_DESC(modeset, |
|
Line 45... | Line 55... | ||
45 | 55 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
|
- | 56 | "1=on, -1=force vga console preference [default])"); |
|
- | 57 | ||
Line 46... | Line 58... | ||
46 | #define __read_mostly |
58 | |
Line -... | Line 59... | ||
- | 59 | int i915_panel_ignore_lid __read_mostly = 0; |
|
47 | 60 | MODULE_PARM_DESC(panel_ignore_lid, |
|
Line -... | Line 61... | ||
- | 61 | "Override lid status (0=autodetect [default], 1=lid open, " |
|
- | 62 | "-1=lid closed)"); |
|
- | 63 | ||
- | 64 | unsigned int i915_powersave __read_mostly = 0; |
|
- | 65 | MODULE_PARM_DESC(powersave, |
|
- | 66 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); |
|
- | 67 | ||
- | 68 | int i915_semaphores __read_mostly = -1; |
|
48 | int init_display_kms(struct drm_device *dev); |
69 | |
- | 70 | MODULE_PARM_DESC(semaphores, |
|
- | 71 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
|
- | 72 | ||
Line -... | Line 73... | ||
- | 73 | int i915_enable_rc6 __read_mostly = 0; |
|
- | 74 | MODULE_PARM_DESC(i915_enable_rc6, |
|
- | 75 | "Enable power-saving render C-state 6. " |
|
- | 76 | "Different stages can be selected via bitmask values " |
|
- | 77 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " |
|
- | 78 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " |
|
- | 79 | "default: -1 (use per-chip default)"); |
|
- | 80 | ||
- | 81 | int i915_enable_fbc __read_mostly = 0; |
|
- | 82 | MODULE_PARM_DESC(i915_enable_fbc, |
|
49 | 83 | "Enable frame buffer compression for power savings " |
|
- | 84 | "(default: -1 (use per-chip default))"); |
|
- | 85 | ||
- | 86 | unsigned int i915_lvds_downclock __read_mostly = 0; |
|
Line 50... | Line 87... | ||
50 | struct drm_device *main_device; |
87 | MODULE_PARM_DESC(lvds_downclock, |
- | 88 | "Use panel (LVDS/eDP) downclocking for power savings " |
|
- | 89 | "(default: false)"); |
|
- | 90 | ||
- | 91 | int i915_lvds_channel_mode __read_mostly; |
|
- | 92 | MODULE_PARM_DESC(lvds_channel_mode, |
|
- | 93 | "Specify LVDS channel mode " |
|
- | 94 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); |
|
- | 95 | ||
- | 96 | int i915_panel_use_ssc __read_mostly = -1; |
|
- | 97 | MODULE_PARM_DESC(lvds_use_ssc, |
|
- | 98 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " |
|
- | 99 | "(default: auto from VBT)"); |
|
- | 100 | ||
- | 101 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
|
- | 102 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
|
- | 103 | "Override/Ignore selection of SDVO panel mode in the VBT " |
|
- | 104 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); |
|
- | 105 | ||
- | 106 | static bool i915_try_reset __read_mostly = true; |
|
- | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
|
- | 108 | ||
- | 109 | bool i915_enable_hangcheck __read_mostly = false; |
|
- | 110 | MODULE_PARM_DESC(enable_hangcheck, |
|
Line 51... | Line 111... | ||
51 | 111 | "Periodically check GPU activity for detecting hangs. " |
|
Line 52... | Line 112... | ||
52 | int i915_panel_ignore_lid __read_mostly = 0; |
112 | "WARNING: Disabling this can cause system wide hangs. " |
53 | 113 | "(default: true)"); |
|
Line 135... | Line 195... | ||
135 | .has_overlay = 1, |
195 | .has_overlay = 1, |
136 | }; |
196 | }; |
Line 137... | Line 197... | ||
137 | 197 | ||
138 | static const struct intel_device_info intel_ironlake_d_info = { |
198 | static const struct intel_device_info intel_ironlake_d_info = { |
139 | .gen = 5, |
199 | .gen = 5, |
140 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
200 | .need_gfx_hws = 1, .has_hotplug = 1, |
141 | .has_bsd_ring = 1, |
201 | .has_bsd_ring = 1, |
Line 142... | Line 202... | ||
142 | }; |
202 | }; |
143 | 203 | ||
Line 151... | Line 211... | ||
151 | static const struct intel_device_info intel_sandybridge_d_info = { |
211 | static const struct intel_device_info intel_sandybridge_d_info = { |
152 | .gen = 6, |
212 | .gen = 6, |
153 | .need_gfx_hws = 1, .has_hotplug = 1, |
213 | .need_gfx_hws = 1, .has_hotplug = 1, |
154 | .has_bsd_ring = 1, |
214 | .has_bsd_ring = 1, |
155 | .has_blt_ring = 1, |
215 | .has_blt_ring = 1, |
- | 216 | .has_llc = 1, |
|
- | 217 | .has_force_wake = 1, |
|
156 | }; |
218 | }; |
Line 157... | Line 219... | ||
157 | 219 | ||
158 | static const struct intel_device_info intel_sandybridge_m_info = { |
220 | static const struct intel_device_info intel_sandybridge_m_info = { |
159 | .gen = 6, .is_mobile = 1, |
221 | .gen = 6, .is_mobile = 1, |
160 | .need_gfx_hws = 1, .has_hotplug = 1, |
222 | .need_gfx_hws = 1, .has_hotplug = 1, |
161 | .has_fbc = 1, |
223 | .has_fbc = 1, |
162 | .has_bsd_ring = 1, |
224 | .has_bsd_ring = 1, |
- | 225 | .has_blt_ring = 1, |
|
- | 226 | .has_llc = 1, |
|
163 | .has_blt_ring = 1, |
227 | .has_force_wake = 1, |
Line 164... | Line 228... | ||
164 | }; |
228 | }; |
165 | 229 | ||
166 | static const struct intel_device_info intel_ivybridge_d_info = { |
230 | static const struct intel_device_info intel_ivybridge_d_info = { |
167 | .is_ivybridge = 1, .gen = 7, |
231 | .is_ivybridge = 1, .gen = 7, |
168 | .need_gfx_hws = 1, .has_hotplug = 1, |
232 | .need_gfx_hws = 1, .has_hotplug = 1, |
- | 233 | .has_bsd_ring = 1, |
|
- | 234 | .has_blt_ring = 1, |
|
169 | .has_bsd_ring = 1, |
235 | .has_llc = 1, |
Line 170... | Line 236... | ||
170 | .has_blt_ring = 1, |
236 | .has_force_wake = 1, |
171 | }; |
237 | }; |
172 | 238 | ||
173 | static const struct intel_device_info intel_ivybridge_m_info = { |
239 | static const struct intel_device_info intel_ivybridge_m_info = { |
174 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
240 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
175 | .need_gfx_hws = 1, .has_hotplug = 1, |
241 | .need_gfx_hws = 1, .has_hotplug = 1, |
- | 242 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
|
- | 243 | .has_bsd_ring = 1, |
|
- | 244 | .has_blt_ring = 1, |
|
- | 245 | .has_llc = 1, |
|
- | 246 | .has_force_wake = 1, |
|
- | 247 | }; |
|
- | 248 | ||
- | 249 | static const struct intel_device_info intel_valleyview_m_info = { |
|
- | 250 | .gen = 7, .is_mobile = 1, |
|
- | 251 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
- | 252 | .has_fbc = 0, |
|
- | 253 | .has_bsd_ring = 1, |
|
- | 254 | .has_blt_ring = 1, |
|
- | 255 | .is_valleyview = 1, |
|
- | 256 | }; |
|
- | 257 | ||
- | 258 | static const struct intel_device_info intel_valleyview_d_info = { |
|
- | 259 | .gen = 7, |
|
- | 260 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
- | 261 | .has_fbc = 0, |
|
- | 262 | .has_bsd_ring = 1, |
|
- | 263 | .has_blt_ring = 1, |
|
- | 264 | .is_valleyview = 1, |
|
- | 265 | }; |
|
- | 266 | ||
- | 267 | static const struct intel_device_info intel_haswell_d_info = { |
|
- | 268 | .is_haswell = 1, .gen = 7, |
|
- | 269 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
- | 270 | .has_bsd_ring = 1, |
|
- | 271 | .has_blt_ring = 1, |
|
- | 272 | .has_llc = 1, |
|
- | 273 | .has_force_wake = 1, |
|
- | 274 | }; |
|
- | 275 | ||
- | 276 | static const struct intel_device_info intel_haswell_m_info = { |
|
- | 277 | .is_haswell = 1, .gen = 7, .is_mobile = 1, |
|
- | 278 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
- | 279 | .has_bsd_ring = 1, |
|
176 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
280 | .has_blt_ring = 1, |
Line 177... | Line 281... | ||
177 | .has_bsd_ring = 1, |
281 | .has_llc = 1, |
178 | .has_blt_ring = 1, |
282 | .has_force_wake = 1, |
179 | }; |
283 | }; |
Line 215... | Line 319... | ||
215 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
319 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
216 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
320 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
217 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
321 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
218 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
322 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
219 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
323 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
- | 324 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
|
- | 325 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
|
- | 326 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
|
- | 327 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
|
- | 328 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
|
- | 329 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
|
- | 330 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
|
- | 331 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
|
- | 332 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
|
- | 333 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
|
- | 334 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
|
- | 335 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
|
- | 336 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ |
|
- | 337 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
|
- | 338 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
|
- | 339 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ |
|
- | 340 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
|
- | 341 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
|
- | 342 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ |
|
- | 343 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
|
- | 344 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
|
- | 345 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ |
|
- | 346 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
|
- | 347 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
|
- | 348 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ |
|
- | 349 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
|
- | 350 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
|
- | 351 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
|
- | 352 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ |
|
- | 353 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
|
- | 354 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ |
|
- | 355 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ |
|
- | 356 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
|
- | 357 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ |
|
- | 358 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ |
|
- | 359 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
|
- | 360 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ |
|
- | 361 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
|
- | 362 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
|
- | 363 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
|
220 | {0, 0, 0} |
364 | {0, 0, 0} |
221 | }; |
365 | }; |
Line 222... | Line 366... | ||
222 | 366 | ||
223 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
367 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
224 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
368 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
225 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
369 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
- | 370 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
|
Line 226... | Line 371... | ||
226 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
371 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
227 | 372 | ||
228 | void intel_detect_pch(struct drm_device *dev) |
373 | void intel_detect_pch(struct drm_device *dev) |
229 | { |
374 | { |
Line 242... | Line 387... | ||
242 | int id; |
387 | int id; |
243 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
388 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
Line 244... | Line 389... | ||
244 | 389 | ||
245 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
390 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
- | 391 | dev_priv->pch_type = PCH_IBX; |
|
246 | dev_priv->pch_type = PCH_IBX; |
392 | dev_priv->num_pch_pll = 2; |
247 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
393 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
248 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
394 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
- | 395 | dev_priv->pch_type = PCH_CPT; |
|
249 | dev_priv->pch_type = PCH_CPT; |
396 | dev_priv->num_pch_pll = 2; |
250 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
397 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
251 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
398 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
252 | /* PantherPoint is CPT compatible */ |
399 | /* PantherPoint is CPT compatible */ |
- | 400 | dev_priv->pch_type = PCH_CPT; |
|
253 | dev_priv->pch_type = PCH_CPT; |
401 | dev_priv->num_pch_pll = 2; |
- | 402 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
|
- | 403 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
|
- | 404 | dev_priv->pch_type = PCH_LPT; |
|
- | 405 | dev_priv->num_pch_pll = 0; |
|
254 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
406 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
- | 407 | } |
|
255 | } |
408 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
256 | } |
409 | } |
257 | } |
410 | } |
Line 258... | Line -... | ||
258 | } |
- | |
259 | - | ||
260 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
- | |
261 | { |
- | |
262 | int count; |
- | |
263 | - | ||
264 | count = 0; |
- | |
265 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
- | |
266 | udelay(10); |
- | |
267 | - | ||
268 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
- | |
269 | POSTING_READ(FORCEWAKE); |
- | |
270 | - | ||
271 | count = 0; |
- | |
272 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) |
- | |
273 | udelay(10); |
- | |
274 | } |
- | |
275 | - | ||
276 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
- | |
277 | { |
- | |
278 | int count; |
- | |
279 | - | ||
280 | count = 0; |
- | |
281 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) |
- | |
282 | udelay(10); |
- | |
283 | - | ||
284 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); |
- | |
285 | POSTING_READ(FORCEWAKE_MT); |
- | |
286 | - | ||
287 | count = 0; |
- | |
288 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) |
- | |
289 | udelay(10); |
- | |
290 | } |
- | |
291 | - | ||
292 | /* |
- | |
293 | * Generally this is called implicitly by the register read function. However, |
- | |
294 | * if some sequence requires the GT to not power down then this function should |
- | |
295 | * be called at the beginning of the sequence followed by a call to |
- | |
296 | * gen6_gt_force_wake_put() at the end of the sequence. |
411 | } |
297 | */ |
- | |
298 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
- | |
299 | { |
- | |
300 | unsigned long irqflags; |
- | |
301 | - | ||
302 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
- | |
303 | if (dev_priv->forcewake_count++ == 0) |
- | |
304 | dev_priv->display.force_wake_get(dev_priv); |
- | |
305 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
- | |
306 | } |
- | |
307 | - | ||
308 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
- | |
309 | { |
- | |
310 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
- | |
311 | POSTING_READ(FORCEWAKE); |
- | |
312 | } |
- | |
313 | 412 | ||
314 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
413 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
315 | { |
414 | { |
316 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0); |
- | |
Line 317... | Line -... | ||
317 | POSTING_READ(FORCEWAKE_MT); |
- | |
318 | } |
415 | if (INTEL_INFO(dev)->gen < 6) |
319 | - | ||
320 | /* |
- | |
321 | * see gen6_gt_force_wake_get() |
- | |
322 | */ |
416 | return 0; |
Line 323... | Line 417... | ||
323 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
417 | |
324 | { |
418 | if (i915_semaphores >= 0) |
325 | unsigned long irqflags; |
419 | return i915_semaphores; |
326 | 420 | ||
327 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
421 | #ifdef CONFIG_INTEL_IOMMU |
Line 328... | Line -... | ||
328 | if (--dev_priv->forcewake_count == 0) |
- | |
329 | dev_priv->display.force_wake_put(dev_priv); |
- | |
330 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
- | |
331 | } |
- | |
332 | - | ||
333 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
- | |
334 | { |
- | |
335 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
- | |
336 | int loop = 500; |
422 | /* Enable semaphores on SNB when IO remapping is off */ |
337 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
- | |
338 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
- | |
339 | udelay(10); |
- | |
340 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
- | |
341 | } |
423 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
Line 355... | Line 437... | ||
355 | { |
437 | { |
356 | static pci_dev_t device; |
438 | static pci_dev_t device; |
357 | const struct pci_device_id *ent; |
439 | const struct pci_device_id *ent; |
358 | int err; |
440 | int err; |
Line 359... | Line -... | ||
359 | - | ||
360 | if( init_agp() != 0) |
- | |
361 | { |
- | |
362 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
- | |
363 | return 0; |
- | |
364 | }; |
- | |
365 | 441 | ||
366 | ent = find_pci_device(&device, pciidlist); |
- | |
367 | 442 | ent = find_pci_device(&device, pciidlist); |
|
368 | if( unlikely(ent == NULL) ) |
443 | if( unlikely(ent == NULL) ) |
369 | { |
444 | { |
370 | dbgprintf("device not found\n"); |
445 | dbgprintf("device not found\n"); |
371 | return 0; |
446 | return 0; |
Line -... | Line 447... | ||
- | 447 | }; |
|
- | 448 | ||
- | 449 | struct intel_device_info *intel_info = |
|
- | 450 | (struct intel_device_info *) ent->driver_data; |
|
- | 451 | ||
- | 452 | if (intel_info->is_haswell || intel_info->is_valleyview) |
|
- | 453 | if(!i915_preliminary_hw_support) { |
|
- | 454 | DRM_ERROR("Preliminary hardware support disabled\n"); |
|
- | 455 | return -ENODEV; |
|
372 | }; |
456 | } |
373 | 457 | ||
Line -... | Line 458... | ||
- | 458 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
|
- | 459 | device.pci_dev.device); |
|
- | 460 | ||
- | 461 | if (intel_info->gen != 3) { |
|
- | 462 | ||
- | 463 | } else if (init_agp() != 0) { |
|
- | 464 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
|
374 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
465 | return -ENODEV; |
Line 375... | Line 466... | ||
375 | device.pci_dev.device); |
466 | } |
376 | 467 | ||
Line 392... | Line 483... | ||
392 | 483 | ||
393 | // ret = pci_enable_device(pdev); |
484 | // ret = pci_enable_device(pdev); |
394 | // if (ret) |
485 | // if (ret) |
Line 395... | Line 486... | ||
395 | // goto err_g1; |
486 | // goto err_g1; |
Line 396... | Line 487... | ||
396 | 487 | ||
397 | // pci_set_master(pdev); |
488 | pci_set_master(pdev); |
398 | 489 | ||
399 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
490 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
Line 441... | Line 532... | ||
441 | LEAVE(); |
532 | LEAVE(); |
Line 442... | Line 533... | ||
442 | 533 | ||
443 | return ret; |
534 | return ret; |
Line -... | Line 535... | ||
- | 535 | } |
|
- | 536 | ||
- | 537 | /* We give fast paths for the really cool registers */ |
|
- | 538 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
|
- | 539 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
|
- | 540 | ((reg) < 0x40000) && \ |
|
- | 541 | ((reg) != FORCEWAKE)) |
|
- | 542 | ||
- | 543 | static bool IS_DISPLAYREG(u32 reg) |
|
- | 544 | { |
|
- | 545 | /* |
|
- | 546 | * This should make it easier to transition modules over to the |
|
- | 547 | * new register block scheme, since we can do it incrementally. |
|
- | 548 | */ |
|
- | 549 | if (reg >= VLV_DISPLAY_BASE) |
|
- | 550 | return false; |
|
- | 551 | ||
- | 552 | if (reg >= RENDER_RING_BASE && |
|
- | 553 | reg < RENDER_RING_BASE + 0xff) |
|
- | 554 | return false; |
|
- | 555 | if (reg >= GEN6_BSD_RING_BASE && |
|
- | 556 | reg < GEN6_BSD_RING_BASE + 0xff) |
|
- | 557 | return false; |
|
- | 558 | if (reg >= BLT_RING_BASE && |
|
- | 559 | reg < BLT_RING_BASE + 0xff) |
|
- | 560 | return false; |
|
- | 561 | ||
- | 562 | if (reg == PGTBL_ER) |
|
- | 563 | return false; |
|
- | 564 | ||
- | 565 | if (reg >= IPEIR_I965 && |
|
- | 566 | reg < HWSTAM) |
|
- | 567 | return false; |
|
- | 568 | ||
- | 569 | if (reg == MI_MODE) |
|
- | 570 | return false; |
|
- | 571 | ||
- | 572 | if (reg == GFX_MODE_GEN7) |
|
- | 573 | return false; |
|
- | 574 | ||
- | 575 | if (reg == RENDER_HWS_PGA_GEN7 || |
|
- | 576 | reg == BSD_HWS_PGA_GEN7 || |
|
- | 577 | reg == BLT_HWS_PGA_GEN7) |
|
- | 578 | return false; |
|
- | 579 | ||
- | 580 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
|
- | 581 | reg == GEN6_BSD_RNCID) |
|
- | 582 | return false; |
|
- | 583 | ||
- | 584 | if (reg == GEN6_BLITTER_ECOSKPD) |
|
- | 585 | return false; |
|
- | 586 | ||
- | 587 | if (reg >= 0x4000c && |
|
- | 588 | reg <= 0x4002c) |
|
- | 589 | return false; |
|
- | 590 | ||
- | 591 | if (reg >= 0x4f000 && |
|
- | 592 | reg <= 0x4f08f) |
|
- | 593 | return false; |
|
- | 594 | ||
- | 595 | if (reg >= 0x4f100 && |
|
- | 596 | reg <= 0x4f11f) |
|
- | 597 | return false; |
|
- | 598 | ||
- | 599 | if (reg >= VLV_MASTER_IER && |
|
- | 600 | reg <= GEN6_PMIER) |
|
- | 601 | return false; |
|
- | 602 | ||
- | 603 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
|
- | 604 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
|
- | 605 | return false; |
|
- | 606 | ||
- | 607 | if (reg >= VLV_IIR_RW && |
|
- | 608 | reg <= VLV_ISR) |
|
- | 609 | return false; |
|
- | 610 | ||
- | 611 | if (reg == FORCEWAKE_VLV || |
|
- | 612 | reg == FORCEWAKE_ACK_VLV) |
|
- | 613 | return false; |
|
- | 614 | ||
- | 615 | if (reg == GEN6_GDRST) |
|
- | 616 | return false; |
|
- | 617 | ||
Line 444... | Line 618... | ||
444 | } |
618 | return true; |
445 | 619 | } |
|
446 | 620 | ||
447 | #define __i915_read(x, y) \ |
621 | #define __i915_read(x, y) \ |
448 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
622 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
449 | u##x val = 0; \ |
623 | u##x val = 0; \ |
450 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
624 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
451 | unsigned long irqflags; \ |
625 | unsigned long irqflags; \ |
452 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
626 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
453 | if (dev_priv->forcewake_count == 0) \ |
627 | if (dev_priv->forcewake_count == 0) \ |
454 | dev_priv->display.force_wake_get(dev_priv); \ |
628 | dev_priv->gt.force_wake_get(dev_priv); \ |
455 | val = read##y(dev_priv->regs + reg); \ |
629 | val = read##y(dev_priv->regs + reg); \ |
- | 630 | if (dev_priv->forcewake_count == 0) \ |
|
- | 631 | dev_priv->gt.force_wake_put(dev_priv); \ |
|
456 | if (dev_priv->forcewake_count == 0) \ |
632 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
457 | dev_priv->display.force_wake_put(dev_priv); \ |
633 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
458 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
634 | val = read##y(dev_priv->regs + reg + 0x180000); \ |
459 | } else { \ |
635 | } else { \ |
460 | val = read##y(dev_priv->regs + reg); \ |
636 | val = read##y(dev_priv->regs + reg); \ |