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| 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
- | |
| 2 | */ |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
| 3 | /* |
2 | */ |
| 4 | * |
3 | /* |
| 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
4 | * |
| 6 | * All Rights Reserved. |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 7 | * |
6 | * All Rights Reserved. |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * |
| 9 | * copy of this software and associated documentation files (the |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 10 | * "Software"), to deal in the Software without restriction, including |
9 | * copy of this software and associated documentation files (the |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
10 | * "Software"), to deal in the Software without restriction, including |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 14 | * the following conditions: |
13 | * permit persons to whom the Software is furnished to do so, subject to |
| 15 | * |
14 | * the following conditions: |
| 16 | * The above copyright notice and this permission notice (including the |
15 | * |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
16 | * The above copyright notice and this permission notice (including the |
| 18 | * of the Software. |
17 | * next paragraph) shall be included in all copies or substantial portions |
| 19 | * |
18 | * of the Software. |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
19 | * |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 27 | * |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 28 | */ |
27 | * |
| 29 | 28 | */ |
|
| 30 | //#include |
29 | |
| 31 | #include "drmP.h" |
30 | //#include |
| 32 | #include "drm.h" |
31 | #include "drmP.h" |
| 33 | #include "i915_drm.h" |
32 | #include "drm.h" |
| 34 | #include "i915_drv.h" |
33 | #include "i915_drm.h" |
| 35 | #include "intel_drv.h" |
34 | #include "i915_drv.h" |
| 36 | 35 | #include "intel_drv.h" |
|
| 37 | 36 | ||
| 38 | #include |
37 | |
| 39 | #include |
38 | #include |
| 40 | #include |
39 | #include |
| 41 | #include |
40 | #include |
| 42 | #include |
41 | #include |
| 43 | 42 | #include |
|
| 44 | #include |
43 | |
| 45 | 44 | #include |
|
| 46 | #define __read_mostly |
45 | |
| 47 | 46 | #define __read_mostly |
|
| 48 | int init_display_kms(struct drm_device *dev); |
47 | |
| 49 | 48 | int init_display_kms(struct drm_device *dev); |
|
| 50 | 49 | ||
| 51 | int i915_panel_ignore_lid __read_mostly = 0; |
50 | |
| 52 | 51 | int i915_panel_ignore_lid __read_mostly = 0; |
|
| 53 | unsigned int i915_powersave __read_mostly = 0; |
52 | |
| 54 | 53 | unsigned int i915_powersave __read_mostly = 0; |
|
| 55 | unsigned int i915_enable_rc6 __read_mostly = 0; |
54 | |
| 56 | 55 | unsigned int i915_enable_rc6 __read_mostly = 0; |
|
| 57 | unsigned int i915_enable_fbc __read_mostly = 0; |
56 | |
| 58 | 57 | unsigned int i915_enable_fbc __read_mostly = 0; |
|
| 59 | unsigned int i915_lvds_downclock __read_mostly = 0; |
58 | |
| 60 | 59 | unsigned int i915_lvds_downclock __read_mostly = 0; |
|
| 61 | unsigned int i915_panel_use_ssc __read_mostly = 1; |
60 | |
| 62 | 61 | unsigned int i915_panel_use_ssc __read_mostly = 1; |
|
| 63 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
62 | |
| 64 | 63 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
|
| 65 | #define PCI_VENDOR_ID_INTEL 0x8086 |
64 | |
| 66 | 65 | #define PCI_VENDOR_ID_INTEL 0x8086 |
|
| 67 | #define INTEL_VGA_DEVICE(id, info) { \ |
66 | |
| 68 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
67 | #define INTEL_VGA_DEVICE(id, info) { \ |
| 69 | .class_mask = 0xff0000, \ |
68 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
| 70 | .vendor = 0x8086, \ |
69 | .class_mask = 0xff0000, \ |
| 71 | .device = id, \ |
70 | .vendor = 0x8086, \ |
| 72 | .subvendor = PCI_ANY_ID, \ |
71 | .device = id, \ |
| 73 | .subdevice = PCI_ANY_ID, \ |
72 | .subvendor = PCI_ANY_ID, \ |
| 74 | .driver_data = (unsigned long) info } |
73 | .subdevice = PCI_ANY_ID, \ |
| 75 | 74 | .driver_data = (unsigned long) info } |
|
| - | 75 | ||
| - | 76 | static const struct intel_device_info intel_i830_info = { |
|
| - | 77 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
|
| - | 78 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 79 | }; |
|
| - | 80 | ||
| - | 81 | static const struct intel_device_info intel_845g_info = { |
|
| - | 82 | .gen = 2, |
|
| - | 83 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 84 | }; |
|
| - | 85 | ||
| - | 86 | static const struct intel_device_info intel_i85x_info = { |
|
| - | 87 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
|
| - | 88 | .cursor_needs_physical = 1, |
|
| - | 89 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 90 | }; |
|
| - | 91 | ||
| - | 92 | static const struct intel_device_info intel_i865g_info = { |
|
| - | 93 | .gen = 2, |
|
| - | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 95 | }; |
|
| - | 96 | ||
| - | 97 | static const struct intel_device_info intel_i915g_info = { |
|
| - | 98 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
|
| - | 99 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 100 | }; |
|
| - | 101 | static const struct intel_device_info intel_i915gm_info = { |
|
| - | 102 | .gen = 3, .is_mobile = 1, |
|
| - | 103 | .cursor_needs_physical = 1, |
|
| - | 104 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 105 | .supports_tv = 1, |
|
| - | 106 | }; |
|
| - | 107 | static const struct intel_device_info intel_i945g_info = { |
|
| - | 108 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
|
| - | 109 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 110 | }; |
|
| - | 111 | static const struct intel_device_info intel_i945gm_info = { |
|
| - | 112 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
|
| - | 113 | .has_hotplug = 1, .cursor_needs_physical = 1, |
|
| - | 114 | .has_overlay = 1, .overlay_needs_physical = 1, |
|
| - | 115 | .supports_tv = 1, |
|
| - | 116 | }; |
|
| - | 117 | ||
| - | 118 | static const struct intel_device_info intel_i965g_info = { |
|
| - | 119 | .gen = 4, .is_broadwater = 1, |
|
| - | 120 | .has_hotplug = 1, |
|
| - | 121 | .has_overlay = 1, |
|
| - | 122 | }; |
|
| - | 123 | ||
| - | 124 | static const struct intel_device_info intel_i965gm_info = { |
|
| - | 125 | .gen = 4, .is_crestline = 1, |
|
| - | 126 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
|
| - | 127 | .has_overlay = 1, |
|
| - | 128 | .supports_tv = 1, |
|
| - | 129 | }; |
|
| - | 130 | ||
| - | 131 | static const struct intel_device_info intel_g33_info = { |
|
| - | 132 | .gen = 3, .is_g33 = 1, |
|
| - | 133 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
| - | 134 | .has_overlay = 1, |
|
| - | 135 | }; |
|
| - | 136 | ||
| - | 137 | static const struct intel_device_info intel_g45_info = { |
|
| - | 138 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
|
| - | 139 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
|
| - | 140 | .has_bsd_ring = 1, |
|
| - | 141 | }; |
|
| - | 142 | ||
| - | 143 | static const struct intel_device_info intel_gm45_info = { |
|
| - | 144 | .gen = 4, .is_g4x = 1, |
|
| - | 145 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
|
| - | 146 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
|
| - | 147 | .supports_tv = 1, |
|
| - | 148 | .has_bsd_ring = 1, |
|
| - | 149 | }; |
|
| - | 150 | ||
| - | 151 | static const struct intel_device_info intel_pineview_info = { |
|
| - | 152 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
|
| - | 153 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
| - | 154 | .has_overlay = 1, |
|
| - | 155 | }; |
|
| - | 156 | ||
| - | 157 | static const struct intel_device_info intel_ironlake_d_info = { |
|
| - | 158 | .gen = 5, |
|
| - | 159 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
|
| - | 160 | .has_bsd_ring = 1, |
|
| - | 161 | }; |
|
| - | 162 | ||
| - | 163 | static const struct intel_device_info intel_ironlake_m_info = { |
|
| - | 164 | .gen = 5, .is_mobile = 1, |
|
| - | 165 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
| - | 166 | .has_fbc = 1, |
|
| - | 167 | .has_bsd_ring = 1, |
|
| - | 168 | }; |
|
| 76 | static const struct intel_device_info intel_sandybridge_d_info = { |
169 | |
| 77 | .gen = 6, |
170 | static const struct intel_device_info intel_sandybridge_d_info = { |
| 78 | .need_gfx_hws = 1, .has_hotplug = 1, |
171 | .gen = 6, |
| 79 | .has_bsd_ring = 1, |
172 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 80 | .has_blt_ring = 1, |
173 | .has_bsd_ring = 1, |
| 81 | }; |
174 | .has_blt_ring = 1, |
| 82 | 175 | }; |
|
| 83 | static const struct intel_device_info intel_sandybridge_m_info = { |
176 | |
| 84 | .gen = 6, .is_mobile = 1, |
177 | static const struct intel_device_info intel_sandybridge_m_info = { |
| 85 | .need_gfx_hws = 1, .has_hotplug = 1, |
178 | .gen = 6, .is_mobile = 1, |
| 86 | .has_fbc = 1, |
179 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 87 | .has_bsd_ring = 1, |
180 | .has_fbc = 1, |
| 88 | .has_blt_ring = 1, |
181 | .has_bsd_ring = 1, |
| 89 | }; |
182 | .has_blt_ring = 1, |
| 90 | 183 | }; |
|
| - | 184 | ||
| - | 185 | static const struct intel_device_info intel_ivybridge_d_info = { |
|
| - | 186 | .is_ivybridge = 1, .gen = 7, |
|
| - | 187 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
| - | 188 | .has_bsd_ring = 1, |
|
| - | 189 | .has_blt_ring = 1, |
|
| - | 190 | }; |
|
| - | 191 | ||
| - | 192 | static const struct intel_device_info intel_ivybridge_m_info = { |
|
| - | 193 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
|
| - | 194 | .need_gfx_hws = 1, .has_hotplug = 1, |
|
| - | 195 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
|
| - | 196 | .has_bsd_ring = 1, |
|
| - | 197 | .has_blt_ring = 1, |
|
| 91 | 198 | }; |
|
| - | 199 | ||
| - | 200 | static const struct pci_device_id pciidlist[] = { /* aka */ |
|
| - | 201 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
|
| - | 202 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
|
| - | 203 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
|
| - | 204 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
|
| - | 205 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
|
| - | 206 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
|
| - | 207 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
|
| - | 208 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
|
| - | 209 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
|
| - | 210 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
|
| - | 211 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
|
| - | 212 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
|
| - | 213 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
|
| - | 214 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
|
| - | 215 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
|
| - | 216 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
|
| - | 217 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
|
| - | 218 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
|
| - | 219 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
|
| - | 220 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
|
| - | 221 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
|
| - | 222 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
|
| - | 223 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
|
| - | 224 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
|
| 92 | static const struct pci_device_id pciidlist[] = { /* aka */ |
225 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
| 93 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
226 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
| 94 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
227 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
| 95 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
228 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
| 96 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
229 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
| 97 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
230 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
| 98 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
231 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
| 99 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
232 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
| 100 | {0, 0, 0} |
233 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
| - | 234 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
|
| - | 235 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
|
| - | 236 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
|
| - | 237 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
|
| - | 238 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
|
| 101 | }; |
239 | {0, 0, 0} |
| 102 | 240 | }; |
|
| 103 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
241 | |
| 104 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
242 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
| 105 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
243 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 106 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
244 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 107 | 245 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
|
| 108 | void intel_detect_pch (struct drm_device *dev) |
246 | |
| 109 | { |
247 | void intel_detect_pch (struct drm_device *dev) |
| 110 | struct drm_i915_private *dev_priv = dev->dev_private; |
248 | { |
| 111 | struct pci_dev *pch; |
249 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 112 | 250 | struct pci_dev *pch; |
|
| 113 | /* |
251 | |
| 114 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
252 | /* |
| 115 | * make graphics device passthrough work easy for VMM, that only |
253 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
| 116 | * need to expose ISA bridge to let driver know the real hardware |
254 | * make graphics device passthrough work easy for VMM, that only |
| 117 | * underneath. This is a requirement from virtualization team. |
255 | * need to expose ISA bridge to let driver know the real hardware |
| 118 | */ |
256 | * underneath. This is a requirement from virtualization team. |
| 119 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
257 | */ |
| 120 | if (pch) { |
258 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 121 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
259 | if (pch) { |
| 122 | int id; |
260 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
| 123 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
261 | int id; |
| 124 | 262 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
|
| 125 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
263 | |
| 126 | dev_priv->pch_type = PCH_IBX; |
264 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
| 127 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
265 | dev_priv->pch_type = PCH_IBX; |
| 128 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
266 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
| 129 | dev_priv->pch_type = PCH_CPT; |
267 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
| 130 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
268 | dev_priv->pch_type = PCH_CPT; |
| 131 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
269 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
| 132 | /* PantherPoint is CPT compatible */ |
270 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
| 133 | dev_priv->pch_type = PCH_CPT; |
271 | /* PantherPoint is CPT compatible */ |
| 134 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
272 | dev_priv->pch_type = PCH_CPT; |
| 135 | } |
273 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
| 136 | } |
274 | } |
| 137 | } |
275 | } |
| 138 | } |
276 | } |
| 139 | 277 | } |
|
| 140 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
278 | |
| 141 | { |
279 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 142 | int count; |
280 | { |
| 143 | 281 | int count; |
|
| 144 | count = 0; |
282 | |
| 145 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
283 | count = 0; |
| 146 | udelay(10); |
284 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 147 | 285 | udelay(10); |
|
| 148 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
286 | |
| 149 | POSTING_READ(FORCEWAKE); |
287 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
| 150 | 288 | POSTING_READ(FORCEWAKE); |
|
| 151 | count = 0; |
289 | |
| 152 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) |
290 | count = 0; |
| 153 | udelay(10); |
291 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) |
| 154 | } |
292 | udelay(10); |
| 155 | 293 | } |
|
| 156 | /* |
294 | |
| 157 | * Generally this is called implicitly by the register read function. However, |
295 | /* |
| 158 | * if some sequence requires the GT to not power down then this function should |
296 | * Generally this is called implicitly by the register read function. However, |
| 159 | * be called at the beginning of the sequence followed by a call to |
297 | * if some sequence requires the GT to not power down then this function should |
| 160 | * gen6_gt_force_wake_put() at the end of the sequence. |
298 | * be called at the beginning of the sequence followed by a call to |
| 161 | */ |
299 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 162 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
300 | */ |
| 163 | { |
301 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 164 | // WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
302 | { |
| 165 | 303 | // WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
|
| 166 | /* Forcewake is atomic in case we get in here without the lock */ |
304 | |
| 167 | if (atomic_add_return(1, &dev_priv->forcewake_count) == 1) |
305 | /* Forcewake is atomic in case we get in here without the lock */ |
| 168 | __gen6_gt_force_wake_get(dev_priv); |
306 | if (atomic_add_return(1, &dev_priv->forcewake_count) == 1) |
| 169 | } |
307 | __gen6_gt_force_wake_get(dev_priv); |
| 170 | 308 | } |
|
| 171 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
309 | |
| 172 | { |
310 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 173 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
311 | { |
| 174 | POSTING_READ(FORCEWAKE); |
312 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
| 175 | } |
313 | POSTING_READ(FORCEWAKE); |
| 176 | 314 | } |
|
| 177 | /* |
315 | |
| 178 | * see gen6_gt_force_wake_get() |
316 | /* |
| 179 | */ |
317 | * see gen6_gt_force_wake_get() |
| 180 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
318 | */ |
| 181 | { |
319 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 182 | // WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
320 | { |
| 183 | 321 | // WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
|
| 184 | if (atomic_dec_and_test(&dev_priv->forcewake_count)) |
322 | |
| 185 | __gen6_gt_force_wake_put(dev_priv); |
323 | if (atomic_dec_and_test(&dev_priv->forcewake_count)) |
| 186 | } |
324 | __gen6_gt_force_wake_put(dev_priv); |
| 187 | 325 | } |
|
| 188 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
326 | |
| 189 | { |
327 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 190 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) { |
328 | { |
| 191 | int loop = 500; |
329 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) { |
| 192 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
330 | int loop = 500; |
| 193 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
331 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 194 | udelay(10); |
332 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 195 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
333 | udelay(10); |
| 196 | } |
334 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 197 | // WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES); |
335 | } |
| 198 | dev_priv->gt_fifo_count = fifo; |
336 | // WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES); |
| 199 | } |
337 | dev_priv->gt_fifo_count = fifo; |
| 200 | dev_priv->gt_fifo_count--; |
338 | } |
| 201 | } |
339 | dev_priv->gt_fifo_count--; |
| 202 | 340 | } |
|
| 203 | 341 | ||
| 204 | 342 | ||
| 205 | 343 | ||
| 206 | 344 | ||
| 207 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent); |
345 | |
| 208 | 346 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent); |
|
| 209 | int i915_init(void) |
347 | |
| 210 | { |
348 | int i915_init(void) |
| 211 | static pci_dev_t device; |
349 | { |
| 212 | const struct pci_device_id *ent; |
350 | static pci_dev_t device; |
| 213 | int err; |
351 | const struct pci_device_id *ent; |
| 214 | 352 | int err; |
|
| 215 | if( init_agp() != 0) |
353 | |
| 216 | { |
354 | if( init_agp() != 0) |
| 217 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
355 | { |
| 218 | return 0; |
356 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
| 219 | }; |
357 | return 0; |
| 220 | 358 | }; |
|
| 221 | ent = find_pci_device(&device, pciidlist); |
359 | |
| 222 | 360 | ent = find_pci_device(&device, pciidlist); |
|
| 223 | if( unlikely(ent == NULL) ) |
361 | |
| 224 | { |
362 | if( unlikely(ent == NULL) ) |
| 225 | dbgprintf("device not found\n"); |
363 | { |
| 226 | return 0; |
364 | dbgprintf("device not found\n"); |
| 227 | }; |
365 | return 0; |
| 228 | 366 | }; |
|
| 229 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
367 | |
| 230 | device.pci_dev.device); |
368 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
| 231 | 369 | device.pci_dev.device); |
|
| 232 | err = drm_get_dev(&device.pci_dev, ent); |
370 | |
| 233 | 371 | err = drm_get_dev(&device.pci_dev, ent); |
|
| 234 | return err; |
372 | |
| 235 | } |
373 | return err; |
| 236 | 374 | } |
|
| 237 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
375 | |
| 238 | { |
376 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 239 | static struct drm_device *dev; |
377 | { |
| 240 | int ret; |
378 | static struct drm_device *dev; |
| 241 | 379 | int ret; |
|
| 242 | ENTER(); |
380 | |
| 243 | 381 | ENTER(); |
|
| 244 | dev = kzalloc(sizeof(*dev), 0); |
382 | |
| 245 | if (!dev) |
383 | dev = kzalloc(sizeof(*dev), 0); |
| 246 | return -ENOMEM; |
384 | if (!dev) |
| 247 | 385 | return -ENOMEM; |
|
| 248 | // ret = pci_enable_device(pdev); |
386 | |
| 249 | // if (ret) |
387 | // ret = pci_enable_device(pdev); |
| 250 | // goto err_g1; |
388 | // if (ret) |
| 251 | 389 | // goto err_g1; |
|
| 252 | // pci_set_master(pdev); |
390 | |
| 253 | 391 | // pci_set_master(pdev); |
|
| 254 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
392 | |
| 255 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
393 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
| 256 | // goto err_g2; |
394 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
| 257 | // } |
395 | // goto err_g2; |
| 258 | 396 | // } |
|
| 259 | dev->pdev = pdev; |
397 | |
| 260 | dev->pci_device = pdev->device; |
398 | dev->pdev = pdev; |
| 261 | dev->pci_vendor = pdev->vendor; |
399 | dev->pci_device = pdev->device; |
| 262 | 400 | dev->pci_vendor = pdev->vendor; |
|
| 263 | INIT_LIST_HEAD(&dev->filelist); |
401 | |
| 264 | INIT_LIST_HEAD(&dev->ctxlist); |
402 | INIT_LIST_HEAD(&dev->filelist); |
| 265 | INIT_LIST_HEAD(&dev->vmalist); |
403 | INIT_LIST_HEAD(&dev->ctxlist); |
| 266 | INIT_LIST_HEAD(&dev->maplist); |
404 | INIT_LIST_HEAD(&dev->vmalist); |
| 267 | 405 | INIT_LIST_HEAD(&dev->maplist); |
|
| 268 | spin_lock_init(&dev->count_lock); |
406 | |
| 269 | mutex_init(&dev->struct_mutex); |
407 | spin_lock_init(&dev->count_lock); |
| 270 | mutex_init(&dev->ctxlist_mutex); |
408 | mutex_init(&dev->struct_mutex); |
| 271 | 409 | mutex_init(&dev->ctxlist_mutex); |
|
| 272 | ret = i915_driver_load(dev, ent->driver_data ); |
410 | |
| 273 | 411 | ret = i915_driver_load(dev, ent->driver_data ); |
|
| 274 | if (ret) |
412 | |
| 275 | goto err_g4; |
413 | if (ret) |
| 276 | 414 | goto err_g4; |
|
| 277 | ret = init_display_kms(dev); |
415 | |
| 278 | 416 | ret = init_display_kms(dev); |
|
| 279 | if (ret) |
417 | |
| 280 | goto err_g4; |
418 | if (ret) |
| 281 | 419 | goto err_g4; |
|
| 282 | 420 | ||
| 283 | // if( radeon_modeset ) |
421 | |
| 284 | // init_display_kms(dev->dev_private, &usermode); |
422 | // if( radeon_modeset ) |
| 285 | // else |
423 | // init_display_kms(dev->dev_private, &usermode); |
| 286 | // init_display(dev->dev_private, &usermode); |
424 | // else |
| 287 | 425 | // init_display(dev->dev_private, &usermode); |
|
| 288 | LEAVE(); |
426 | |
| 289 | 427 | LEAVE(); |
|
| 290 | return 0; |
428 | |
| 291 | 429 | return 0; |
|
| 292 | err_g4: |
430 | |
| 293 | // drm_put_minor(&dev->primary); |
431 | err_g4: |
| 294 | //err_g3: |
432 | // drm_put_minor(&dev->primary); |
| 295 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
433 | //err_g3: |
| 296 | // drm_put_minor(&dev->control); |
434 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 297 | //err_g2: |
435 | // drm_put_minor(&dev->control); |
| 298 | // pci_disable_device(pdev); |
436 | //err_g2: |
| 299 | //err_g1: |
437 | // pci_disable_device(pdev); |
| 300 | free(dev); |
438 | //err_g1: |
| 301 | 439 | free(dev); |
|
| 302 | LEAVE(); |
440 | |
| 303 | 441 | LEAVE(); |
|
| 304 | return ret; |
442 | |
| 305 | } |
443 | return ret; |
| - | 444 | } |
|