Subversion Repositories Kolibri OS

Rev

Rev 2330 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 2330 Rev 2342
Line 196... Line 196...
196
#define DRM_I915_GET_PIPE_FROM_CRTC_ID	0x25
196
#define DRM_I915_GET_PIPE_FROM_CRTC_ID	0x25
197
#define DRM_I915_GEM_MADVISE	0x26
197
#define DRM_I915_GEM_MADVISE	0x26
198
#define DRM_I915_OVERLAY_PUT_IMAGE	0x27
198
#define DRM_I915_OVERLAY_PUT_IMAGE	0x27
199
#define DRM_I915_OVERLAY_ATTRS	0x28
199
#define DRM_I915_OVERLAY_ATTRS	0x28
200
#define DRM_I915_GEM_EXECBUFFER2	0x29
200
#define DRM_I915_GEM_EXECBUFFER2	0x29
-
 
201
#define DRM_I915_GET_SPRITE_COLORKEY	0x2a
-
 
202
#define DRM_I915_SET_SPRITE_COLORKEY	0x2b
Line 201... Line 203...
201
 
203
 
202
#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
204
#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
203
#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
205
#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
204
#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
206
#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
Line 237... Line 239...
237
#define DRM_IOCTL_I915_GEM_GET_APERTURE	DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
239
#define DRM_IOCTL_I915_GEM_GET_APERTURE	DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
238
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
240
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
239
#define DRM_IOCTL_I915_GEM_MADVISE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
241
#define DRM_IOCTL_I915_GEM_MADVISE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
240
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
242
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
241
#define DRM_IOCTL_I915_OVERLAY_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
243
#define DRM_IOCTL_I915_OVERLAY_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
-
 
244
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
-
 
245
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
Line 242... Line 246...
242
 
246
 
243
/* Allow drivers to submit batchbuffers directly to hardware, relying
247
/* Allow drivers to submit batchbuffers directly to hardware, relying
244
 * on the security mechanisms provided by hardware.
248
 * on the security mechanisms provided by hardware.
245
 */
249
 */
Line 289... Line 293...
289
#define I915_PARAM_HAS_BLT		 11
293
#define I915_PARAM_HAS_BLT		 11
290
#define I915_PARAM_HAS_RELAXED_FENCING	 12
294
#define I915_PARAM_HAS_RELAXED_FENCING	 12
291
#define I915_PARAM_HAS_COHERENT_RINGS	 13
295
#define I915_PARAM_HAS_COHERENT_RINGS	 13
292
#define I915_PARAM_HAS_EXEC_CONSTANTS	 14
296
#define I915_PARAM_HAS_EXEC_CONSTANTS	 14
293
#define I915_PARAM_HAS_RELAXED_DELTA	 15
297
#define I915_PARAM_HAS_RELAXED_DELTA	 15
-
 
298
#define I915_PARAM_HAS_GEN7_SOL_RESET	 16
Line 294... Line 299...
294
 
299
 
295
typedef struct drm_i915_getparam {
300
typedef struct drm_i915_getparam {
296
	int param;
301
	int param;
297
	int __user *value;
302
	int __user *value;
Line 651... Line 656...
651
	__u64 flags;
656
	__u64 flags;
652
	__u64 rsvd1;
657
	__u64 rsvd1;
653
	__u64 rsvd2;
658
	__u64 rsvd2;
654
};
659
};
Line -... Line 660...
-
 
660
 
-
 
661
/** Resets the SO write offset registers for transform feedback on gen7. */
-
 
662
#define I915_EXEC_GEN7_SOL_RESET	(1<<8)
655
 
663
 
656
struct drm_i915_gem_pin {
664
struct drm_i915_gem_pin {
657
	/** Handle of the buffer to be pinned. */
665
	/** Handle of the buffer to be pinned. */
658
	__u32 handle;
666
	__u32 handle;
Line 842... Line 850...
842
	__u32 gamma3;
850
	__u32 gamma3;
843
	__u32 gamma4;
851
	__u32 gamma4;
844
	__u32 gamma5;
852
	__u32 gamma5;
845
};
853
};
Line -... Line 854...
-
 
854
 
-
 
855
/*
-
 
856
 * Intel sprite handling
-
 
857
 *
-
 
858
 * Color keying works with a min/mask/max tuple.  Both source and destination
-
 
859
 * color keying is allowed.
-
 
860
 *
-
 
861
 * Source keying:
-
 
862
 * Sprite pixels within the min & max values, masked against the color channels
-
 
863
 * specified in the mask field, will be transparent.  All other pixels will
-
 
864
 * be displayed on top of the primary plane.  For RGB surfaces, only the min
-
 
865
 * and mask fields will be used; ranged compares are not allowed.
-
 
866
 *
-
 
867
 * Destination keying:
-
 
868
 * Primary plane pixels that match the min value, masked against the color
-
 
869
 * channels specified in the mask field, will be replaced by corresponding
-
 
870
 * pixels from the sprite plane.
-
 
871
 *
-
 
872
 * Note that source & destination keying are exclusive; only one can be
-
 
873
 * active on a given plane.
-
 
874
 */
-
 
875
 
-
 
876
#define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
-
 
877
#define I915_SET_COLORKEY_DESTINATION	(1<<1)
-
 
878
#define I915_SET_COLORKEY_SOURCE	(1<<2)
-
 
879
struct drm_intel_sprite_colorkey {
-
 
880
	__u32 plane_id;
-
 
881
	__u32 min_value;
-
 
882
	__u32 channel_mask;
-
 
883
	__u32 max_value;
-
 
884
	__u32 flags;
-
 
885
};
846
 
886