WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/i915_dma.c


/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
 */
/*
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
#include 
#include 
#include 
#include "intel_drv.h"
#include 
#include "i915_drv.h"
#include "i915_trace.h"
#include 
//#include 
//#include 
//#include 
//#include 
#include 
//#include 
 
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
 
 
#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
 
#define BEGIN_LP_RING(n) \
	intel_ring_begin(LP_RING(dev_priv), (n))
 
#define OUT_RING(x) \
	intel_ring_emit(LP_RING(dev_priv), x)
 
#define ADVANCE_LP_RING() \
	intel_ring_advance(LP_RING(dev_priv))
 
/**
 * Lock test for when it's just for synchronization of ring access.
 *
 * In that case, we don't need to do it when GEM is initialized as nobody else
 * has access to the ring.
 */
#define RING_LOCK_TEST_WITH_RETURN(dev, file) do {			\
	if (LP_RING(dev->dev_private)->obj == NULL)			\
		LOCK_TEST_WITH_RETURN(dev, file);			\
} while (0)
 
static inline u32
intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
{
	if (I915_NEED_GFX_HWS(dev_priv->dev))
		return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
	else
		return intel_read_status_page(LP_RING(dev_priv), reg);
}
 
#define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
#define I915_BREADCRUMB_INDEX		0x21
 
void i915_update_dri1_breadcrumb(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv;
 
	if (dev->primary->master) {
		master_priv = dev->primary->master->driver_priv;
		if (master_priv->sarea_priv)
			master_priv->sarea_priv->last_dispatch =
				READ_BREADCRUMB(dev_priv);
	}
}
 
static void i915_write_hws_pga(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 addr;
 
	addr = dev_priv->status_page_dmah->busaddr;
	if (INTEL_INFO(dev)->gen >= 4)
		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
	I915_WRITE(HWS_PGA, addr);
}
 
/**
 * Frees the hardware status page, whether it's a physical address or a virtual
 * address set up by the X Server.
 */
static void i915_free_hws(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 
	if (dev_priv->status_page_dmah) {
		drm_pci_free(dev, dev_priv->status_page_dmah);
		dev_priv->status_page_dmah = NULL;
	}
 
	if (ring->status_page.gfx_addr) {
		ring->status_page.gfx_addr = 0;
		iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
	}
 
	/* Need to rewrite hardware status page */
	I915_WRITE(HWS_PGA, 0x1ffff000);
}
 
#if 0
 
void i915_kernel_lost_context(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv;
	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 
	/*
	 * We should never lose context on the ring with modesetting
	 * as we don't expose it to userspace
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;
 
	ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
	ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
	if (ring->space < 0)
		ring->space += ring->size;
 
	if (!dev->primary->master)
		return;
 
	master_priv = dev->primary->master->driver_priv;
	if (ring->head == ring->tail && master_priv->sarea_priv)
		master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
}
 
static int i915_dma_cleanup(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;
 
	/* Make sure interrupts are disabled here because the uninstall ioctl
	 * may not have been called from userspace and after dev_private
	 * is freed, it's too late.
	 */
	if (dev->irq_enabled)
		drm_irq_uninstall(dev);
 
	mutex_lock(&dev->struct_mutex);
	for (i = 0; i < I915_NUM_RINGS; i++)
		intel_cleanup_ring_buffer(&dev_priv->ring[i]);
	mutex_unlock(&dev->struct_mutex);
 
	/* Clear the HWS virtual address at teardown */
	if (I915_NEED_GFX_HWS(dev))
		i915_free_hws(dev);
 
	return 0;
}
 
static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
	int ret;
 
	master_priv->sarea = drm_getsarea(dev);
	if (master_priv->sarea) {
		master_priv->sarea_priv = (drm_i915_sarea_t *)
			((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
	} else {
		DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
	}
 
	if (init->ring_size != 0) {
		if (LP_RING(dev_priv)->obj != NULL) {
			i915_dma_cleanup(dev);
			DRM_ERROR("Client tried to initialize ringbuffer in "
				  "GEM mode\n");
			return -EINVAL;
		}
 
		ret = intel_render_ring_init_dri(dev,
						 init->ring_start,
						 init->ring_size);
		if (ret) {
			i915_dma_cleanup(dev);
			return ret;
		}
	}
 
	dev_priv->dri1.cpp = init->cpp;
	dev_priv->dri1.back_offset = init->back_offset;
	dev_priv->dri1.front_offset = init->front_offset;
	dev_priv->dri1.current_page = 0;
	if (master_priv->sarea_priv)
		master_priv->sarea_priv->pf_current_page = 0;
 
	/* Allow hardware batchbuffers unless told otherwise.
	 */
	dev_priv->dri1.allow_batchbuffer = 1;
 
	return 0;
}
 
static int i915_dma_resume(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 
	DRM_DEBUG_DRIVER("%s\n", __func__);
 
	if (ring->virtual_start == NULL) {
		DRM_ERROR("can not ioremap virtual address for"
			  " ring buffer\n");
		return -ENOMEM;
	}
 
	/* Program Hardware Status Page */
	if (!ring->status_page.page_addr) {
		DRM_ERROR("Can not find hardware status page\n");
		return -EINVAL;
	}
	DRM_DEBUG_DRIVER("hw status page @ %p\n",
				ring->status_page.page_addr);
	if (ring->status_page.gfx_addr != 0)
		intel_ring_setup_status_page(ring);
	else
		i915_write_hws_pga(dev);
 
	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 
	return 0;
}
 
static int i915_dma_init(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_init_t *init = data;
	int retcode = 0;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	switch (init->func) {
	case I915_INIT_DMA:
		retcode = i915_initialize(dev, init);
		break;
	case I915_CLEANUP_DMA:
		retcode = i915_dma_cleanup(dev);
		break;
	case I915_RESUME_DMA:
		retcode = i915_dma_resume(dev);
		break;
	default:
		retcode = -EINVAL;
		break;
	}
 
	return retcode;
}
 
/* Implement basically the same security restrictions as hardware does
 * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 *
 * Most of the calculations below involve calculating the size of a
 * particular instruction.  It's important to get the size right as
 * that tells us where the next instruction to check is.  Any illegal
 * instruction detected will be given a size of zero, which is a
 * signal to abort the rest of the buffer.
 */
static int validate_cmd(int cmd)
{
	switch (((cmd >> 29) & 0x7)) {
	case 0x0:
		switch ((cmd >> 23) & 0x3f) {
		case 0x0:
			return 1;	/* MI_NOOP */
		case 0x4:
			return 1;	/* MI_FLUSH */
		default:
			return 0;	/* disallow everything else */
		}
		break;
	case 0x1:
		return 0;	/* reserved */
	case 0x2:
		return (cmd & 0xff) + 2;	/* 2d commands */
	case 0x3:
		if (((cmd >> 24) & 0x1f) <= 0x18)
			return 1;
 
		switch ((cmd >> 24) & 0x1f) {
		case 0x1c:
			return 1;
		case 0x1d:
			switch ((cmd >> 16) & 0xff) {
			case 0x3:
				return (cmd & 0x1f) + 2;
			case 0x4:
				return (cmd & 0xf) + 2;
			default:
				return (cmd & 0xffff) + 2;
			}
		case 0x1e:
			if (cmd & (1 << 23))
				return (cmd & 0xffff) + 1;
			else
				return 1;
		case 0x1f:
			if ((cmd & (1 << 23)) == 0)	/* inline vertices */
				return (cmd & 0x1ffff) + 2;
			else if (cmd & (1 << 17))	/* indirect random */
				if ((cmd & 0xffff) == 0)
					return 0;	/* unknown length, too hard */
				else
					return (((cmd & 0xffff) + 1) / 2) + 1;
			else
				return 2;	/* indirect sequential */
		default:
			return 0;
		}
	default:
		return 0;
	}
 
	return 0;
}
 
static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i, ret;
 
	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
		return -EINVAL;
 
	for (i = 0; i < dwords;) {
		int sz = validate_cmd(buffer[i]);
		if (sz == 0 || i + sz > dwords)
			return -EINVAL;
		i += sz;
	}
 
	ret = BEGIN_LP_RING((dwords+1)&~1);
	if (ret)
		return ret;
 
	for (i = 0; i < dwords; i++)
		OUT_RING(buffer[i]);
	if (dwords & 1)
		OUT_RING(0);
 
	ADVANCE_LP_RING();
 
	return 0;
}
 
int
i915_emit_box(struct drm_device *dev,
	      struct drm_clip_rect *box,
	      int DR1, int DR4)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
	    box->y2 <= 0 || box->x2 <= 0) {
		DRM_ERROR("Bad box %d,%d..%d,%d\n",
			  box->x1, box->y1, box->x2, box->y2);
		return -EINVAL;
	}
 
	if (INTEL_INFO(dev)->gen >= 4) {
		ret = BEGIN_LP_RING(4);
		if (ret)
			return ret;
 
		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
		OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
		OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
		OUT_RING(DR4);
	} else {
		ret = BEGIN_LP_RING(6);
		if (ret)
			return ret;
 
		OUT_RING(GFX_OP_DRAWRECT_INFO);
		OUT_RING(DR1);
		OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
		OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
		OUT_RING(DR4);
		OUT_RING(0);
	}
	ADVANCE_LP_RING();
 
	return 0;
}
 
/* XXX: Emitting the counter should really be moved to part of the IRQ
 * emit. For now, do it in both places:
 */
 
static void i915_emit_breadcrumb(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 
	dev_priv->dri1.counter++;
	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
		dev_priv->dri1.counter = 0;
	if (master_priv->sarea_priv)
		master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 
	if (BEGIN_LP_RING(4) == 0) {
		OUT_RING(MI_STORE_DWORD_INDEX);
		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
		OUT_RING(dev_priv->dri1.counter);
		OUT_RING(0);
		ADVANCE_LP_RING();
	}
}
 
static int i915_dispatch_cmdbuffer(struct drm_device * dev,
				   drm_i915_cmdbuffer_t *cmd,
				   struct drm_clip_rect *cliprects,
				   void *cmdbuf)
{
	int nbox = cmd->num_cliprects;
	int i = 0, count, ret;
 
	if (cmd->sz & 0x3) {
		DRM_ERROR("alignment");
		return -EINVAL;
	}
 
	i915_kernel_lost_context(dev);
 
	count = nbox ? nbox : 1;
 
	for (i = 0; i < count; i++) {
		if (i < nbox) {
			ret = i915_emit_box(dev, &cliprects[i],
					    cmd->DR1, cmd->DR4);
			if (ret)
				return ret;
		}
 
		ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
		if (ret)
			return ret;
	}
 
	i915_emit_breadcrumb(dev);
	return 0;
}
 
static int i915_dispatch_batchbuffer(struct drm_device * dev,
				     drm_i915_batchbuffer_t * batch,
				     struct drm_clip_rect *cliprects)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int nbox = batch->num_cliprects;
	int i, count, ret;
 
	if ((batch->start | batch->used) & 0x7) {
		DRM_ERROR("alignment");
		return -EINVAL;
	}
 
	i915_kernel_lost_context(dev);
 
	count = nbox ? nbox : 1;
	for (i = 0; i < count; i++) {
		if (i < nbox) {
			ret = i915_emit_box(dev, &cliprects[i],
					    batch->DR1, batch->DR4);
			if (ret)
				return ret;
		}
 
		if (!IS_I830(dev) && !IS_845G(dev)) {
			ret = BEGIN_LP_RING(2);
			if (ret)
				return ret;
 
			if (INTEL_INFO(dev)->gen >= 4) {
				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
				OUT_RING(batch->start);
			} else {
				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
				OUT_RING(batch->start | MI_BATCH_NON_SECURE);
			}
		} else {
			ret = BEGIN_LP_RING(4);
			if (ret)
				return ret;
 
			OUT_RING(MI_BATCH_BUFFER);
			OUT_RING(batch->start | MI_BATCH_NON_SECURE);
			OUT_RING(batch->start + batch->used - 4);
			OUT_RING(0);
		}
		ADVANCE_LP_RING();
	}
 
 
	if (IS_G4X(dev) || IS_GEN5(dev)) {
		if (BEGIN_LP_RING(2) == 0) {
			OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
			OUT_RING(MI_NOOP);
			ADVANCE_LP_RING();
		}
	}
 
	i915_emit_breadcrumb(dev);
	return 0;
}
 
static int i915_dispatch_flip(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv =
		dev->primary->master->driver_priv;
	int ret;
 
	if (!master_priv->sarea_priv)
		return -EINVAL;
 
	DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
			  __func__,
			 dev_priv->dri1.current_page,
			 master_priv->sarea_priv->pf_current_page);
 
	i915_kernel_lost_context(dev);
 
	ret = BEGIN_LP_RING(10);
	if (ret)
		return ret;
 
	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
	OUT_RING(0);
 
	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
	OUT_RING(0);
	if (dev_priv->dri1.current_page == 0) {
		OUT_RING(dev_priv->dri1.back_offset);
		dev_priv->dri1.current_page = 1;
	} else {
		OUT_RING(dev_priv->dri1.front_offset);
		dev_priv->dri1.current_page = 0;
	}
	OUT_RING(0);
 
	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
	OUT_RING(0);
 
	ADVANCE_LP_RING();
 
	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 
	if (BEGIN_LP_RING(4) == 0) {
		OUT_RING(MI_STORE_DWORD_INDEX);
		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
		OUT_RING(dev_priv->dri1.counter);
		OUT_RING(0);
		ADVANCE_LP_RING();
	}
 
	master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
	return 0;
}
 
static int i915_quiescent(struct drm_device *dev)
{
	i915_kernel_lost_context(dev);
	return intel_ring_idle(LP_RING(dev->dev_private));
}
 
static int i915_flush_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
{
	int ret;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
	mutex_lock(&dev->struct_mutex);
	ret = i915_quiescent(dev);
	mutex_unlock(&dev->struct_mutex);
 
	return ret;
}
 
static int i915_batchbuffer(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
	    master_priv->sarea_priv;
	drm_i915_batchbuffer_t *batch = data;
	int ret;
	struct drm_clip_rect *cliprects = NULL;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	if (!dev_priv->dri1.allow_batchbuffer) {
		DRM_ERROR("Batchbuffer ioctl disabled\n");
		return -EINVAL;
	}
 
	DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
			batch->start, batch->used, batch->num_cliprects);
 
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
	if (batch->num_cliprects < 0)
		return -EINVAL;
 
	if (batch->num_cliprects) {
		cliprects = kcalloc(batch->num_cliprects,
				    sizeof(struct drm_clip_rect),
				    GFP_KERNEL);
		if (cliprects == NULL)
			return -ENOMEM;
 
		ret = copy_from_user(cliprects, batch->cliprects,
				     batch->num_cliprects *
				     sizeof(struct drm_clip_rect));
		if (ret != 0) {
			ret = -EFAULT;
			goto fail_free;
		}
	}
 
	mutex_lock(&dev->struct_mutex);
	ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
	mutex_unlock(&dev->struct_mutex);
 
	if (sarea_priv)
		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 
fail_free:
	kfree(cliprects);
 
	return ret;
}
 
static int i915_cmdbuffer(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
	    master_priv->sarea_priv;
	drm_i915_cmdbuffer_t *cmdbuf = data;
	struct drm_clip_rect *cliprects = NULL;
	void *batch_data;
	int ret;
 
	DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
			cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
	if (cmdbuf->num_cliprects < 0)
		return -EINVAL;
 
	batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
	if (batch_data == NULL)
		return -ENOMEM;
 
	ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
	if (ret != 0) {
		ret = -EFAULT;
		goto fail_batch_free;
	}
 
	if (cmdbuf->num_cliprects) {
		cliprects = kcalloc(cmdbuf->num_cliprects,
				    sizeof(struct drm_clip_rect), GFP_KERNEL);
		if (cliprects == NULL) {
			ret = -ENOMEM;
			goto fail_batch_free;
		}
 
		ret = copy_from_user(cliprects, cmdbuf->cliprects,
				     cmdbuf->num_cliprects *
				     sizeof(struct drm_clip_rect));
		if (ret != 0) {
			ret = -EFAULT;
			goto fail_clip_free;
		}
	}
 
	mutex_lock(&dev->struct_mutex);
	ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
	mutex_unlock(&dev->struct_mutex);
	if (ret) {
		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
		goto fail_clip_free;
	}
 
	if (sarea_priv)
		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 
fail_clip_free:
	kfree(cliprects);
fail_batch_free:
	kfree(batch_data);
 
	return ret;
}
 
static int i915_emit_irq(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 
	i915_kernel_lost_context(dev);
 
	DRM_DEBUG_DRIVER("\n");
 
	dev_priv->dri1.counter++;
	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
		dev_priv->dri1.counter = 1;
	if (master_priv->sarea_priv)
		master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 
	if (BEGIN_LP_RING(4) == 0) {
		OUT_RING(MI_STORE_DWORD_INDEX);
		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
		OUT_RING(dev_priv->dri1.counter);
		OUT_RING(MI_USER_INTERRUPT);
		ADVANCE_LP_RING();
	}
 
	return dev_priv->dri1.counter;
}
 
static int i915_wait_irq(struct drm_device * dev, int irq_nr)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
	int ret = 0;
	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 
	DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
		  READ_BREADCRUMB(dev_priv));
 
	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
		if (master_priv->sarea_priv)
			master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
		return 0;
	}
 
	if (master_priv->sarea_priv)
		master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 
	if (ring->irq_get(ring)) {
		DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
			    READ_BREADCRUMB(dev_priv) >= irq_nr);
		ring->irq_put(ring);
	} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
		ret = -EBUSY;
 
	if (ret == -EBUSY) {
		DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
			  READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
	}
 
	return ret;
}
 
/* Needs the lock as it touches the ring.
 */
static int i915_irq_emit(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_irq_emit_t *emit = data;
	int result;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
 
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
	mutex_lock(&dev->struct_mutex);
	result = i915_emit_irq(dev);
	mutex_unlock(&dev->struct_mutex);
 
	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
		DRM_ERROR("copy_to_user\n");
		return -EFAULT;
	}
 
	return 0;
}
 
/* Doesn't need the hardware lock.
 */
static int i915_irq_wait(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_irq_wait_t *irqwait = data;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
 
	return i915_wait_irq(dev, irqwait->irq_seq);
}
 
static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_vblank_pipe_t *pipe = data;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
 
	pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
	return 0;
}
 
/**
 * Schedule buffer swap at given vertical blank.
 */
static int i915_vblank_swap(struct drm_device *dev, void *data,
		     struct drm_file *file_priv)
{
	/* The delayed swap mechanism was fundamentally racy, and has been
	 * removed.  The model was that the client requested a delayed flip/swap
	 * from the kernel, then waited for vblank before continuing to perform
	 * rendering.  The problem was that the kernel might wake the client
	 * up before it dispatched the vblank swap (since the lock has to be
	 * held while touching the ringbuffer), in which case the client would
	 * clear and start the next frame before the swap occurred, and
	 * flicker would occur in addition to likely missing the vblank.
	 *
	 * In the absence of this ioctl, userland falls back to a correct path
	 * of waiting for a vblank, then dispatching the swap on its own.
	 * Context switching to userland and back is plenty fast enough for
	 * meeting the requirements of vblank swapping.
	 */
	return -EINVAL;
}
 
static int i915_flip_bufs(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
{
	int ret;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
 
	DRM_DEBUG_DRIVER("%s\n", __func__);
 
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
	mutex_lock(&dev->struct_mutex);
	ret = i915_dispatch_flip(dev);
	mutex_unlock(&dev->struct_mutex);
 
	return ret;
}
#endif
 
static int i915_getparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_getparam_t *param = data;
	int value;
 
	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
 
	switch (param->param) {
	case I915_PARAM_IRQ_ACTIVE:
		value = dev->pdev->irq ? 1 : 0;
		break;
	case I915_PARAM_ALLOW_BATCHBUFFER:
		value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
		break;
	case I915_PARAM_LAST_DISPATCH:
		value = READ_BREADCRUMB(dev_priv);
		break;
	case I915_PARAM_CHIPSET_ID:
		value = dev->pci_device;
		break;
	case I915_PARAM_HAS_GEM:
		value = 1;
		break;
	case I915_PARAM_NUM_FENCES_AVAIL:
		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
		break;
	case I915_PARAM_HAS_OVERLAY:
		value = dev_priv->overlay ? 1 : 0;
		break;
	case I915_PARAM_HAS_PAGEFLIPPING:
		value = 1;
		break;
	case I915_PARAM_HAS_EXECBUF2:
		/* depends on GEM */
		value = 1;
		break;
	case I915_PARAM_HAS_BSD:
		value = intel_ring_initialized(&dev_priv->ring[VCS]);
		break;
	case I915_PARAM_HAS_BLT:
		value = intel_ring_initialized(&dev_priv->ring[BCS]);
		break;
	case I915_PARAM_HAS_RELAXED_FENCING:
		value = 1;
		break;
	case I915_PARAM_HAS_COHERENT_RINGS:
		value = 1;
		break;
	case I915_PARAM_HAS_EXEC_CONSTANTS:
		value = INTEL_INFO(dev)->gen >= 4;
		break;
	case I915_PARAM_HAS_RELAXED_DELTA:
		value = 1;
		break;
	case I915_PARAM_HAS_GEN7_SOL_RESET:
		value = 1;
		break;
	case I915_PARAM_HAS_LLC:
		value = HAS_LLC(dev);
		break;
	case I915_PARAM_HAS_ALIASING_PPGTT:
		value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
		break;
	case I915_PARAM_HAS_WAIT_TIMEOUT:
		value = 1;
		break;
	case I915_PARAM_HAS_SEMAPHORES:
		value = i915_semaphore_is_enabled(dev);
		break;
	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
		value = 1;
		break;
	case I915_PARAM_HAS_SECURE_BATCHES:
        value = 1;
		break;
	case I915_PARAM_HAS_PINNED_BATCHES:
		value = 1;
		break;
	case I915_PARAM_HAS_EXEC_NO_RELOC:
		value = 1;
        break;
	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
        value = 1;
        break;
	default:
		DRM_DEBUG_DRIVER("Unknown parameter %d\n",
				 param->param);
		return -EINVAL;
	}
 
//   if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
//       DRM_ERROR("DRM_COPY_TO_USER failed\n");
//       return -EFAULT;
//   }
 
    *param->value = value;
 
	return 0;
}
 
#if 0
static int i915_setparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_setparam_t *param = data;
 
	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
 
	switch (param->param) {
	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
		break;
	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
		break;
	case I915_SETPARAM_ALLOW_BATCHBUFFER:
		dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
		break;
	case I915_SETPARAM_NUM_USED_FENCES:
		if (param->value > dev_priv->num_fence_regs ||
		    param->value < 0)
			return -EINVAL;
		/* Userspace can use first N regs */
		dev_priv->fence_reg_start = param->value;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown parameter %d\n",
					param->param);
		return -EINVAL;
	}
 
	return 0;
}
#endif
 
 
 
static int i915_get_bridge_dev(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
 
	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	if (!dev_priv->bridge_dev) {
		DRM_ERROR("bridge device not found\n");
		return -1;
	}
	return 0;
}
 
#define MCHBAR_I915 0x44
#define MCHBAR_I965 0x48
#define MCHBAR_SIZE (4*4096)
 
#define DEVEN_REG 0x54
#define   DEVEN_MCHBAR_EN (1 << 28)
 
 
 
 
/* Setup MCHBAR if possible, return true if we should disable it again */
static void
intel_setup_mchbar(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
	u32 temp;
	bool enabled;
 
	dev_priv->mchbar_need_disable = false;
 
	if (IS_I915G(dev) || IS_I915GM(dev)) {
		pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
		enabled = !!(temp & DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		enabled = temp & 1;
	}
 
	/* If it's already enabled, don't have to do anything */
	if (enabled)
		return;
 
	dbgprintf("Epic fail\n");
 
#if 0
	if (intel_alloc_mchbar_resource(dev))
		return;
 
	dev_priv->mchbar_need_disable = true;
 
	/* Space is allocated or reserved, so enable it. */
	if (IS_I915G(dev) || IS_I915GM(dev)) {
		pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
				       temp | DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
	}
#endif
}
 
 
/* true = enable decode, false = disable decoder */
static unsigned int i915_vga_set_decode(void *cookie, bool state)
{
	struct drm_device *dev = cookie;
 
	intel_modeset_vga_set_state(dev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
 
 
 
 
 
 
static int i915_load_modeset_init(struct drm_device *dev)
{
    struct drm_i915_private *dev_priv = dev->dev_private;
    int ret;
 
    ret = intel_parse_bios(dev);
    if (ret)
        DRM_INFO("failed to find VBIOS tables\n");
 
//    intel_register_dsm_handler();
 
	/* Initialise stolen first so that we may reserve preallocated
	 * objects for the BIOS to KMS transition.
	 */
	ret = i915_gem_init_stolen(dev);
	if (ret)
		goto cleanup_vga_switcheroo;
 
	ret = drm_irq_install(dev);
	if (ret)
		goto cleanup_gem_stolen;
 
	/* Important: The output setup functions called by modeset_init need
	 * working irqs for e.g. gmbus and dp aux transfers. */
    intel_modeset_init(dev);
 
	ret = i915_gem_init(dev);
    if (ret)
		goto cleanup_irq;
 
 
    intel_modeset_gem_init(dev);
 
    /* Always safe in the mode setting case. */
    /* FIXME: do pre/post-mode set stuff in core KMS code */
    dev->vblank_disable_allowed = 1;
 
    ret = intel_fbdev_init(dev);
    if (ret)
		goto cleanup_gem;
 
	/* Only enable hotplug handling once the fbdev is fully set up. */
	intel_hpd_init(dev);
 
	/*
	 * Some ports require correctly set-up hpd registers for detection to
	 * work properly (leading to ghost connected connector status), e.g. VGA
	 * on gm45.  Hence we can only set up the initial fbdev config after hpd
	 * irqs are fully enabled. Now we should scan for the initial config
	 * only once hotplug handling is enabled, but due to screwed-up locking
	 * around kms/fbdev init we can't protect the fdbev initial config
	 * scanning against hotplug events. Hence do this first and ignore the
	 * tiny window where we will loose hotplug notifactions.
	 */
	intel_fbdev_initial_config(dev);
 
	/* Only enable hotplug handling once the fbdev is fully set up. */
	dev_priv->enable_hotplug_processing = true;
 
	drm_kms_helper_poll_init(dev);
 
    /* We're off and running w/KMS */
    dev_priv->mm.suspended = 0;
 
    return 0;
 
cleanup_gem:
	mutex_lock(&dev->struct_mutex);
	i915_gem_cleanup_ringbuffer(dev);
	mutex_unlock(&dev->struct_mutex);
	i915_gem_cleanup_aliasing_ppgtt(dev);
cleanup_irq:
//    drm_irq_uninstall(dev);
cleanup_gem_stolen:
//	i915_gem_cleanup_stolen(dev);
cleanup_vga_switcheroo:
//    vga_switcheroo_unregister_client(dev->pdev);
cleanup_vga_client:
//    vga_client_register(dev->pdev, NULL, NULL, NULL);
out:
    return ret;
}
 
 
 
 
static void i915_dump_device_info(struct drm_i915_private *dev_priv)
{
	const struct intel_device_info *info = dev_priv->info;
 
#define DEV_INFO_FLAG(name) info->name ? #name "," : ""
#define DEV_INFO_SEP ,
	DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
			 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
			 info->gen,
			 dev_priv->dev->pdev->device,
			 DEV_INFO_FLAGS);
#undef DEV_INFO_FLAG
#undef DEV_INFO_SEP
}
 
/**
 * i915_driver_load - setup chip and create an initial config
 * @dev: DRM device
 * @flags: startup flags
 *
 * The driver load routine has to do several things:
 *   - drive output discovery via intel_modeset_init()
 *   - initialize the memory manager
 *   - allocate initial config memory
 *   - setup the DRM framebuffer with the allocated memory
 */
int i915_driver_load(struct drm_device *dev, unsigned long flags)
{
    struct drm_i915_private *dev_priv;
	struct intel_device_info *info;
	int ret = 0, mmio_bar, mmio_size;
	uint32_t aperture_size;
 
	info = (struct intel_device_info *) flags;
 
 
    dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
    if (dev_priv == NULL)
        return -ENOMEM;
 
    dev->dev_private = (void *)dev_priv;
    dev_priv->dev = dev;
	dev_priv->info = info;
 
	i915_dump_device_info(dev_priv);
 
    if (i915_get_bridge_dev(dev)) {
        ret = -EIO;
        goto free_priv;
    }
 
	ret = i915_gem_gtt_init(dev);
	if (ret)
		goto put_bridge;
 
 
	pci_set_master(dev->pdev);
 
    /* overlay on gen2 is broken and can't address above 1G */
 
    /* 965GM sometimes incorrectly writes to hardware status page (HWS)
     * using 32bit addressing, overwriting memory if HWS is located
     * above 4GB.
     *
     * The documentation also mentions an issue with undefined
     * behaviour if any general state is accessed within a page above 4GB,
     * which also needs to be handled carefully.
     */
 
    mmio_bar = IS_GEN2(dev) ? 1 : 0;
	/* Before gen4, the registers and the GTT are behind different BARs.
	 * However, from gen4 onwards, the registers and the GTT are shared
	 * in the same BAR, so we want to restrict this ioremap from
	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
	 * the register BAR remains the same size for all the earlier
	 * generations up to Ironlake.
	 */
	if (info->gen < 5)
		mmio_size = 512*1024;
	else
		mmio_size = 2*1024*1024;
 
	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
    if (!dev_priv->regs) {
        DRM_ERROR("failed to map registers\n");
        ret = -EIO;
		goto put_gmch;
    }
 
	aperture_size = dev_priv->gtt.mappable_end;
 
 
 
    /* The i915 workqueue is primarily used for batched retirement of
     * requests (and thus managing bo) once the task has been completed
     * by the GPU. i915_gem_retire_requests() is called directly when we
     * need high-priority retirement, such as waiting for an explicit
     * bo.
     *
     * It is also used for periodic low-priority events, such as
     * idle-timers and recording error state.
     *
     * All tasks on the workqueue are expected to acquire the dev mutex
     * so there is no point in running more than one instance of the
	 * workqueue at any time.  Use an ordered one.
     */
	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
      if (dev_priv->wq == NULL) {
          DRM_ERROR("Failed to create our workqueue.\n");
          ret = -ENOMEM;
          goto out_mtrrfree;
      }
    system_wq = dev_priv->wq;
 
	/* This must be called before any calls to HAS_PCH_* */
	intel_detect_pch(dev);
 
	intel_irq_init(dev);
	intel_gt_init(dev);
 
    /* Try to make sure MCHBAR is enabled before poking at it */
	intel_setup_mchbar(dev);
    intel_setup_gmbus(dev);
    intel_opregion_setup(dev);
 
    intel_setup_bios(dev);
 
    i915_gem_load(dev);
 
    /* On the 945G/GM, the chipset reports the MSI capability on the
     * integrated graphics even though the support isn't actually there
     * according to the published specs.  It doesn't appear to function
     * correctly in testing on 945G.
     * This may be a side effect of MSI having been made available for PEG
     * and the registers being closely associated.
     *
     * According to chipset errata, on the 965GM, MSI interrupts may
     * be lost or delayed, but we use them anyways to avoid
     * stuck interrupts on some machines.
     */
 
    spin_lock_init(&dev_priv->irq_lock);
	spin_lock_init(&dev_priv->gpu_error.lock);
	spin_lock_init(&dev_priv->rps.lock);
	mutex_init(&dev_priv->dpio_lock);
 
	mutex_init(&dev_priv->rps.hw_lock);
	mutex_init(&dev_priv->modeset_restore_lock);
 
	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
		dev_priv->num_pipe = 3;
	else if (IS_MOBILE(dev) || !IS_GEN2(dev))
        dev_priv->num_pipe = 2;
    else
        dev_priv->num_pipe = 1;
 
//    ret = drm_vblank_init(dev, dev_priv->num_pipe);
//    if (ret)
//        goto out_gem_unload;
 
    /* Start out suspended */
    dev_priv->mm.suspended = 1;
 
    ret = i915_load_modeset_init(dev);
    if (ret < 0) {
        DRM_ERROR("failed to init modeset\n");
            goto out_gem_unload;
    }
 
    /* Must be done after probing outputs */
 
 
	if (IS_GEN5(dev))
		intel_gpu_ips_init(dev_priv);
 
    return 0;
 
out_gem_unload:
//    if (dev_priv->mm.inactive_shrinker.shrink)
//        unregister_shrinker(&dev_priv->mm.inactive_shrinker);
 
//    if (dev->pdev->msi_enabled)
//        pci_disable_msi(dev->pdev);
 
//    intel_teardown_gmbus(dev);
//    intel_teardown_mchbar(dev);
//    destroy_workqueue(dev_priv->wq);
out_mtrrfree:
//	if (dev_priv->mm.gtt_mtrr >= 0) {
//		mtrr_del(dev_priv->mm.gtt_mtrr,
//			 dev_priv->mm.gtt_base_addr,
//			 aperture_size);
//		dev_priv->mm.gtt_mtrr = -1;
//	}
//	io_mapping_free(dev_priv->mm.gtt_mapping);
out_rmmap:
    pci_iounmap(dev->pdev, dev_priv->regs);
put_gmch:
//	dev_priv->gtt.gtt_remove(dev);
put_bridge:
//    pci_dev_put(dev_priv->bridge_dev);
free_priv:
    kfree(dev_priv);
    return ret;
}
 
#if 0
 
int i915_driver_unload(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;
 
	intel_gpu_ips_teardown();
 
	i915_teardown_sysfs(dev);
 
	if (dev_priv->mm.inactive_shrinker.shrink)
		unregister_shrinker(&dev_priv->mm.inactive_shrinker);
 
	mutex_lock(&dev->struct_mutex);
	ret = i915_gpu_idle(dev);
	if (ret)
		DRM_ERROR("failed to idle hardware: %d\n", ret);
	i915_gem_retire_requests(dev);
	mutex_unlock(&dev->struct_mutex);
 
	/* Cancel the retire work handler, which should be idle now. */
	cancel_delayed_work_sync(&dev_priv->mm.retire_work);
 
	io_mapping_free(dev_priv->gtt.mappable);
	if (dev_priv->mm.gtt_mtrr >= 0) {
		mtrr_del(dev_priv->mm.gtt_mtrr,
			 dev_priv->gtt.mappable_base,
			 dev_priv->gtt.mappable_end);
		dev_priv->mm.gtt_mtrr = -1;
	}
 
	acpi_video_unregister();
 
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		intel_fbdev_fini(dev);
		intel_modeset_cleanup(dev);
		cancel_work_sync(&dev_priv->console_resume_work);
 
		/*
		 * free the memory space allocated for the child device
		 * config parsed from VBT
		 */
		if (dev_priv->child_dev && dev_priv->child_dev_num) {
			kfree(dev_priv->child_dev);
			dev_priv->child_dev = NULL;
			dev_priv->child_dev_num = 0;
		}
 
		vga_switcheroo_unregister_client(dev->pdev);
		vga_client_register(dev->pdev, NULL, NULL, NULL);
	}
 
	/* Free error state after interrupts are fully disabled. */
	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
	cancel_work_sync(&dev_priv->gpu_error.work);
	i915_destroy_error_state(dev);
 
	if (dev->pdev->msi_enabled)
		pci_disable_msi(dev->pdev);
 
	intel_opregion_fini(dev);
 
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Flush any outstanding unpin_work. */
		flush_workqueue(dev_priv->wq);
 
		mutex_lock(&dev->struct_mutex);
		i915_gem_free_all_phys_object(dev);
		i915_gem_cleanup_ringbuffer(dev);
		i915_gem_context_fini(dev);
		mutex_unlock(&dev->struct_mutex);
		i915_gem_cleanup_aliasing_ppgtt(dev);
		i915_gem_cleanup_stolen(dev);
 
		if (!I915_NEED_GFX_HWS(dev))
			i915_free_hws(dev);
	}
 
	if (dev_priv->regs != NULL)
		pci_iounmap(dev->pdev, dev_priv->regs);
 
	intel_teardown_gmbus(dev);
	intel_teardown_mchbar(dev);
 
	destroy_workqueue(dev_priv->wq);
	pm_qos_remove_request(&dev_priv->pm_qos);
 
	if (dev_priv->slab)
		kmem_cache_destroy(dev_priv->slab);
 
	pci_dev_put(dev_priv->bridge_dev);
	kfree(dev->dev_private);
 
	return 0;
}
#endif
 
int i915_driver_open(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv;
 
	DRM_DEBUG_DRIVER("\n");
	file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
	if (!file_priv)
		return -ENOMEM;
 
	file->driver_priv = file_priv;
 
	spin_lock_init(&file_priv->mm.lock);
	INIT_LIST_HEAD(&file_priv->mm.request_list);
 
	idr_init(&file_priv->context_idr);
 
	return 0;
}
 
#if 0
/**
 * i915_driver_lastclose - clean up after all DRM clients have exited
 * @dev: DRM device
 *
 * Take care of cleaning up after all DRM clients have exited.  In the
 * mode setting case, we want to restore the kernel's initial mode (just
 * in case the last client left us in a bad state).
 *
 * Additionally, in the non-mode setting case, we'll tear down the GTT
 * and DMA structures, since the kernel won't be using them, and clea
 * up any GEM state.
 */
void i915_driver_lastclose(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
 
	/* On gen6+ we refuse to init without kms enabled, but then the drm core
	 * goes right around and calls lastclose. Check for this and don't clean
	 * up anything. */
	if (!dev_priv)
		return;
 
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		intel_fb_restore_mode(dev);
		vga_switcheroo_process_delayed_switch();
		return;
	}
 
	i915_gem_lastclose(dev);
 
	i915_dma_cleanup(dev);
}
 
void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
{
	i915_gem_context_close(dev, file_priv);
	i915_gem_release(dev, file_priv);
}
 
void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv = file->driver_priv;
 
	kfree(file_priv);
}
 
struct drm_ioctl_desc i915_ioctls[] = {
	DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
};
 
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 
/*
 * This is really ugly: Because old userspace abused the linux agp interface to
 * manage the gtt, we need to claim that all intel devices are agp.  For
 * otherwise the drm core refuses to initialize the agp support code.
 */
int i915_driver_device_is_agp(struct drm_device * dev)
{
	return 1;
}
#endif
 
 
int gem_getparam(struct drm_device *dev, void *data)
{
    return i915_getparam(dev, data, NULL);
};

Rev 3480	Rev 3482
1	/* i915_dma.c -- DMA support for the I915 -- linux-c --	1	/* i915_dma.c -- DMA support for the I915 -- linux-c --
2	*/	2	*/
3	/*	3	/*
4	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.	4	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5	* All Rights Reserved.	5	* All Rights Reserved.
6	*	6	*
7	* Permission is hereby granted, free of charge, to any person obtaining a	7	* Permission is hereby granted, free of charge, to any person obtaining a
8	* copy of this software and associated documentation files (the	8	* copy of this software and associated documentation files (the
9	* "Software"), to deal in the Software without restriction, including	9	* "Software"), to deal in the Software without restriction, including
10	* without limitation the rights to use, copy, modify, merge, publish,	10	* without limitation the rights to use, copy, modify, merge, publish,
11	* distribute, sub license, and/or sell copies of the Software, and to	11	* distribute, sub license, and/or sell copies of the Software, and to
12	* permit persons to whom the Software is furnished to do so, subject to	12	* permit persons to whom the Software is furnished to do so, subject to
13	* the following conditions:	13	* the following conditions:
14	*	14	*
15	* The above copyright notice and this permission notice (including the	15	* The above copyright notice and this permission notice (including the
16	* next paragraph) shall be included in all copies or substantial portions	16	* next paragraph) shall be included in all copies or substantial portions
17	* of the Software.	17	* of the Software.
18	*	18	*
19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF	20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.	21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR	22	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,	23	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE	24	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.	25	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26	*	26	*
27	*/	27	*/
28		28
29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30		30
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	#include "intel_drv.h"	34	#include "intel_drv.h"
35	#include	35	#include
36	#include "i915_drv.h"	36	#include "i915_drv.h"
37	#include "i915_trace.h"	37	#include "i915_trace.h"
38	#include	38	#include
39	//#include	39	//#include
40	//#include	40	//#include
41	//#include	41	//#include
42	//#include	42	//#include
43	#include	43	#include
44	//#include	44	//#include
45		45
46	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen);	46	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen);
47		47
48		48
49	#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])	49	#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
50		50
51	#define BEGIN_LP_RING(n) \	51	#define BEGIN_LP_RING(n) \
52	intel_ring_begin(LP_RING(dev_priv), (n))	52	intel_ring_begin(LP_RING(dev_priv), (n))
53		53
54	#define OUT_RING(x) \	54	#define OUT_RING(x) \
55	intel_ring_emit(LP_RING(dev_priv), x)	55	intel_ring_emit(LP_RING(dev_priv), x)
56		56
57	#define ADVANCE_LP_RING() \	57	#define ADVANCE_LP_RING() \
58	intel_ring_advance(LP_RING(dev_priv))	58	intel_ring_advance(LP_RING(dev_priv))
59		59
60	/**	60	/**
61	* Lock test for when it's just for synchronization of ring access.	61	* Lock test for when it's just for synchronization of ring access.
62	*	62	*
63	* In that case, we don't need to do it when GEM is initialized as nobody else	63	* In that case, we don't need to do it when GEM is initialized as nobody else
64	* has access to the ring.	64	* has access to the ring.
65	*/	65	*/
66	#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \	66	#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
67	if (LP_RING(dev->dev_private)->obj == NULL) \	67	if (LP_RING(dev->dev_private)->obj == NULL) \
68	LOCK_TEST_WITH_RETURN(dev, file); \	68	LOCK_TEST_WITH_RETURN(dev, file); \
69	} while (0)	69	} while (0)
70		70
71	static inline u32	71	static inline u32
72	intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)	72	intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
73	{	73	{
74	if (I915_NEED_GFX_HWS(dev_priv->dev))	74	if (I915_NEED_GFX_HWS(dev_priv->dev))
75	return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);	75	return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
76	else	76	else
77	return intel_read_status_page(LP_RING(dev_priv), reg);	77	return intel_read_status_page(LP_RING(dev_priv), reg);
78	}	78	}
79		79
80	#define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)	80	#define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
81	#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)	81	#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
82	#define I915_BREADCRUMB_INDEX 0x21	82	#define I915_BREADCRUMB_INDEX 0x21
83		83
84	void i915_update_dri1_breadcrumb(struct drm_device *dev)	84	void i915_update_dri1_breadcrumb(struct drm_device *dev)
85	{	85	{
86	drm_i915_private_t *dev_priv = dev->dev_private;	86	drm_i915_private_t *dev_priv = dev->dev_private;
87	struct drm_i915_master_private *master_priv;	87	struct drm_i915_master_private *master_priv;
88		88
89	if (dev->primary->master) {	89	if (dev->primary->master) {
90	master_priv = dev->primary->master->driver_priv;	90	master_priv = dev->primary->master->driver_priv;
91	if (master_priv->sarea_priv)	91	if (master_priv->sarea_priv)
92	master_priv->sarea_priv->last_dispatch =	92	master_priv->sarea_priv->last_dispatch =
93	READ_BREADCRUMB(dev_priv);	93	READ_BREADCRUMB(dev_priv);
94	}	94	}
95	}	95	}
96		96
97	static void i915_write_hws_pga(struct drm_device *dev)	97	static void i915_write_hws_pga(struct drm_device *dev)
98	{	98	{
99	drm_i915_private_t *dev_priv = dev->dev_private;	99	drm_i915_private_t *dev_priv = dev->dev_private;
100	u32 addr;	100	u32 addr;
101		101
102	addr = dev_priv->status_page_dmah->busaddr;	102	addr = dev_priv->status_page_dmah->busaddr;
103	if (INTEL_INFO(dev)->gen >= 4)	103	if (INTEL_INFO(dev)->gen >= 4)
104	addr \|= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;	104	addr \|= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
105	I915_WRITE(HWS_PGA, addr);	105	I915_WRITE(HWS_PGA, addr);
106	}	106	}
107		107
108	/**	108	/**
109	* Frees the hardware status page, whether it's a physical address or a virtual	109	* Frees the hardware status page, whether it's a physical address or a virtual
110	* address set up by the X Server.	110	* address set up by the X Server.
111	*/	111	*/
112	static void i915_free_hws(struct drm_device *dev)	112	static void i915_free_hws(struct drm_device *dev)
113	{	113	{
114	drm_i915_private_t *dev_priv = dev->dev_private;	114	drm_i915_private_t *dev_priv = dev->dev_private;
115	struct intel_ring_buffer *ring = LP_RING(dev_priv);	115	struct intel_ring_buffer *ring = LP_RING(dev_priv);
116		116
117	if (dev_priv->status_page_dmah) {	117	if (dev_priv->status_page_dmah) {
118	drm_pci_free(dev, dev_priv->status_page_dmah);	118	drm_pci_free(dev, dev_priv->status_page_dmah);
119	dev_priv->status_page_dmah = NULL;	119	dev_priv->status_page_dmah = NULL;
120	}	120	}
121		121
122	if (ring->status_page.gfx_addr) {	122	if (ring->status_page.gfx_addr) {
123	ring->status_page.gfx_addr = 0;	123	ring->status_page.gfx_addr = 0;
124	iounmap(dev_priv->dri1.gfx_hws_cpu_addr);	124	iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
125	}	125	}
126		126
127	/* Need to rewrite hardware status page */	127	/* Need to rewrite hardware status page */
128	I915_WRITE(HWS_PGA, 0x1ffff000);	128	I915_WRITE(HWS_PGA, 0x1ffff000);
129	}	129	}
130		130
131	#if 0	131	#if 0
132		132
133	void i915_kernel_lost_context(struct drm_device * dev)	133	void i915_kernel_lost_context(struct drm_device * dev)
134	{	134	{
135	drm_i915_private_t *dev_priv = dev->dev_private;	135	drm_i915_private_t *dev_priv = dev->dev_private;
136	struct drm_i915_master_private *master_priv;	136	struct drm_i915_master_private *master_priv;
137	struct intel_ring_buffer *ring = LP_RING(dev_priv);	137	struct intel_ring_buffer *ring = LP_RING(dev_priv);
138		138
139	/*	139	/*
140	* We should never lose context on the ring with modesetting	140	* We should never lose context on the ring with modesetting
141	* as we don't expose it to userspace	141	* as we don't expose it to userspace
142	*/	142	*/
143	if (drm_core_check_feature(dev, DRIVER_MODESET))	143	if (drm_core_check_feature(dev, DRIVER_MODESET))
144	return;	144	return;
145		145
146	ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;	146	ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
147	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;	147	ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
148	ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);	148	ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
149	if (ring->space < 0)	149	if (ring->space < 0)
150	ring->space += ring->size;	150	ring->space += ring->size;
151		151
152	if (!dev->primary->master)	152	if (!dev->primary->master)
153	return;	153	return;
154		154
155	master_priv = dev->primary->master->driver_priv;	155	master_priv = dev->primary->master->driver_priv;
156	if (ring->head == ring->tail && master_priv->sarea_priv)	156	if (ring->head == ring->tail && master_priv->sarea_priv)
157	master_priv->sarea_priv->perf_boxes \|= I915_BOX_RING_EMPTY;	157	master_priv->sarea_priv->perf_boxes \|= I915_BOX_RING_EMPTY;
158	}	158	}
159		159
160	static int i915_dma_cleanup(struct drm_device * dev)	160	static int i915_dma_cleanup(struct drm_device * dev)
161	{	161	{
162	drm_i915_private_t *dev_priv = dev->dev_private;	162	drm_i915_private_t *dev_priv = dev->dev_private;
163	int i;	163	int i;
164		164
165	/* Make sure interrupts are disabled here because the uninstall ioctl	165	/* Make sure interrupts are disabled here because the uninstall ioctl
166	* may not have been called from userspace and after dev_private	166	* may not have been called from userspace and after dev_private
167	* is freed, it's too late.	167	* is freed, it's too late.
168	*/	168	*/
169	if (dev->irq_enabled)	169	if (dev->irq_enabled)
170	drm_irq_uninstall(dev);	170	drm_irq_uninstall(dev);
171		171
172	mutex_lock(&dev->struct_mutex);	172	mutex_lock(&dev->struct_mutex);
173	for (i = 0; i < I915_NUM_RINGS; i++)	173	for (i = 0; i < I915_NUM_RINGS; i++)
174	intel_cleanup_ring_buffer(&dev_priv->ring[i]);	174	intel_cleanup_ring_buffer(&dev_priv->ring[i]);
175	mutex_unlock(&dev->struct_mutex);	175	mutex_unlock(&dev->struct_mutex);
176		176
177	/* Clear the HWS virtual address at teardown */	177	/* Clear the HWS virtual address at teardown */
178	if (I915_NEED_GFX_HWS(dev))	178	if (I915_NEED_GFX_HWS(dev))
179	i915_free_hws(dev);	179	i915_free_hws(dev);
180		180
181	return 0;	181	return 0;
182	}	182	}
183		183
184	static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)	184	static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
185	{	185	{
186	drm_i915_private_t *dev_priv = dev->dev_private;	186	drm_i915_private_t *dev_priv = dev->dev_private;
187	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;	187	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
188	int ret;	188	int ret;
189		189
190	master_priv->sarea = drm_getsarea(dev);	190	master_priv->sarea = drm_getsarea(dev);
191	if (master_priv->sarea) {	191	if (master_priv->sarea) {
192	master_priv->sarea_priv = (drm_i915_sarea_t *)	192	master_priv->sarea_priv = (drm_i915_sarea_t *)
193	((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);	193	((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
194	} else {	194	} else {
195	DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");	195	DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
196	}	196	}
197		197
198	if (init->ring_size != 0) {	198	if (init->ring_size != 0) {
199	if (LP_RING(dev_priv)->obj != NULL) {	199	if (LP_RING(dev_priv)->obj != NULL) {
200	i915_dma_cleanup(dev);	200	i915_dma_cleanup(dev);
201	DRM_ERROR("Client tried to initialize ringbuffer in "	201	DRM_ERROR("Client tried to initialize ringbuffer in "
202	"GEM mode\n");	202	"GEM mode\n");
203	return -EINVAL;	203	return -EINVAL;
204	}	204	}
205		205
206	ret = intel_render_ring_init_dri(dev,	206	ret = intel_render_ring_init_dri(dev,
207	init->ring_start,	207	init->ring_start,
208	init->ring_size);	208	init->ring_size);
209	if (ret) {	209	if (ret) {
210	i915_dma_cleanup(dev);	210	i915_dma_cleanup(dev);
211	return ret;	211	return ret;
212	}	212	}
213	}	213	}
214		214
215	dev_priv->dri1.cpp = init->cpp;	215	dev_priv->dri1.cpp = init->cpp;
216	dev_priv->dri1.back_offset = init->back_offset;	216	dev_priv->dri1.back_offset = init->back_offset;
217	dev_priv->dri1.front_offset = init->front_offset;	217	dev_priv->dri1.front_offset = init->front_offset;
218	dev_priv->dri1.current_page = 0;	218	dev_priv->dri1.current_page = 0;
219	if (master_priv->sarea_priv)	219	if (master_priv->sarea_priv)
220	master_priv->sarea_priv->pf_current_page = 0;	220	master_priv->sarea_priv->pf_current_page = 0;
221		221
222	/* Allow hardware batchbuffers unless told otherwise.	222	/* Allow hardware batchbuffers unless told otherwise.
223	*/	223	*/
224	dev_priv->dri1.allow_batchbuffer = 1;	224	dev_priv->dri1.allow_batchbuffer = 1;
225		225
226	return 0;	226	return 0;
227	}	227	}
228		228
229	static int i915_dma_resume(struct drm_device * dev)	229	static int i915_dma_resume(struct drm_device * dev)
230	{	230	{
231	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;	231	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
232	struct intel_ring_buffer *ring = LP_RING(dev_priv);	232	struct intel_ring_buffer *ring = LP_RING(dev_priv);
233		233
234	DRM_DEBUG_DRIVER("%s\n", __func__);	234	DRM_DEBUG_DRIVER("%s\n", __func__);
235		235
236	if (ring->virtual_start == NULL) {	236	if (ring->virtual_start == NULL) {
237	DRM_ERROR("can not ioremap virtual address for"	237	DRM_ERROR("can not ioremap virtual address for"
238	" ring buffer\n");	238	" ring buffer\n");
239	return -ENOMEM;	239	return -ENOMEM;
240	}	240	}
241		241
242	/* Program Hardware Status Page */	242	/* Program Hardware Status Page */
243	if (!ring->status_page.page_addr) {	243	if (!ring->status_page.page_addr) {
244	DRM_ERROR("Can not find hardware status page\n");	244	DRM_ERROR("Can not find hardware status page\n");
245	return -EINVAL;	245	return -EINVAL;
246	}	246	}
247	DRM_DEBUG_DRIVER("hw status page @ %p\n",	247	DRM_DEBUG_DRIVER("hw status page @ %p\n",
248	ring->status_page.page_addr);	248	ring->status_page.page_addr);
249	if (ring->status_page.gfx_addr != 0)	249	if (ring->status_page.gfx_addr != 0)
250	intel_ring_setup_status_page(ring);	250	intel_ring_setup_status_page(ring);
251	else	251	else
252	i915_write_hws_pga(dev);	252	i915_write_hws_pga(dev);
253		253
254	DRM_DEBUG_DRIVER("Enabled hardware status page\n");	254	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
255		255
256	return 0;	256	return 0;
257	}	257	}
258		258
259	static int i915_dma_init(struct drm_device dev, void data,	259	static int i915_dma_init(struct drm_device dev, void data,
260	struct drm_file *file_priv)	260	struct drm_file *file_priv)
261	{	261	{
262	drm_i915_init_t *init = data;	262	drm_i915_init_t *init = data;
263	int retcode = 0;	263	int retcode = 0;
264		264
265	if (drm_core_check_feature(dev, DRIVER_MODESET))	265	if (drm_core_check_feature(dev, DRIVER_MODESET))
266	return -ENODEV;	266	return -ENODEV;
267		267
268	switch (init->func) {	268	switch (init->func) {
269	case I915_INIT_DMA:	269	case I915_INIT_DMA:
270	retcode = i915_initialize(dev, init);	270	retcode = i915_initialize(dev, init);
271	break;	271	break;
272	case I915_CLEANUP_DMA:	272	case I915_CLEANUP_DMA:
273	retcode = i915_dma_cleanup(dev);	273	retcode = i915_dma_cleanup(dev);
274	break;	274	break;
275	case I915_RESUME_DMA:	275	case I915_RESUME_DMA:
276	retcode = i915_dma_resume(dev);	276	retcode = i915_dma_resume(dev);
277	break;	277	break;
278	default:	278	default:
279	retcode = -EINVAL;	279	retcode = -EINVAL;
280	break;	280	break;
281	}	281	}
282		282
283	return retcode;	283	return retcode;
284	}	284	}
285		285
286	/* Implement basically the same security restrictions as hardware does	286	/* Implement basically the same security restrictions as hardware does
287	* for MI_BATCH_NON_SECURE. These can be made stricter at any time.	287	* for MI_BATCH_NON_SECURE. These can be made stricter at any time.
288	*	288	*
289	* Most of the calculations below involve calculating the size of a	289	* Most of the calculations below involve calculating the size of a
290	* particular instruction. It's important to get the size right as	290	* particular instruction. It's important to get the size right as
291	* that tells us where the next instruction to check is. Any illegal	291	* that tells us where the next instruction to check is. Any illegal
292	* instruction detected will be given a size of zero, which is a	292	* instruction detected will be given a size of zero, which is a
293	* signal to abort the rest of the buffer.	293	* signal to abort the rest of the buffer.
294	*/	294	*/
295	static int validate_cmd(int cmd)	295	static int validate_cmd(int cmd)
296	{	296	{
297	switch (((cmd >> 29) & 0x7)) {	297	switch (((cmd >> 29) & 0x7)) {
298	case 0x0:	298	case 0x0:
299	switch ((cmd >> 23) & 0x3f) {	299	switch ((cmd >> 23) & 0x3f) {
300	case 0x0:	300	case 0x0:
301	return 1; /* MI_NOOP */	301	return 1; /* MI_NOOP */
302	case 0x4:	302	case 0x4:
303	return 1; /* MI_FLUSH */	303	return 1; /* MI_FLUSH */
304	default:	304	default:
305	return 0; /* disallow everything else */	305	return 0; /* disallow everything else */
306	}	306	}
307	break;	307	break;
308	case 0x1:	308	case 0x1:
309	return 0; /* reserved */	309	return 0; /* reserved */
310	case 0x2:	310	case 0x2:
311	return (cmd & 0xff) + 2; /* 2d commands */	311	return (cmd & 0xff) + 2; /* 2d commands */
312	case 0x3:	312	case 0x3:
313	if (((cmd >> 24) & 0x1f) <= 0x18)	313	if (((cmd >> 24) & 0x1f) <= 0x18)
314	return 1;	314	return 1;
315		315
316	switch ((cmd >> 24) & 0x1f) {	316	switch ((cmd >> 24) & 0x1f) {
317	case 0x1c:	317	case 0x1c:
318	return 1;	318	return 1;
319	case 0x1d:	319	case 0x1d:
320	switch ((cmd >> 16) & 0xff) {	320	switch ((cmd >> 16) & 0xff) {
321	case 0x3:	321	case 0x3:
322	return (cmd & 0x1f) + 2;	322	return (cmd & 0x1f) + 2;
323	case 0x4:	323	case 0x4:
324	return (cmd & 0xf) + 2;	324	return (cmd & 0xf) + 2;
325	default:	325	default:
326	return (cmd & 0xffff) + 2;	326	return (cmd & 0xffff) + 2;
327	}	327	}
328	case 0x1e:	328	case 0x1e:
329	if (cmd & (1 << 23))	329	if (cmd & (1 << 23))
330	return (cmd & 0xffff) + 1;	330	return (cmd & 0xffff) + 1;
331	else	331	else
332	return 1;	332	return 1;
333	case 0x1f:	333	case 0x1f:
334	if ((cmd & (1 << 23)) == 0) /* inline vertices */	334	if ((cmd & (1 << 23)) == 0) /* inline vertices */
335	return (cmd & 0x1ffff) + 2;	335	return (cmd & 0x1ffff) + 2;
336	else if (cmd & (1 << 17)) /* indirect random */	336	else if (cmd & (1 << 17)) /* indirect random */
337	if ((cmd & 0xffff) == 0)	337	if ((cmd & 0xffff) == 0)
338	return 0; /* unknown length, too hard */	338	return 0; /* unknown length, too hard */
339	else	339	else
340	return (((cmd & 0xffff) + 1) / 2) + 1;	340	return (((cmd & 0xffff) + 1) / 2) + 1;
341	else	341	else
342	return 2; /* indirect sequential */	342	return 2; /* indirect sequential */
343	default:	343	default:
344	return 0;	344	return 0;
345	}	345	}
346	default:	346	default:
347	return 0;	347	return 0;
348	}	348	}
349		349
350	return 0;	350	return 0;
351	}	351	}
352		352
353	static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)	353	static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
354	{	354	{
355	drm_i915_private_t *dev_priv = dev->dev_private;	355	drm_i915_private_t *dev_priv = dev->dev_private;
356	int i, ret;	356	int i, ret;
357		357
358	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)	358	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
359	return -EINVAL;	359	return -EINVAL;
360		360
361	for (i = 0; i < dwords;) {	361	for (i = 0; i < dwords;) {
362	int sz = validate_cmd(buffer[i]);	362	int sz = validate_cmd(buffer[i]);
363	if (sz == 0 \|\| i + sz > dwords)	363	if (sz == 0 \|\| i + sz > dwords)
364	return -EINVAL;	364	return -EINVAL;
365	i += sz;	365	i += sz;
366	}	366	}
367		367
368	ret = BEGIN_LP_RING((dwords+1)&~1);	368	ret = BEGIN_LP_RING((dwords+1)&~1);
369	if (ret)	369	if (ret)
370	return ret;	370	return ret;
371		371
372	for (i = 0; i < dwords; i++)	372	for (i = 0; i < dwords; i++)
373	OUT_RING(buffer[i]);	373	OUT_RING(buffer[i]);
374	if (dwords & 1)	374	if (dwords & 1)
375	OUT_RING(0);	375	OUT_RING(0);
376		376
377	ADVANCE_LP_RING();	377	ADVANCE_LP_RING();
378		378
379	return 0;	379	return 0;
380	}	380	}
381		381
382	int	382	int
383	i915_emit_box(struct drm_device *dev,	383	i915_emit_box(struct drm_device *dev,
384	struct drm_clip_rect *box,	384	struct drm_clip_rect *box,
385	int DR1, int DR4)	385	int DR1, int DR4)
386	{	386	{
387	struct drm_i915_private *dev_priv = dev->dev_private;	387	struct drm_i915_private *dev_priv = dev->dev_private;
388	int ret;	388	int ret;
389		389
390	if (box->y2 <= box->y1 \|\| box->x2 <= box->x1 \|\|	390	if (box->y2 <= box->y1 \|\| box->x2 <= box->x1 \|\|
391	box->y2 <= 0 \|\| box->x2 <= 0) {	391	box->y2 <= 0 \|\| box->x2 <= 0) {
392	DRM_ERROR("Bad box %d,%d..%d,%d\n",	392	DRM_ERROR("Bad box %d,%d..%d,%d\n",
393	box->x1, box->y1, box->x2, box->y2);	393	box->x1, box->y1, box->x2, box->y2);
394	return -EINVAL;	394	return -EINVAL;
395	}	395	}
396		396
397	if (INTEL_INFO(dev)->gen >= 4) {	397	if (INTEL_INFO(dev)->gen >= 4) {
398	ret = BEGIN_LP_RING(4);	398	ret = BEGIN_LP_RING(4);
399	if (ret)	399	if (ret)
400	return ret;	400	return ret;
401		401
402	OUT_RING(GFX_OP_DRAWRECT_INFO_I965);	402	OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
403	OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));	403	OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));
404	OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));	404	OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));
405	OUT_RING(DR4);	405	OUT_RING(DR4);
406	} else {	406	} else {
407	ret = BEGIN_LP_RING(6);	407	ret = BEGIN_LP_RING(6);
408	if (ret)	408	if (ret)
409	return ret;	409	return ret;
410		410
411	OUT_RING(GFX_OP_DRAWRECT_INFO);	411	OUT_RING(GFX_OP_DRAWRECT_INFO);
412	OUT_RING(DR1);	412	OUT_RING(DR1);
413	OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));	413	OUT_RING((box->x1 & 0xffff) \| (box->y1 << 16));
414	OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));	414	OUT_RING(((box->x2 - 1) & 0xffff) \| ((box->y2 - 1) << 16));
415	OUT_RING(DR4);	415	OUT_RING(DR4);
416	OUT_RING(0);	416	OUT_RING(0);
417	}	417	}
418	ADVANCE_LP_RING();	418	ADVANCE_LP_RING();
419		419
420	return 0;	420	return 0;
421	}	421	}
422		422
423	/* XXX: Emitting the counter should really be moved to part of the IRQ	423	/* XXX: Emitting the counter should really be moved to part of the IRQ
424	* emit. For now, do it in both places:	424	* emit. For now, do it in both places:
425	*/	425	*/
426		426
427	static void i915_emit_breadcrumb(struct drm_device *dev)	427	static void i915_emit_breadcrumb(struct drm_device *dev)
428	{	428	{
429	drm_i915_private_t *dev_priv = dev->dev_private;	429	drm_i915_private_t *dev_priv = dev->dev_private;
430	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;	430	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
431		431
432	dev_priv->dri1.counter++;	432	dev_priv->dri1.counter++;
433	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)	433	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
434	dev_priv->dri1.counter = 0;	434	dev_priv->dri1.counter = 0;
435	if (master_priv->sarea_priv)	435	if (master_priv->sarea_priv)
436	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;	436	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
437		437
438	if (BEGIN_LP_RING(4) == 0) {	438	if (BEGIN_LP_RING(4) == 0) {
439	OUT_RING(MI_STORE_DWORD_INDEX);	439	OUT_RING(MI_STORE_DWORD_INDEX);
440	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);	440	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
441	OUT_RING(dev_priv->dri1.counter);	441	OUT_RING(dev_priv->dri1.counter);
442	OUT_RING(0);	442	OUT_RING(0);
443	ADVANCE_LP_RING();	443	ADVANCE_LP_RING();
444	}	444	}
445	}	445	}
446		446
447	static int i915_dispatch_cmdbuffer(struct drm_device * dev,	447	static int i915_dispatch_cmdbuffer(struct drm_device * dev,
448	drm_i915_cmdbuffer_t *cmd,	448	drm_i915_cmdbuffer_t *cmd,
449	struct drm_clip_rect *cliprects,	449	struct drm_clip_rect *cliprects,
450	void *cmdbuf)	450	void *cmdbuf)
451	{	451	{
452	int nbox = cmd->num_cliprects;	452	int nbox = cmd->num_cliprects;
453	int i = 0, count, ret;	453	int i = 0, count, ret;
454		454
455	if (cmd->sz & 0x3) {	455	if (cmd->sz & 0x3) {
456	DRM_ERROR("alignment");	456	DRM_ERROR("alignment");
457	return -EINVAL;	457	return -EINVAL;
458	}	458	}
459		459
460	i915_kernel_lost_context(dev);	460	i915_kernel_lost_context(dev);
461		461
462	count = nbox ? nbox : 1;	462	count = nbox ? nbox : 1;
463		463
464	for (i = 0; i < count; i++) {	464	for (i = 0; i < count; i++) {
465	if (i < nbox) {	465	if (i < nbox) {
466	ret = i915_emit_box(dev, &cliprects[i],	466	ret = i915_emit_box(dev, &cliprects[i],
467	cmd->DR1, cmd->DR4);	467	cmd->DR1, cmd->DR4);
468	if (ret)	468	if (ret)
469	return ret;	469	return ret;
470	}	470	}
471		471
472	ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);	472	ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
473	if (ret)	473	if (ret)
474	return ret;	474	return ret;
475	}	475	}
476		476
477	i915_emit_breadcrumb(dev);	477	i915_emit_breadcrumb(dev);
478	return 0;	478	return 0;
479	}	479	}
480		480
481	static int i915_dispatch_batchbuffer(struct drm_device * dev,	481	static int i915_dispatch_batchbuffer(struct drm_device * dev,
482	drm_i915_batchbuffer_t * batch,	482	drm_i915_batchbuffer_t * batch,
483	struct drm_clip_rect *cliprects)	483	struct drm_clip_rect *cliprects)
484	{	484	{
485	struct drm_i915_private *dev_priv = dev->dev_private;	485	struct drm_i915_private *dev_priv = dev->dev_private;
486	int nbox = batch->num_cliprects;	486	int nbox = batch->num_cliprects;
487	int i, count, ret;	487	int i, count, ret;
488		488
489	if ((batch->start \| batch->used) & 0x7) {	489	if ((batch->start \| batch->used) & 0x7) {
490	DRM_ERROR("alignment");	490	DRM_ERROR("alignment");
491	return -EINVAL;	491	return -EINVAL;
492	}	492	}
493		493
494	i915_kernel_lost_context(dev);	494	i915_kernel_lost_context(dev);
495		495
496	count = nbox ? nbox : 1;	496	count = nbox ? nbox : 1;
497	for (i = 0; i < count; i++) {	497	for (i = 0; i < count; i++) {
498	if (i < nbox) {	498	if (i < nbox) {
499	ret = i915_emit_box(dev, &cliprects[i],	499	ret = i915_emit_box(dev, &cliprects[i],
500	batch->DR1, batch->DR4);	500	batch->DR1, batch->DR4);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/i915_dma.c – Rev 3480 → 3482