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Line 89... Line 89...
89
static struct _intel_private {
89
static struct _intel_private {
90
    const struct intel_gtt_driver *driver;
90
    const struct intel_gtt_driver *driver;
91
    struct pci_dev *pcidev; /* device one */
91
    struct pci_dev *pcidev; /* device one */
92
    struct pci_dev *bridge_dev;
92
    struct pci_dev *bridge_dev;
93
    u8 __iomem *registers;
93
    u8 __iomem *registers;
94
    phys_addr_t gtt_bus_addr;
94
	phys_addr_t gtt_phys_addr;
95
    u32 PGETBL_save;
95
    u32 PGETBL_save;
96
    u32 __iomem *gtt;       /* I915G */
96
    u32 __iomem *gtt;       /* I915G */
97
    bool clear_fake_agp; /* on first access via agp, fill with scratch */
97
    bool clear_fake_agp; /* on first access via agp, fill with scratch */
98
    int num_dcache_entries;
98
    int num_dcache_entries;
99
    void __iomem *i9xx_flush_page;
99
    void __iomem *i9xx_flush_page;
Line 397... Line 397...
397
	return true;
397
	return true;
398
}
398
}
Line 399... Line 399...
399
 
399
 
400
static int intel_gtt_init(void)
400
static int intel_gtt_init(void)
401
{
-
 
402
	u32 gma_addr;
401
{
403
    u32 gtt_map_size;
402
    u32 gtt_map_size;
Line 404... Line 403...
404
    int ret;
403
	int ret, bar;
405
 
404
 
406
    ret = intel_private.driver->setup();
405
    ret = intel_private.driver->setup();
Line 425... Line 424...
425
 
424
 
Line 426... Line 425...
426
	gtt_map_size = intel_private.gtt_total_entries * 4;
425
	gtt_map_size = intel_private.gtt_total_entries * 4;
427
 
426
 
428
	intel_private.gtt = NULL;
427
	intel_private.gtt = NULL;
429
	if (intel_private.gtt == NULL)
428
	if (intel_private.gtt == NULL)
430
		intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
429
		intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
431
					    gtt_map_size);
430
					    gtt_map_size);
432
	if (intel_private.gtt == NULL) {
431
	if (intel_private.gtt == NULL) {
433
        intel_private.driver->cleanup();
432
        intel_private.driver->cleanup();
434
		iounmap(intel_private.registers);
433
		iounmap(intel_private.registers);
Line -... Line 434...
-
 
434
        return -ENOMEM;
435
        return -ENOMEM;
435
    }
-
 
436
 
Line 436... Line 437...
436
    }
437
#if IS_ENABLED(CONFIG_AGP_INTEL)
Line 437... Line 438...
437
 
438
	global_cache_flush();   /* FIXME: ? */
Line 446... Line 447...
446
        intel_gtt_cleanup();
447
        intel_gtt_cleanup();
447
        return ret;
448
        return ret;
448
    }
449
    }
Line 449... Line 450...
449
 
450
 
450
	if (INTEL_GTT_GEN <= 2)
-
 
451
		pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
451
	if (INTEL_GTT_GEN <= 2)
452
				      &gma_addr);
452
		bar = I810_GMADR_BAR;
453
	else
-
 
454
		pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
453
	else
455
				      &gma_addr);
-
 
456
 
-
 
457
	intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
-
 
Line -... Line 454...
-
 
454
		bar = I915_GMADR_BAR;
458
 
455
 
459
 
456
	intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
Line -... Line 457...
-
 
457
	return 0;
460
    return 0;
458
}
461
}
459
 
462
 
460
 
463
static void i830_write_entry(dma_addr_t addr, unsigned int entry,
461
static void i830_write_entry(dma_addr_t addr, unsigned int entry,
Line 550... Line 548...
550
	}
548
	}
551
	readl(intel_private.gtt+j-1);
549
	readl(intel_private.gtt+j-1);
552
}
550
}
553
EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
551
EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
Line -... Line 552...
-
 
552
 
554
 
553
#if IS_ENABLED(CONFIG_AGP_INTEL)
555
static void intel_gtt_insert_pages(unsigned int first_entry,
554
static void intel_gtt_insert_pages(unsigned int first_entry,
556
				   unsigned int num_entries,
555
				   unsigned int num_entries,
557
				   struct page **pages,
556
				   struct page **pages,
558
				   unsigned int flags)
557
				   unsigned int flags)
Line 565... Line 564...
565
                          j, flags);
564
                          j, flags);
566
    }
565
    }
567
    readl(intel_private.gtt+j-1);
566
    readl(intel_private.gtt+j-1);
568
}
567
}
Line -... Line 568...
-
 
568
 
-
 
569
static int intel_fake_agp_insert_entries(struct agp_memory *mem,
-
 
570
					 off_t pg_start, int type)
-
 
571
{
-
 
572
	int ret = -EINVAL;
-
 
573
 
-
 
574
	if (intel_private.clear_fake_agp) {
-
 
575
		int start = intel_private.stolen_size / PAGE_SIZE;
-
 
576
		int end = intel_private.gtt_mappable_entries;
-
 
577
		intel_gtt_clear_range(start, end - start);
-
 
578
		intel_private.clear_fake_agp = false;
-
 
579
	}
-
 
580
 
-
 
581
	if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
-
 
582
		return i810_insert_dcache_entries(mem, pg_start, type);
-
 
583
 
-
 
584
	if (mem->page_count == 0)
-
 
585
		goto out;
-
 
586
 
-
 
587
	if (pg_start + mem->page_count > intel_private.gtt_total_entries)
-
 
588
		goto out_err;
-
 
589
 
-
 
590
	if (type != mem->type)
-
 
591
		goto out_err;
-
 
592
 
-
 
593
	if (!intel_private.driver->check_flags(type))
-
 
594
		goto out_err;
-
 
595
 
-
 
596
	if (!mem->is_flushed)
-
 
597
		global_cache_flush();
-
 
598
 
-
 
599
	if (intel_private.needs_dmar) {
-
 
600
		struct sg_table st;
-
 
601
 
-
 
602
		ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
-
 
603
		if (ret != 0)
-
 
604
			return ret;
-
 
605
 
-
 
606
		intel_gtt_insert_sg_entries(&st, pg_start, type);
-
 
607
		mem->sg_list = st.sgl;
-
 
608
		mem->num_sg = st.nents;
-
 
609
	} else
-
 
610
		intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
-
 
611
				       type);
-
 
612
 
-
 
613
out:
-
 
614
	ret = 0;
-
 
615
out_err:
-
 
616
	mem->is_flushed = true;
-
 
617
	return ret;
-
 
618
}
Line 569... Line 619...
569
 
619
#endif
570
 
620
 
571
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
621
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
Line 691... Line 741...
691
	writel(addr | pte_flags, intel_private.gtt + entry);
741
	writel(addr | pte_flags, intel_private.gtt + entry);
692
}
742
}
Line 693... Line 743...
693
 
743
 
694
static int i9xx_setup(void)
744
static int i9xx_setup(void)
695
{
745
{
696
	u32 reg_addr, gtt_addr;
746
	phys_addr_t reg_addr;
Line 697... Line 747...
697
	int size = KB(512);
747
	int size = KB(512);
698
 
-
 
699
    pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr);
-
 
Line 700... Line 748...
700
 
748
 
701
    reg_addr &= 0xfff80000;
749
	reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
702
 
750
 
Line 703... Line 751...
703
	intel_private.registers = ioremap(reg_addr, size);
751
	intel_private.registers = ioremap(reg_addr, size);
704
    if (!intel_private.registers)
752
    if (!intel_private.registers)
705
        return -ENOMEM;
-
 
706
 
753
        return -ENOMEM;
707
	switch (INTEL_GTT_GEN) {
754
 
708
	case 3:
755
	switch (INTEL_GTT_GEN) {
709
        pci_read_config_dword(intel_private.pcidev,
756
	case 3:
710
                      I915_PTEADDR, >t_addr);
757
		intel_private.gtt_phys_addr =
711
        intel_private.gtt_bus_addr = gtt_addr;
758
			pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
712
		break;
759
		break;
713
        case 5:
760
        case 5:
714
		intel_private.gtt_bus_addr = reg_addr + MB(2);
761
		intel_private.gtt_phys_addr = reg_addr + MB(2);
715
            break;
762
            break;
Line 716... Line 763...
716
        default:
763
        default:
Line 892... Line 939...
892
    if (!intel_private.driver)
939
    if (!intel_private.driver)
893
        return 0;
940
        return 0;
Line 894... Line 941...
894
 
941
 
Line -... Line 942...
-
 
942
	intel_private.refcount++;
895
	intel_private.refcount++;
943
 
-
 
944
#if IS_ENABLED(CONFIG_AGP_INTEL)
896
 
945
	if (bridge) {
897
	if (bridge) {
946
		bridge->driver = &intel_fake_agp_driver;
898
   		bridge->dev_private_data = &intel_private;
947
   		bridge->dev_private_data = &intel_private;
-
 
948
		bridge->dev = bridge_pdev;
Line 899... Line 949...
899
		bridge->dev = bridge_pdev;
949
	}
Line 900... Line 950...
900
	}
950
#endif