Rev 4104 | Rev 5060 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 4104 | Rev 4389 | ||
|---|---|---|---|
| Line 433... | Line 433... | ||
| 433 | intel_private.driver->cleanup(); |
433 | intel_private.driver->cleanup(); |
| 434 | iounmap(intel_private.registers); |
434 | iounmap(intel_private.registers); |
| 435 | return -ENOMEM; |
435 | return -ENOMEM; |
| 436 | } |
436 | } |
| Line 437... | Line 437... | ||
| 437 | 437 | ||
| Line 438... | Line 438... | ||
| 438 | asm volatile("wbinvd"); |
438 | asm volatile("wbinvd":::"memory"); |
| Line 439... | Line 439... | ||
| 439 | 439 | ||
| Line 576... | Line 576... | ||
| 576 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
576 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
| 577 | i, 0); |
577 | i, 0); |
| 578 | } |
578 | } |
| 579 | readl(intel_private.gtt+i-1); |
579 | readl(intel_private.gtt+i-1); |
| 580 | } |
580 | } |
| - | 581 | static void intel_i915_setup_chipset_flush(void) |
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| - | 582 | { |
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| - | 583 | int ret; |
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| - | 584 | u32 temp; |
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| - | 585 | ||
| - | 586 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
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| - | 587 | if (!(temp & 0x1)) { |
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| - | 588 | // intel_alloc_chipset_flush_resource(); |
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| - | 589 | // intel_private.resource_valid = 1; |
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| - | 590 | // pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
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| - | 591 | } else { |
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| - | 592 | temp &= ~1; |
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| - | 593 | ||
| - | 594 | intel_private.resource_valid = 1; |
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| - | 595 | intel_private.ifp_resource.start = temp; |
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| - | 596 | intel_private.ifp_resource.end = temp + PAGE_SIZE; |
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| - | 597 | // ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
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| - | 598 | /* some BIOSes reserve this area in a pnp some don't */ |
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| - | 599 | // if (ret) |
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| - | 600 | // intel_private.resource_valid = 0; |
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| - | 601 | } |
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| - | 602 | } |
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| - | 603 | ||
| - | 604 | static void intel_i965_g33_setup_chipset_flush(void) |
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| - | 605 | { |
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| - | 606 | u32 temp_hi, temp_lo; |
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| - | 607 | int ret; |
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| - | 608 | ||
| - | 609 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
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| - | 610 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); |
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| - | 611 | ||
| - | 612 | if (!(temp_lo & 0x1)) { |
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| - | 613 | ||
| - | 614 | // intel_alloc_chipset_flush_resource(); |
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| - | 615 | ||
| - | 616 | // intel_private.resource_valid = 1; |
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| - | 617 | // pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
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| - | 618 | // upper_32_bits(intel_private.ifp_resource.start)); |
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| - | 619 | // pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
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| - | 620 | } else { |
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| - | 621 | u64 l64; |
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| - | 622 | ||
| - | 623 | temp_lo &= ~0x1; |
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| - | 624 | l64 = ((u64)temp_hi << 32) | temp_lo; |
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| - | 625 | ||
| - | 626 | intel_private.resource_valid = 1; |
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| - | 627 | intel_private.ifp_resource.start = l64; |
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| - | 628 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; |
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| - | 629 | // ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
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| - | 630 | /* some BIOSes reserve this area in a pnp some don't */ |
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| - | 631 | // if (ret) |
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| - | 632 | // intel_private.resource_valid = 0; |
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| - | 633 | } |
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| - | 634 | } |
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| Line 581... | Line 635... | ||
| 581 | 635 | ||
| 582 | static void intel_i9xx_setup_flush(void) |
636 | static void intel_i9xx_setup_flush(void) |
| 583 | { |
637 | { |
| 584 | /* return if already configured */ |
638 | /* return if already configured */ |
| Line 587... | Line 641... | ||
| 587 | 641 | ||
| 588 | if (INTEL_GTT_GEN == 6) |
642 | if (INTEL_GTT_GEN == 6) |
| Line 589... | Line 643... | ||
| 589 | return; |
643 | return; |
| 590 | 644 | ||
| 591 | /* setup a resource for this object */ |
645 | /* setup a resource for this object */ |
| 592 | // intel_private.ifp_resource.name = "Intel Flush Page"; |
- | |
| 593 | // intel_private.ifp_resource.flags = IORESOURCE_MEM; |
- | |
| Line 594... | Line 646... | ||
| 594 | 646 | intel_private.ifp_resource.name = "Intel Flush Page"; |
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| 595 | intel_private.resource_valid = 0; |
647 | intel_private.ifp_resource.flags = IORESOURCE_MEM; |
| 596 | 648 | ||
| 597 | /* Setup chipset flush for 915 */ |
649 | /* Setup chipset flush for 915 */ |
| 598 | // if (IS_G33 || INTEL_GTT_GEN >= 4) { |
650 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
| 599 | // intel_i965_g33_setup_chipset_flush(); |
651 | intel_i965_g33_setup_chipset_flush(); |
| Line 600... | Line 652... | ||
| 600 | // } else { |
652 | } else { |
| 601 | // intel_i915_setup_chipset_flush(); |
653 | intel_i915_setup_chipset_flush(); |
| 602 | // } |
654 | } |
| 603 | 655 | ||
| 604 | // if (intel_private.ifp_resource.start) |
656 | if (intel_private.ifp_resource.start) |
| 605 | // intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
657 | intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE); |