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| Rev 3037 | Rev 3243 | ||
|---|---|---|---|
| Line 18... | Line 18... | ||
| 18 | #include |
18 | #include |
| 19 | #include |
19 | #include |
| 20 | #include |
20 | #include |
| 21 | #include |
21 | #include |
| 22 | #include |
22 | #include |
| - | 23 | #include |
|
| - | 24 | ||
| 23 | //#include |
25 | //#include |
| 24 | //#include |
26 | //#include |
| 25 | //#include |
27 | //#include |
| 26 | #include |
28 | #include |
| 27 | #include "agp.h" |
29 | #include "agp.h" |
| 28 | #include "intel-agp.h" |
30 | #include "intel-agp.h" |
| 29 | #include "intel-gtt.h" |
31 | #include |
| Line 30... | Line 32... | ||
| 30 | 32 | ||
| Line 31... | Line 33... | ||
| 31 | #include |
33 | #include |
| 32 | 34 | ||
| Line 108... | Line 110... | ||
| 108 | #define IS_IRONLAKE intel_private.driver->is_ironlake |
110 | #define IS_IRONLAKE intel_private.driver->is_ironlake |
| 109 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
111 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
| Line 110... | Line 112... | ||
| 110 | 112 | ||
| 111 | static int intel_gtt_setup_scratch_page(void) |
113 | static int intel_gtt_setup_scratch_page(void) |
| - | 114 | { |
|
| 112 | { |
115 | struct page *page; |
| Line 113... | Line 116... | ||
| 113 | dma_addr_t dma_addr; |
116 | dma_addr_t dma_addr; |
| 114 | 117 | ||
| 115 | dma_addr = AllocPage(); |
118 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
| - | 119 | if (page == NULL) |
|
| Line 116... | Line -... | ||
| 116 | if (dma_addr == 0) |
- | |
| 117 | return -ENOMEM; |
120 | return -ENOMEM; |
| Line 118... | Line 121... | ||
| 118 | 121 | intel_private.base.scratch_page_dma = page_to_phys(page); |
|
| 119 | intel_private.base.scratch_page_dma = dma_addr; |
122 | |
| Line 120... | Line 123... | ||
| 120 | intel_private.scratch_page = NULL; |
123 | intel_private.scratch_page = page; |
| Line 156... | Line 159... | ||
| 156 | break; |
159 | break; |
| 157 | default: |
160 | default: |
| 158 | stolen_size = 0; |
161 | stolen_size = 0; |
| 159 | break; |
162 | break; |
| 160 | } |
163 | } |
| 161 | } else if (INTEL_GTT_GEN == 6) { |
- | |
| 162 | /* |
- | |
| 163 | * SandyBridge has new memory control reg at 0x50.w |
- | |
| 164 | */ |
- | |
| 165 | u16 snb_gmch_ctl; |
- | |
| 166 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
- | |
| 167 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { |
- | |
| 168 | case SNB_GMCH_GMS_STOLEN_32M: |
- | |
| 169 | stolen_size = MB(32); |
- | |
| 170 | break; |
- | |
| 171 | case SNB_GMCH_GMS_STOLEN_64M: |
- | |
| 172 | stolen_size = MB(64); |
- | |
| 173 | break; |
- | |
| 174 | case SNB_GMCH_GMS_STOLEN_96M: |
- | |
| 175 | stolen_size = MB(96); |
- | |
| 176 | break; |
- | |
| 177 | case SNB_GMCH_GMS_STOLEN_128M: |
- | |
| 178 | stolen_size = MB(128); |
- | |
| 179 | break; |
- | |
| 180 | case SNB_GMCH_GMS_STOLEN_160M: |
- | |
| 181 | stolen_size = MB(160); |
- | |
| 182 | break; |
- | |
| 183 | case SNB_GMCH_GMS_STOLEN_192M: |
- | |
| 184 | stolen_size = MB(192); |
- | |
| 185 | break; |
- | |
| 186 | case SNB_GMCH_GMS_STOLEN_224M: |
- | |
| 187 | stolen_size = MB(224); |
- | |
| 188 | break; |
- | |
| 189 | case SNB_GMCH_GMS_STOLEN_256M: |
- | |
| 190 | stolen_size = MB(256); |
- | |
| 191 | break; |
- | |
| 192 | case SNB_GMCH_GMS_STOLEN_288M: |
- | |
| 193 | stolen_size = MB(288); |
- | |
| 194 | break; |
- | |
| 195 | case SNB_GMCH_GMS_STOLEN_320M: |
- | |
| 196 | stolen_size = MB(320); |
- | |
| 197 | break; |
- | |
| 198 | case SNB_GMCH_GMS_STOLEN_352M: |
- | |
| 199 | stolen_size = MB(352); |
- | |
| 200 | break; |
- | |
| 201 | case SNB_GMCH_GMS_STOLEN_384M: |
- | |
| 202 | stolen_size = MB(384); |
- | |
| 203 | break; |
- | |
| 204 | case SNB_GMCH_GMS_STOLEN_416M: |
- | |
| 205 | stolen_size = MB(416); |
- | |
| 206 | break; |
- | |
| 207 | case SNB_GMCH_GMS_STOLEN_448M: |
- | |
| 208 | stolen_size = MB(448); |
- | |
| 209 | break; |
- | |
| 210 | case SNB_GMCH_GMS_STOLEN_480M: |
- | |
| 211 | stolen_size = MB(480); |
- | |
| 212 | break; |
- | |
| 213 | case SNB_GMCH_GMS_STOLEN_512M: |
- | |
| 214 | stolen_size = MB(512); |
- | |
| 215 | break; |
- | |
| 216 | } |
- | |
| 217 | } else { |
164 | } else { |
| 218 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
165 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
| 219 | case I855_GMCH_GMS_STOLEN_1M: |
166 | case I855_GMCH_GMS_STOLEN_1M: |
| 220 | stolen_size = MB(1); |
167 | stolen_size = MB(1); |
| 221 | break; |
168 | break; |
| Line 345... | Line 292... | ||
| 345 | return size/4; |
292 | return size/4; |
| 346 | } |
293 | } |
| Line 347... | Line 294... | ||
| 347 | 294 | ||
| 348 | static unsigned int intel_gtt_total_entries(void) |
295 | static unsigned int intel_gtt_total_entries(void) |
| 349 | { |
- | |
| 350 | int size; |
- | |
| 351 | 296 | { |
|
| 352 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
297 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
| 353 | return i965_gtt_total_entries(); |
- | |
| 354 | else if (INTEL_GTT_GEN == 6) { |
- | |
| 355 | u16 snb_gmch_ctl; |
- | |
| 356 | - | ||
| 357 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
- | |
| 358 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { |
- | |
| 359 | default: |
- | |
| 360 | case SNB_GTT_SIZE_0M: |
- | |
| 361 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); |
- | |
| 362 | size = MB(0); |
- | |
| 363 | break; |
- | |
| 364 | case SNB_GTT_SIZE_1M: |
- | |
| 365 | size = MB(1); |
- | |
| 366 | break; |
- | |
| 367 | case SNB_GTT_SIZE_2M: |
- | |
| 368 | size = MB(2); |
- | |
| 369 | break; |
- | |
| 370 | } |
- | |
| 371 | return size/4; |
298 | return i965_gtt_total_entries(); |
| 372 | } else { |
299 | else { |
| 373 | /* On previous hardware, the GTT size was just what was |
300 | /* On previous hardware, the GTT size was just what was |
| 374 | * required to map the aperture. |
301 | * required to map the aperture. |
| 375 | */ |
302 | */ |
| 376 | return intel_private.base.gtt_mappable_entries; |
303 | return intel_private.base.gtt_mappable_entries; |
| Line 431... | Line 358... | ||
| 431 | u32 gtt_map_size; |
358 | u32 gtt_map_size; |
| 432 | int ret; |
359 | int ret; |
| Line 433... | Line 360... | ||
| 433 | 360 | ||
| 434 | ret = intel_private.driver->setup(); |
361 | ret = intel_private.driver->setup(); |
| 435 | if (ret != 0) |
- | |
| 436 | { |
362 | if (ret != 0) |
| 437 | return ret; |
- | |
| 438 | }; |
- | |
| Line 439... | Line 363... | ||
| 439 | 363 | return ret; |
|
| 440 | 364 | ||
| Line 441... | Line 365... | ||
| 441 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); |
365 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); |
| Line 455... | Line 379... | ||
| 455 | intel_private.base.gtt_mappable_entries * 4); |
379 | intel_private.base.gtt_mappable_entries * 4); |
| Line 456... | Line 380... | ||
| 456 | 380 | ||
| Line 457... | Line 381... | ||
| 457 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
381 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
| 458 | - | ||
| 459 | intel_private.gtt = NULL; |
- | |
| 460 | // if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2) |
- | |
| 461 | // intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, |
382 | |
| 462 | // gtt_map_size); |
383 | intel_private.gtt = NULL; |
| 463 | if (intel_private.gtt == NULL) |
384 | if (intel_private.gtt == NULL) |
| 464 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, |
385 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, |
| 465 | gtt_map_size); |
386 | gtt_map_size); |
| Line 507... | Line 428... | ||
| 507 | 428 | ||
| 508 | bool intel_enable_gtt(void) |
429 | bool intel_enable_gtt(void) |
| 509 | { |
430 | { |
| Line 510... | Line -... | ||
| 510 | u8 __iomem *reg; |
- | |
| 511 | - | ||
| 512 | if (INTEL_GTT_GEN >= 6) |
- | |
| 513 | return true; |
431 | u8 __iomem *reg; |
| 514 | 432 | ||
| Line 515... | Line 433... | ||
| 515 | if (INTEL_GTT_GEN == 2) { |
433 | if (INTEL_GTT_GEN == 2) { |
| 516 | u16 gmch_ctrl; |
434 | u16 gmch_ctrl; |
| Line 563... | Line 481... | ||
| 563 | } |
481 | } |
| Line 564... | Line 482... | ||
| 564 | 482 | ||
| 565 | return false; |
483 | return false; |
| Line 566... | Line 484... | ||
| 566 | } |
484 | } |
| 567 | 485 | ||
| 568 | void intel_gtt_insert_sg_entries(struct pagelist *st, |
486 | void intel_gtt_insert_sg_entries(struct sg_table *st, |
| 569 | unsigned int pg_start, |
487 | unsigned int pg_start, |
| - | 488 | unsigned int flags) |
|
| - | 489 | { |
|
| 570 | unsigned int flags) |
490 | struct scatterlist *sg; |
| Line 571... | Line 491... | ||
| 571 | { |
491 | unsigned int len, m; |
| Line -... | Line 492... | ||
| - | 492 | int i, j; |
|
| - | 493 | ||
| 572 | int i, j; |
494 | j = pg_start; |
| - | 495 | ||
| 573 | 496 | /* sg may merge pages, but we have to separate |
|
| 574 | j = pg_start; |
497 | * per-page addr for GTT */ |
| 575 | 498 | for_each_sg(st->sgl, sg, st->nents, i) { |
|
| 576 | for(i = 0; i < st->nents; i++) |
499 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
| 577 | { |
500 | for (m = 0; m < len; m++) { |
| 578 | dma_addr_t addr = st->page[i]; |
501 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
| 579 | intel_private.driver->write_entry(addr, j, flags); |
502 | intel_private.driver->write_entry(addr, j, flags); |
| 580 | j++; |
503 | j++; |
| - | 504 | } |
|
| Line 581... | Line 505... | ||
| 581 | }; |
505 | } |
| 582 | 506 | readl(intel_private.gtt+j-1); |
|
| 583 | readl(intel_private.gtt+j-1); |
507 | } |
| 584 | } |
508 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
| 585 | 509 | ||
| 586 | static void intel_gtt_insert_pages(unsigned int first_entry, |
510 | static void intel_gtt_insert_pages(unsigned int first_entry, |
| Line 587... | Line 511... | ||
| 587 | unsigned int num_entries, |
511 | unsigned int num_entries, |
| 588 | dma_addr_t *pages, |
512 | struct page **pages, |
| 589 | unsigned int flags) |
513 | unsigned int flags) |
| 590 | { |
514 | { |
| 591 | int i, j; |
515 | int i, j; |
| 592 | 516 | ||
| 593 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { |
517 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { |
| Line 668... | Line 592... | ||
| 668 | /* Shift high bits down */ |
592 | /* Shift high bits down */ |
| 669 | addr |= (addr >> 28) & 0xf0; |
593 | addr |= (addr >> 28) & 0xf0; |
| 670 | writel(addr | pte_flags, intel_private.gtt + entry); |
594 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 671 | } |
595 | } |
| Line 672... | Line -... | ||
| 672 | - | ||
| 673 | static bool gen6_check_flags(unsigned int flags) |
- | |
| 674 | { |
- | |
| 675 | return true; |
- | |
| 676 | } |
- | |
| 677 | - | ||
| 678 | static void haswell_write_entry(dma_addr_t addr, unsigned int entry, |
- | |
| 679 | unsigned int flags) |
- | |
| 680 | { |
- | |
| 681 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
- | |
| 682 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; |
- | |
| 683 | u32 pte_flags; |
- | |
| 684 | - | ||
| 685 | if (type_mask == AGP_USER_MEMORY) |
- | |
| 686 | pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID; |
- | |
| 687 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
- | |
| 688 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
- | |
| 689 | if (gfdt) |
- | |
| 690 | pte_flags |= GEN6_PTE_GFDT; |
- | |
| 691 | } else { /* set 'normal'/'cached' to LLC by default */ |
- | |
| 692 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
- | |
| 693 | if (gfdt) |
- | |
| 694 | pte_flags |= GEN6_PTE_GFDT; |
- | |
| 695 | } |
- | |
| 696 | - | ||
| 697 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
- | |
| 698 | addr |= (addr >> 28) & 0xff0; |
- | |
| 699 | writel(addr | pte_flags, intel_private.gtt + entry); |
- | |
| 700 | } |
- | |
| 701 | - | ||
| 702 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
- | |
| 703 | unsigned int flags) |
- | |
| 704 | { |
- | |
| 705 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
- | |
| 706 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; |
- | |
| 707 | u32 pte_flags; |
- | |
| 708 | - | ||
| 709 | if (type_mask == AGP_USER_MEMORY) |
- | |
| 710 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
- | |
| 711 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
- | |
| 712 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
- | |
| 713 | if (gfdt) |
- | |
| 714 | pte_flags |= GEN6_PTE_GFDT; |
- | |
| 715 | } else { /* set 'normal'/'cached' to LLC by default */ |
- | |
| 716 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
- | |
| 717 | if (gfdt) |
- | |
| 718 | pte_flags |= GEN6_PTE_GFDT; |
- | |
| 719 | } |
- | |
| 720 | - | ||
| 721 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
- | |
| 722 | addr |= (addr >> 28) & 0xff0; |
- | |
| 723 | writel(addr | pte_flags, intel_private.gtt + entry); |
- | |
| 724 | } |
- | |
| 725 | - | ||
| 726 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, |
- | |
| 727 | unsigned int flags) |
- | |
| 728 | { |
- | |
| 729 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
- | |
| 730 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; |
- | |
| 731 | u32 pte_flags; |
- | |
| 732 | - | ||
| 733 | if (type_mask == AGP_USER_MEMORY) |
- | |
| 734 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
- | |
| 735 | else { |
- | |
| 736 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
- | |
| 737 | if (gfdt) |
- | |
| 738 | pte_flags |= GEN6_PTE_GFDT; |
- | |
| 739 | } |
- | |
| 740 | - | ||
| 741 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
- | |
| 742 | addr |= (addr >> 28) & 0xff0; |
- | |
| 743 | writel(addr | pte_flags, intel_private.gtt + entry); |
- | |
| 744 | - | ||
| 745 | writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV); |
- | |
| 746 | } |
- | |
| 747 | - | ||
| 748 | static void gen6_cleanup(void) |
- | |
| 749 | { |
- | |
| 750 | } |
- | |
| 751 | 596 | ||
| 752 | /* Certain Gen5 chipsets require require idling the GPU before |
597 | /* Certain Gen5 chipsets require require idling the GPU before |
| 753 | * unmapping anything from the GTT when VT-d is enabled. |
598 | * unmapping anything from the GTT when VT-d is enabled. |
| 754 | */ |
599 | */ |
| 755 | static inline int needs_idle_maps(void) |
600 | static inline int needs_idle_maps(void) |
| Line 768... | Line 613... | ||
| 768 | return 0; |
613 | return 0; |
| 769 | } |
614 | } |
| Line 770... | Line 615... | ||
| 770 | 615 | ||
| 771 | static int i9xx_setup(void) |
616 | static int i9xx_setup(void) |
| 772 | { |
617 | { |
| 773 | u32 reg_addr; |
618 | u32 reg_addr, gtt_addr; |
| Line 774... | Line 619... | ||
| 774 | int size = KB(512); |
619 | int size = KB(512); |
| Line 775... | Line 620... | ||
| 775 | 620 | ||
| Line 776... | Line -... | ||
| 776 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
- | |
| 777 | - | ||
| 778 | reg_addr &= 0xfff80000; |
- | |
| 779 | 621 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
|
| 780 | if (INTEL_GTT_GEN >= 7) |
622 | |
| 781 | size = MB(2); |
623 | reg_addr &= 0xfff80000; |
| Line 782... | Line 624... | ||
| 782 | 624 | ||
| 783 | intel_private.registers = ioremap(reg_addr, size); |
625 | intel_private.registers = ioremap(reg_addr, size); |
| 784 | if (!intel_private.registers) |
- | |
| 785 | return -ENOMEM; |
626 | if (!intel_private.registers) |
| 786 | 627 | return -ENOMEM; |
|
| 787 | if (INTEL_GTT_GEN == 3) { |
628 | |
| 788 | u32 gtt_addr; |
629 | switch (INTEL_GTT_GEN) { |
| 789 | - | ||
| 790 | pci_read_config_dword(intel_private.pcidev, |
- | |
| 791 | I915_PTEADDR, >t_addr); |
- | |
| 792 | intel_private.gtt_bus_addr = gtt_addr; |
630 | case 3: |
| 793 | } else { |
- | |
| 794 | u32 gtt_offset; |
- | |
| 795 | 631 | pci_read_config_dword(intel_private.pcidev, |
|
| 796 | switch (INTEL_GTT_GEN) { |
632 | I915_PTEADDR, >t_addr); |
| 797 | case 5: |
- | |
| 798 | case 6: |
633 | intel_private.gtt_bus_addr = gtt_addr; |
| 799 | case 7: |
634 | break; |
| 800 | gtt_offset = MB(2); |
635 | case 5: |
| 801 | break; |
636 | intel_private.gtt_bus_addr = reg_addr + MB(2); |
| 802 | case 4: |
- | |
| 803 | default: |
- | |
| Line 804... | Line 637... | ||
| 804 | gtt_offset = KB(512); |
637 | break; |
| 805 | break; |
638 | default: |
| Line 806... | Line 639... | ||
| 806 | } |
639 | intel_private.gtt_bus_addr = reg_addr + KB(512); |
| Line 873... | Line 706... | ||
| 873 | .write_entry = i965_write_entry, |
706 | .write_entry = i965_write_entry, |
| 874 | .dma_mask_size = 36, |
707 | .dma_mask_size = 36, |
| 875 | .check_flags = i830_check_flags, |
708 | .check_flags = i830_check_flags, |
| 876 | .chipset_flush = i9xx_chipset_flush, |
709 | .chipset_flush = i9xx_chipset_flush, |
| 877 | }; |
710 | }; |
| 878 | static const struct intel_gtt_driver sandybridge_gtt_driver = { |
- | |
| 879 | .gen = 6, |
- | |
| 880 | .setup = i9xx_setup, |
- | |
| 881 | .cleanup = gen6_cleanup, |
- | |
| 882 | .write_entry = gen6_write_entry, |
- | |
| 883 | .dma_mask_size = 40, |
- | |
| 884 | .check_flags = gen6_check_flags, |
- | |
| 885 | .chipset_flush = i9xx_chipset_flush, |
- | |
| 886 | }; |
- | |
| 887 | static const struct intel_gtt_driver haswell_gtt_driver = { |
- | |
| 888 | .gen = 6, |
- | |
| 889 | .setup = i9xx_setup, |
- | |
| 890 | .cleanup = gen6_cleanup, |
- | |
| 891 | .write_entry = haswell_write_entry, |
- | |
| 892 | .dma_mask_size = 40, |
- | |
| 893 | .check_flags = gen6_check_flags, |
- | |
| 894 | .chipset_flush = i9xx_chipset_flush, |
- | |
| 895 | }; |
- | |
| 896 | static const struct intel_gtt_driver valleyview_gtt_driver = { |
- | |
| 897 | .gen = 7, |
- | |
| 898 | .setup = i9xx_setup, |
- | |
| 899 | .cleanup = gen6_cleanup, |
- | |
| 900 | .write_entry = valleyview_write_entry, |
- | |
| 901 | .dma_mask_size = 40, |
- | |
| 902 | .check_flags = gen6_check_flags, |
- | |
| 903 | }; |
- | |
| Line 904... | Line 711... | ||
| 904 | 711 | ||
| 905 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
712 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
| 906 | * driver and gmch_driver must be non-null, and find_gmch will determine |
713 | * driver and gmch_driver must be non-null, and find_gmch will determine |
| 907 | * which one should be used if a gmch_chip_id is present. |
714 | * which one should be used if a gmch_chip_id is present. |
| Line 961... | Line 768... | ||
| 961 | &g4x_gtt_driver }, |
768 | &g4x_gtt_driver }, |
| 962 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
769 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
| 963 | "HD Graphics", &ironlake_gtt_driver }, |
770 | "HD Graphics", &ironlake_gtt_driver }, |
| 964 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
771 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
| 965 | "HD Graphics", &ironlake_gtt_driver }, |
772 | "HD Graphics", &ironlake_gtt_driver }, |
| 966 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
- | |
| 967 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 968 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
- | |
| 969 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 970 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
- | |
| 971 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 972 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
- | |
| 973 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 974 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
- | |
| 975 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 976 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
- | |
| 977 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 978 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
- | |
| 979 | "Sandybridge", &sandybridge_gtt_driver }, |
- | |
| 980 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, |
- | |
| 981 | "Ivybridge", &sandybridge_gtt_driver }, |
- | |
| 982 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, |
- | |
| 983 | "Ivybridge", &sandybridge_gtt_driver }, |
- | |
| 984 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, |
- | |
| 985 | "Ivybridge", &sandybridge_gtt_driver }, |
- | |
| 986 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, |
- | |
| 987 | "Ivybridge", &sandybridge_gtt_driver }, |
- | |
| 988 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, |
- | |
| 989 | "Ivybridge", &sandybridge_gtt_driver }, |
- | |
| 990 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG, |
- | |
| 991 | "Ivybridge", &sandybridge_gtt_driver }, |
- | |
| 992 | { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, |
- | |
| 993 | "ValleyView", &valleyview_gtt_driver }, |
- | |
| 994 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, |
- | |
| 995 | "Haswell", &haswell_gtt_driver }, |
- | |
| 996 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, |
- | |
| 997 | "Haswell", &haswell_gtt_driver }, |
- | |
| 998 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG, |
- | |
| 999 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1000 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, |
- | |
| 1001 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1002 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, |
- | |
| 1003 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1004 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG, |
- | |
| 1005 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1006 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, |
- | |
| 1007 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1008 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, |
- | |
| 1009 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1010 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG, |
- | |
| 1011 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1012 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG, |
- | |
| 1013 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1014 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG, |
- | |
| 1015 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1016 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG, |
- | |
| 1017 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1018 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG, |
- | |
| 1019 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1020 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG, |
- | |
| 1021 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1022 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG, |
- | |
| 1023 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1024 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG, |
- | |
| 1025 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1026 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG, |
- | |
| 1027 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1028 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG, |
- | |
| 1029 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1030 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG, |
- | |
| 1031 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1032 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG, |
- | |
| 1033 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1034 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG, |
- | |
| 1035 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1036 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG, |
- | |
| 1037 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1038 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG, |
- | |
| 1039 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1040 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG, |
- | |
| 1041 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1042 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG, |
- | |
| 1043 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1044 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG, |
- | |
| 1045 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1046 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG, |
- | |
| 1047 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1048 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG, |
- | |
| 1049 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1050 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG, |
- | |
| 1051 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1052 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG, |
- | |
| 1053 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1054 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG, |
- | |
| 1055 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1056 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG, |
- | |
| 1057 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1058 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG, |
- | |
| 1059 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1060 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG, |
- | |
| 1061 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1062 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG, |
- | |
| 1063 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1064 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG, |
- | |
| 1065 | "Haswell", &haswell_gtt_driver }, |
- | |
| 1066 | { 0, NULL, NULL } |
773 | { 0, NULL, NULL } |
| 1067 | }; |
774 | }; |
| Line 1068... | Line 775... | ||
| 1068 | 775 | ||
| 1069 | static int find_gmch(u16 device) |
776 | static int find_gmch(u16 device) |
| Line 1105... | Line 812... | ||
| 1105 | bridge->dev = bridge_pdev; |
812 | bridge->dev = bridge_pdev; |
| 1106 | } |
813 | } |
| Line 1107... | Line 814... | ||
| 1107 | 814 | ||
| Line 1108... | Line 815... | ||
| 1108 | intel_private.bridge_dev = bridge_pdev; |
815 | intel_private.bridge_dev = bridge_pdev; |
| Line 1109... | Line 816... | ||
| 1109 | 816 | ||
| 1110 | dbgprintf("Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
817 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
| 1111 | 818 | ||
| 1112 | mask = intel_private.driver->dma_mask_size; |
819 | mask = intel_private.driver->dma_mask_size; |
| Line 1125... | Line 832... | ||
| 1125 | 832 | ||
| 1126 | return 1; |
833 | return 1; |
| 1127 | } |
834 | } |
| Line 1128... | Line 835... | ||
| 1128 | EXPORT_SYMBOL(intel_gmch_probe); |
835 | EXPORT_SYMBOL(intel_gmch_probe); |
| 1129 | 836 | ||
| 1130 | const struct intel_gtt *intel_gtt_get(void) |
837 | struct intel_gtt *intel_gtt_get(void) |
| 1131 | { |
838 | { |
| 1132 | return &intel_private.base; |
839 | return &intel_private.base; |
| Line 1139... | Line 846... | ||
| 1139 | intel_private.driver->chipset_flush(); |
846 | intel_private.driver->chipset_flush(); |
| 1140 | } |
847 | } |
| 1141 | EXPORT_SYMBOL(intel_gtt_chipset_flush); |
848 | EXPORT_SYMBOL(intel_gtt_chipset_flush); |
| Line 1142... | Line 849... | ||
| 1142 | 849 | ||
| 1143 | - | ||
| 1144 | //phys_addr_t get_bus_addr(void) |
850 | |
| 1145 | //{ |
- | |