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| Rev 2325 | Rev 3031 | ||
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| Line 62... | Line 62... | ||
| 62 | #define I810_PTE_LOCAL 0x00000002 |
62 | #define I810_PTE_LOCAL 0x00000002 |
| 63 | #define I810_PTE_VALID 0x00000001 |
63 | #define I810_PTE_VALID 0x00000001 |
| 64 | #define I830_PTE_SYSTEM_CACHED 0x00000006 |
64 | #define I830_PTE_SYSTEM_CACHED 0x00000006 |
| 65 | /* GT PTE cache control fields */ |
65 | /* GT PTE cache control fields */ |
| 66 | #define GEN6_PTE_UNCACHED 0x00000002 |
66 | #define GEN6_PTE_UNCACHED 0x00000002 |
| - | 67 | #define HSW_PTE_UNCACHED 0x00000000 |
|
| 67 | #define GEN6_PTE_LLC 0x00000004 |
68 | #define GEN6_PTE_LLC 0x00000004 |
| 68 | #define GEN6_PTE_LLC_MLC 0x00000006 |
69 | #define GEN6_PTE_LLC_MLC 0x00000006 |
| 69 | #define GEN6_PTE_GFDT 0x00000008 |
70 | #define GEN6_PTE_GFDT 0x00000008 |
| Line 70... | Line 71... | ||
| 70 | 71 | ||
| Line 94... | Line 95... | ||
| 94 | #define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN) |
95 | #define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN) |
| 95 | #define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN) |
96 | #define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN) |
| 96 | #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) |
97 | #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) |
| Line 97... | Line 98... | ||
| 97 | 98 | ||
| - | 99 | #define GFX_FLSH_CNTL 0x2170 /* 915+ */ |
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| Line 98... | Line 100... | ||
| 98 | #define GFX_FLSH_CNTL 0x2170 /* 915+ */ |
100 | #define GFX_FLSH_CNTL_VLV 0x101008 |
| 99 | 101 | ||
| 100 | #define I810_DRAM_CTL 0x3000 |
102 | #define I810_DRAM_CTL 0x3000 |
| Line 209... | Line 211... | ||
| 209 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 |
211 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 |
| 210 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 |
212 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 |
| 211 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
213 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
| 212 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 |
214 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 |
| 213 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 |
215 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 |
| - | 216 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069 |
|
| 214 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 |
217 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 |
| 215 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 |
218 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 |
| 216 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 |
219 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 |
| 217 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a |
220 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a |
| 218 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 |
221 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 |
| Line 232... | Line 235... | ||
| 232 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */ |
235 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */ |
| 233 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156 |
236 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156 |
| 234 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166 |
237 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166 |
| 235 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */ |
238 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */ |
| 236 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A |
239 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A |
| - | 240 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A |
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| - | 241 | #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */ |
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| - | 242 | #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30 |
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| - | 243 | #define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */ |
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| - | 244 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402 |
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| - | 245 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412 |
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| - | 246 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422 |
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| - | 247 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */ |
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| - | 248 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406 |
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| - | 249 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416 |
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| - | 250 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426 |
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| - | 251 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */ |
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| - | 252 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a |
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| - | 253 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a |
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| - | 254 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a |
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| - | 255 | #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04 |
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| - | 256 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02 |
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| - | 257 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12 |
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| - | 258 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22 |
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| - | 259 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06 |
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| - | 260 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16 |
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| - | 261 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26 |
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| - | 262 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A |
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| - | 263 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A |
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| - | 264 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A |
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| - | 265 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02 |
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| - | 266 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12 |
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| - | 267 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22 |
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| - | 268 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06 |
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| - | 269 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16 |
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| - | 270 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26 |
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| - | 271 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A |
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| - | 272 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A |
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| - | 273 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A |
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| - | 274 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12 |
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| - | 275 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22 |
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| - | 276 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32 |
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| - | 277 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16 |
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| - | 278 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26 |
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| - | 279 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36 |
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| - | 280 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A |
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| - | 281 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A |
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| - | 282 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A |
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| Line 237... | Line -... | ||
| 237 | - | ||
| 238 | int intel_gmch_probe(struct pci_dev *pdev, |
- | |
| 239 | struct agp_bridge_data *bridge); |
- | |
| 240 | void intel_gmch_remove(struct pci_dev *pdev); |
283 | |