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Line 226... | Line 226... | ||
226 | return error; |
226 | return error; |
227 | } |
227 | } |
228 | EXPORT_SYMBOL(i2c_dp_aux_add_bus); |
228 | EXPORT_SYMBOL(i2c_dp_aux_add_bus); |
Line 229... | Line 229... | ||
229 | 229 | ||
230 | /* Helpers for DP link training */ |
230 | /* Helpers for DP link training */ |
231 | static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) |
231 | static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) |
232 | { |
232 | { |
233 | return link_status[r - DP_LANE0_1_STATUS]; |
233 | return link_status[r - DP_LANE0_1_STATUS]; |
Line 234... | Line 234... | ||
234 | } |
234 | } |
235 | 235 | ||
236 | static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], |
236 | static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], |
237 | int lane) |
237 | int lane) |
238 | { |
238 | { |
239 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
239 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
240 | int s = (lane & 1) * 4; |
240 | int s = (lane & 1) * 4; |
241 | u8 l = dp_link_status(link_status, i); |
241 | u8 l = dp_link_status(link_status, i); |
Line 242... | Line 242... | ||
242 | return (l >> s) & 0xf; |
242 | return (l >> s) & 0xf; |
243 | } |
243 | } |
244 | 244 | ||
245 | bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
245 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
246 | int lane_count) |
246 | int lane_count) |
247 | { |
247 | { |
Line 260... | Line 260... | ||
260 | } |
260 | } |
261 | return true; |
261 | return true; |
262 | } |
262 | } |
263 | EXPORT_SYMBOL(drm_dp_channel_eq_ok); |
263 | EXPORT_SYMBOL(drm_dp_channel_eq_ok); |
Line 264... | Line 264... | ||
264 | 264 | ||
265 | bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
265 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
266 | int lane_count) |
266 | int lane_count) |
267 | { |
267 | { |
268 | int lane; |
268 | int lane; |
Line 275... | Line 275... | ||
275 | } |
275 | } |
276 | return true; |
276 | return true; |
277 | } |
277 | } |
278 | EXPORT_SYMBOL(drm_dp_clock_recovery_ok); |
278 | EXPORT_SYMBOL(drm_dp_clock_recovery_ok); |
Line 279... | Line 279... | ||
279 | 279 | ||
280 | u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
280 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
281 | int lane) |
281 | int lane) |
282 | { |
282 | { |
283 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
283 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
284 | int s = ((lane & 1) ? |
284 | int s = ((lane & 1) ? |
Line 288... | Line 288... | ||
288 | 288 | ||
289 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
289 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
290 | } |
290 | } |
Line 291... | Line 291... | ||
291 | EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); |
291 | EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); |
292 | 292 | ||
293 | u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
293 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
294 | int lane) |
294 | int lane) |
295 | { |
295 | { |
296 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
296 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
Line 301... | Line 301... | ||
301 | 301 | ||
302 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
302 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
303 | } |
303 | } |
Line 304... | Line 304... | ||
304 | EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); |
304 | EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); |
305 | 305 | ||
306 | void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
306 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
307 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
307 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
308 | udelay(100); |
308 | udelay(100); |
309 | else |
309 | else |
310 | mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); |
310 | mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); |
Line 311... | Line 311... | ||
311 | } |
311 | } |
312 | EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); |
312 | EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); |
313 | 313 | ||
314 | void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
314 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
315 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
315 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
316 | udelay(400); |
316 | udelay(400); |