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1 | /* |
1 | /* |
2 | * Copyright © 2006,2008,2011 Intel Corporation |
2 | * Copyright © 2006,2008,2011 Intel Corporation |
3 | * Copyright © 2007 Red Hat, Inc. |
3 | * Copyright © 2007 Red Hat, Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice (including the next |
12 | * The above copyright notice and this permission notice (including the next |
13 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * paragraph) shall be included in all copies or substantial portions of the |
14 | * Software. |
14 | * Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
22 | * SOFTWARE. |
22 | * SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: |
24 | * Authors: |
25 | * Wang Zhenyu |
25 | * Wang Zhenyu |
26 | * Eric Anholt |
26 | * Eric Anholt |
27 | * Carl Worth |
27 | * Carl Worth |
28 | * Keith Packard |
28 | * Keith Packard |
29 | * Chris Wilson |
29 | * Chris Wilson |
30 | * |
30 | * |
31 | */ |
31 | */ |
32 | 32 | ||
33 | #ifdef HAVE_CONFIG_H |
33 | #ifdef HAVE_CONFIG_H |
34 | #include "config.h" |
34 | #include "config.h" |
35 | #endif |
35 | #endif |
36 | 36 | ||
37 | #include "sna.h" |
37 | #include "sna.h" |
38 | #include "sna_reg.h" |
38 | #include "sna_reg.h" |
39 | #include "sna_render.h" |
39 | #include "sna_render.h" |
40 | #include "sna_render_inline.h" |
40 | #include "sna_render_inline.h" |
41 | //#include "sna_video.h" |
41 | //#include "sna_video.h" |
42 | 42 | ||
43 | #include "brw/brw.h" |
43 | #include "brw/brw.h" |
44 | #include "gen5_render.h" |
44 | #include "gen5_render.h" |
45 | #include "gen4_source.h" |
45 | #include "gen4_source.h" |
46 | #include "gen4_vertex.h" |
46 | #include "gen4_vertex.h" |
47 | 47 | ||
48 | #define NO_COMPOSITE 0 |
48 | #define NO_COMPOSITE 0 |
49 | #define NO_COMPOSITE_SPANS 0 |
49 | #define NO_COMPOSITE_SPANS 0 |
50 | 50 | ||
51 | #define PREFER_BLT_FILL 1 |
51 | #define PREFER_BLT_FILL 1 |
52 | 52 | ||
53 | #define DBG_NO_STATE_CACHE 0 |
53 | #define DBG_NO_STATE_CACHE 0 |
54 | #define DBG_NO_SURFACE_CACHE 0 |
54 | #define DBG_NO_SURFACE_CACHE 0 |
55 | 55 | ||
56 | #define MAX_3D_SIZE 8192 |
56 | #define MAX_3D_SIZE 8192 |
57 | 57 | ||
58 | #define GEN5_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1) |
58 | #define GEN5_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1) |
59 | 59 | ||
60 | /* Set up a default static partitioning of the URB, which is supposed to |
60 | /* Set up a default static partitioning of the URB, which is supposed to |
61 | * allow anything we would want to do, at potentially lower performance. |
61 | * allow anything we would want to do, at potentially lower performance. |
62 | */ |
62 | */ |
63 | #define URB_CS_ENTRY_SIZE 1 |
63 | #define URB_CS_ENTRY_SIZE 1 |
64 | #define URB_CS_ENTRIES 0 |
64 | #define URB_CS_ENTRIES 0 |
65 | 65 | ||
66 | #define URB_VS_ENTRY_SIZE 1 |
66 | #define URB_VS_ENTRY_SIZE 1 |
67 | #define URB_VS_ENTRIES 256 /* minimum of 8 */ |
67 | #define URB_VS_ENTRIES 256 /* minimum of 8 */ |
68 | 68 | ||
69 | #define URB_GS_ENTRY_SIZE 0 |
69 | #define URB_GS_ENTRY_SIZE 0 |
70 | #define URB_GS_ENTRIES 0 |
70 | #define URB_GS_ENTRIES 0 |
71 | 71 | ||
72 | #define URB_CLIP_ENTRY_SIZE 0 |
72 | #define URB_CLIP_ENTRY_SIZE 0 |
73 | #define URB_CLIP_ENTRIES 0 |
73 | #define URB_CLIP_ENTRIES 0 |
74 | 74 | ||
75 | #define URB_SF_ENTRY_SIZE 2 |
75 | #define URB_SF_ENTRY_SIZE 2 |
76 | #define URB_SF_ENTRIES 64 |
76 | #define URB_SF_ENTRIES 64 |
77 | 77 | ||
78 | /* |
78 | /* |
79 | * this program computes dA/dx and dA/dy for the texture coordinates along |
79 | * this program computes dA/dx and dA/dy for the texture coordinates along |
80 | * with the base texture coordinate. It was extracted from the Mesa driver |
80 | * with the base texture coordinate. It was extracted from the Mesa driver |
81 | */ |
81 | */ |
82 | 82 | ||
83 | #define SF_KERNEL_NUM_GRF 16 |
83 | #define SF_KERNEL_NUM_GRF 16 |
84 | #define SF_MAX_THREADS 48 |
84 | #define SF_MAX_THREADS 48 |
85 | 85 | ||
86 | #define PS_KERNEL_NUM_GRF 32 |
86 | #define PS_KERNEL_NUM_GRF 32 |
87 | #define PS_MAX_THREADS 72 |
87 | #define PS_MAX_THREADS 72 |
88 | 88 | ||
89 | static const uint32_t ps_kernel_packed_static[][4] = { |
89 | static const uint32_t ps_kernel_packed_static[][4] = { |
90 | #include "exa_wm_xy.g5b" |
90 | #include "exa_wm_xy.g5b" |
91 | #include "exa_wm_src_affine.g5b" |
91 | #include "exa_wm_src_affine.g5b" |
92 | #include "exa_wm_src_sample_argb.g5b" |
92 | #include "exa_wm_src_sample_argb.g5b" |
93 | #include "exa_wm_yuv_rgb.g5b" |
93 | #include "exa_wm_yuv_rgb.g5b" |
94 | #include "exa_wm_write.g5b" |
94 | #include "exa_wm_write.g5b" |
95 | }; |
95 | }; |
96 | 96 | ||
97 | static const uint32_t ps_kernel_planar_static[][4] = { |
97 | static const uint32_t ps_kernel_planar_static[][4] = { |
98 | #include "exa_wm_xy.g5b" |
98 | #include "exa_wm_xy.g5b" |
99 | #include "exa_wm_src_affine.g5b" |
99 | #include "exa_wm_src_affine.g5b" |
100 | #include "exa_wm_src_sample_planar.g5b" |
100 | #include "exa_wm_src_sample_planar.g5b" |
101 | #include "exa_wm_yuv_rgb.g5b" |
101 | #include "exa_wm_yuv_rgb.g5b" |
102 | #include "exa_wm_write.g5b" |
102 | #include "exa_wm_write.g5b" |
103 | }; |
103 | }; |
104 | 104 | ||
105 | #define NOKERNEL(kernel_enum, func, masked) \ |
105 | #define NOKERNEL(kernel_enum, func, masked) \ |
106 | [kernel_enum] = {func, 0, masked} |
106 | [kernel_enum] = {func, 0, masked} |
107 | #define KERNEL(kernel_enum, kernel, masked) \ |
107 | #define KERNEL(kernel_enum, kernel, masked) \ |
108 | [kernel_enum] = {&kernel, sizeof(kernel), masked} |
108 | [kernel_enum] = {&kernel, sizeof(kernel), masked} |
109 | static const struct wm_kernel_info { |
109 | static const struct wm_kernel_info { |
110 | const void *data; |
110 | const void *data; |
111 | unsigned int size; |
111 | unsigned int size; |
112 | bool has_mask; |
112 | bool has_mask; |
113 | } wm_kernels[] = { |
113 | } wm_kernels[] = { |
114 | NOKERNEL(WM_KERNEL, brw_wm_kernel__affine, false), |
114 | NOKERNEL(WM_KERNEL, brw_wm_kernel__affine, false), |
115 | NOKERNEL(WM_KERNEL_P, brw_wm_kernel__projective, false), |
115 | NOKERNEL(WM_KERNEL_P, brw_wm_kernel__projective, false), |
116 | 116 | ||
117 | NOKERNEL(WM_KERNEL_MASK, brw_wm_kernel__affine_mask, true), |
117 | NOKERNEL(WM_KERNEL_MASK, brw_wm_kernel__affine_mask, true), |
118 | NOKERNEL(WM_KERNEL_MASK_P, brw_wm_kernel__projective_mask, true), |
118 | NOKERNEL(WM_KERNEL_MASK_P, brw_wm_kernel__projective_mask, true), |
119 | 119 | ||
120 | NOKERNEL(WM_KERNEL_MASKCA, brw_wm_kernel__affine_mask_ca, true), |
120 | NOKERNEL(WM_KERNEL_MASKCA, brw_wm_kernel__affine_mask_ca, true), |
121 | NOKERNEL(WM_KERNEL_MASKCA_P, brw_wm_kernel__projective_mask_ca, true), |
121 | NOKERNEL(WM_KERNEL_MASKCA_P, brw_wm_kernel__projective_mask_ca, true), |
122 | 122 | ||
123 | NOKERNEL(WM_KERNEL_MASKSA, brw_wm_kernel__affine_mask_sa, true), |
123 | NOKERNEL(WM_KERNEL_MASKSA, brw_wm_kernel__affine_mask_sa, true), |
124 | NOKERNEL(WM_KERNEL_MASKSA_P, brw_wm_kernel__projective_mask_sa, true), |
124 | NOKERNEL(WM_KERNEL_MASKSA_P, brw_wm_kernel__projective_mask_sa, true), |
125 | 125 | ||
126 | NOKERNEL(WM_KERNEL_OPACITY, brw_wm_kernel__affine_opacity, true), |
126 | NOKERNEL(WM_KERNEL_OPACITY, brw_wm_kernel__affine_opacity, true), |
127 | NOKERNEL(WM_KERNEL_OPACITY_P, brw_wm_kernel__projective_opacity, true), |
127 | NOKERNEL(WM_KERNEL_OPACITY_P, brw_wm_kernel__projective_opacity, true), |
128 | 128 | ||
129 | KERNEL(WM_KERNEL_VIDEO_PLANAR, ps_kernel_planar_static, false), |
129 | KERNEL(WM_KERNEL_VIDEO_PLANAR, ps_kernel_planar_static, false), |
130 | KERNEL(WM_KERNEL_VIDEO_PACKED, ps_kernel_packed_static, false), |
130 | KERNEL(WM_KERNEL_VIDEO_PACKED, ps_kernel_packed_static, false), |
131 | }; |
131 | }; |
132 | #undef KERNEL |
132 | #undef KERNEL |
133 | 133 | ||
134 | static const struct blendinfo { |
134 | static const struct blendinfo { |
135 | bool src_alpha; |
135 | bool src_alpha; |
136 | uint32_t src_blend; |
136 | uint32_t src_blend; |
137 | uint32_t dst_blend; |
137 | uint32_t dst_blend; |
138 | } gen5_blend_op[] = { |
138 | } gen5_blend_op[] = { |
139 | /* Clear */ {0, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_ZERO}, |
139 | /* Clear */ {0, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_ZERO}, |
140 | /* Src */ {0, GEN5_BLENDFACTOR_ONE, GEN5_BLENDFACTOR_ZERO}, |
140 | /* Src */ {0, GEN5_BLENDFACTOR_ONE, GEN5_BLENDFACTOR_ZERO}, |
141 | /* Dst */ {0, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_ONE}, |
141 | /* Dst */ {0, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_ONE}, |
142 | /* Over */ {1, GEN5_BLENDFACTOR_ONE, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
142 | /* Over */ {1, GEN5_BLENDFACTOR_ONE, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
143 | /* OverReverse */ {0, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_ONE}, |
143 | /* OverReverse */ {0, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_ONE}, |
144 | /* In */ {0, GEN5_BLENDFACTOR_DST_ALPHA, GEN5_BLENDFACTOR_ZERO}, |
144 | /* In */ {0, GEN5_BLENDFACTOR_DST_ALPHA, GEN5_BLENDFACTOR_ZERO}, |
145 | /* InReverse */ {1, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_SRC_ALPHA}, |
145 | /* InReverse */ {1, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_SRC_ALPHA}, |
146 | /* Out */ {0, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_ZERO}, |
146 | /* Out */ {0, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_ZERO}, |
147 | /* OutReverse */ {1, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
147 | /* OutReverse */ {1, GEN5_BLENDFACTOR_ZERO, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
148 | /* Atop */ {1, GEN5_BLENDFACTOR_DST_ALPHA, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
148 | /* Atop */ {1, GEN5_BLENDFACTOR_DST_ALPHA, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
149 | /* AtopReverse */ {1, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_SRC_ALPHA}, |
149 | /* AtopReverse */ {1, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_SRC_ALPHA}, |
150 | /* Xor */ {1, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
150 | /* Xor */ {1, GEN5_BLENDFACTOR_INV_DST_ALPHA, GEN5_BLENDFACTOR_INV_SRC_ALPHA}, |
151 | /* Add */ {0, GEN5_BLENDFACTOR_ONE, GEN5_BLENDFACTOR_ONE}, |
151 | /* Add */ {0, GEN5_BLENDFACTOR_ONE, GEN5_BLENDFACTOR_ONE}, |
152 | }; |
152 | }; |
153 | 153 | ||
154 | /** |
154 | /** |
155 | * Highest-valued BLENDFACTOR used in gen5_blend_op. |
155 | * Highest-valued BLENDFACTOR used in gen5_blend_op. |
156 | * |
156 | * |
157 | * This leaves out GEN5_BLENDFACTOR_INV_DST_COLOR, |
157 | * This leaves out GEN5_BLENDFACTOR_INV_DST_COLOR, |
158 | * GEN5_BLENDFACTOR_INV_CONST_{COLOR,ALPHA}, |
158 | * GEN5_BLENDFACTOR_INV_CONST_{COLOR,ALPHA}, |
159 | * GEN5_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA} |
159 | * GEN5_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA} |
160 | */ |
160 | */ |
161 | #define GEN5_BLENDFACTOR_COUNT (GEN5_BLENDFACTOR_INV_DST_ALPHA + 1) |
161 | #define GEN5_BLENDFACTOR_COUNT (GEN5_BLENDFACTOR_INV_DST_ALPHA + 1) |
162 | 162 | ||
163 | #define BLEND_OFFSET(s, d) \ |
163 | #define BLEND_OFFSET(s, d) \ |
164 | (((s) * GEN5_BLENDFACTOR_COUNT + (d)) * 64) |
164 | (((s) * GEN5_BLENDFACTOR_COUNT + (d)) * 64) |
165 | 165 | ||
166 | #define SAMPLER_OFFSET(sf, se, mf, me, k) \ |
166 | #define SAMPLER_OFFSET(sf, se, mf, me, k) \ |
167 | ((((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * KERNEL_COUNT + (k)) * 64) |
167 | ((((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * KERNEL_COUNT + (k)) * 64) |
168 | 168 | ||
169 | static bool |
169 | static bool |
170 | gen5_emit_pipelined_pointers(struct sna *sna, |
170 | gen5_emit_pipelined_pointers(struct sna *sna, |
171 | const struct sna_composite_op *op, |
171 | const struct sna_composite_op *op, |
172 | int blend, int kernel); |
172 | int blend, int kernel); |
173 | 173 | ||
174 | #define OUT_BATCH(v) batch_emit(sna, v) |
174 | #define OUT_BATCH(v) batch_emit(sna, v) |
175 | #define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y) |
175 | #define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y) |
176 | #define OUT_VERTEX_F(v) vertex_emit(sna, v) |
176 | #define OUT_VERTEX_F(v) vertex_emit(sna, v) |
177 | 177 | ||
178 | static inline bool too_large(int width, int height) |
178 | static inline bool too_large(int width, int height) |
179 | { |
179 | { |
180 | return width > MAX_3D_SIZE || height > MAX_3D_SIZE; |
180 | return width > MAX_3D_SIZE || height > MAX_3D_SIZE; |
181 | } |
181 | } |
182 | 182 | ||
183 | static int |
183 | static int |
184 | gen5_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine) |
184 | gen5_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine) |
185 | { |
185 | { |
186 | int base; |
186 | int base; |
187 | 187 | ||
188 | if (has_mask) { |
188 | if (has_mask) { |
189 | if (is_ca) { |
189 | if (is_ca) { |
190 | if (gen5_blend_op[op].src_alpha) |
190 | if (gen5_blend_op[op].src_alpha) |
191 | base = WM_KERNEL_MASKSA; |
191 | base = WM_KERNEL_MASKSA; |
192 | else |
192 | else |
193 | base = WM_KERNEL_MASKCA; |
193 | base = WM_KERNEL_MASKCA; |
194 | } else |
194 | } else |
195 | base = WM_KERNEL_MASK; |
195 | base = WM_KERNEL_MASK; |
196 | } else |
196 | } else |
197 | base = WM_KERNEL; |
197 | base = WM_KERNEL; |
198 | 198 | ||
199 | return base + !is_affine; |
199 | return base + !is_affine; |
200 | } |
200 | } |
201 | 201 | ||
202 | static bool gen5_magic_ca_pass(struct sna *sna, |
202 | static bool gen5_magic_ca_pass(struct sna *sna, |
203 | const struct sna_composite_op *op) |
203 | const struct sna_composite_op *op) |
204 | { |
204 | { |
205 | struct gen5_render_state *state = &sna->render_state.gen5; |
205 | struct gen5_render_state *state = &sna->render_state.gen5; |
206 | 206 | ||
207 | if (!op->need_magic_ca_pass) |
207 | if (!op->need_magic_ca_pass) |
208 | return false; |
208 | return false; |
209 | 209 | ||
210 | assert(sna->render.vertex_index > sna->render.vertex_start); |
210 | assert(sna->render.vertex_index > sna->render.vertex_start); |
211 | 211 | ||
212 | DBG(("%s: CA fixup\n", __FUNCTION__)); |
212 | DBG(("%s: CA fixup\n", __FUNCTION__)); |
213 | assert(op->mask.bo != NULL); |
213 | assert(op->mask.bo != NULL); |
214 | assert(op->has_component_alpha); |
214 | assert(op->has_component_alpha); |
215 | 215 | ||
216 | gen5_emit_pipelined_pointers |
216 | gen5_emit_pipelined_pointers |
217 | (sna, op, PictOpAdd, |
217 | (sna, op, PictOpAdd, |
218 | gen5_choose_composite_kernel(PictOpAdd, |
218 | gen5_choose_composite_kernel(PictOpAdd, |
219 | true, true, op->is_affine)); |
219 | true, true, op->is_affine)); |
220 | 220 | ||
221 | OUT_BATCH(GEN5_3DPRIMITIVE | |
221 | OUT_BATCH(GEN5_3DPRIMITIVE | |
222 | GEN5_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
222 | GEN5_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
223 | (_3DPRIM_RECTLIST << GEN5_3DPRIMITIVE_TOPOLOGY_SHIFT) | |
223 | (_3DPRIM_RECTLIST << GEN5_3DPRIMITIVE_TOPOLOGY_SHIFT) | |
224 | (0 << 9) | |
224 | (0 << 9) | |
225 | 4); |
225 | 4); |
226 | OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start); |
226 | OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start); |
227 | OUT_BATCH(sna->render.vertex_start); |
227 | OUT_BATCH(sna->render.vertex_start); |
228 | OUT_BATCH(1); /* single instance */ |
228 | OUT_BATCH(1); /* single instance */ |
229 | OUT_BATCH(0); /* start instance location */ |
229 | OUT_BATCH(0); /* start instance location */ |
230 | OUT_BATCH(0); /* index buffer offset, ignored */ |
230 | OUT_BATCH(0); /* index buffer offset, ignored */ |
231 | 231 | ||
232 | state->last_primitive = sna->kgem.nbatch; |
232 | state->last_primitive = sna->kgem.nbatch; |
233 | return true; |
233 | return true; |
234 | } |
234 | } |
235 | 235 | ||
236 | static uint32_t gen5_get_blend(int op, |
236 | static uint32_t gen5_get_blend(int op, |
237 | bool has_component_alpha, |
237 | bool has_component_alpha, |
238 | uint32_t dst_format) |
238 | uint32_t dst_format) |
239 | { |
239 | { |
240 | uint32_t src, dst; |
240 | uint32_t src, dst; |
241 | 241 | ||
242 | src = GEN5_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend; |
242 | src = GEN5_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend; |
243 | dst = GEN5_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend; |
243 | dst = GEN5_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend; |
244 | #if 0 |
244 | #if 0 |
245 | /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
245 | /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
246 | * it as always 1. |
246 | * it as always 1. |
247 | */ |
247 | */ |
248 | if (PICT_FORMAT_A(dst_format) == 0) { |
248 | if (PICT_FORMAT_A(dst_format) == 0) { |
249 | if (src == GEN5_BLENDFACTOR_DST_ALPHA) |
249 | if (src == GEN5_BLENDFACTOR_DST_ALPHA) |
250 | src = GEN5_BLENDFACTOR_ONE; |
250 | src = GEN5_BLENDFACTOR_ONE; |
251 | else if (src == GEN5_BLENDFACTOR_INV_DST_ALPHA) |
251 | else if (src == GEN5_BLENDFACTOR_INV_DST_ALPHA) |
252 | src = GEN5_BLENDFACTOR_ZERO; |
252 | src = GEN5_BLENDFACTOR_ZERO; |
253 | } |
253 | } |
254 | 254 | ||
255 | /* If the source alpha is being used, then we should only be in a |
255 | /* If the source alpha is being used, then we should only be in a |
256 | * case where the source blend factor is 0, and the source blend |
256 | * case where the source blend factor is 0, and the source blend |
257 | * value is the mask channels multiplied by the source picture's alpha. |
257 | * value is the mask channels multiplied by the source picture's alpha. |
258 | */ |
258 | */ |
259 | if (has_component_alpha && gen5_blend_op[op].src_alpha) { |
259 | if (has_component_alpha && gen5_blend_op[op].src_alpha) { |
260 | if (dst == GEN5_BLENDFACTOR_SRC_ALPHA) |
260 | if (dst == GEN5_BLENDFACTOR_SRC_ALPHA) |
261 | dst = GEN5_BLENDFACTOR_SRC_COLOR; |
261 | dst = GEN5_BLENDFACTOR_SRC_COLOR; |
262 | else if (dst == GEN5_BLENDFACTOR_INV_SRC_ALPHA) |
262 | else if (dst == GEN5_BLENDFACTOR_INV_SRC_ALPHA) |
263 | dst = GEN5_BLENDFACTOR_INV_SRC_COLOR; |
263 | dst = GEN5_BLENDFACTOR_INV_SRC_COLOR; |
264 | } |
264 | } |
265 | #endif |
265 | #endif |
266 | 266 | ||
267 | DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n", |
267 | DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n", |
268 | op, dst_format, PICT_FORMAT_A(dst_format), |
268 | op, dst_format, PICT_FORMAT_A(dst_format), |
269 | src, dst, BLEND_OFFSET(src, dst))); |
269 | src, dst, BLEND_OFFSET(src, dst))); |
270 | return BLEND_OFFSET(src, dst); |
270 | return BLEND_OFFSET(src, dst); |
271 | } |
271 | } |
272 | 272 | ||
273 | static uint32_t gen5_get_card_format(PictFormat format) |
273 | static uint32_t gen5_get_card_format(PictFormat format) |
274 | { |
274 | { |
275 | switch (format) { |
275 | switch (format) { |
276 | default: |
276 | default: |
277 | return -1; |
277 | return -1; |
278 | case PICT_a8r8g8b8: |
278 | case PICT_a8r8g8b8: |
279 | return GEN5_SURFACEFORMAT_B8G8R8A8_UNORM; |
279 | return GEN5_SURFACEFORMAT_B8G8R8A8_UNORM; |
280 | case PICT_x8r8g8b8: |
280 | case PICT_x8r8g8b8: |
281 | return GEN5_SURFACEFORMAT_B8G8R8X8_UNORM; |
281 | return GEN5_SURFACEFORMAT_B8G8R8X8_UNORM; |
282 | case PICT_a8: |
282 | case PICT_a8: |
283 | return GEN5_SURFACEFORMAT_A8_UNORM; |
283 | return GEN5_SURFACEFORMAT_A8_UNORM; |
284 | } |
284 | } |
285 | } |
285 | } |
286 | 286 | ||
287 | static uint32_t gen5_get_dest_format(PictFormat format) |
287 | static uint32_t gen5_get_dest_format(PictFormat format) |
288 | { |
288 | { |
289 | switch (format) { |
289 | switch (format) { |
290 | default: |
290 | default: |
291 | return -1; |
291 | return -1; |
292 | case PICT_a8r8g8b8: |
292 | case PICT_a8r8g8b8: |
293 | case PICT_x8r8g8b8: |
293 | case PICT_x8r8g8b8: |
294 | return GEN5_SURFACEFORMAT_B8G8R8A8_UNORM; |
294 | return GEN5_SURFACEFORMAT_B8G8R8A8_UNORM; |
295 | case PICT_a8: |
295 | case PICT_a8: |
296 | return GEN5_SURFACEFORMAT_A8_UNORM; |
296 | return GEN5_SURFACEFORMAT_A8_UNORM; |
297 | } |
297 | } |
298 | } |
298 | } |
299 | typedef struct gen5_surface_state_padded { |
299 | typedef struct gen5_surface_state_padded { |
300 | struct gen5_surface_state state; |
300 | struct gen5_surface_state state; |
301 | char pad[32 - sizeof(struct gen5_surface_state)]; |
301 | char pad[32 - sizeof(struct gen5_surface_state)]; |
302 | } gen5_surface_state_padded; |
302 | } gen5_surface_state_padded; |
303 | 303 | ||
304 | static void null_create(struct sna_static_stream *stream) |
304 | static void null_create(struct sna_static_stream *stream) |
305 | { |
305 | { |
306 | /* A bunch of zeros useful for legacy border color and depth-stencil */ |
306 | /* A bunch of zeros useful for legacy border color and depth-stencil */ |
307 | sna_static_stream_map(stream, 64, 64); |
307 | sna_static_stream_map(stream, 64, 64); |
308 | } |
308 | } |
309 | 309 | ||
310 | static void |
310 | static void |
311 | sampler_state_init(struct gen5_sampler_state *sampler_state, |
311 | sampler_state_init(struct gen5_sampler_state *sampler_state, |
312 | sampler_filter_t filter, |
312 | sampler_filter_t filter, |
313 | sampler_extend_t extend) |
313 | sampler_extend_t extend) |
314 | { |
314 | { |
315 | sampler_state->ss0.lod_preclamp = 1; /* GL mode */ |
315 | sampler_state->ss0.lod_preclamp = 1; /* GL mode */ |
316 | 316 | ||
317 | /* We use the legacy mode to get the semantics specified by |
317 | /* We use the legacy mode to get the semantics specified by |
318 | * the Render extension. */ |
318 | * the Render extension. */ |
319 | sampler_state->ss0.border_color_mode = GEN5_BORDER_COLOR_MODE_LEGACY; |
319 | sampler_state->ss0.border_color_mode = GEN5_BORDER_COLOR_MODE_LEGACY; |
320 | 320 | ||
321 | switch (filter) { |
321 | switch (filter) { |
322 | default: |
322 | default: |
323 | case SAMPLER_FILTER_NEAREST: |
323 | case SAMPLER_FILTER_NEAREST: |
324 | sampler_state->ss0.min_filter = GEN5_MAPFILTER_NEAREST; |
324 | sampler_state->ss0.min_filter = GEN5_MAPFILTER_NEAREST; |
325 | sampler_state->ss0.mag_filter = GEN5_MAPFILTER_NEAREST; |
325 | sampler_state->ss0.mag_filter = GEN5_MAPFILTER_NEAREST; |
326 | break; |
326 | break; |
327 | case SAMPLER_FILTER_BILINEAR: |
327 | case SAMPLER_FILTER_BILINEAR: |
328 | sampler_state->ss0.min_filter = GEN5_MAPFILTER_LINEAR; |
328 | sampler_state->ss0.min_filter = GEN5_MAPFILTER_LINEAR; |
329 | sampler_state->ss0.mag_filter = GEN5_MAPFILTER_LINEAR; |
329 | sampler_state->ss0.mag_filter = GEN5_MAPFILTER_LINEAR; |
330 | break; |
330 | break; |
331 | } |
331 | } |
332 | 332 | ||
333 | switch (extend) { |
333 | switch (extend) { |
334 | default: |
334 | default: |
335 | case SAMPLER_EXTEND_NONE: |
335 | case SAMPLER_EXTEND_NONE: |
336 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_CLAMP_BORDER; |
336 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_CLAMP_BORDER; |
337 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_CLAMP_BORDER; |
337 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_CLAMP_BORDER; |
338 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_CLAMP_BORDER; |
338 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_CLAMP_BORDER; |
339 | break; |
339 | break; |
340 | case SAMPLER_EXTEND_REPEAT: |
340 | case SAMPLER_EXTEND_REPEAT: |
341 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_WRAP; |
341 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_WRAP; |
342 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_WRAP; |
342 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_WRAP; |
343 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_WRAP; |
343 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_WRAP; |
344 | break; |
344 | break; |
345 | case SAMPLER_EXTEND_PAD: |
345 | case SAMPLER_EXTEND_PAD: |
346 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_CLAMP; |
346 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_CLAMP; |
347 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_CLAMP; |
347 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_CLAMP; |
348 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_CLAMP; |
348 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_CLAMP; |
349 | break; |
349 | break; |
350 | case SAMPLER_EXTEND_REFLECT: |
350 | case SAMPLER_EXTEND_REFLECT: |
351 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_MIRROR; |
351 | sampler_state->ss1.r_wrap_mode = GEN5_TEXCOORDMODE_MIRROR; |
352 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_MIRROR; |
352 | sampler_state->ss1.s_wrap_mode = GEN5_TEXCOORDMODE_MIRROR; |
353 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_MIRROR; |
353 | sampler_state->ss1.t_wrap_mode = GEN5_TEXCOORDMODE_MIRROR; |
354 | break; |
354 | break; |
355 | } |
355 | } |
356 | } |
356 | } |
357 | 357 | ||
358 | static uint32_t |
358 | static uint32_t |
359 | gen5_tiling_bits(uint32_t tiling) |
359 | gen5_tiling_bits(uint32_t tiling) |
360 | { |
360 | { |
361 | switch (tiling) { |
361 | switch (tiling) { |
362 | default: assert(0); |
362 | default: assert(0); |
363 | case I915_TILING_NONE: return 0; |
363 | case I915_TILING_NONE: return 0; |
364 | case I915_TILING_X: return GEN5_SURFACE_TILED; |
364 | case I915_TILING_X: return GEN5_SURFACE_TILED; |
365 | case I915_TILING_Y: return GEN5_SURFACE_TILED | GEN5_SURFACE_TILED_Y; |
365 | case I915_TILING_Y: return GEN5_SURFACE_TILED | GEN5_SURFACE_TILED_Y; |
366 | } |
366 | } |
367 | } |
367 | } |
368 | 368 | ||
369 | /** |
369 | /** |
370 | * Sets up the common fields for a surface state buffer for the given |
370 | * Sets up the common fields for a surface state buffer for the given |
371 | * picture in the given surface state buffer. |
371 | * picture in the given surface state buffer. |
372 | */ |
372 | */ |
373 | static uint32_t |
373 | static uint32_t |
374 | gen5_bind_bo(struct sna *sna, |
374 | gen5_bind_bo(struct sna *sna, |
375 | struct kgem_bo *bo, |
375 | struct kgem_bo *bo, |
376 | uint32_t width, |
376 | uint32_t width, |
377 | uint32_t height, |
377 | uint32_t height, |
378 | uint32_t format, |
378 | uint32_t format, |
379 | bool is_dst) |
379 | bool is_dst) |
380 | { |
380 | { |
381 | uint32_t domains; |
381 | uint32_t domains; |
382 | uint16_t offset; |
382 | uint16_t offset; |
383 | uint32_t *ss; |
383 | uint32_t *ss; |
384 | 384 | ||
385 | /* After the first bind, we manage the cache domains within the batch */ |
385 | /* After the first bind, we manage the cache domains within the batch */ |
386 | if (!DBG_NO_SURFACE_CACHE) { |
386 | if (!DBG_NO_SURFACE_CACHE) { |
387 | offset = kgem_bo_get_binding(bo, format); |
387 | offset = kgem_bo_get_binding(bo, format); |
388 | if (offset) { |
388 | if (offset) { |
389 | if (is_dst) |
389 | if (is_dst) |
390 | kgem_bo_mark_dirty(bo); |
390 | kgem_bo_mark_dirty(bo); |
391 | return offset * sizeof(uint32_t); |
391 | return offset * sizeof(uint32_t); |
392 | } |
392 | } |
393 | } |
393 | } |
394 | 394 | ||
395 | offset = sna->kgem.surface -= |
395 | offset = sna->kgem.surface -= |
396 | sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t); |
396 | sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t); |
397 | ss = sna->kgem.batch + offset; |
397 | ss = sna->kgem.batch + offset; |
398 | 398 | ||
399 | ss[0] = (GEN5_SURFACE_2D << GEN5_SURFACE_TYPE_SHIFT | |
399 | ss[0] = (GEN5_SURFACE_2D << GEN5_SURFACE_TYPE_SHIFT | |
400 | GEN5_SURFACE_BLEND_ENABLED | |
400 | GEN5_SURFACE_BLEND_ENABLED | |
401 | format << GEN5_SURFACE_FORMAT_SHIFT); |
401 | format << GEN5_SURFACE_FORMAT_SHIFT); |
402 | 402 | ||
403 | if (is_dst) |
403 | if (is_dst) |
404 | domains = I915_GEM_DOMAIN_RENDER << 16 | I915_GEM_DOMAIN_RENDER; |
404 | domains = I915_GEM_DOMAIN_RENDER << 16 | I915_GEM_DOMAIN_RENDER; |
405 | else |
405 | else |
406 | domains = I915_GEM_DOMAIN_SAMPLER << 16; |
406 | domains = I915_GEM_DOMAIN_SAMPLER << 16; |
407 | ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0); |
407 | ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0); |
408 | 408 | ||
409 | ss[2] = ((width - 1) << GEN5_SURFACE_WIDTH_SHIFT | |
409 | ss[2] = ((width - 1) << GEN5_SURFACE_WIDTH_SHIFT | |
410 | (height - 1) << GEN5_SURFACE_HEIGHT_SHIFT); |
410 | (height - 1) << GEN5_SURFACE_HEIGHT_SHIFT); |
411 | ss[3] = (gen5_tiling_bits(bo->tiling) | |
411 | ss[3] = (gen5_tiling_bits(bo->tiling) | |
412 | (bo->pitch - 1) << GEN5_SURFACE_PITCH_SHIFT); |
412 | (bo->pitch - 1) << GEN5_SURFACE_PITCH_SHIFT); |
413 | ss[4] = 0; |
413 | ss[4] = 0; |
414 | ss[5] = 0; |
414 | ss[5] = 0; |
415 | 415 | ||
416 | kgem_bo_set_binding(bo, format, offset); |
416 | kgem_bo_set_binding(bo, format, offset); |
417 | 417 | ||
418 | DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n", |
418 | DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n", |
419 | offset, bo->handle, ss[1], |
419 | offset, bo->handle, ss[1], |
420 | format, width, height, bo->pitch, bo->tiling, |
420 | format, width, height, bo->pitch, bo->tiling, |
421 | domains & 0xffff ? "render" : "sampler")); |
421 | domains & 0xffff ? "render" : "sampler")); |
422 | 422 | ||
423 | return offset * sizeof(uint32_t); |
423 | return offset * sizeof(uint32_t); |
424 | } |
424 | } |
425 | 425 | ||
426 | static void gen5_emit_vertex_buffer(struct sna *sna, |
426 | static void gen5_emit_vertex_buffer(struct sna *sna, |
427 | const struct sna_composite_op *op) |
427 | const struct sna_composite_op *op) |
428 | { |
428 | { |
429 | int id = op->u.gen5.ve_id; |
429 | int id = op->u.gen5.ve_id; |
430 | 430 | ||
431 | assert((sna->render.vb_id & (1 << id)) == 0); |
431 | assert((sna->render.vb_id & (1 << id)) == 0); |
432 | 432 | ||
433 | OUT_BATCH(GEN5_3DSTATE_VERTEX_BUFFERS | 3); |
433 | OUT_BATCH(GEN5_3DSTATE_VERTEX_BUFFERS | 3); |
434 | OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA | |
434 | OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA | |
435 | (4*op->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT)); |
435 | (4*op->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT)); |
436 | assert(sna->render.nvertex_reloc < ARRAY_SIZE(sna->render.vertex_reloc)); |
436 | assert(sna->render.nvertex_reloc < ARRAY_SIZE(sna->render.vertex_reloc)); |
437 | sna->render.vertex_reloc[sna->render.nvertex_reloc++] = sna->kgem.nbatch; |
437 | sna->render.vertex_reloc[sna->render.nvertex_reloc++] = sna->kgem.nbatch; |
438 | OUT_BATCH(0); |
438 | OUT_BATCH(0); |
439 | OUT_BATCH(~0); /* max address: disabled */ |
439 | OUT_BATCH(~0); /* max address: disabled */ |
440 | OUT_BATCH(0); |
440 | OUT_BATCH(0); |
441 | 441 | ||
442 | sna->render.vb_id |= 1 << id; |
442 | sna->render.vb_id |= 1 << id; |
443 | } |
443 | } |
444 | 444 | ||
445 | static void gen5_emit_primitive(struct sna *sna) |
445 | static void gen5_emit_primitive(struct sna *sna) |
446 | { |
446 | { |
447 | if (sna->kgem.nbatch == sna->render_state.gen5.last_primitive) { |
447 | if (sna->kgem.nbatch == sna->render_state.gen5.last_primitive) { |
448 | sna->render.vertex_offset = sna->kgem.nbatch - 5; |
448 | sna->render.vertex_offset = sna->kgem.nbatch - 5; |
449 | return; |
449 | return; |
450 | } |
450 | } |
451 | 451 | ||
452 | OUT_BATCH(GEN5_3DPRIMITIVE | |
452 | OUT_BATCH(GEN5_3DPRIMITIVE | |
453 | GEN5_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
453 | GEN5_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
454 | (_3DPRIM_RECTLIST << GEN5_3DPRIMITIVE_TOPOLOGY_SHIFT) | |
454 | (_3DPRIM_RECTLIST << GEN5_3DPRIMITIVE_TOPOLOGY_SHIFT) | |
455 | (0 << 9) | |
455 | (0 << 9) | |
456 | 4); |
456 | 4); |
457 | sna->render.vertex_offset = sna->kgem.nbatch; |
457 | sna->render.vertex_offset = sna->kgem.nbatch; |
458 | OUT_BATCH(0); /* vertex count, to be filled in later */ |
458 | OUT_BATCH(0); /* vertex count, to be filled in later */ |
459 | OUT_BATCH(sna->render.vertex_index); |
459 | OUT_BATCH(sna->render.vertex_index); |
460 | OUT_BATCH(1); /* single instance */ |
460 | OUT_BATCH(1); /* single instance */ |
461 | OUT_BATCH(0); /* start instance location */ |
461 | OUT_BATCH(0); /* start instance location */ |
462 | OUT_BATCH(0); /* index buffer offset, ignored */ |
462 | OUT_BATCH(0); /* index buffer offset, ignored */ |
463 | sna->render.vertex_start = sna->render.vertex_index; |
463 | sna->render.vertex_start = sna->render.vertex_index; |
464 | 464 | ||
465 | sna->render_state.gen5.last_primitive = sna->kgem.nbatch; |
465 | sna->render_state.gen5.last_primitive = sna->kgem.nbatch; |
466 | } |
466 | } |
467 | 467 | ||
468 | static bool gen5_rectangle_begin(struct sna *sna, |
468 | static bool gen5_rectangle_begin(struct sna *sna, |
469 | const struct sna_composite_op *op) |
469 | const struct sna_composite_op *op) |
470 | { |
470 | { |
471 | int id = op->u.gen5.ve_id; |
471 | int id = op->u.gen5.ve_id; |
472 | int ndwords; |
472 | int ndwords; |
473 | 473 | ||
474 | if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset) |
474 | if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset) |
475 | return true; |
475 | return true; |
476 | 476 | ||
477 | ndwords = op->need_magic_ca_pass ? 20 : 6; |
477 | ndwords = op->need_magic_ca_pass ? 20 : 6; |
478 | if ((sna->render.vb_id & (1 << id)) == 0) |
478 | if ((sna->render.vb_id & (1 << id)) == 0) |
479 | ndwords += 5; |
479 | ndwords += 5; |
480 | 480 | ||
481 | if (!kgem_check_batch(&sna->kgem, ndwords)) |
481 | if (!kgem_check_batch(&sna->kgem, ndwords)) |
482 | return false; |
482 | return false; |
483 | 483 | ||
484 | if ((sna->render.vb_id & (1 << id)) == 0) |
484 | if ((sna->render.vb_id & (1 << id)) == 0) |
485 | gen5_emit_vertex_buffer(sna, op); |
485 | gen5_emit_vertex_buffer(sna, op); |
486 | if (sna->render.vertex_offset == 0) |
486 | if (sna->render.vertex_offset == 0) |
487 | gen5_emit_primitive(sna); |
487 | gen5_emit_primitive(sna); |
488 | 488 | ||
489 | return true; |
489 | return true; |
490 | } |
490 | } |
491 | 491 | ||
492 | static int gen5_get_rectangles__flush(struct sna *sna, |
492 | static int gen5_get_rectangles__flush(struct sna *sna, |
493 | const struct sna_composite_op *op) |
493 | const struct sna_composite_op *op) |
494 | { |
494 | { |
495 | /* Preventing discarding new vbo after lock contention */ |
495 | /* Preventing discarding new vbo after lock contention */ |
496 | if (sna_vertex_wait__locked(&sna->render)) { |
496 | if (sna_vertex_wait__locked(&sna->render)) { |
497 | int rem = vertex_space(sna); |
497 | int rem = vertex_space(sna); |
498 | if (rem > op->floats_per_rect) |
498 | if (rem > op->floats_per_rect) |
499 | return rem; |
499 | return rem; |
500 | } |
500 | } |
501 | 501 | ||
502 | if (!kgem_check_batch(&sna->kgem, op->need_magic_ca_pass ? 20 : 6)) |
502 | if (!kgem_check_batch(&sna->kgem, op->need_magic_ca_pass ? 20 : 6)) |
503 | return 0; |
503 | return 0; |
504 | if (!kgem_check_reloc_and_exec(&sna->kgem, 2)) |
504 | if (!kgem_check_reloc_and_exec(&sna->kgem, 2)) |
505 | return 0; |
505 | return 0; |
506 | 506 | ||
507 | if (sna->render.vertex_offset) { |
507 | if (sna->render.vertex_offset) { |
508 | gen4_vertex_flush(sna); |
508 | gen4_vertex_flush(sna); |
509 | if (gen5_magic_ca_pass(sna, op)) |
509 | if (gen5_magic_ca_pass(sna, op)) |
510 | gen5_emit_pipelined_pointers(sna, op, op->op, |
510 | gen5_emit_pipelined_pointers(sna, op, op->op, |
511 | op->u.gen5.wm_kernel); |
511 | op->u.gen5.wm_kernel); |
512 | } |
512 | } |
513 | 513 | ||
514 | return gen4_vertex_finish(sna); |
514 | return gen4_vertex_finish(sna); |
515 | } |
515 | } |
516 | 516 | ||
517 | inline static int gen5_get_rectangles(struct sna *sna, |
517 | inline static int gen5_get_rectangles(struct sna *sna, |
518 | const struct sna_composite_op *op, |
518 | const struct sna_composite_op *op, |
519 | int want, |
519 | int want, |
520 | void (*emit_state)(struct sna *sna, |
520 | void (*emit_state)(struct sna *sna, |
521 | const struct sna_composite_op *op)) |
521 | const struct sna_composite_op *op)) |
522 | { |
522 | { |
523 | int rem; |
523 | int rem; |
524 | 524 | ||
525 | assert(want); |
525 | assert(want); |
526 | 526 | ||
527 | start: |
527 | start: |
528 | rem = vertex_space(sna); |
528 | rem = vertex_space(sna); |
529 | if (unlikely(rem < op->floats_per_rect)) { |
529 | if (unlikely(rem < op->floats_per_rect)) { |
530 | DBG(("flushing vbo for %s: %d < %d\n", |
530 | DBG(("flushing vbo for %s: %d < %d\n", |
531 | __FUNCTION__, rem, op->floats_per_rect)); |
531 | __FUNCTION__, rem, op->floats_per_rect)); |
532 | rem = gen5_get_rectangles__flush(sna, op); |
532 | rem = gen5_get_rectangles__flush(sna, op); |
533 | if (unlikely (rem == 0)) |
533 | if (unlikely (rem == 0)) |
534 | goto flush; |
534 | goto flush; |
535 | } |
535 | } |
536 | 536 | ||
537 | if (unlikely(sna->render.vertex_offset == 0)) { |
537 | if (unlikely(sna->render.vertex_offset == 0)) { |
538 | if (!gen5_rectangle_begin(sna, op)) |
538 | if (!gen5_rectangle_begin(sna, op)) |
539 | goto flush; |
539 | goto flush; |
540 | else |
540 | else |
541 | goto start; |
541 | goto start; |
542 | } |
542 | } |
543 | 543 | ||
544 | assert(op->floats_per_rect >= vertex_space(sna)); |
544 | assert(op->floats_per_rect >= vertex_space(sna)); |
545 | assert(rem <= vertex_space(sna)); |
545 | assert(rem <= vertex_space(sna)); |
546 | if (want > 1 && want * op->floats_per_rect > rem) |
546 | if (want > 1 && want * op->floats_per_rect > rem) |
547 | want = rem / op->floats_per_rect; |
547 | want = rem / op->floats_per_rect; |
548 | 548 | ||
549 | sna->render.vertex_index += 3*want; |
549 | sna->render.vertex_index += 3*want; |
550 | return want; |
550 | return want; |
551 | 551 | ||
552 | flush: |
552 | flush: |
553 | if (sna->render.vertex_offset) { |
553 | if (sna->render.vertex_offset) { |
554 | gen4_vertex_flush(sna); |
554 | gen4_vertex_flush(sna); |
555 | gen5_magic_ca_pass(sna, op); |
555 | gen5_magic_ca_pass(sna, op); |
556 | } |
556 | } |
557 | sna_vertex_wait__locked(&sna->render); |
557 | sna_vertex_wait__locked(&sna->render); |
558 | _kgem_submit(&sna->kgem); |
558 | _kgem_submit(&sna->kgem); |
559 | emit_state(sna, op); |
559 | emit_state(sna, op); |
560 | goto start; |
560 | goto start; |
561 | } |
561 | } |
562 | 562 | ||
563 | static uint32_t * |
563 | static uint32_t * |
564 | gen5_composite_get_binding_table(struct sna *sna, |
564 | gen5_composite_get_binding_table(struct sna *sna, |
565 | uint16_t *offset) |
565 | uint16_t *offset) |
566 | { |
566 | { |
567 | sna->kgem.surface -= |
567 | sna->kgem.surface -= |
568 | sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t); |
568 | sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t); |
569 | 569 | ||
570 | DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface)); |
570 | DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface)); |
571 | 571 | ||
572 | /* Clear all surplus entries to zero in case of prefetch */ |
572 | /* Clear all surplus entries to zero in case of prefetch */ |
573 | *offset = sna->kgem.surface; |
573 | *offset = sna->kgem.surface; |
574 | return memset(sna->kgem.batch + sna->kgem.surface, |
574 | return memset(sna->kgem.batch + sna->kgem.surface, |
575 | 0, sizeof(struct gen5_surface_state_padded)); |
575 | 0, sizeof(struct gen5_surface_state_padded)); |
576 | } |
576 | } |
577 | 577 | ||
578 | static void |
578 | static void |
579 | gen5_emit_urb(struct sna *sna) |
579 | gen5_emit_urb(struct sna *sna) |
580 | { |
580 | { |
581 | int urb_vs_start, urb_vs_size; |
581 | int urb_vs_start, urb_vs_size; |
582 | int urb_gs_start, urb_gs_size; |
582 | int urb_gs_start, urb_gs_size; |
583 | int urb_clip_start, urb_clip_size; |
583 | int urb_clip_start, urb_clip_size; |
584 | int urb_sf_start, urb_sf_size; |
584 | int urb_sf_start, urb_sf_size; |
585 | int urb_cs_start, urb_cs_size; |
585 | int urb_cs_start, urb_cs_size; |
586 | 586 | ||
587 | urb_vs_start = 0; |
587 | urb_vs_start = 0; |
588 | urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE; |
588 | urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE; |
589 | urb_gs_start = urb_vs_start + urb_vs_size; |
589 | urb_gs_start = urb_vs_start + urb_vs_size; |
590 | urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE; |
590 | urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE; |
591 | urb_clip_start = urb_gs_start + urb_gs_size; |
591 | urb_clip_start = urb_gs_start + urb_gs_size; |
592 | urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE; |
592 | urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE; |
593 | urb_sf_start = urb_clip_start + urb_clip_size; |
593 | urb_sf_start = urb_clip_start + urb_clip_size; |
594 | urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE; |
594 | urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE; |
595 | urb_cs_start = urb_sf_start + urb_sf_size; |
595 | urb_cs_start = urb_sf_start + urb_sf_size; |
596 | urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; |
596 | urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; |
597 | 597 | ||
598 | OUT_BATCH(GEN5_URB_FENCE | |
598 | OUT_BATCH(GEN5_URB_FENCE | |
599 | UF0_CS_REALLOC | |
599 | UF0_CS_REALLOC | |
600 | UF0_SF_REALLOC | |
600 | UF0_SF_REALLOC | |
601 | UF0_CLIP_REALLOC | |
601 | UF0_CLIP_REALLOC | |
602 | UF0_GS_REALLOC | |
602 | UF0_GS_REALLOC | |
603 | UF0_VS_REALLOC | |
603 | UF0_VS_REALLOC | |
604 | 1); |
604 | 1); |
605 | OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) | |
605 | OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) | |
606 | ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) | |
606 | ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) | |
607 | ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT)); |
607 | ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT)); |
608 | OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) | |
608 | OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) | |
609 | ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT)); |
609 | ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT)); |
610 | 610 | ||
611 | /* Constant buffer state */ |
611 | /* Constant buffer state */ |
612 | OUT_BATCH(GEN5_CS_URB_STATE | 0); |
612 | OUT_BATCH(GEN5_CS_URB_STATE | 0); |
613 | OUT_BATCH((URB_CS_ENTRY_SIZE - 1) << 4 | URB_CS_ENTRIES << 0); |
613 | OUT_BATCH((URB_CS_ENTRY_SIZE - 1) << 4 | URB_CS_ENTRIES << 0); |
614 | } |
614 | } |
615 | 615 | ||
616 | static void |
616 | static void |
617 | gen5_emit_state_base_address(struct sna *sna) |
617 | gen5_emit_state_base_address(struct sna *sna) |
618 | { |
618 | { |
619 | assert(sna->render_state.gen5.general_bo->proxy == NULL); |
619 | assert(sna->render_state.gen5.general_bo->proxy == NULL); |
620 | OUT_BATCH(GEN5_STATE_BASE_ADDRESS | 6); |
620 | OUT_BATCH(GEN5_STATE_BASE_ADDRESS | 6); |
621 | OUT_BATCH(kgem_add_reloc(&sna->kgem, /* general */ |
621 | OUT_BATCH(kgem_add_reloc(&sna->kgem, /* general */ |
622 | sna->kgem.nbatch, |
622 | sna->kgem.nbatch, |
623 | sna->render_state.gen5.general_bo, |
623 | sna->render_state.gen5.general_bo, |
624 | I915_GEM_DOMAIN_INSTRUCTION << 16, |
624 | I915_GEM_DOMAIN_INSTRUCTION << 16, |
625 | BASE_ADDRESS_MODIFY)); |
625 | BASE_ADDRESS_MODIFY)); |
626 | OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */ |
626 | OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */ |
627 | sna->kgem.nbatch, |
627 | sna->kgem.nbatch, |
628 | NULL, |
628 | NULL, |
629 | I915_GEM_DOMAIN_INSTRUCTION << 16, |
629 | I915_GEM_DOMAIN_INSTRUCTION << 16, |
630 | BASE_ADDRESS_MODIFY)); |
630 | BASE_ADDRESS_MODIFY)); |
631 | OUT_BATCH(0); /* media */ |
631 | OUT_BATCH(0); /* media */ |
632 | OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */ |
632 | OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */ |
633 | sna->kgem.nbatch, |
633 | sna->kgem.nbatch, |
634 | sna->render_state.gen5.general_bo, |
634 | sna->render_state.gen5.general_bo, |
635 | I915_GEM_DOMAIN_INSTRUCTION << 16, |
635 | I915_GEM_DOMAIN_INSTRUCTION << 16, |
636 | BASE_ADDRESS_MODIFY)); |
636 | BASE_ADDRESS_MODIFY)); |
637 | 637 | ||
638 | /* upper bounds, all disabled */ |
638 | /* upper bounds, all disabled */ |
639 | OUT_BATCH(BASE_ADDRESS_MODIFY); |
639 | OUT_BATCH(BASE_ADDRESS_MODIFY); |
640 | OUT_BATCH(0); |
640 | OUT_BATCH(0); |
641 | OUT_BATCH(BASE_ADDRESS_MODIFY); |
641 | OUT_BATCH(BASE_ADDRESS_MODIFY); |
642 | } |
642 | } |
643 | 643 | ||
644 | static void |
644 | static void |
645 | gen5_emit_invariant(struct sna *sna) |
645 | gen5_emit_invariant(struct sna *sna) |
646 | { |
646 | { |
647 | /* Ironlake errata workaround: Before disabling the clipper, |
647 | /* Ironlake errata workaround: Before disabling the clipper, |
648 | * you have to MI_FLUSH to get the pipeline idle. |
648 | * you have to MI_FLUSH to get the pipeline idle. |
649 | * |
649 | * |
650 | * However, the kernel flushes the pipeline between batches, |
650 | * However, the kernel flushes the pipeline between batches, |
651 | * so we should be safe.... |
651 | * so we should be safe.... |
652 | * OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); |
652 | * OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); |
653 | */ |
653 | */ |
654 | OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D); |
654 | OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D); |
655 | 655 | ||
656 | gen5_emit_state_base_address(sna); |
656 | gen5_emit_state_base_address(sna); |
657 | 657 | ||
658 | sna->render_state.gen5.needs_invariant = false; |
658 | sna->render_state.gen5.needs_invariant = false; |
659 | } |
659 | } |
660 | 660 | ||
661 | static void |
661 | static void |
662 | gen5_get_batch(struct sna *sna, const struct sna_composite_op *op) |
662 | gen5_get_batch(struct sna *sna, const struct sna_composite_op *op) |
663 | { |
663 | { |
664 | kgem_set_mode(&sna->kgem, KGEM_RENDER, op->dst.bo); |
664 | kgem_set_mode(&sna->kgem, KGEM_RENDER, op->dst.bo); |
665 | 665 | ||
666 | if (!kgem_check_batch_with_surfaces(&sna->kgem, 150, 4)) { |
666 | if (!kgem_check_batch_with_surfaces(&sna->kgem, 150, 4)) { |
667 | DBG(("%s: flushing batch: %d < %d+%d\n", |
667 | DBG(("%s: flushing batch: %d < %d+%d\n", |
668 | __FUNCTION__, sna->kgem.surface - sna->kgem.nbatch, |
668 | __FUNCTION__, sna->kgem.surface - sna->kgem.nbatch, |
669 | 150, 4*8)); |
669 | 150, 4*8)); |
670 | kgem_submit(&sna->kgem); |
670 | kgem_submit(&sna->kgem); |
671 | _kgem_set_mode(&sna->kgem, KGEM_RENDER); |
671 | _kgem_set_mode(&sna->kgem, KGEM_RENDER); |
672 | } |
672 | } |
673 | 673 | ||
674 | if (sna->render_state.gen5.needs_invariant) |
674 | if (sna->render_state.gen5.needs_invariant) |
675 | gen5_emit_invariant(sna); |
675 | gen5_emit_invariant(sna); |
676 | } |
676 | } |
677 | 677 | ||
678 | static void |
678 | static void |
679 | gen5_align_vertex(struct sna *sna, const struct sna_composite_op *op) |
679 | gen5_align_vertex(struct sna *sna, const struct sna_composite_op *op) |
680 | { |
680 | { |
681 | assert(op->floats_per_rect == 3*op->floats_per_vertex); |
681 | assert(op->floats_per_rect == 3*op->floats_per_vertex); |
682 | if (op->floats_per_vertex != sna->render_state.gen5.floats_per_vertex) { |
682 | if (op->floats_per_vertex != sna->render_state.gen5.floats_per_vertex) { |
683 | if (sna->render.vertex_size - sna->render.vertex_used < 2*op->floats_per_rect) |
683 | if (sna->render.vertex_size - sna->render.vertex_used < 2*op->floats_per_rect) |
684 | gen4_vertex_finish(sna); |
684 | gen4_vertex_finish(sna); |
685 | 685 | ||
686 | DBG(("aligning vertex: was %d, now %d floats per vertex, %d->%d\n", |
686 | DBG(("aligning vertex: was %d, now %d floats per vertex, %d->%d\n", |
687 | sna->render_state.gen5.floats_per_vertex, |
687 | sna->render_state.gen5.floats_per_vertex, |
688 | op->floats_per_vertex, |
688 | op->floats_per_vertex, |
689 | sna->render.vertex_index, |
689 | sna->render.vertex_index, |
690 | (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex)); |
690 | (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex)); |
691 | sna->render.vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex; |
691 | sna->render.vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex; |
692 | sna->render.vertex_used = sna->render.vertex_index * op->floats_per_vertex; |
692 | sna->render.vertex_used = sna->render.vertex_index * op->floats_per_vertex; |
693 | sna->render_state.gen5.floats_per_vertex = op->floats_per_vertex; |
693 | sna->render_state.gen5.floats_per_vertex = op->floats_per_vertex; |
694 | } |
694 | } |
695 | } |
695 | } |
696 | 696 | ||
697 | static void |
697 | static void |
698 | gen5_emit_binding_table(struct sna *sna, uint16_t offset) |
698 | gen5_emit_binding_table(struct sna *sna, uint16_t offset) |
699 | { |
699 | { |
700 | if (!DBG_NO_STATE_CACHE && |
700 | if (!DBG_NO_STATE_CACHE && |
701 | sna->render_state.gen5.surface_table == offset) |
701 | sna->render_state.gen5.surface_table == offset) |
702 | return; |
702 | return; |
703 | 703 | ||
704 | sna->render_state.gen5.surface_table = offset; |
704 | sna->render_state.gen5.surface_table = offset; |
705 | 705 | ||
706 | /* Binding table pointers */ |
706 | /* Binding table pointers */ |
707 | OUT_BATCH(GEN5_3DSTATE_BINDING_TABLE_POINTERS | 4); |
707 | OUT_BATCH(GEN5_3DSTATE_BINDING_TABLE_POINTERS | 4); |
708 | OUT_BATCH(0); /* vs */ |
708 | OUT_BATCH(0); /* vs */ |
709 | OUT_BATCH(0); /* gs */ |
709 | OUT_BATCH(0); /* gs */ |
710 | OUT_BATCH(0); /* clip */ |
710 | OUT_BATCH(0); /* clip */ |
711 | OUT_BATCH(0); /* sf */ |
711 | OUT_BATCH(0); /* sf */ |
712 | /* Only the PS uses the binding table */ |
712 | /* Only the PS uses the binding table */ |
713 | OUT_BATCH(offset*4); |
713 | OUT_BATCH(offset*4); |
714 | } |
714 | } |
715 | 715 | ||
716 | static bool |
716 | static bool |
717 | gen5_emit_pipelined_pointers(struct sna *sna, |
717 | gen5_emit_pipelined_pointers(struct sna *sna, |
718 | const struct sna_composite_op *op, |
718 | const struct sna_composite_op *op, |
719 | int blend, int kernel) |
719 | int blend, int kernel) |
720 | { |
720 | { |
721 | uint16_t sp, bp; |
721 | uint16_t sp, bp; |
722 | uint32_t key; |
722 | uint32_t key; |
723 | 723 | ||
724 | DBG(("%s: has_mask=%d, src=(%d, %d), mask=(%d, %d),kernel=%d, blend=%d, ca=%d, format=%x\n", |
724 | DBG(("%s: has_mask=%d, src=(%d, %d), mask=(%d, %d),kernel=%d, blend=%d, ca=%d, format=%x\n", |
725 | __FUNCTION__, op->u.gen5.ve_id & 2, |
725 | __FUNCTION__, op->u.gen5.ve_id & 2, |
726 | op->src.filter, op->src.repeat, |
726 | op->src.filter, op->src.repeat, |
727 | op->mask.filter, op->mask.repeat, |
727 | op->mask.filter, op->mask.repeat, |
728 | kernel, blend, op->has_component_alpha, (int)op->dst.format)); |
728 | kernel, blend, op->has_component_alpha, (int)op->dst.format)); |
729 | 729 | ||
730 | sp = SAMPLER_OFFSET(op->src.filter, op->src.repeat, |
730 | sp = SAMPLER_OFFSET(op->src.filter, op->src.repeat, |
731 | op->mask.filter, op->mask.repeat, |
731 | op->mask.filter, op->mask.repeat, |
732 | kernel); |
732 | kernel); |
733 | bp = gen5_get_blend(blend, op->has_component_alpha, op->dst.format); |
733 | bp = gen5_get_blend(blend, op->has_component_alpha, op->dst.format); |
734 | 734 | ||
735 | DBG(("%s: sp=%d, bp=%d\n", __FUNCTION__, sp, bp)); |
735 | DBG(("%s: sp=%d, bp=%d\n", __FUNCTION__, sp, bp)); |
736 | key = sp | (uint32_t)bp << 16 | (op->mask.bo != NULL) << 31; |
736 | key = sp | (uint32_t)bp << 16 | (op->mask.bo != NULL) << 31; |
737 | if (key == sna->render_state.gen5.last_pipelined_pointers) |
737 | if (key == sna->render_state.gen5.last_pipelined_pointers) |
738 | return false; |
738 | return false; |
739 | 739 | ||
740 | 740 | ||
741 | OUT_BATCH(GEN5_3DSTATE_PIPELINED_POINTERS | 5); |
741 | OUT_BATCH(GEN5_3DSTATE_PIPELINED_POINTERS | 5); |
742 | OUT_BATCH(sna->render_state.gen5.vs); |
742 | OUT_BATCH(sna->render_state.gen5.vs); |
743 | OUT_BATCH(GEN5_GS_DISABLE); /* passthrough */ |
743 | OUT_BATCH(GEN5_GS_DISABLE); /* passthrough */ |
744 | OUT_BATCH(GEN5_CLIP_DISABLE); /* passthrough */ |
744 | OUT_BATCH(GEN5_CLIP_DISABLE); /* passthrough */ |
745 | OUT_BATCH(sna->render_state.gen5.sf[op->mask.bo != NULL]); |
745 | OUT_BATCH(sna->render_state.gen5.sf[op->mask.bo != NULL]); |
746 | OUT_BATCH(sna->render_state.gen5.wm + sp); |
746 | OUT_BATCH(sna->render_state.gen5.wm + sp); |
747 | OUT_BATCH(sna->render_state.gen5.cc + bp); |
747 | OUT_BATCH(sna->render_state.gen5.cc + bp); |
748 | 748 | ||
749 | sna->render_state.gen5.last_pipelined_pointers = key; |
749 | sna->render_state.gen5.last_pipelined_pointers = key; |
750 | return true; |
750 | return true; |
751 | } |
751 | } |
752 | 752 | ||
753 | static void |
753 | static void |
754 | gen5_emit_drawing_rectangle(struct sna *sna, const struct sna_composite_op *op) |
754 | gen5_emit_drawing_rectangle(struct sna *sna, const struct sna_composite_op *op) |
755 | { |
755 | { |
756 | uint32_t limit = (op->dst.height - 1) << 16 | (op->dst.width - 1); |
756 | uint32_t limit = (op->dst.height - 1) << 16 | (op->dst.width - 1); |
757 | uint32_t offset = (uint16_t)op->dst.y << 16 | (uint16_t)op->dst.x; |
757 | uint32_t offset = (uint16_t)op->dst.y << 16 | (uint16_t)op->dst.x; |
758 | 758 | ||
759 | assert(!too_large(op->dst.x, op->dst.y)); |
759 | assert(!too_large(op->dst.x, op->dst.y)); |
760 | assert(!too_large(op->dst.width, op->dst.height)); |
760 | assert(!too_large(op->dst.width, op->dst.height)); |
761 | 761 | ||
762 | if (!DBG_NO_STATE_CACHE && |
762 | if (!DBG_NO_STATE_CACHE && |
763 | sna->render_state.gen5.drawrect_limit == limit && |
763 | sna->render_state.gen5.drawrect_limit == limit && |
764 | sna->render_state.gen5.drawrect_offset == offset) |
764 | sna->render_state.gen5.drawrect_offset == offset) |
765 | return; |
765 | return; |
766 | 766 | ||
767 | sna->render_state.gen5.drawrect_offset = offset; |
767 | sna->render_state.gen5.drawrect_offset = offset; |
768 | sna->render_state.gen5.drawrect_limit = limit; |
768 | sna->render_state.gen5.drawrect_limit = limit; |
769 | 769 | ||
770 | OUT_BATCH(GEN5_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); |
770 | OUT_BATCH(GEN5_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); |
771 | OUT_BATCH(0x00000000); |
771 | OUT_BATCH(0x00000000); |
772 | OUT_BATCH(limit); |
772 | OUT_BATCH(limit); |
773 | OUT_BATCH(offset); |
773 | OUT_BATCH(offset); |
774 | } |
774 | } |
775 | 775 | ||
776 | static void |
776 | static void |
777 | gen5_emit_vertex_elements(struct sna *sna, |
777 | gen5_emit_vertex_elements(struct sna *sna, |
778 | const struct sna_composite_op *op) |
778 | const struct sna_composite_op *op) |
779 | { |
779 | { |
780 | /* |
780 | /* |
781 | * vertex data in vertex buffer |
781 | * vertex data in vertex buffer |
782 | * position: (x, y) |
782 | * position: (x, y) |
783 | * texture coordinate 0: (u0, v0) if (is_affine is true) else (u0, v0, w0) |
783 | * texture coordinate 0: (u0, v0) if (is_affine is true) else (u0, v0, w0) |
784 | * texture coordinate 1 if (has_mask is true): same as above |
784 | * texture coordinate 1 if (has_mask is true): same as above |
785 | */ |
785 | */ |
786 | struct gen5_render_state *render = &sna->render_state.gen5; |
786 | struct gen5_render_state *render = &sna->render_state.gen5; |
787 | int id = op->u.gen5.ve_id; |
787 | int id = op->u.gen5.ve_id; |
788 | bool has_mask = id >> 2; |
788 | bool has_mask = id >> 2; |
789 | uint32_t format, dw; |
789 | uint32_t format, dw; |
790 | 790 | ||
791 | if (!DBG_NO_STATE_CACHE && render->ve_id == id) |
791 | if (!DBG_NO_STATE_CACHE && render->ve_id == id) |
792 | return; |
792 | return; |
793 | 793 | ||
794 | DBG(("%s: changing %d -> %d\n", __FUNCTION__, render->ve_id, id)); |
794 | DBG(("%s: changing %d -> %d\n", __FUNCTION__, render->ve_id, id)); |
795 | render->ve_id = id; |
795 | render->ve_id = id; |
796 | 796 | ||
797 | /* The VUE layout |
797 | /* The VUE layout |
798 | * dword 0-3: pad (0.0, 0.0, 0.0. 0.0) |
798 | * dword 0-3: pad (0.0, 0.0, 0.0. 0.0) |
799 | * dword 4-7: position (x, y, 1.0, 1.0), |
799 | * dword 4-7: position (x, y, 1.0, 1.0), |
800 | * dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0) |
800 | * dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0) |
801 | * dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0) |
801 | * dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0) |
802 | * |
802 | * |
803 | * dword 4-15 are fetched from vertex buffer |
803 | * dword 4-15 are fetched from vertex buffer |
804 | */ |
804 | */ |
805 | OUT_BATCH(GEN5_3DSTATE_VERTEX_ELEMENTS | |
805 | OUT_BATCH(GEN5_3DSTATE_VERTEX_ELEMENTS | |
806 | ((2 * (has_mask ? 4 : 3)) + 1 - 2)); |
806 | ((2 * (has_mask ? 4 : 3)) + 1 - 2)); |
807 | 807 | ||
808 | OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | |
808 | OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | |
809 | (GEN5_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT) | |
809 | (GEN5_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT) | |
810 | (0 << VE0_OFFSET_SHIFT)); |
810 | (0 << VE0_OFFSET_SHIFT)); |
811 | OUT_BATCH((VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | |
811 | OUT_BATCH((VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | |
812 | (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | |
812 | (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | |
813 | (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | |
813 | (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | |
814 | (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); |
814 | (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); |
815 | 815 | ||
816 | /* x,y */ |
816 | /* x,y */ |
817 | OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
817 | OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
818 | GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | |
818 | GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | |
819 | 0 << VE0_OFFSET_SHIFT); |
819 | 0 << VE0_OFFSET_SHIFT); |
820 | OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | |
820 | OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | |
821 | VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | |
821 | VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | |
822 | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | |
822 | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | |
823 | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); |
823 | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); |
824 | 824 | ||
825 | /* u0, v0, w0 */ |
825 | /* u0, v0, w0 */ |
826 | DBG(("%s: id=%d, first channel %d floats, offset=4b\n", __FUNCTION__, |
826 | DBG(("%s: id=%d, first channel %d floats, offset=4b\n", __FUNCTION__, |
827 | id, id & 3)); |
827 | id, id & 3)); |
828 | dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; |
828 | dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; |
829 | switch (id & 3) { |
829 | switch (id & 3) { |
830 | default: |
830 | default: |
831 | assert(0); |
831 | assert(0); |
832 | case 0: |
832 | case 0: |
833 | format = GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT; |
833 | format = GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT; |
834 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
834 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
835 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
835 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
836 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
836 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
837 | break; |
837 | break; |
838 | case 1: |
838 | case 1: |
839 | format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT; |
839 | format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT; |
840 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
840 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
841 | dw |= VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; |
841 | dw |= VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; |
842 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
842 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
843 | break; |
843 | break; |
844 | case 2: |
844 | case 2: |
845 | format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT; |
845 | format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT; |
846 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
846 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
847 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
847 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
848 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
848 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
849 | break; |
849 | break; |
850 | case 3: |
850 | case 3: |
851 | format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT; |
851 | format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT; |
852 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
852 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
853 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
853 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
854 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT; |
854 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT; |
855 | break; |
855 | break; |
856 | } |
856 | } |
857 | OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
857 | OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
858 | format | 4 << VE0_OFFSET_SHIFT); |
858 | format | 4 << VE0_OFFSET_SHIFT); |
859 | OUT_BATCH(dw); |
859 | OUT_BATCH(dw); |
860 | 860 | ||
861 | /* u1, v1, w1 */ |
861 | /* u1, v1, w1 */ |
862 | if (has_mask) { |
862 | if (has_mask) { |
863 | unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float); |
863 | unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float); |
864 | DBG(("%s: id=%x, second channel %d floats, offset=%db\n", __FUNCTION__, |
864 | DBG(("%s: id=%x, second channel %d floats, offset=%db\n", __FUNCTION__, |
865 | id, id >> 2, offset)); |
865 | id, id >> 2, offset)); |
866 | dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; |
866 | dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; |
867 | switch (id >> 2) { |
867 | switch (id >> 2) { |
868 | case 1: |
868 | case 1: |
869 | format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT; |
869 | format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT; |
870 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
870 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
871 | dw |= VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; |
871 | dw |= VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; |
872 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
872 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
873 | break; |
873 | break; |
874 | default: |
874 | default: |
875 | assert(0); |
875 | assert(0); |
876 | case 2: |
876 | case 2: |
877 | format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT; |
877 | format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT; |
878 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
878 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
879 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
879 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
880 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
880 | dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; |
881 | break; |
881 | break; |
882 | case 3: |
882 | case 3: |
883 | format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT; |
883 | format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT; |
884 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
884 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; |
885 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
885 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; |
886 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT; |
886 | dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_2_SHIFT; |
887 | break; |
887 | break; |
888 | } |
888 | } |
889 | OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
889 | OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
890 | format | offset << VE0_OFFSET_SHIFT); |
890 | format | offset << VE0_OFFSET_SHIFT); |
891 | OUT_BATCH(dw); |
891 | OUT_BATCH(dw); |
892 | } |
892 | } |
893 | } |
893 | } |
894 | 894 | ||
895 | static void |
895 | static void |
896 | gen5_emit_state(struct sna *sna, |
896 | gen5_emit_state(struct sna *sna, |
897 | const struct sna_composite_op *op, |
897 | const struct sna_composite_op *op, |
898 | uint16_t offset) |
898 | uint16_t offset) |
899 | { |
899 | { |
900 | if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) { |
900 | if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) { |
901 | DBG(("%s: flushing dirty (%d, %d)\n", __FUNCTION__, |
901 | DBG(("%s: flushing dirty (%d, %d)\n", __FUNCTION__, |
902 | kgem_bo_is_dirty(op->src.bo), |
902 | kgem_bo_is_dirty(op->src.bo), |
903 | kgem_bo_is_dirty(op->mask.bo))); |
903 | kgem_bo_is_dirty(op->mask.bo))); |
904 | OUT_BATCH(MI_FLUSH); |
904 | OUT_BATCH(MI_FLUSH); |
905 | kgem_clear_dirty(&sna->kgem); |
905 | kgem_clear_dirty(&sna->kgem); |
906 | kgem_bo_mark_dirty(op->dst.bo); |
906 | kgem_bo_mark_dirty(op->dst.bo); |
907 | } |
907 | } |
908 | 908 | ||
909 | /* drawrect must be first for Ironlake BLT workaround */ |
909 | /* drawrect must be first for Ironlake BLT workaround */ |
910 | gen5_emit_drawing_rectangle(sna, op); |
910 | gen5_emit_drawing_rectangle(sna, op); |
911 | gen5_emit_binding_table(sna, offset); |
911 | gen5_emit_binding_table(sna, offset); |
912 | if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel)) |
912 | if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel)) |
913 | gen5_emit_urb(sna); |
913 | gen5_emit_urb(sna); |
914 | gen5_emit_vertex_elements(sna, op); |
914 | gen5_emit_vertex_elements(sna, op); |
915 | } |
915 | } |
916 | 916 | ||
917 | static void gen5_bind_surfaces(struct sna *sna, |
917 | static void gen5_bind_surfaces(struct sna *sna, |
918 | const struct sna_composite_op *op) |
918 | const struct sna_composite_op *op) |
919 | { |
919 | { |
920 | uint32_t *binding_table; |
920 | uint32_t *binding_table; |
921 | uint16_t offset; |
921 | uint16_t offset; |
922 | 922 | ||
923 | gen5_get_batch(sna, op); |
923 | gen5_get_batch(sna, op); |
924 | 924 | ||
925 | binding_table = gen5_composite_get_binding_table(sna, &offset); |
925 | binding_table = gen5_composite_get_binding_table(sna, &offset); |
926 | 926 | ||
927 | binding_table[0] = |
927 | binding_table[0] = |
928 | gen5_bind_bo(sna, |
928 | gen5_bind_bo(sna, |
929 | op->dst.bo, op->dst.width, op->dst.height, |
929 | op->dst.bo, op->dst.width, op->dst.height, |
930 | gen5_get_dest_format(op->dst.format), |
930 | gen5_get_dest_format(op->dst.format), |
931 | true); |
931 | true); |
932 | binding_table[1] = |
932 | binding_table[1] = |
933 | gen5_bind_bo(sna, |
933 | gen5_bind_bo(sna, |
934 | op->src.bo, op->src.width, op->src.height, |
934 | op->src.bo, op->src.width, op->src.height, |
935 | op->src.card_format, |
935 | op->src.card_format, |
936 | false); |
936 | false); |
937 | if (op->mask.bo) { |
937 | if (op->mask.bo) { |
938 | assert(op->u.gen5.ve_id >> 2); |
938 | assert(op->u.gen5.ve_id >> 2); |
939 | binding_table[2] = |
939 | binding_table[2] = |
940 | gen5_bind_bo(sna, |
940 | gen5_bind_bo(sna, |
941 | op->mask.bo, |
941 | op->mask.bo, |
942 | op->mask.width, |
942 | op->mask.width, |
943 | op->mask.height, |
943 | op->mask.height, |
944 | op->mask.card_format, |
944 | op->mask.card_format, |
945 | false); |
945 | false); |
946 | } |
946 | } |
947 | 947 | ||
948 | if (sna->kgem.surface == offset && |
948 | if (sna->kgem.surface == offset && |
949 | *(uint64_t *)(sna->kgem.batch + sna->render_state.gen5.surface_table) == *(uint64_t*)binding_table && |
949 | *(uint64_t *)(sna->kgem.batch + sna->render_state.gen5.surface_table) == *(uint64_t*)binding_table && |
950 | (op->mask.bo == NULL || |
950 | (op->mask.bo == NULL || |
951 | sna->kgem.batch[sna->render_state.gen5.surface_table+2] == binding_table[2])) { |
951 | sna->kgem.batch[sna->render_state.gen5.surface_table+2] == binding_table[2])) { |
952 | sna->kgem.surface += sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t); |
952 | sna->kgem.surface += sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t); |
953 | offset = sna->render_state.gen5.surface_table; |
953 | offset = sna->render_state.gen5.surface_table; |
954 | } |
954 | } |
955 | 955 | ||
956 | gen5_emit_state(sna, op, offset); |
956 | gen5_emit_state(sna, op, offset); |
957 | } |
957 | } |
958 | 958 | ||
959 | fastcall static void |
959 | fastcall static void |
960 | gen5_render_composite_blt(struct sna *sna, |
960 | gen5_render_composite_blt(struct sna *sna, |
961 | const struct sna_composite_op *op, |
961 | const struct sna_composite_op *op, |
962 | const struct sna_composite_rectangles *r) |
962 | const struct sna_composite_rectangles *r) |
963 | { |
963 | { |
964 | DBG(("%s: src=(%d, %d)+(%d, %d), mask=(%d, %d)+(%d, %d), dst=(%d, %d)+(%d, %d), size=(%d, %d)\n", |
964 | DBG(("%s: src=(%d, %d)+(%d, %d), mask=(%d, %d)+(%d, %d), dst=(%d, %d)+(%d, %d), size=(%d, %d)\n", |
965 | __FUNCTION__, |
965 | __FUNCTION__, |
966 | r->src.x, r->src.y, op->src.offset[0], op->src.offset[1], |
966 | r->src.x, r->src.y, op->src.offset[0], op->src.offset[1], |
967 | r->mask.x, r->mask.y, op->mask.offset[0], op->mask.offset[1], |
967 | r->mask.x, r->mask.y, op->mask.offset[0], op->mask.offset[1], |
968 | r->dst.x, r->dst.y, op->dst.x, op->dst.y, |
968 | r->dst.x, r->dst.y, op->dst.x, op->dst.y, |
969 | r->width, r->height)); |
969 | r->width, r->height)); |
970 | 970 | ||
971 | gen5_get_rectangles(sna, op, 1, gen5_bind_surfaces); |
971 | gen5_get_rectangles(sna, op, 1, gen5_bind_surfaces); |
972 | op->prim_emit(sna, op, r); |
972 | op->prim_emit(sna, op, r); |
973 | } |
973 | } |
974 | 974 | ||
975 | 975 | ||
976 | static void |
976 | static void |
977 | gen5_render_composite_done(struct sna *sna, |
977 | gen5_render_composite_done(struct sna *sna, |
978 | const struct sna_composite_op *op) |
978 | const struct sna_composite_op *op) |
979 | { |
979 | { |
980 | if (sna->render.vertex_offset) { |
980 | if (sna->render.vertex_offset) { |
981 | gen4_vertex_flush(sna); |
981 | gen4_vertex_flush(sna); |
982 | gen5_magic_ca_pass(sna,op); |
982 | gen5_magic_ca_pass(sna,op); |
983 | } |
983 | } |
984 | 984 | ||
985 | DBG(("%s()\n", __FUNCTION__)); |
985 | DBG(("%s()\n", __FUNCTION__)); |
986 | 986 | ||
987 | } |
987 | } |
988 | 988 | ||
989 | 989 | ||
990 | static bool |
990 | static bool |
991 | gen5_blit_tex(struct sna *sna, |
991 | gen5_blit_tex(struct sna *sna, |
992 | uint8_t op, |
992 | uint8_t op, bool scale, |
993 | PixmapPtr src, struct kgem_bo *src_bo, |
993 | PixmapPtr src, struct kgem_bo *src_bo, |
994 | PixmapPtr mask,struct kgem_bo *mask_bo, |
994 | PixmapPtr mask,struct kgem_bo *mask_bo, |
995 | PixmapPtr dst, struct kgem_bo *dst_bo, |
995 | PixmapPtr dst, struct kgem_bo *dst_bo, |
996 | int32_t src_x, int32_t src_y, |
996 | int32_t src_x, int32_t src_y, |
997 | int32_t msk_x, int32_t msk_y, |
997 | int32_t msk_x, int32_t msk_y, |
998 | int32_t dst_x, int32_t dst_y, |
998 | int32_t dst_x, int32_t dst_y, |
999 | int32_t width, int32_t height, |
999 | int32_t width, int32_t height, |
1000 | struct sna_composite_op *tmp) |
1000 | struct sna_composite_op *tmp) |
1001 | { |
1001 | { |
1002 | DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__, |
1002 | DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__, |
1003 | width, height, sna->kgem.mode)); |
1003 | width, height, sna->kgem.mode)); |
1004 | 1004 | ||
1005 | tmp->op = PictOpSrc; |
1005 | tmp->op = PictOpSrc; |
1006 | 1006 | ||
1007 | tmp->dst.pixmap = dst; |
1007 | tmp->dst.pixmap = dst; |
1008 | tmp->dst.bo = dst_bo; |
1008 | tmp->dst.bo = dst_bo; |
1009 | tmp->dst.width = dst->drawable.width; |
1009 | tmp->dst.width = dst->drawable.width; |
1010 | tmp->dst.height = dst->drawable.height; |
1010 | tmp->dst.height = dst->drawable.height; |
1011 | tmp->dst.format = PICT_x8r8g8b8; |
1011 | tmp->dst.format = PICT_x8r8g8b8; |
1012 | 1012 | ||
1013 | 1013 | ||
1014 | tmp->src.repeat = RepeatNone; |
1014 | tmp->src.repeat = RepeatNone; |
1015 | tmp->src.filter = PictFilterNearest; |
1015 | tmp->src.filter = PictFilterNearest; |
1016 | tmp->src.is_affine = true; |
1016 | tmp->src.is_affine = true; |
1017 | 1017 | ||
1018 | tmp->src.bo = src_bo; |
1018 | tmp->src.bo = src_bo; |
1019 | tmp->src.pict_format = PICT_x8r8g8b8; |
1019 | tmp->src.pict_format = PICT_x8r8g8b8; |
1020 | tmp->src.card_format = gen5_get_card_format(tmp->src.pict_format); |
1020 | tmp->src.card_format = gen5_get_card_format(tmp->src.pict_format); |
1021 | tmp->src.width = src->drawable.width; |
1021 | tmp->src.width = src->drawable.width; |
1022 | tmp->src.height = src->drawable.height; |
1022 | tmp->src.height = src->drawable.height; |
1023 | 1023 | ||
1024 | 1024 | ||
1025 | tmp->is_affine = tmp->src.is_affine; |
1025 | tmp->is_affine = tmp->src.is_affine; |
1026 | tmp->has_component_alpha = false; |
1026 | tmp->has_component_alpha = false; |
1027 | tmp->need_magic_ca_pass = false; |
1027 | tmp->need_magic_ca_pass = false; |
1028 | 1028 | ||
1029 | tmp->mask.is_affine = true; |
1029 | tmp->mask.is_affine = true; |
1030 | tmp->mask.repeat = SAMPLER_EXTEND_NONE; |
1030 | tmp->mask.repeat = SAMPLER_EXTEND_NONE; |
1031 | tmp->mask.filter = SAMPLER_FILTER_NEAREST; |
1031 | tmp->mask.filter = SAMPLER_FILTER_NEAREST; |
1032 | tmp->mask.bo = mask_bo; |
1032 | tmp->mask.bo = mask_bo; |
1033 | tmp->mask.pict_format = PIXMAN_a8; |
1033 | tmp->mask.pict_format = PIXMAN_a8; |
1034 | tmp->mask.card_format = gen5_get_card_format(tmp->mask.pict_format); |
1034 | tmp->mask.card_format = gen5_get_card_format(tmp->mask.pict_format); |
1035 | tmp->mask.width = mask->drawable.width; |
1035 | tmp->mask.width = mask->drawable.width; |
1036 | tmp->mask.height = mask->drawable.height; |
1036 | tmp->mask.height = mask->drawable.height; |
- | 1037 | ||
- | 1038 | if( scale ) |
|
- | 1039 | { |
|
- | 1040 | tmp->src.scale[0] = 1.f/width; |
|
- | 1041 | tmp->src.scale[1] = 1.f/height; |
|
- | 1042 | } |
|
- | 1043 | else |
|
1037 | 1044 | { |
|
1038 | tmp->src.scale[0] = 1.f/width; //src->width; |
1045 | tmp->src.scale[0] = 1.f/src->drawable.width; |
- | 1046 | tmp->src.scale[1] = 1.f/src->drawable.height; |
|
1039 | tmp->src.scale[1] = 1.f/height; //src->height; |
1047 | } |
1040 | 1048 | ||
1041 | tmp->mask.scale[0] = 1.f/mask->drawable.width; |
1049 | tmp->mask.scale[0] = 1.f/mask->drawable.width; |
1042 | tmp->mask.scale[1] = 1.f/mask->drawable.height; |
1050 | tmp->mask.scale[1] = 1.f/mask->drawable.height; |
1043 | 1051 | ||
1044 | 1052 | ||
1045 | tmp->u.gen5.wm_kernel = |
1053 | tmp->u.gen5.wm_kernel = |
1046 | gen5_choose_composite_kernel(tmp->op, |
1054 | gen5_choose_composite_kernel(tmp->op, |
1047 | tmp->mask.bo != NULL, |
1055 | tmp->mask.bo != NULL, |
1048 | tmp->has_component_alpha, |
1056 | tmp->has_component_alpha, |
1049 | tmp->is_affine); |
1057 | tmp->is_affine); |
1050 | tmp->u.gen5.ve_id = gen4_choose_composite_emitter(tmp); |
1058 | tmp->u.gen5.ve_id = gen4_choose_composite_emitter(tmp); |
1051 | 1059 | ||
1052 | tmp->blt = gen5_render_composite_blt; |
1060 | tmp->blt = gen5_render_composite_blt; |
1053 | // tmp->box = gen5_render_composite_box; |
1061 | // tmp->box = gen5_render_composite_box; |
1054 | tmp->done = gen5_render_composite_done; |
1062 | tmp->done = gen5_render_composite_done; |
1055 | 1063 | ||
1056 | if (!kgem_check_bo(&sna->kgem, |
1064 | if (!kgem_check_bo(&sna->kgem, |
1057 | tmp->dst.bo, tmp->src.bo, tmp->mask.bo, NULL)) { |
1065 | tmp->dst.bo, tmp->src.bo, tmp->mask.bo, NULL)) { |
1058 | kgem_submit(&sna->kgem); |
1066 | kgem_submit(&sna->kgem); |
1059 | } |
1067 | } |
1060 | 1068 | ||
1061 | gen5_bind_surfaces(sna, tmp); |
1069 | gen5_bind_surfaces(sna, tmp); |
1062 | gen5_align_vertex(sna, tmp); |
1070 | gen5_align_vertex(sna, tmp); |
1063 | return true; |
1071 | return true; |
1064 | 1072 | ||
1065 | } |
1073 | } |
1066 | 1074 | ||
1067 | 1075 | ||
1068 | 1076 | ||
1069 | static void |
1077 | static void |
1070 | gen5_render_flush(struct sna *sna) |
1078 | gen5_render_flush(struct sna *sna) |
1071 | { |
1079 | { |
1072 | gen4_vertex_close(sna); |
1080 | gen4_vertex_close(sna); |
1073 | 1081 | ||
1074 | assert(sna->render.vb_id == 0); |
1082 | assert(sna->render.vb_id == 0); |
1075 | assert(sna->render.vertex_offset == 0); |
1083 | assert(sna->render.vertex_offset == 0); |
1076 | } |
1084 | } |
1077 | 1085 | ||
1078 | static void |
1086 | static void |
1079 | gen5_render_context_switch(struct kgem *kgem, |
1087 | gen5_render_context_switch(struct kgem *kgem, |
1080 | int new_mode) |
1088 | int new_mode) |
1081 | { |
1089 | { |
1082 | if (!kgem->nbatch) |
1090 | if (!kgem->nbatch) |
1083 | return; |
1091 | return; |
1084 | 1092 | ||
1085 | /* WaNonPipelinedStateCommandFlush |
1093 | /* WaNonPipelinedStateCommandFlush |
1086 | * |
1094 | * |
1087 | * Ironlake has a limitation that a 3D or Media command can't |
1095 | * Ironlake has a limitation that a 3D or Media command can't |
1088 | * be the first command after a BLT, unless it's |
1096 | * be the first command after a BLT, unless it's |
1089 | * non-pipelined. |
1097 | * non-pipelined. |
1090 | * |
1098 | * |
1091 | * We do this by ensuring that the non-pipelined drawrect |
1099 | * We do this by ensuring that the non-pipelined drawrect |
1092 | * is always emitted first following a switch from BLT. |
1100 | * is always emitted first following a switch from BLT. |
1093 | */ |
1101 | */ |
1094 | if (kgem->mode == KGEM_BLT) { |
1102 | if (kgem->mode == KGEM_BLT) { |
1095 | struct sna *sna = to_sna_from_kgem(kgem); |
1103 | struct sna *sna = to_sna_from_kgem(kgem); |
1096 | DBG(("%s: forcing drawrect on next state emission\n", |
1104 | DBG(("%s: forcing drawrect on next state emission\n", |
1097 | __FUNCTION__)); |
1105 | __FUNCTION__)); |
1098 | sna->render_state.gen5.drawrect_limit = -1; |
1106 | sna->render_state.gen5.drawrect_limit = -1; |
1099 | } |
1107 | } |
1100 | 1108 | ||
1101 | if (kgem_ring_is_idle(kgem, kgem->ring)) { |
1109 | if (kgem_ring_is_idle(kgem, kgem->ring)) { |
1102 | DBG(("%s: GPU idle, flushing\n", __FUNCTION__)); |
1110 | DBG(("%s: GPU idle, flushing\n", __FUNCTION__)); |
1103 | _kgem_submit(kgem); |
1111 | _kgem_submit(kgem); |
1104 | } |
1112 | } |
1105 | } |
1113 | } |
1106 | 1114 | ||
1107 | static void |
1115 | static void |
1108 | discard_vbo(struct sna *sna) |
1116 | discard_vbo(struct sna *sna) |
1109 | { |
1117 | { |
1110 | kgem_bo_destroy(&sna->kgem, sna->render.vbo); |
1118 | kgem_bo_destroy(&sna->kgem, sna->render.vbo); |
1111 | sna->render.vbo = NULL; |
1119 | sna->render.vbo = NULL; |
1112 | sna->render.vertices = sna->render.vertex_data; |
1120 | sna->render.vertices = sna->render.vertex_data; |
1113 | sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data); |
1121 | sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data); |
1114 | sna->render.vertex_used = 0; |
1122 | sna->render.vertex_used = 0; |
1115 | sna->render.vertex_index = 0; |
1123 | sna->render.vertex_index = 0; |
1116 | } |
1124 | } |
1117 | 1125 | ||
1118 | static void |
1126 | static void |
1119 | gen5_render_retire(struct kgem *kgem) |
1127 | gen5_render_retire(struct kgem *kgem) |
1120 | { |
1128 | { |
1121 | struct sna *sna; |
1129 | struct sna *sna; |
1122 | 1130 | ||
1123 | sna = container_of(kgem, struct sna, kgem); |
1131 | sna = container_of(kgem, struct sna, kgem); |
1124 | if (kgem->nbatch == 0 && sna->render.vbo && !kgem_bo_is_busy(sna->render.vbo)) { |
1132 | if (kgem->nbatch == 0 && sna->render.vbo && !kgem_bo_is_busy(sna->render.vbo)) { |
1125 | DBG(("%s: resetting idle vbo\n", __FUNCTION__)); |
1133 | DBG(("%s: resetting idle vbo\n", __FUNCTION__)); |
1126 | sna->render.vertex_used = 0; |
1134 | sna->render.vertex_used = 0; |
1127 | sna->render.vertex_index = 0; |
1135 | sna->render.vertex_index = 0; |
1128 | } |
1136 | } |
1129 | } |
1137 | } |
1130 | 1138 | ||
1131 | static void |
1139 | static void |
1132 | gen5_render_expire(struct kgem *kgem) |
1140 | gen5_render_expire(struct kgem *kgem) |
1133 | { |
1141 | { |
1134 | struct sna *sna; |
1142 | struct sna *sna; |
1135 | 1143 | ||
1136 | sna = container_of(kgem, struct sna, kgem); |
1144 | sna = container_of(kgem, struct sna, kgem); |
1137 | if (sna->render.vbo && !sna->render.vertex_used) { |
1145 | if (sna->render.vbo && !sna->render.vertex_used) { |
1138 | DBG(("%s: discarding vbo\n", __FUNCTION__)); |
1146 | DBG(("%s: discarding vbo\n", __FUNCTION__)); |
1139 | discard_vbo(sna); |
1147 | discard_vbo(sna); |
1140 | } |
1148 | } |
1141 | } |
1149 | } |
1142 | 1150 | ||
1143 | static void gen5_render_reset(struct sna *sna) |
1151 | static void gen5_render_reset(struct sna *sna) |
1144 | { |
1152 | { |
1145 | sna->render_state.gen5.needs_invariant = true; |
1153 | sna->render_state.gen5.needs_invariant = true; |
1146 | sna->render_state.gen5.ve_id = -1; |
1154 | sna->render_state.gen5.ve_id = -1; |
1147 | sna->render_state.gen5.last_primitive = -1; |
1155 | sna->render_state.gen5.last_primitive = -1; |
1148 | sna->render_state.gen5.last_pipelined_pointers = 0; |
1156 | sna->render_state.gen5.last_pipelined_pointers = 0; |
1149 | 1157 | ||
1150 | sna->render_state.gen5.drawrect_offset = -1; |
1158 | sna->render_state.gen5.drawrect_offset = -1; |
1151 | sna->render_state.gen5.drawrect_limit = -1; |
1159 | sna->render_state.gen5.drawrect_limit = -1; |
1152 | sna->render_state.gen5.surface_table = -1; |
1160 | sna->render_state.gen5.surface_table = -1; |
1153 | 1161 | ||
1154 | if (sna->render.vbo && |
1162 | if (sna->render.vbo && |
1155 | !kgem_bo_is_mappable(&sna->kgem, sna->render.vbo)) { |
1163 | !kgem_bo_is_mappable(&sna->kgem, sna->render.vbo)) { |
1156 | DBG(("%s: discarding unmappable vbo\n", __FUNCTION__)); |
1164 | DBG(("%s: discarding unmappable vbo\n", __FUNCTION__)); |
1157 | discard_vbo(sna); |
1165 | discard_vbo(sna); |
1158 | } |
1166 | } |
1159 | 1167 | ||
1160 | sna->render.vertex_offset = 0; |
1168 | sna->render.vertex_offset = 0; |
1161 | sna->render.nvertex_reloc = 0; |
1169 | sna->render.nvertex_reloc = 0; |
1162 | sna->render.vb_id = 0; |
1170 | sna->render.vb_id = 0; |
1163 | } |
1171 | } |
1164 | 1172 | ||
1165 | static void gen5_render_fini(struct sna *sna) |
1173 | static void gen5_render_fini(struct sna *sna) |
1166 | { |
1174 | { |
1167 | kgem_bo_destroy(&sna->kgem, sna->render_state.gen5.general_bo); |
1175 | kgem_bo_destroy(&sna->kgem, sna->render_state.gen5.general_bo); |
1168 | } |
1176 | } |
1169 | 1177 | ||
1170 | static uint32_t gen5_create_vs_unit_state(struct sna_static_stream *stream) |
1178 | static uint32_t gen5_create_vs_unit_state(struct sna_static_stream *stream) |
1171 | { |
1179 | { |
1172 | struct gen5_vs_unit_state *vs = sna_static_stream_map(stream, sizeof(*vs), 32); |
1180 | struct gen5_vs_unit_state *vs = sna_static_stream_map(stream, sizeof(*vs), 32); |
1173 | 1181 | ||
1174 | /* Set up the vertex shader to be disabled (passthrough) */ |
1182 | /* Set up the vertex shader to be disabled (passthrough) */ |
1175 | vs->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; |
1183 | vs->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; |
1176 | vs->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1; |
1184 | vs->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1; |
1177 | vs->vs6.vs_enable = 0; |
1185 | vs->vs6.vs_enable = 0; |
1178 | vs->vs6.vert_cache_disable = 1; |
1186 | vs->vs6.vert_cache_disable = 1; |
1179 | 1187 | ||
1180 | return sna_static_stream_offsetof(stream, vs); |
1188 | return sna_static_stream_offsetof(stream, vs); |
1181 | } |
1189 | } |
1182 | 1190 | ||
1183 | static uint32_t gen5_create_sf_state(struct sna_static_stream *stream, |
1191 | static uint32_t gen5_create_sf_state(struct sna_static_stream *stream, |
1184 | uint32_t kernel) |
1192 | uint32_t kernel) |
1185 | { |
1193 | { |
1186 | struct gen5_sf_unit_state *sf_state; |
1194 | struct gen5_sf_unit_state *sf_state; |
1187 | 1195 | ||
1188 | sf_state = sna_static_stream_map(stream, sizeof(*sf_state), 32); |
1196 | sf_state = sna_static_stream_map(stream, sizeof(*sf_state), 32); |
1189 | 1197 | ||
1190 | sf_state->thread0.grf_reg_count = GEN5_GRF_BLOCKS(SF_KERNEL_NUM_GRF); |
1198 | sf_state->thread0.grf_reg_count = GEN5_GRF_BLOCKS(SF_KERNEL_NUM_GRF); |
1191 | sf_state->thread0.kernel_start_pointer = kernel >> 6; |
1199 | sf_state->thread0.kernel_start_pointer = kernel >> 6; |
1192 | 1200 | ||
1193 | sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */ |
1201 | sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */ |
1194 | sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */ |
1202 | sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */ |
1195 | sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */ |
1203 | sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */ |
1196 | /* don't smash vertex header, read start from dw8 */ |
1204 | /* don't smash vertex header, read start from dw8 */ |
1197 | sf_state->thread3.urb_entry_read_offset = 1; |
1205 | sf_state->thread3.urb_entry_read_offset = 1; |
1198 | sf_state->thread3.dispatch_grf_start_reg = 3; |
1206 | sf_state->thread3.dispatch_grf_start_reg = 3; |
1199 | sf_state->thread4.max_threads = SF_MAX_THREADS - 1; |
1207 | sf_state->thread4.max_threads = SF_MAX_THREADS - 1; |
1200 | sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1; |
1208 | sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1; |
1201 | sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES; |
1209 | sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES; |
1202 | sf_state->sf5.viewport_transform = false; /* skip viewport */ |
1210 | sf_state->sf5.viewport_transform = false; /* skip viewport */ |
1203 | sf_state->sf6.cull_mode = GEN5_CULLMODE_NONE; |
1211 | sf_state->sf6.cull_mode = GEN5_CULLMODE_NONE; |
1204 | sf_state->sf6.scissor = 0; |
1212 | sf_state->sf6.scissor = 0; |
1205 | sf_state->sf7.trifan_pv = 2; |
1213 | sf_state->sf7.trifan_pv = 2; |
1206 | sf_state->sf6.dest_org_vbias = 0x8; |
1214 | sf_state->sf6.dest_org_vbias = 0x8; |
1207 | sf_state->sf6.dest_org_hbias = 0x8; |
1215 | sf_state->sf6.dest_org_hbias = 0x8; |
1208 | 1216 | ||
1209 | return sna_static_stream_offsetof(stream, sf_state); |
1217 | return sna_static_stream_offsetof(stream, sf_state); |
1210 | } |
1218 | } |
1211 | 1219 | ||
1212 | static uint32_t gen5_create_sampler_state(struct sna_static_stream *stream, |
1220 | static uint32_t gen5_create_sampler_state(struct sna_static_stream *stream, |
1213 | sampler_filter_t src_filter, |
1221 | sampler_filter_t src_filter, |
1214 | sampler_extend_t src_extend, |
1222 | sampler_extend_t src_extend, |
1215 | sampler_filter_t mask_filter, |
1223 | sampler_filter_t mask_filter, |
1216 | sampler_extend_t mask_extend) |
1224 | sampler_extend_t mask_extend) |
1217 | { |
1225 | { |
1218 | struct gen5_sampler_state *sampler_state; |
1226 | struct gen5_sampler_state *sampler_state; |
1219 | 1227 | ||
1220 | sampler_state = sna_static_stream_map(stream, |
1228 | sampler_state = sna_static_stream_map(stream, |
1221 | sizeof(struct gen5_sampler_state) * 2, |
1229 | sizeof(struct gen5_sampler_state) * 2, |
1222 | 32); |
1230 | 32); |
1223 | sampler_state_init(&sampler_state[0], src_filter, src_extend); |
1231 | sampler_state_init(&sampler_state[0], src_filter, src_extend); |
1224 | sampler_state_init(&sampler_state[1], mask_filter, mask_extend); |
1232 | sampler_state_init(&sampler_state[1], mask_filter, mask_extend); |
1225 | 1233 | ||
1226 | return sna_static_stream_offsetof(stream, sampler_state); |
1234 | return sna_static_stream_offsetof(stream, sampler_state); |
1227 | } |
1235 | } |
1228 | 1236 | ||
1229 | static void gen5_init_wm_state(struct gen5_wm_unit_state *state, |
1237 | static void gen5_init_wm_state(struct gen5_wm_unit_state *state, |
1230 | bool has_mask, |
1238 | bool has_mask, |
1231 | uint32_t kernel, |
1239 | uint32_t kernel, |
1232 | uint32_t sampler) |
1240 | uint32_t sampler) |
1233 | { |
1241 | { |
1234 | state->thread0.grf_reg_count = GEN5_GRF_BLOCKS(PS_KERNEL_NUM_GRF); |
1242 | state->thread0.grf_reg_count = GEN5_GRF_BLOCKS(PS_KERNEL_NUM_GRF); |
1235 | state->thread0.kernel_start_pointer = kernel >> 6; |
1243 | state->thread0.kernel_start_pointer = kernel >> 6; |
1236 | 1244 | ||
1237 | state->thread1.single_program_flow = 0; |
1245 | state->thread1.single_program_flow = 0; |
1238 | 1246 | ||
1239 | /* scratch space is not used in our kernel */ |
1247 | /* scratch space is not used in our kernel */ |
1240 | state->thread2.scratch_space_base_pointer = 0; |
1248 | state->thread2.scratch_space_base_pointer = 0; |
1241 | state->thread2.per_thread_scratch_space = 0; |
1249 | state->thread2.per_thread_scratch_space = 0; |
1242 | 1250 | ||
1243 | state->thread3.const_urb_entry_read_length = 0; |
1251 | state->thread3.const_urb_entry_read_length = 0; |
1244 | state->thread3.const_urb_entry_read_offset = 0; |
1252 | state->thread3.const_urb_entry_read_offset = 0; |
1245 | 1253 | ||
1246 | state->thread3.urb_entry_read_offset = 0; |
1254 | state->thread3.urb_entry_read_offset = 0; |
1247 | /* wm kernel use urb from 3, see wm_program in compiler module */ |
1255 | /* wm kernel use urb from 3, see wm_program in compiler module */ |
1248 | state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */ |
1256 | state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */ |
1249 | 1257 | ||
1250 | state->wm4.sampler_count = 0; /* hardware requirement */ |
1258 | state->wm4.sampler_count = 0; /* hardware requirement */ |
1251 | 1259 | ||
1252 | state->wm4.sampler_state_pointer = sampler >> 5; |
1260 | state->wm4.sampler_state_pointer = sampler >> 5; |
1253 | state->wm5.max_threads = PS_MAX_THREADS - 1; |
1261 | state->wm5.max_threads = PS_MAX_THREADS - 1; |
1254 | state->wm5.transposed_urb_read = 0; |
1262 | state->wm5.transposed_urb_read = 0; |
1255 | state->wm5.thread_dispatch_enable = 1; |
1263 | state->wm5.thread_dispatch_enable = 1; |
1256 | /* just use 16-pixel dispatch (4 subspans), don't need to change kernel |
1264 | /* just use 16-pixel dispatch (4 subspans), don't need to change kernel |
1257 | * start point |
1265 | * start point |
1258 | */ |
1266 | */ |
1259 | state->wm5.enable_16_pix = 1; |
1267 | state->wm5.enable_16_pix = 1; |
1260 | state->wm5.enable_8_pix = 0; |
1268 | state->wm5.enable_8_pix = 0; |
1261 | state->wm5.early_depth_test = 1; |
1269 | state->wm5.early_depth_test = 1; |
1262 | 1270 | ||
1263 | /* Each pair of attributes (src/mask coords) is two URB entries */ |
1271 | /* Each pair of attributes (src/mask coords) is two URB entries */ |
1264 | if (has_mask) { |
1272 | if (has_mask) { |
1265 | state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */ |
1273 | state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */ |
1266 | state->thread3.urb_entry_read_length = 4; |
1274 | state->thread3.urb_entry_read_length = 4; |
1267 | } else { |
1275 | } else { |
1268 | state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */ |
1276 | state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */ |
1269 | state->thread3.urb_entry_read_length = 2; |
1277 | state->thread3.urb_entry_read_length = 2; |
1270 | } |
1278 | } |
1271 | 1279 | ||
1272 | /* binding table entry count is only used for prefetching, |
1280 | /* binding table entry count is only used for prefetching, |
1273 | * and it has to be set 0 for Ironlake |
1281 | * and it has to be set 0 for Ironlake |
1274 | */ |
1282 | */ |
1275 | state->thread1.binding_table_entry_count = 0; |
1283 | state->thread1.binding_table_entry_count = 0; |
1276 | } |
1284 | } |
1277 | 1285 | ||
1278 | static uint32_t gen5_create_cc_unit_state(struct sna_static_stream *stream) |
1286 | static uint32_t gen5_create_cc_unit_state(struct sna_static_stream *stream) |
1279 | { |
1287 | { |
1280 | uint8_t *ptr, *base; |
1288 | uint8_t *ptr, *base; |
1281 | int i, j; |
1289 | int i, j; |
1282 | 1290 | ||
1283 | base = ptr = |
1291 | base = ptr = |
1284 | sna_static_stream_map(stream, |
1292 | sna_static_stream_map(stream, |
1285 | GEN5_BLENDFACTOR_COUNT*GEN5_BLENDFACTOR_COUNT*64, |
1293 | GEN5_BLENDFACTOR_COUNT*GEN5_BLENDFACTOR_COUNT*64, |
1286 | 64); |
1294 | 64); |
1287 | 1295 | ||
1288 | for (i = 0; i < GEN5_BLENDFACTOR_COUNT; i++) { |
1296 | for (i = 0; i < GEN5_BLENDFACTOR_COUNT; i++) { |
1289 | for (j = 0; j < GEN5_BLENDFACTOR_COUNT; j++) { |
1297 | for (j = 0; j < GEN5_BLENDFACTOR_COUNT; j++) { |
1290 | struct gen5_cc_unit_state *state = |
1298 | struct gen5_cc_unit_state *state = |
1291 | (struct gen5_cc_unit_state *)ptr; |
1299 | (struct gen5_cc_unit_state *)ptr; |
1292 | 1300 | ||
1293 | state->cc3.blend_enable = |
1301 | state->cc3.blend_enable = |
1294 | !(j == GEN5_BLENDFACTOR_ZERO && i == GEN5_BLENDFACTOR_ONE); |
1302 | !(j == GEN5_BLENDFACTOR_ZERO && i == GEN5_BLENDFACTOR_ONE); |
1295 | 1303 | ||
1296 | state->cc5.logicop_func = 0xc; /* COPY */ |
1304 | state->cc5.logicop_func = 0xc; /* COPY */ |
1297 | state->cc5.ia_blend_function = GEN5_BLENDFUNCTION_ADD; |
1305 | state->cc5.ia_blend_function = GEN5_BLENDFUNCTION_ADD; |
1298 | 1306 | ||
1299 | /* Fill in alpha blend factors same as color, for the future. */ |
1307 | /* Fill in alpha blend factors same as color, for the future. */ |
1300 | state->cc5.ia_src_blend_factor = i; |
1308 | state->cc5.ia_src_blend_factor = i; |
1301 | state->cc5.ia_dest_blend_factor = j; |
1309 | state->cc5.ia_dest_blend_factor = j; |
1302 | 1310 | ||
1303 | state->cc6.blend_function = GEN5_BLENDFUNCTION_ADD; |
1311 | state->cc6.blend_function = GEN5_BLENDFUNCTION_ADD; |
1304 | state->cc6.clamp_post_alpha_blend = 1; |
1312 | state->cc6.clamp_post_alpha_blend = 1; |
1305 | state->cc6.clamp_pre_alpha_blend = 1; |
1313 | state->cc6.clamp_pre_alpha_blend = 1; |
1306 | state->cc6.src_blend_factor = i; |
1314 | state->cc6.src_blend_factor = i; |
1307 | state->cc6.dest_blend_factor = j; |
1315 | state->cc6.dest_blend_factor = j; |
1308 | 1316 | ||
1309 | ptr += 64; |
1317 | ptr += 64; |
1310 | } |
1318 | } |
1311 | } |
1319 | } |
1312 | 1320 | ||
1313 | return sna_static_stream_offsetof(stream, base); |
1321 | return sna_static_stream_offsetof(stream, base); |
1314 | } |
1322 | } |
1315 | 1323 | ||
1316 | static bool gen5_render_setup(struct sna *sna) |
1324 | static bool gen5_render_setup(struct sna *sna) |
1317 | { |
1325 | { |
1318 | struct gen5_render_state *state = &sna->render_state.gen5; |
1326 | struct gen5_render_state *state = &sna->render_state.gen5; |
1319 | struct sna_static_stream general; |
1327 | struct sna_static_stream general; |
1320 | struct gen5_wm_unit_state_padded *wm_state; |
1328 | struct gen5_wm_unit_state_padded *wm_state; |
1321 | uint32_t sf[2], wm[KERNEL_COUNT]; |
1329 | uint32_t sf[2], wm[KERNEL_COUNT]; |
1322 | int i, j, k, l, m; |
1330 | int i, j, k, l, m; |
1323 | 1331 | ||
1324 | sna_static_stream_init(&general); |
1332 | sna_static_stream_init(&general); |
1325 | 1333 | ||
1326 | /* Zero pad the start. If you see an offset of 0x0 in the batchbuffer |
1334 | /* Zero pad the start. If you see an offset of 0x0 in the batchbuffer |
1327 | * dumps, you know it points to zero. |
1335 | * dumps, you know it points to zero. |
1328 | */ |
1336 | */ |
1329 | null_create(&general); |
1337 | null_create(&general); |
1330 | 1338 | ||
1331 | /* Set up the two SF states (one for blending with a mask, one without) */ |
1339 | /* Set up the two SF states (one for blending with a mask, one without) */ |
1332 | sf[0] = sna_static_stream_compile_sf(sna, &general, brw_sf_kernel__nomask); |
1340 | sf[0] = sna_static_stream_compile_sf(sna, &general, brw_sf_kernel__nomask); |
1333 | sf[1] = sna_static_stream_compile_sf(sna, &general, brw_sf_kernel__mask); |
1341 | sf[1] = sna_static_stream_compile_sf(sna, &general, brw_sf_kernel__mask); |
1334 | 1342 | ||
1335 | for (m = 0; m < KERNEL_COUNT; m++) { |
1343 | for (m = 0; m < KERNEL_COUNT; m++) { |
1336 | if (wm_kernels[m].size) { |
1344 | if (wm_kernels[m].size) { |
1337 | wm[m] = sna_static_stream_add(&general, |
1345 | wm[m] = sna_static_stream_add(&general, |
1338 | wm_kernels[m].data, |
1346 | wm_kernels[m].data, |
1339 | wm_kernels[m].size, |
1347 | wm_kernels[m].size, |
1340 | 64); |
1348 | 64); |
1341 | } else { |
1349 | } else { |
1342 | wm[m] = sna_static_stream_compile_wm(sna, &general, |
1350 | wm[m] = sna_static_stream_compile_wm(sna, &general, |
1343 | wm_kernels[m].data, |
1351 | wm_kernels[m].data, |
1344 | 16); |
1352 | 16); |
1345 | } |
1353 | } |
1346 | assert(wm[m]); |
1354 | assert(wm[m]); |
1347 | } |
1355 | } |
1348 | 1356 | ||
1349 | state->vs = gen5_create_vs_unit_state(&general); |
1357 | state->vs = gen5_create_vs_unit_state(&general); |
1350 | 1358 | ||
1351 | state->sf[0] = gen5_create_sf_state(&general, sf[0]); |
1359 | state->sf[0] = gen5_create_sf_state(&general, sf[0]); |
1352 | state->sf[1] = gen5_create_sf_state(&general, sf[1]); |
1360 | state->sf[1] = gen5_create_sf_state(&general, sf[1]); |
1353 | 1361 | ||
1354 | 1362 | ||
1355 | /* Set up the WM states: each filter/extend type for source and mask, per |
1363 | /* Set up the WM states: each filter/extend type for source and mask, per |
1356 | * kernel. |
1364 | * kernel. |
1357 | */ |
1365 | */ |
1358 | wm_state = sna_static_stream_map(&general, |
1366 | wm_state = sna_static_stream_map(&general, |
1359 | sizeof(*wm_state) * KERNEL_COUNT * |
1367 | sizeof(*wm_state) * KERNEL_COUNT * |
1360 | FILTER_COUNT * EXTEND_COUNT * |
1368 | FILTER_COUNT * EXTEND_COUNT * |
1361 | FILTER_COUNT * EXTEND_COUNT, |
1369 | FILTER_COUNT * EXTEND_COUNT, |
1362 | 64); |
1370 | 64); |
1363 | state->wm = sna_static_stream_offsetof(&general, wm_state); |
1371 | state->wm = sna_static_stream_offsetof(&general, wm_state); |
1364 | for (i = 0; i < FILTER_COUNT; i++) { |
1372 | for (i = 0; i < FILTER_COUNT; i++) { |
1365 | for (j = 0; j < EXTEND_COUNT; j++) { |
1373 | for (j = 0; j < EXTEND_COUNT; j++) { |
1366 | for (k = 0; k < FILTER_COUNT; k++) { |
1374 | for (k = 0; k < FILTER_COUNT; k++) { |
1367 | for (l = 0; l < EXTEND_COUNT; l++) { |
1375 | for (l = 0; l < EXTEND_COUNT; l++) { |
1368 | uint32_t sampler_state; |
1376 | uint32_t sampler_state; |
1369 | 1377 | ||
1370 | sampler_state = |
1378 | sampler_state = |
1371 | gen5_create_sampler_state(&general, |
1379 | gen5_create_sampler_state(&general, |
1372 | i, j, |
1380 | i, j, |
1373 | k, l); |
1381 | k, l); |
1374 | 1382 | ||
1375 | for (m = 0; m < KERNEL_COUNT; m++) { |
1383 | for (m = 0; m < KERNEL_COUNT; m++) { |
1376 | gen5_init_wm_state(&wm_state->state, |
1384 | gen5_init_wm_state(&wm_state->state, |
1377 | wm_kernels[m].has_mask, |
1385 | wm_kernels[m].has_mask, |
1378 | wm[m], sampler_state); |
1386 | wm[m], sampler_state); |
1379 | wm_state++; |
1387 | wm_state++; |
1380 | } |
1388 | } |
1381 | } |
1389 | } |
1382 | } |
1390 | } |
1383 | } |
1391 | } |
1384 | } |
1392 | } |
1385 | 1393 | ||
1386 | state->cc = gen5_create_cc_unit_state(&general); |
1394 | state->cc = gen5_create_cc_unit_state(&general); |
1387 | 1395 | ||
1388 | state->general_bo = sna_static_stream_fini(sna, &general); |
1396 | state->general_bo = sna_static_stream_fini(sna, &general); |
1389 | return state->general_bo != NULL; |
1397 | return state->general_bo != NULL; |
1390 | } |
1398 | } |
1391 | 1399 | ||
1392 | bool gen5_render_init(struct sna *sna) |
1400 | bool gen5_render_init(struct sna *sna) |
1393 | { |
1401 | { |
1394 | if (!gen5_render_setup(sna)) |
1402 | if (!gen5_render_setup(sna)) |
1395 | return false; |
1403 | return false; |
1396 | 1404 | ||
1397 | sna->kgem.context_switch = gen5_render_context_switch; |
1405 | sna->kgem.context_switch = gen5_render_context_switch; |
1398 | sna->kgem.retire = gen5_render_retire; |
1406 | sna->kgem.retire = gen5_render_retire; |
1399 | sna->kgem.expire = gen5_render_expire; |
1407 | sna->kgem.expire = gen5_render_expire; |
1400 | 1408 | ||
1401 | sna->render.blit_tex = gen5_blit_tex; |
1409 | sna->render.blit_tex = gen5_blit_tex; |
1402 | 1410 | ||
1403 | sna->render.flush = gen5_render_flush; |
1411 | sna->render.flush = gen5_render_flush; |
1404 | sna->render.reset = gen5_render_reset; |
1412 | sna->render.reset = gen5_render_reset; |
1405 | sna->render.fini = gen5_render_fini; |
1413 | sna->render.fini = gen5_render_fini; |
1406 | 1414 | ||
1407 | sna->render.max_3d_size = MAX_3D_SIZE; |
1415 | sna->render.max_3d_size = MAX_3D_SIZE; |
1408 | sna->render.max_3d_pitch = 1 << 18; |
1416 | sna->render.max_3d_pitch = 1 << 18; |
1409 | sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT; |
1417 | sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT; |
1410 | 1418 | ||
1411 | return true; |
1419 | return true; |
1412 | }><>>>>>>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>><>=>>>><>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><> |
1420 | }><>>>>>>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>><>=>>>><>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><> |