Subversion Repositories Kolibri OS

Rev

Rev 5866 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 5866 Rev 8038
Line 1... Line 1...
1 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 1 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 
;;                                                              ;;
 2 
;;                                                              ;;
3 
;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;
 3 
;; Copyright (C) KolibriOS team 2004-2020. All rights reserved. ;;
4 
;; Distributed under terms of the GNU General Public License    ;;
 4 
;; Distributed under terms of the GNU General Public License    ;;
5 
;;                                                              ;;
 5 
;;                                                              ;;
6 
;;  PCMCIA aka cardbus driver for KolibriOS                     ;;
 6 
;;  PCMCIA aka cardbus driver for KolibriOS                     ;;
7 
;;  Written by hidnplayr@gmail.com                              ;;
 7 
;;  Written by hidnplayr@gmail.com                              ;;
8 
;;                                                              ;;
 8 
;;                                                              ;;
Line 29... Line 29...
29 
 
 29 
 
30 
        CURRENT_API             = 0x0200
 30 
        CURRENT_API             = 0x0200
31 
        COMPATIBLE_API          = 0x0100
 31 
        COMPATIBLE_API          = 0x0100
Line -... Line 32...
- 
 
 32 
        API_VERSION             = (COMPATIBLE_API shl 16) + CURRENT_API
- 
 
 33 
 
32 
        API_VERSION             = (COMPATIBLE_API shl 16) + CURRENT_API
 34 
        CARDBUS_IO_BASE         = 0x1400
Line 33... Line 35...
33 
 
 35 
        CARDBUS_IO_SIZE         = 0x100
34 
        CARDBUS_IO              = 0xFC00
 36 
        CARDBUS_IRQ             = 0x0A
Line 35... Line 37...
35 
 
 37 
 
Line 174... Line 176...
174 
 
 176 
 
175 
        invoke  PciRead32, [bus], [devfn], PCI_header02.pci_bus_nr      ; PCcard latency settings + Card bus number, PCI bus number
 177 
        invoke  PciRead32, [bus], [devfn], PCI_header02.pci_bus_nr      ; PCcard latency settings + Card bus number, PCI bus number
176 
        and     eax, 0xff000000                                         ; Keep original latency setting, clear the rest
 178 
        and     eax, 0xff000000                                         ; Keep original latency setting, clear the rest
177 
        mov     al, byte[bus]
 179 
        mov     al, byte[bus]
178 
        mov     ah, byte[card_bus]
 180 
        mov     ah, byte[card_bus]
179 
        mov     ebx, [card_bus]
 181 
        mov     ebx, [card_bus]         ; sub bus nr???
180 
        shl     ebx, 16
 182 
        shl     ebx, 16
181 
        or      eax, ebx
 183 
        or      eax, ebx
182 
        DEBUGF  1, "Latency, bus,.. 0x%x\n", eax
 184 
        DEBUGF  1, "Latency, bus,.. 0x%x\n", eax
Line 202... Line 204...
202 
 
 204 
 
203 
        mov     eax, 0x7f000000
 205 
        mov     eax, 0x7f000000
204 
        push    eax
 206 
        push    eax
205 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.base_addr, eax ; base is 4 Kbyte aligned
 207 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.base_addr, eax ; base is 4 Kbyte aligned
206 
        pop     ebx
 208 
        pop     ebx
207 
        invoke  MapIoMem, ebx, 4096, 0x1b
 209 
        invoke  MapIoMem, ebx, 4096, PG_SW+PG_NOCACHE
Line 208... Line 210...
208 
        mov     ecx, eax
 210 
        mov     ecx, eax
Line 209... Line 211...
209 
 
 211 
 
Line 224... Line 226...
224 
  .CardbusInserted:
 226 
  .CardbusInserted:
225 
        DEBUGF  1, "Card inserted\n"
 227 
        DEBUGF  1, "Card inserted\n"
226 
        ;mov     word[ecx + 0x802], 0x00F9       ; Assert reset, output enable, vcc=vpp=3.3V
 228 
        ;mov     word[ecx + 0x802], 0x00F9       ; Assert reset, output enable, vcc=vpp=3.3V
227 
        mov     dword[ecx + 0x10], 0x33         ; Request 3.3V for Vcc and Vpp (Control register)
 229 
        mov     dword[ecx + 0x10], 0x33         ; Request 3.3V for Vcc and Vpp (Control register)
228 
        ;push    ecx
 230 
        ;push    ecx
229 
        ;mov     esi, 10
 231 
        ;mov     esi, 1
230 
        ;invoke  Sleep
 232 
        ;invoke  Sleep
231 
        ;pop     ecx
 233 
        ;pop     ecx
232 
        ;mov     byte[ecx + 0x803], 0x40         ; stop reset
 234 
        ;mov     byte[ecx + 0x803], 0x40         ; stop reset
233 
        mov     dword[ecx + 0xC], 0x4000        ; force Card CV test (Force register)   ;;; WHY???
 235 
        mov     dword[ecx + 0xC], 0x4000        ; force Card CV test (Force register)   ;;; WHY???
234 
        DEBUGF  1, "Resetting card\n"
 236 
        DEBUGF  1, "Resetting card\n"
Line 243... Line 245...
243 
; Write MemBase-Limit 0 and 1, then IOBase-Limit 0 and 1
 245 
; Write MemBase-Limit 0 and 1, then IOBase-Limit 0 and 1
244 
; mem0 space limit = base => size is 4 kilobytes
 246 
; mem0 space limit = base => size is 4 kilobytes
245 
; set to 0 the second interval (mem1 and IO1)
 247 
; set to 0 the second interval (mem1 and IO1)
246 
; IO0: size is 256 bytes
 248 
; IO0: size is 256 bytes
Line -... Line 249...
- 
 
 249 
 
247 
 
 250 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.mbar_0, 0x7EFFF000
248 
irp     regvalue,   0x7efff000, 0x7effffff, 0x7effe000, 0x7effe000, CARDBUS_IO, CARDBUS_IO + 0xFF, 0, 0
 - 
 
249 
{
 - 
 
250 
common
 251 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.mlimit_0, 0x7EFFF000
251 
        reg = 0x1C
 - 
 
252 
forward
 252 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.mbar_1, 0
- 
 
 253 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.mlimit_1, 0
- 
 
 254 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.iobar_0, CARDBUS_IO
253 
        invoke  PciWrite32, [bus], [devfn], reg, regvalue
 255 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.iolimit_0, CARDBUS_IO + 0xFC
254 
        DEBUGF  1, "Writing 0x%x to 0x%x\n", regvalue, reg
 256 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.iobar_1, 0
255 
        reg = reg + 4
 - 
 
256 
}
 - 
 
257 
 
 257 
        invoke  PciWrite32, [bus], [devfn], PCI_header02.iolimit_1, 0
258 
        invoke  PciWrite8, [bus], [devfn], PCI_header02.interrupt_line, 0xc    ; IRQ line
 - 
 
259 
 
 258 
        invoke  PciWrite8, [bus], [devfn], PCI_header02.interrupt_line, CARDBUS_IRQ     ; IRQ line
260 
        invoke  PciRead16, [bus], [devfn], PCI_header02.bridge_ctrl                 ; Bridge control
 259 
        invoke  PciRead16, [bus], [devfn], PCI_header02.bridge_ctrl                     ; Bridge control
261 
        or      ax, 0x0700                                      ; Enable write posting, both memory windows prefetchable
 260 
        or      ax, 0x0700                                      ; Enable write posting, both memory windows prefetchable
262 
        invoke  PciWrite16, [bus], [devfn], PCI_header02.bridge_ctrl, eax
 261 
        invoke  PciWrite16, [bus], [devfn], PCI_header02.bridge_ctrl, eax
Line 274... Line 273...
274 
 
 273 
 
275 
 
 274 
 
276 
        mov     ecx, 100
 275 
        mov     ecx, 100
277 
  .waitactive:
 276 
  .waitactive:
278 
        push    ecx
 277 
        push    ecx
279 
        invoke  PciRead32, [card_bus], 0, PCI_header02.vendor_id         ; Check if the card is awake yet
 278 
        invoke  PciRead32, [card_bus], 0, PCI_header.vendor_id         ; Check if the card is awake yet
280 
        inc     eax
 279 
        inc     eax
281 
        jnz     .got_it
 280 
        jnz     .got_it
282 
        mov     esi, 2
 281 
        mov     esi, 2