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Line 169... Line 169...
169
#define I915_BOX_FLIP          0x2
169
#define I915_BOX_FLIP          0x2
170
#define I915_BOX_WAIT          0x4
170
#define I915_BOX_WAIT          0x4
171
#define I915_BOX_TEXTURE_LOAD  0x8
171
#define I915_BOX_TEXTURE_LOAD  0x8
172
#define I915_BOX_LOST_CONTEXT  0x10
172
#define I915_BOX_LOST_CONTEXT  0x10
Line -... Line 173...
-
 
173
 
173
 
174
/*
-
 
175
 * i915 specific ioctls.
174
/* I915 specific ioctls
176
 *
-
 
177
 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
-
 
178
 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
175
 * The device specific ioctl range is 0x40 to 0x79.
179
 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
176
 */
180
 */
177
#define DRM_I915_INIT		0x00
181
#define DRM_I915_INIT		0x00
178
#define DRM_I915_FLUSH		0x01
182
#define DRM_I915_FLUSH		0x01
179
#define DRM_I915_FLIP		0x02
183
#define DRM_I915_FLIP		0x02
Line 222... Line 226...
222
#define DRM_I915_GEM_SET_CACHING	0x2f
226
#define DRM_I915_GEM_SET_CACHING	0x2f
223
#define DRM_I915_GEM_GET_CACHING	0x30
227
#define DRM_I915_GEM_GET_CACHING	0x30
224
#define DRM_I915_REG_READ		0x31
228
#define DRM_I915_REG_READ		0x31
225
#define DRM_I915_GET_RESET_STATS	0x32
229
#define DRM_I915_GET_RESET_STATS	0x32
226
#define DRM_I915_GEM_USERPTR		0x33
230
#define DRM_I915_GEM_USERPTR		0x33
-
 
231
#define DRM_I915_GEM_CONTEXT_GETPARAM	0x34
-
 
232
#define DRM_I915_GEM_CONTEXT_SETPARAM	0x35
Line 227... Line 233...
227
 
233
 
228
#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
234
#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
229
#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
235
#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
230
#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
236
#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
Line 266... Line 272...
266
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
272
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
267
#define DRM_IOCTL_I915_GEM_MADVISE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
273
#define DRM_IOCTL_I915_GEM_MADVISE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
268
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
274
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
269
#define DRM_IOCTL_I915_OVERLAY_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
275
#define DRM_IOCTL_I915_OVERLAY_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
270
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
276
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
271
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
277
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
272
#define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
278
#define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
273
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
279
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
274
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
280
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
275
#define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
281
#define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
276
#define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
282
#define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
277
#define DRM_IOCTL_I915_GEM_USERPTR			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
283
#define DRM_IOCTL_I915_GEM_USERPTR			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
-
 
284
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
-
 
285
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
Line 278... Line 286...
278
 
286
 
279
/* Allow drivers to submit batchbuffers directly to hardware, relying
287
/* Allow drivers to submit batchbuffers directly to hardware, relying
280
 * on the security mechanisms provided by hardware.
288
 * on the security mechanisms provided by hardware.
281
 */
289
 */
Line 339... Line 347...
339
#define I915_PARAM_HAS_EXEC_NO_RELOC	 25
347
#define I915_PARAM_HAS_EXEC_NO_RELOC	 25
340
#define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
348
#define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
341
#define I915_PARAM_HAS_WT     	 	 27
349
#define I915_PARAM_HAS_WT     	 	 27
342
#define I915_PARAM_CMD_PARSER_VERSION	 28
350
#define I915_PARAM_CMD_PARSER_VERSION	 28
343
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
351
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
-
 
352
#define I915_PARAM_MMAP_VERSION          30
-
 
353
#define I915_PARAM_HAS_BSD2		 31
-
 
354
#define I915_PARAM_REVISION              32
-
 
355
#define I915_PARAM_SUBSLICE_TOTAL	 33
-
 
356
#define I915_PARAM_EU_TOTAL		 34
-
 
357
#define I915_PARAM_HAS_GPU_RESET	 35
-
 
358
#define I915_PARAM_HAS_RESOURCE_STREAMER 36
Line 344... Line 359...
344
 
359
 
345
typedef struct drm_i915_getparam {
360
typedef struct drm_i915_getparam {
-
 
361
	__s32 param;
-
 
362
	/*
-
 
363
	 * WARNING: Using pointers instead of fixed-size u64 means we need to write
-
 
364
	 * compat32 code. Don't repeat this mistake.
346
	int param;
365
	 */
347
	int __user *value;
366
	int __user *value;
Line 348... Line 367...
348
} drm_i915_getparam_t;
367
} drm_i915_getparam_t;
349
 
368
 
Line 486... Line 505...
486
	 * Returned pointer the data was mapped at.
505
	 * Returned pointer the data was mapped at.
487
	 *
506
	 *
488
	 * This is a fixed-size type for 32/64 compatibility.
507
	 * This is a fixed-size type for 32/64 compatibility.
489
	 */
508
	 */
490
	__u64 addr_ptr;
509
	__u64 addr_ptr;
-
 
510
 
-
 
511
	/**
-
 
512
	 * Flags for extended behaviour.
-
 
513
	 *
-
 
514
	 * Added in version 2.
-
 
515
	 */
-
 
516
	__u64 flags;
-
 
517
#define I915_MMAP_WC 0x1
491
};
518
};
Line 492... Line 519...
492
 
519
 
493
struct drm_i915_gem_mmap_gtt {
520
struct drm_i915_gem_mmap_gtt {
494
	/** Handle for the object being mapped. */
521
	/** Handle for the object being mapped. */
Line 661... Line 688...
661
	__u64 offset;
688
	__u64 offset;
Line 662... Line 689...
662
 
689
 
663
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
690
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
664
#define EXEC_OBJECT_NEEDS_GTT	(1<<1)
691
#define EXEC_OBJECT_NEEDS_GTT	(1<<1)
-
 
692
#define EXEC_OBJECT_WRITE	(1<<2)
665
#define EXEC_OBJECT_WRITE	(1<<2)
693
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
666
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
694
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48B_ADDRESS<<1)
Line 667... Line 695...
667
	__u64 flags;
695
	__u64 flags;
668
 
696
 
669
	__u64 rsvd1;
697
	__u64 rsvd1;
Line 735... Line 763...
735
/** Use the reloc.handle as an index into the exec object array rather
763
/** Use the reloc.handle as an index into the exec object array rather
736
 * than as the per-file handle.
764
 * than as the per-file handle.
737
 */
765
 */
738
#define I915_EXEC_HANDLE_LUT		(1<<12)
766
#define I915_EXEC_HANDLE_LUT		(1<<12)
Line -... Line 767...
-
 
767
 
-
 
768
/** Used for switching BSD rings on the platforms with two BSD rings */
-
 
769
#define I915_EXEC_BSD_MASK		(3<<13)
-
 
770
#define I915_EXEC_BSD_DEFAULT		(0<<13) /* default ping-pong mode */
-
 
771
#define I915_EXEC_BSD_RING1		(1<<13)
-
 
772
#define I915_EXEC_BSD_RING2		(2<<13)
-
 
773
 
-
 
774
/** Tell the kernel that the batchbuffer is processed by
-
 
775
 *  the resource streamer.
-
 
776
 */
-
 
777
#define I915_EXEC_RESOURCE_STREAMER     (1<<15)
739
 
778
 
Line 740... Line 779...
740
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
779
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
741
 
780
 
742
#define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
781
#define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
743
#define i915_execbuffer2_set_context_id(eb2, context) \
782
#define i915_execbuffer2_set_context_id(eb2, context) \
Line 971... Line 1010...
971
};
1010
};
Line 972... Line 1011...
972
 
1011
 
973
/* flags */
1012
/* flags */
974
#define I915_OVERLAY_UPDATE_ATTRS	(1<<0)
1013
#define I915_OVERLAY_UPDATE_ATTRS	(1<<0)
-
 
1014
#define I915_OVERLAY_UPDATE_GAMMA	(1<<1)
975
#define I915_OVERLAY_UPDATE_GAMMA	(1<<1)
1015
#define I915_OVERLAY_DISABLE_DEST_COLORKEY	(1<<2)
976
struct drm_intel_overlay_attrs {
1016
struct drm_intel_overlay_attrs {
977
	__u32 flags;
1017
	__u32 flags;
978
	__u32 color_key;
1018
	__u32 color_key;
979
	__s32 brightness;
1019
	__s32 brightness;
Line 1040... Line 1080...
1040
 
1080
 
1041
struct drm_i915_reg_read {
1081
struct drm_i915_reg_read {
1042
	__u64 offset;
1082
	__u64 offset;
1043
	__u64 val; /* Return value */
1083
	__u64 val; /* Return value */
-
 
1084
};
-
 
1085
/* Known registers:
-
 
1086
 *
-
 
1087
 * Render engine timestamp - 0x2358 + 64bit - gen7+
-
 
1088
 * - Note this register returns an invalid value if using the default
-
 
1089
 *   single instruction 8byte read, in order to workaround that use
-
 
1090
 *   offset (0x2538 | 1) instead.
-
 
1091
 *
Line 1044... Line 1092...
1044
};
1092
 */
1045
 
1093
 
1046
struct drm_i915_reset_stats {
1094
struct drm_i915_reset_stats {
Line 1071... Line 1119...
1071
	 * Object handles are nonzero.
1119
	 * Object handles are nonzero.
1072
	 */
1120
	 */
1073
	__u32 handle;
1121
	__u32 handle;
1074
};
1122
};
Line -... Line 1123...
-
 
1123
 
-
 
1124
struct drm_i915_gem_context_param {
-
 
1125
	__u32 ctx_id;
-
 
1126
	__u32 size;
-
 
1127
	__u64 param;
-
 
1128
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
-
 
1129
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
-
 
1130
	__u64 value;
-
 
1131
};
-
 
1132
 
1075
 
1133
 
1076
struct drm_i915_mask {
1134
struct drm_i915_mask {
1077
    __u32 handle;
1135
    __u32 handle;
1078
    __u32 width;
1136
    __u32 width;
1079
    __u32 height;
1137
    __u32 height;
Line 1098... Line 1156...
1098
    __u32 dy;
1156
    __u32 dy;
1099
    __u32 width;
1157
    __u32 width;
1100
    __u32 height;
1158
    __u32 height;
1101
    __u32 bo_pitch;
1159
    __u32 bo_pitch;
1102
    __u32 bo_map;
1160
    __u32 bo_map;
-
 
1161
    __u32 forced;
1103
};
1162
};
Line 1104... Line 1163...
1104
 
1163