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36 | /** |
36 | /** |
37 | * DOC: uevents generated by i915 on it's device node |
37 | * DOC: uevents generated by i915 on it's device node |
38 | * |
38 | * |
39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
41 | * BANK, SUBBANK of the affected cacheline. Userspace should keep track of |
41 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
42 | * these events and if a specific cache-line seems to have a persistent |
42 | * track of these events and if a specific cache-line seems to have a |
43 | * error remap it with the l3 remapping tool supplied in intel-gpu-tools. |
43 | * persistent error remap it with the l3 remapping tool supplied in |
44 | * The value supplied with the event is always 1. |
44 | * intel-gpu-tools. The value supplied with the event is always 1. |
45 | * |
45 | * |
46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
47 | * hangcheck. The error detection event is a good indicator of when things |
47 | * hangcheck. The error detection event is a good indicator of when things |
48 | * began to go badly. The value supplied with the event is a 1 upon error |
48 | * began to go badly. The value supplied with the event is a 1 upon error |
49 | * detection, and a 0 upon reset completion, signifying no more error |
49 | * detection, and a 0 upon reset completion, signifying no more error |
Line 220... | Line 220... | ||
220 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
220 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
221 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
221 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
222 | #define DRM_I915_GEM_SET_CACHING 0x2f |
222 | #define DRM_I915_GEM_SET_CACHING 0x2f |
223 | #define DRM_I915_GEM_GET_CACHING 0x30 |
223 | #define DRM_I915_GEM_GET_CACHING 0x30 |
224 | #define DRM_I915_REG_READ 0x31 |
224 | #define DRM_I915_REG_READ 0x31 |
- | 225 | #define DRM_I915_GET_RESET_STATS 0x32 |
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Line 225... | Line 226... | ||
225 | 226 | ||
226 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
227 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
227 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
228 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
228 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
229 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
Line 269... | Line 270... | ||
269 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
270 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
270 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
271 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
271 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
272 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
272 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
273 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
273 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
274 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
- | 275 | #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
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Line 274... | Line 276... | ||
274 | 276 | ||
275 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
277 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
276 | * on the security mechanisms provided by hardware. |
278 | * on the security mechanisms provided by hardware. |
277 | */ |
279 | */ |
Line 717... | Line 719... | ||
717 | * coherent with the CS before execution. If this flag is passed, |
719 | * coherent with the CS before execution. If this flag is passed, |
718 | * userspace assumes the responsibility for ensuring the same. |
720 | * userspace assumes the responsibility for ensuring the same. |
719 | */ |
721 | */ |
720 | #define I915_EXEC_IS_PINNED (1<<10) |
722 | #define I915_EXEC_IS_PINNED (1<<10) |
Line 721... | Line 723... | ||
721 | 723 | ||
722 | /** Provide a hint to the kernel that the command stream and auxilliary |
724 | /** Provide a hint to the kernel that the command stream and auxiliary |
723 | * state buffers already holds the correct presumed addresses and so the |
725 | * state buffers already holds the correct presumed addresses and so the |
724 | * relocation process may be skipped if no buffers need to be moved in |
726 | * relocation process may be skipped if no buffers need to be moved in |
725 | * preparation for the execbuffer. |
727 | * preparation for the execbuffer. |
726 | */ |
728 | */ |
Line 1029... | Line 1031... | ||
1029 | struct drm_i915_reg_read { |
1031 | struct drm_i915_reg_read { |
1030 | __u64 offset; |
1032 | __u64 offset; |
1031 | __u64 val; /* Return value */ |
1033 | __u64 val; /* Return value */ |
1032 | }; |
1034 | }; |
Line -... | Line 1035... | ||
- | 1035 | ||
- | 1036 | struct drm_i915_reset_stats { |
|
- | 1037 | __u32 ctx_id; |
|
- | 1038 | __u32 flags; |
|
- | 1039 | ||
- | 1040 | /* All resets since boot/module reload, for all contexts */ |
|
- | 1041 | __u32 reset_count; |
|
- | 1042 | ||
- | 1043 | /* Number of batches lost when active in GPU, for this context */ |
|
- | 1044 | __u32 batch_active; |
|
- | 1045 | ||
- | 1046 | /* Number of batches lost pending for execution, for this context */ |
|
- | 1047 | __u32 batch_pending; |
|
- | 1048 | ||
- | 1049 | __u32 pad; |
|
- | 1050 | }; |
|
1033 | 1051 | ||
1034 | struct drm_i915_mask { |
1052 | struct drm_i915_mask { |
1035 | __u32 handle; |
1053 | __u32 handle; |
1036 | __u32 width; |
1054 | __u32 width; |
1037 | __u32 height; |
1055 | __u32 height; |