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/**
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/**
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 * DOC: uevents generated by i915 on it's device node
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 * DOC: uevents generated by i915 on it's device node
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 *
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 *
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 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
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 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
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 *	event from the gpu l3 cache. Additional information supplied is ROW,
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 *	event from the gpu l3 cache. Additional information supplied is ROW,
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 *	BANK, SUBBANK of the affected cacheline. Userspace should keep track of
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 *	BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
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 *	these events and if a specific cache-line seems to have a persistent
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 *	track of these events and if a specific cache-line seems to have a
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 *	error remap it with the l3 remapping tool supplied in intel-gpu-tools.
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 *	persistent error remap it with the l3 remapping tool supplied in
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 *	The value supplied with the event is always 1.
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 *	intel-gpu-tools.  The value supplied with the event is always 1.
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 *
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 *
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 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
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 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
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 *	hangcheck. The error detection event is a good indicator of when things
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 *	hangcheck. The error detection event is a good indicator of when things
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 *	began to go badly. The value supplied with the event is a 1 upon error
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 *	began to go badly. The value supplied with the event is a 1 upon error
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 *	detection, and a 0 upon reset completion, signifying no more error
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 *	detection, and a 0 upon reset completion, signifying no more error
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#define DRM_I915_GEM_CONTEXT_CREATE	0x2d
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#define DRM_I915_GEM_CONTEXT_CREATE	0x2d
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#define DRM_I915_GEM_CONTEXT_DESTROY	0x2e
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#define DRM_I915_GEM_CONTEXT_DESTROY	0x2e
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#define DRM_I915_GEM_SET_CACHING	0x2f
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#define DRM_I915_GEM_SET_CACHING	0x2f
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#define DRM_I915_GEM_GET_CACHING	0x30
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#define DRM_I915_GEM_GET_CACHING	0x30
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#define DRM_I915_REG_READ		0x31
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#define DRM_I915_REG_READ		0x31
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#define DRM_I915_GET_RESET_STATS	0x32
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#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
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#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
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#define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
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#define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
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#define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
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#define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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 * on the security mechanisms provided by hardware.
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 * on the security mechanisms provided by hardware.
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 */
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 */
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 * coherent with the CS before execution. If this flag is passed,
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 * coherent with the CS before execution. If this flag is passed,
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 * userspace assumes the responsibility for ensuring the same.
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 * userspace assumes the responsibility for ensuring the same.
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 */
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 */
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#define I915_EXEC_IS_PINNED		(1<<10)
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#define I915_EXEC_IS_PINNED		(1<<10)
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/** Provide a hint to the kernel that the command stream and auxilliary
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/** Provide a hint to the kernel that the command stream and auxiliary
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 * state buffers already holds the correct presumed addresses and so the
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 * state buffers already holds the correct presumed addresses and so the
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 * relocation process may be skipped if no buffers need to be moved in
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 * relocation process may be skipped if no buffers need to be moved in
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 * preparation for the execbuffer.
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 * preparation for the execbuffer.
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 */
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 */
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struct drm_i915_reg_read {
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struct drm_i915_reg_read {
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	__u64 offset;
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	__u64 offset;
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	__u64 val; /* Return value */
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	__u64 val; /* Return value */
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};
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};
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struct drm_i915_reset_stats {
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	__u32 ctx_id;
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	__u32 flags;
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	/* All resets since boot/module reload, for all contexts */
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	__u32 reset_count;
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	/* Number of batches lost when active in GPU, for this context */
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	__u32 batch_active;
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	/* Number of batches lost pending for execution, for this context */
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	__u32 batch_pending;
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	__u32 pad;
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};
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struct drm_i915_mask {
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struct drm_i915_mask {
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    __u32 handle;
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    __u32 handle;
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    __u32 width;
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    __u32 width;
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    __u32 height;
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    __u32 height;