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/* Please note that modifications to all structs defined here are
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/* Please note that modifications to all structs defined here are
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 * subject to backwards-compatibility constraints.
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 * subject to backwards-compatibility constraints.
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 */
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/**
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 * DOC: uevents generated by i915 on it's device node
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 *
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 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
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 *	event from the gpu l3 cache. Additional information supplied is ROW,
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 *	BANK, SUBBANK of the affected cacheline. Userspace should keep track of
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 *	these events and if a specific cache-line seems to have a persistent
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 *	error remap it with the l3 remapping tool supplied in intel-gpu-tools.
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 *	The value supplied with the event is always 1.
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 *
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 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
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 *	hangcheck. The error detection event is a good indicator of when things
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 *	began to go badly. The value supplied with the event is a 1 upon error
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 *	detection, and a 0 upon reset completion, signifying no more error
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 *	exists. NOTE: Disabling hangcheck or reset via module parameter will
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 *	cause the related events to not be seen.
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 *
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 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
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 *	the GPU. The value supplied with the event is always 1. NOTE: Disable
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 *	reset via module parameter will cause this event to not be seen.
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 */
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#define I915_L3_PARITY_UEVENT		"L3_PARITY_ERROR"
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 */
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#define I915_ERROR_UEVENT		"ERROR"
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#define I915_RESET_UEVENT		"RESET"
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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#define I915_PARAM_HAS_LLC     	 	 17
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#define I915_PARAM_HAS_LLC     	 	 17
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#define I915_PARAM_HAS_ALIASING_PPGTT	 18
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#define I915_PARAM_HAS_ALIASING_PPGTT	 18
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#define I915_PARAM_HAS_WAIT_TIMEOUT	 19
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#define I915_PARAM_HAS_WAIT_TIMEOUT	 19
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#define I915_PARAM_HAS_SEMAPHORES	 20
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#define I915_PARAM_HAS_SEMAPHORES	 20
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#define I915_PARAM_HAS_PRIME_VMAP_FLUSH	 21
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#define I915_PARAM_HAS_PRIME_VMAP_FLUSH	 21
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#define I915_PARAM_RSVD_FOR_FUTURE_USE	 22
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#define I915_PARAM_HAS_VEBOX		 22
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#define I915_PARAM_HAS_SECURE_BATCHES	 23
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#define I915_PARAM_HAS_SECURE_BATCHES	 23
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#define I915_PARAM_HAS_PINNED_BATCHES	 24
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#define I915_PARAM_HAS_PINNED_BATCHES	 24
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#define I915_PARAM_HAS_EXEC_NO_RELOC	 25
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#define I915_PARAM_HAS_EXEC_NO_RELOC	 25
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#define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
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#define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
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#define I915_PARAM_HAS_WT     	 	 27
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typedef struct drm_i915_getparam {
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typedef struct drm_i915_getparam {
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	int param;
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	int param;
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	int __user *value;
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	int __user *value;
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#define I915_EXEC_RING_MASK              (7<<0)
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#define I915_EXEC_RING_MASK              (7<<0)
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#define I915_EXEC_DEFAULT                (0<<0)
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#define I915_EXEC_DEFAULT                (0<<0)
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#define I915_EXEC_RENDER                 (1<<0)
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#define I915_EXEC_RENDER                 (1<<0)
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#define I915_EXEC_BSD                    (2<<0)
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#define I915_EXEC_BSD                    (2<<0)
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#define I915_EXEC_BLT                    (3<<0)
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#define I915_EXEC_BLT                    (3<<0)
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#define I915_EXEC_VEBOX                  (4<<0)
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/* Used for switching the constants addressing mode on gen4+ RENDER ring.
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/* Used for switching the constants addressing mode on gen4+ RENDER ring.
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 * Gen6+ only supports relative addressing to dynamic state (default) and
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 * Gen6+ only supports relative addressing to dynamic state (default) and
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 * absolute addressing.
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 * absolute addressing.
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	 *  16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
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	 *  16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
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	 */
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	 */
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	__u32 busy;
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	__u32 busy;
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};
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};
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/**
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 * I915_CACHING_NONE
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 *
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 * GPU access is not coherent with cpu caches. Default for machines without an
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 * LLC.
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 */
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#define I915_CACHING_NONE		0
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/**
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 * I915_CACHING_CACHED
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 *
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 * GPU access is coherent with cpu caches and furthermore the data is cached in
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 * last-level caches shared between cpu cores and the gpu GT. Default on
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 * machines with HAS_LLC.
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#define I915_CACHING_NONE		0
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 */
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#define I915_CACHING_CACHED		1
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/**
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 * I915_CACHING_DISPLAY
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 *
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 * Special GPU caching mode which is coherent with the scanout engines.
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 * Transparently falls back to I915_CACHING_NONE on platforms where no special
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 * cache mode (like write-through or gfdt flushing) is available. The kernel
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 * automatically sets this mode when using a buffer as a scanout target.
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 * Userspace can manually set this mode to avoid a costly stall and clflush in
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 * the hotpath of drawing the first frame.
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 */
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#define I915_CACHING_CACHED		1
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#define I915_CACHING_DISPLAY		2
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struct drm_i915_gem_caching {
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struct drm_i915_gem_caching {
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	/**
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	/**