WebSVN – Kolibri OS – Diff – /drivers/include/linux/uapi/drm/drm.h


/**
 * \file drm.h
 * Header for the Direct Rendering Manager
 *
 * \author Rickard E. (Rik) Faith 
 *
 * \par Acknowledgments:
 * Dec 1999, Richard Henderson , move to generic \c cmpxchg.
 */
 
/*
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
 
#ifndef _DRM_H_
#define _DRM_H_
 
#if defined(__KERNEL__) || defined(__linux__)
 
#include 
#include 
typedef unsigned int drm_handle_t;
 
#else /* One of the BSDs */
 
#include 
#include 
typedef int8_t   __s8;
typedef uint8_t  __u8;
typedef int16_t  __s16;
typedef uint16_t __u16;
typedef int32_t  __s32;
typedef uint32_t __u32;
typedef int64_t  __s64;
typedef uint64_t __u64;
typedef unsigned long drm_handle_t;
 
#endif
 
#define DRM_NAME	"drm"	  /**< Name in kernel, /dev, and /proc */
#define DRM_MIN_ORDER	5	  /**< At least 2^5 bytes = 32 bytes */
#define DRM_MAX_ORDER	22	  /**< Up to 2^22 bytes = 4MB */
#define DRM_RAM_PERCENT 10	  /**< How much system ram can we lock? */
 
#define _DRM_LOCK_HELD	0x80000000U /**< Hardware lock is held */
#define _DRM_LOCK_CONT	0x40000000U /**< Hardware lock is contended */
#define _DRM_LOCK_IS_HELD(lock)	   ((lock) & _DRM_LOCK_HELD)
#define _DRM_LOCK_IS_CONT(lock)	   ((lock) & _DRM_LOCK_CONT)
#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
 
typedef unsigned int drm_context_t;
typedef unsigned int drm_drawable_t;
typedef unsigned int drm_magic_t;
 
/**
 * Cliprect.
 *
 * \warning: If you change this structure, make sure you change
 * XF86DRIClipRectRec in the server as well
 *
 * \note KW: Actually it's illegal to change either for
 * backwards-compatibility reasons.
 */
struct drm_clip_rect {
	unsigned short x1;
	unsigned short y1;
	unsigned short x2;
	unsigned short y2;
};
 
/**
 * Drawable information.
 */
struct drm_drawable_info {
	unsigned int num_rects;
	struct drm_clip_rect *rects;
};
 
/**
 * Texture region,
 */
struct drm_tex_region {
	unsigned char next;
	unsigned char prev;
	unsigned char in_use;
	unsigned char padding;
	unsigned int age;
};
 
/**
 * Hardware lock.
 *
 * The lock structure is a simple cache-line aligned integer.  To avoid
 * processor bus contention on a multiprocessor system, there should not be any
 * other data stored in the same cache line.
 */
struct drm_hw_lock {
	__volatile__ unsigned int lock;		/**< lock variable */
	char padding[60];			/**< Pad to cache line */
};
 
/**
 * DRM_IOCTL_VERSION ioctl argument type.
 *
 * \sa drmGetVersion().
 */
struct drm_version {
	int version_major;	  /**< Major version */
	int version_minor;	  /**< Minor version */
	int version_patchlevel;	  /**< Patch level */
	size_t name_len;	  /**< Length of name buffer */
	char __user *name;	  /**< Name of driver */
	size_t date_len;	  /**< Length of date buffer */
	char __user *date;	  /**< User-space buffer to hold date */
	size_t desc_len;	  /**< Length of desc buffer */
	char __user *desc;	  /**< User-space buffer to hold desc */
};
 
/**
 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
 *
 * \sa drmGetBusid() and drmSetBusId().
 */
struct drm_unique {
	size_t unique_len;	  /**< Length of unique */
	char __user *unique;	  /**< Unique name for driver instantiation */
};
 
struct drm_list {
	int count;		  /**< Length of user-space structures */
	struct drm_version __user *version;
};
 
struct drm_block {
	int unused;
};
 
/**
 * DRM_IOCTL_CONTROL ioctl argument type.
 *
 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
 */
struct drm_control {
	enum {
		DRM_ADD_COMMAND,
		DRM_RM_COMMAND,
		DRM_INST_HANDLER,
		DRM_UNINST_HANDLER
	} func;
	int irq;
};
 
/**
 * Type of memory to map.
 */
enum drm_map_type {
	_DRM_FRAME_BUFFER = 0,	  /**< WC (no caching), no core dump */
	_DRM_REGISTERS = 1,	  /**< no caching, no core dump */
	_DRM_SHM = 2,		  /**< shared, cached */
	_DRM_AGP = 3,		  /**< AGP/GART */
	_DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
	_DRM_CONSISTENT = 5,	  /**< Consistent memory for PCI DMA */
 
};
 
/**
 * Memory mapping flags.
 */
enum drm_map_flags {
	_DRM_RESTRICTED = 0x01,	     /**< Cannot be mapped to user-virtual */
	_DRM_READ_ONLY = 0x02,
	_DRM_LOCKED = 0x04,	     /**< shared, cached, locked */
	_DRM_KERNEL = 0x08,	     /**< kernel requires access */
	_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
	_DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
	_DRM_REMOVABLE = 0x40,	     /**< Removable mapping */
	_DRM_DRIVER = 0x80	     /**< Managed by driver */
};
 
struct drm_ctx_priv_map {
	unsigned int ctx_id;	 /**< Context requesting private mapping */
	void *handle;		 /**< Handle of map */
};
 
/**
 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
 * argument type.
 *
 * \sa drmAddMap().
 */
struct drm_map {
	unsigned long offset;	 /**< Requested physical address (0 for SAREA)*/
	unsigned long size;	 /**< Requested physical size (bytes) */
	enum drm_map_type type;	 /**< Type of memory to map */
	enum drm_map_flags flags;	 /**< Flags */
	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
				 /**< Kernel-space: kernel-virtual address */
	int mtrr;		 /**< MTRR slot used */
	/*   Private data */
};
 
/**
 * DRM_IOCTL_GET_CLIENT ioctl argument type.
 */
struct drm_client {
	int idx;		/**< Which client desired? */
	int auth;		/**< Is client authenticated? */
	unsigned long pid;	/**< Process ID */
	unsigned long uid;	/**< User ID */
	unsigned long magic;	/**< Magic */
	unsigned long iocs;	/**< Ioctl count */
};
 
enum drm_stat_type {
	_DRM_STAT_LOCK,
	_DRM_STAT_OPENS,
	_DRM_STAT_CLOSES,
	_DRM_STAT_IOCTLS,
	_DRM_STAT_LOCKS,
	_DRM_STAT_UNLOCKS,
	_DRM_STAT_VALUE,	/**< Generic value */
	_DRM_STAT_BYTE,		/**< Generic byte counter (1024bytes/K) */
	_DRM_STAT_COUNT,	/**< Generic non-byte counter (1000/k) */
 
	_DRM_STAT_IRQ,		/**< IRQ */
	_DRM_STAT_PRIMARY,	/**< Primary DMA bytes */
	_DRM_STAT_SECONDARY,	/**< Secondary DMA bytes */
	_DRM_STAT_DMA,		/**< DMA */
	_DRM_STAT_SPECIAL,	/**< Special DMA (e.g., priority or polled) */
	_DRM_STAT_MISSED	/**< Missed DMA opportunity */
	    /* Add to the *END* of the list */
};
 
/**
 * DRM_IOCTL_GET_STATS ioctl argument type.
 */
struct drm_stats {
	unsigned long count;
	struct {
		unsigned long value;
		enum drm_stat_type type;
	} data[15];
};
 
/**
 * Hardware locking flags.
 */
enum drm_lock_flags {
	_DRM_LOCK_READY = 0x01,	     /**< Wait until hardware is ready for DMA */
	_DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
	_DRM_LOCK_FLUSH = 0x04,	     /**< Flush this context's DMA queue first */
	_DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
	/* These *HALT* flags aren't supported yet
	   -- they will be used to support the
	   full-screen DGA-like mode. */
	_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
	_DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
};
 
/**
 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
 *
 * \sa drmGetLock() and drmUnlock().
 */
struct drm_lock {
	int context;
	enum drm_lock_flags flags;
};
 
/**
 * DMA flags
 *
 * \warning
 * These values \e must match xf86drm.h.
 *
 * \sa drm_dma.
 */
enum drm_dma_flags {
	/* Flags for DMA buffer dispatch */
	_DRM_DMA_BLOCK = 0x01,	      /**<
				       * Block until buffer dispatched.
				       *
				       * \note The buffer may not yet have
				       * been processed by the hardware --
				       * getting a hardware lock with the
				       * hardware quiescent will ensure
				       * that the buffer has been
				       * processed.
				       */
	_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
	_DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 
	/* Flags for DMA buffer request */
	_DRM_DMA_WAIT = 0x10,	      /**< Wait for free buffers */
	_DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
	_DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
};
 
/**
 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
 *
 * \sa drmAddBufs().
 */
struct drm_buf_desc {
	int count;		 /**< Number of buffers of this size */
	int size;		 /**< Size in bytes */
	int low_mark;		 /**< Low water mark */
	int high_mark;		 /**< High water mark */
	enum {
		_DRM_PAGE_ALIGN = 0x01,	/**< Align on page boundaries for DMA */
		_DRM_AGP_BUFFER = 0x02,	/**< Buffer is in AGP space */
		_DRM_SG_BUFFER = 0x04,	/**< Scatter/gather memory buffer */
		_DRM_FB_BUFFER = 0x08,	/**< Buffer is in frame buffer */
		_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
	} flags;
	unsigned long agp_start; /**<
				  * Start address of where the AGP buffers are
				  * in the AGP aperture
				  */
};
 
/**
 * DRM_IOCTL_INFO_BUFS ioctl argument type.
 */
struct drm_buf_info {
	int count;		/**< Entries in list */
	struct drm_buf_desc __user *list;
};
 
/**
 * DRM_IOCTL_FREE_BUFS ioctl argument type.
 */
struct drm_buf_free {
	int count;
	int __user *list;
};
 
/**
 * Buffer information
 *
 * \sa drm_buf_map.
 */
struct drm_buf_pub {
	int idx;		       /**< Index into the master buffer list */
	int total;		       /**< Buffer size */
	int used;		       /**< Amount of buffer in use (for DMA) */
	void __user *address;	       /**< Address of buffer */
};
 
/**
 * DRM_IOCTL_MAP_BUFS ioctl argument type.
 */
struct drm_buf_map {
	int count;		/**< Length of the buffer list */
	void __user *virtual;		/**< Mmap'd area in user-virtual */
	struct drm_buf_pub __user *list;	/**< Buffer information */
};
 
/**
 * DRM_IOCTL_DMA ioctl argument type.
 *
 * Indices here refer to the offset into the buffer list in drm_buf_get.
 *
 * \sa drmDMA().
 */
struct drm_dma {
	int context;			  /**< Context handle */
	int send_count;			  /**< Number of buffers to send */
	int __user *send_indices;	  /**< List of handles to buffers */
	int __user *send_sizes;		  /**< Lengths of data to send */
	enum drm_dma_flags flags;	  /**< Flags */
	int request_count;		  /**< Number of buffers requested */
	int request_size;		  /**< Desired size for buffers */
	int __user *request_indices;	  /**< Buffer information */
	int __user *request_sizes;
	int granted_count;		  /**< Number of buffers granted */
};
 
enum drm_ctx_flags {
	_DRM_CONTEXT_PRESERVED = 0x01,
	_DRM_CONTEXT_2DONLY = 0x02
};
 
/**
 * DRM_IOCTL_ADD_CTX ioctl argument type.
 *
 * \sa drmCreateContext() and drmDestroyContext().
 */
struct drm_ctx {
	drm_context_t handle;
	enum drm_ctx_flags flags;
};
 
/**
 * DRM_IOCTL_RES_CTX ioctl argument type.
 */
struct drm_ctx_res {
	int count;
	struct drm_ctx __user *contexts;
};
 
/**
 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
 */
struct drm_draw {
	drm_drawable_t handle;
};
 
/**
 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
 */
typedef enum {
	DRM_DRAWABLE_CLIPRECTS,
} drm_drawable_info_type_t;
 
struct drm_update_draw {
	drm_drawable_t handle;
	unsigned int type;
	unsigned int num;
	unsigned long long data;
};
 
/**
 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
 */
struct drm_auth {
	drm_magic_t magic;
};
 
/**
 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
 *
 * \sa drmGetInterruptFromBusID().
 */
struct drm_irq_busid {
	int irq;	/**< IRQ number */
	int busnum;	/**< bus number */
	int devnum;	/**< device number */
	int funcnum;	/**< function number */
};
 
enum drm_vblank_seq_type {
	_DRM_VBLANK_ABSOLUTE = 0x0,	/**< Wait for specific vblank sequence number */
	_DRM_VBLANK_RELATIVE = 0x1,	/**< Wait for given number of vblanks */
	/* bits 1-6 are reserved for high crtcs */
	_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
	_DRM_VBLANK_EVENT = 0x4000000,   /**< Send event instead of blocking */
	_DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
	_DRM_VBLANK_NEXTONMISS = 0x10000000,	/**< If missed, wait for next vblank */
	_DRM_VBLANK_SECONDARY = 0x20000000,	/**< Secondary display controller */
	_DRM_VBLANK_SIGNAL = 0x40000000	/**< Send signal instead of blocking, unsupported */
};
#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
 
#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
				_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
 
struct drm_wait_vblank_request {
	enum drm_vblank_seq_type type;
	unsigned int sequence;
	unsigned long signal;
};
 
struct drm_wait_vblank_reply {
	enum drm_vblank_seq_type type;
	unsigned int sequence;
	long tval_sec;
	long tval_usec;
};
 
/**
 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
 *
 * \sa drmWaitVBlank().
 */
union drm_wait_vblank {
	struct drm_wait_vblank_request request;
	struct drm_wait_vblank_reply reply;
};
 
#define _DRM_PRE_MODESET 1
#define _DRM_POST_MODESET 2
 
/**
 * DRM_IOCTL_MODESET_CTL ioctl argument type
 *
 * \sa drmModesetCtl().
 */
struct drm_modeset_ctl {
	__u32 crtc;
	__u32 cmd;
};
 
/**
 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
 *
 * \sa drmAgpEnable().
 */
struct drm_agp_mode {
	unsigned long mode;	/**< AGP mode */
};
 
/**
 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
 *
 * \sa drmAgpAlloc() and drmAgpFree().
 */
struct drm_agp_buffer {
	unsigned long size;	/**< In bytes -- will round to page boundary */
	unsigned long handle;	/**< Used for binding / unbinding */
	unsigned long type;	/**< Type of memory to allocate */
	unsigned long physical;	/**< Physical used by i810 */
};
 
/**
 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
 *
 * \sa drmAgpBind() and drmAgpUnbind().
 */
struct drm_agp_binding {
	unsigned long handle;	/**< From drm_agp_buffer */
	unsigned long offset;	/**< In bytes -- will round to page boundary */
};
 
/**
 * DRM_IOCTL_AGP_INFO ioctl argument type.
 *
 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
 * drmAgpVendorId() and drmAgpDeviceId().
 */
struct drm_agp_info {
	int agp_version_major;
	int agp_version_minor;
	unsigned long mode;
	unsigned long aperture_base;	/* physical address */
	unsigned long aperture_size;	/* bytes */
	unsigned long memory_allowed;	/* bytes */
	unsigned long memory_used;
 
	/* PCI information */
	unsigned short id_vendor;
	unsigned short id_device;
};
 
/**
 * DRM_IOCTL_SG_ALLOC ioctl argument type.
 */
struct drm_scatter_gather {
	unsigned long size;	/**< In bytes -- will round to page boundary */
	unsigned long handle;	/**< Used for mapping / unmapping */
};
 
/**
 * DRM_IOCTL_SET_VERSION ioctl argument type.
 */
struct drm_set_version {
	int drm_di_major;
	int drm_di_minor;
	int drm_dd_major;
	int drm_dd_minor;
};
 
/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
struct drm_gem_close {
	/** Handle of the object to be closed. */
	__u32 handle;
	__u32 pad;
};
 
/** DRM_IOCTL_GEM_FLINK ioctl argument type */
struct drm_gem_flink {
	/** Handle for the object being named */
	__u32 handle;
 
	/** Returned global name */
	__u32 name;
};
 
/** DRM_IOCTL_GEM_OPEN ioctl argument type */
struct drm_gem_open {
	/** Name of object being opened */
	__u32 name;
 
	/** Returned handle for the object */
	__u32 handle;
 
	/** Returned size of the object */
	__u64 size;
};
 
#define DRM_CAP_DUMB_BUFFER		0x1
#define DRM_CAP_VBLANK_HIGH_CRTC	0x2
#define DRM_CAP_DUMB_PREFERRED_DEPTH	0x3
#define DRM_CAP_DUMB_PREFER_SHADOW	0x4
#define DRM_CAP_PRIME			0x5
#define  DRM_PRIME_CAP_IMPORT		0x1
#define  DRM_PRIME_CAP_EXPORT		0x2
#define DRM_CAP_TIMESTAMP_MONOTONIC	0x6
#define DRM_CAP_ASYNC_PAGE_FLIP		0x7
 
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
	__u64 capability;
	__u64 value;
};
 
/**
 * DRM_CLIENT_CAP_STEREO_3D
 *
 * if set to 1, the DRM core will expose the stereo 3D capabilities of the
 * monitor by advertising the supported 3D layouts in the flags of struct
 * drm_mode_modeinfo.
 */
#define DRM_CLIENT_CAP_STEREO_3D	1
 
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
	__u64 capability;
	__u64 value;
};
 
#define DRM_CLOEXEC O_CLOEXEC
struct drm_prime_handle {
	__u32 handle;
 
	/** Flags.. only applicable for handle->fd */
	__u32 flags;
 
	/** Returned dmabuf file descriptor */
	__s32 fd;
};
 
#include 
 
#define DRM_IOCTL_BASE			'd'
#define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)
#define DRM_IOR(nr,type)		_IOR(DRM_IOCTL_BASE,nr,type)
#define DRM_IOW(nr,type)		_IOW(DRM_IOCTL_BASE,nr,type)
#define DRM_IOWR(nr,type)		_IOWR(DRM_IOCTL_BASE,nr,type)
 
#define DRM_IOCTL_VERSION		DRM_IOWR(0x00, struct drm_version)
#define DRM_IOCTL_GET_UNIQUE		DRM_IOWR(0x01, struct drm_unique)
#define DRM_IOCTL_GET_MAGIC		DRM_IOR( 0x02, struct drm_auth)
#define DRM_IOCTL_IRQ_BUSID		DRM_IOWR(0x03, struct drm_irq_busid)
#define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
#define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
#define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
#define DRM_IOCTL_SET_VERSION		DRM_IOWR(0x07, struct drm_set_version)
#define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
#define DRM_IOCTL_GEM_CLOSE		DRM_IOW (0x09, struct drm_gem_close)
#define DRM_IOCTL_GEM_FLINK		DRM_IOWR(0x0a, struct drm_gem_flink)
#define DRM_IOCTL_GEM_OPEN		DRM_IOWR(0x0b, struct drm_gem_open)
#define DRM_IOCTL_GET_CAP		DRM_IOWR(0x0c, struct drm_get_cap)
#define DRM_IOCTL_SET_CLIENT_CAP	DRM_IOW( 0x0d, struct drm_set_client_cap)
 
#define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, struct drm_unique)
#define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, struct drm_auth)
#define DRM_IOCTL_BLOCK			DRM_IOWR(0x12, struct drm_block)
#define DRM_IOCTL_UNBLOCK		DRM_IOWR(0x13, struct drm_block)
#define DRM_IOCTL_CONTROL		DRM_IOW( 0x14, struct drm_control)
#define DRM_IOCTL_ADD_MAP		DRM_IOWR(0x15, struct drm_map)
#define DRM_IOCTL_ADD_BUFS		DRM_IOWR(0x16, struct drm_buf_desc)
#define DRM_IOCTL_MARK_BUFS		DRM_IOW( 0x17, struct drm_buf_desc)
#define DRM_IOCTL_INFO_BUFS		DRM_IOWR(0x18, struct drm_buf_info)
#define DRM_IOCTL_MAP_BUFS		DRM_IOWR(0x19, struct drm_buf_map)
#define DRM_IOCTL_FREE_BUFS		DRM_IOW( 0x1a, struct drm_buf_free)
 
#define DRM_IOCTL_RM_MAP		DRM_IOW( 0x1b, struct drm_map)
 
#define DRM_IOCTL_SET_SAREA_CTX		DRM_IOW( 0x1c, struct drm_ctx_priv_map)
#define DRM_IOCTL_GET_SAREA_CTX 	DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 
#define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
#define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
 
#define DRM_IOCTL_ADD_CTX		DRM_IOWR(0x20, struct drm_ctx)
#define DRM_IOCTL_RM_CTX		DRM_IOWR(0x21, struct drm_ctx)
#define DRM_IOCTL_MOD_CTX		DRM_IOW( 0x22, struct drm_ctx)
#define DRM_IOCTL_GET_CTX		DRM_IOWR(0x23, struct drm_ctx)
#define DRM_IOCTL_SWITCH_CTX		DRM_IOW( 0x24, struct drm_ctx)
#define DRM_IOCTL_NEW_CTX		DRM_IOW( 0x25, struct drm_ctx)
#define DRM_IOCTL_RES_CTX		DRM_IOWR(0x26, struct drm_ctx_res)
#define DRM_IOCTL_ADD_DRAW		DRM_IOWR(0x27, struct drm_draw)
#define DRM_IOCTL_RM_DRAW		DRM_IOWR(0x28, struct drm_draw)
#define DRM_IOCTL_DMA			DRM_IOWR(0x29, struct drm_dma)
#define DRM_IOCTL_LOCK			DRM_IOW( 0x2a, struct drm_lock)
#define DRM_IOCTL_UNLOCK		DRM_IOW( 0x2b, struct drm_lock)
#define DRM_IOCTL_FINISH		DRM_IOW( 0x2c, struct drm_lock)
 
#define DRM_IOCTL_PRIME_HANDLE_TO_FD    DRM_IOWR(0x2d, struct drm_prime_handle)
#define DRM_IOCTL_PRIME_FD_TO_HANDLE    DRM_IOWR(0x2e, struct drm_prime_handle)
 
#define DRM_IOCTL_AGP_ACQUIRE		DRM_IO(  0x30)
#define DRM_IOCTL_AGP_RELEASE		DRM_IO(  0x31)
#define DRM_IOCTL_AGP_ENABLE		DRM_IOW( 0x32, struct drm_agp_mode)
#define DRM_IOCTL_AGP_INFO		DRM_IOR( 0x33, struct drm_agp_info)
#define DRM_IOCTL_AGP_ALLOC		DRM_IOWR(0x34, struct drm_agp_buffer)
#define DRM_IOCTL_AGP_FREE		DRM_IOW( 0x35, struct drm_agp_buffer)
#define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, struct drm_agp_binding)
#define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, struct drm_agp_binding)
 
#define DRM_IOCTL_SG_ALLOC		DRM_IOWR(0x38, struct drm_scatter_gather)
#define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, struct drm_scatter_gather)
 
#define DRM_IOCTL_WAIT_VBLANK		DRM_IOWR(0x3a, union drm_wait_vblank)
 
#define DRM_IOCTL_UPDATE_DRAW		DRM_IOW(0x3f, struct drm_update_draw)
 
#define DRM_IOCTL_MODE_GETRESOURCES	DRM_IOWR(0xA0, struct drm_mode_card_res)
#define DRM_IOCTL_MODE_GETCRTC		DRM_IOWR(0xA1, struct drm_mode_crtc)
#define DRM_IOCTL_MODE_SETCRTC		DRM_IOWR(0xA2, struct drm_mode_crtc)
#define DRM_IOCTL_MODE_CURSOR		DRM_IOWR(0xA3, struct drm_mode_cursor)
#define DRM_IOCTL_MODE_GETGAMMA		DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
#define DRM_IOCTL_MODE_SETGAMMA		DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
#define DRM_IOCTL_MODE_GETENCODER	DRM_IOWR(0xA6, struct drm_mode_get_encoder)
#define DRM_IOCTL_MODE_GETCONNECTOR	DRM_IOWR(0xA7, struct drm_mode_get_connector)
#define DRM_IOCTL_MODE_ATTACHMODE	DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
#define DRM_IOCTL_MODE_DETACHMODE	DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
 
#define DRM_IOCTL_MODE_GETPROPERTY	DRM_IOWR(0xAA, struct drm_mode_get_property)
#define DRM_IOCTL_MODE_SETPROPERTY	DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
#define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
#define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
#define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
#define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
#define DRM_IOCTL_MODE_PAGE_FLIP	DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
#define DRM_IOCTL_MODE_DIRTYFB		DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
 
#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
#define DRM_IOCTL_MODE_MAP_DUMB    DRM_IOWR(0xB3, struct drm_mode_map_dumb)
#define DRM_IOCTL_MODE_DESTROY_DUMB    DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
#define DRM_IOCTL_MODE_GETPLANE	DRM_IOWR(0xB6, struct drm_mode_get_plane)
#define DRM_IOCTL_MODE_SETPLANE	DRM_IOWR(0xB7, struct drm_mode_set_plane)
#define DRM_IOCTL_MODE_ADDFB2		DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES	DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY	DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
#define DRM_IOCTL_MODE_CURSOR2		DRM_IOWR(0xBB, struct drm_mode_cursor2)
 
/**
 * Device specific ioctls should only be in their respective headers
 * The device specific ioctl range is from 0x40 to 0x99.
 * Generic IOCTLS restart at 0xA0.
 *
 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
 * drmCommandReadWrite().
 */
#define DRM_COMMAND_BASE                0x40
#define DRM_COMMAND_END			0xA0
 
/**
 * Header for events written back to userspace on the drm fd.  The
 * type defines the type of event, the length specifies the total
 * length of the event (including the header), and user_data is
 * typically a 64 bit value passed with the ioctl that triggered the
 * event.  A read on the drm fd will always only return complete
 * events, that is, if for example the read buffer is 100 bytes, and
 * there are two 64 byte events pending, only one will be returned.
 *
 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
 * up are chipset specific.
 */
struct drm_event {
	__u32 type;
	__u32 length;
};
 
#define DRM_EVENT_VBLANK 0x01
#define DRM_EVENT_FLIP_COMPLETE 0x02
 
struct drm_event_vblank {
	struct drm_event base;
	__u64 user_data;
	__u32 tv_sec;
	__u32 tv_usec;
	__u32 sequence;
	__u32 reserved;
};
 
 
 
 
 
 
 
 
 
 
 
 
/* typedef area */
#ifndef __KERNEL__
typedef struct drm_clip_rect drm_clip_rect_t;
typedef struct drm_drawable_info drm_drawable_info_t;
typedef struct drm_tex_region drm_tex_region_t;
typedef struct drm_hw_lock drm_hw_lock_t;
typedef struct drm_version drm_version_t;
typedef struct drm_unique drm_unique_t;
typedef struct drm_list drm_list_t;
typedef struct drm_block drm_block_t;
typedef struct drm_control drm_control_t;
typedef enum drm_map_type drm_map_type_t;
typedef enum drm_map_flags drm_map_flags_t;
typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
typedef struct drm_map drm_map_t;
typedef struct drm_client drm_client_t;
typedef enum drm_stat_type drm_stat_type_t;
typedef struct drm_stats drm_stats_t;
typedef enum drm_lock_flags drm_lock_flags_t;
typedef struct drm_lock drm_lock_t;
typedef enum drm_dma_flags drm_dma_flags_t;
typedef struct drm_buf_desc drm_buf_desc_t;
typedef struct drm_buf_info drm_buf_info_t;
typedef struct drm_buf_free drm_buf_free_t;
typedef struct drm_buf_pub drm_buf_pub_t;
typedef struct drm_buf_map drm_buf_map_t;
typedef struct drm_dma drm_dma_t;
typedef union drm_wait_vblank drm_wait_vblank_t;
typedef struct drm_agp_mode drm_agp_mode_t;
typedef enum drm_ctx_flags drm_ctx_flags_t;
typedef struct drm_ctx drm_ctx_t;
typedef struct drm_ctx_res drm_ctx_res_t;
typedef struct drm_draw drm_draw_t;
typedef struct drm_update_draw drm_update_draw_t;
typedef struct drm_auth drm_auth_t;
typedef struct drm_irq_busid drm_irq_busid_t;
typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
 
typedef struct drm_agp_buffer drm_agp_buffer_t;
typedef struct drm_agp_binding drm_agp_binding_t;
typedef struct drm_agp_info drm_agp_info_t;
typedef struct drm_scatter_gather drm_scatter_gather_t;
typedef struct drm_set_version drm_set_version_t;
#endif
 
#endif
>
>

Rev 4244	Rev 4559
1	/**	1	/**
2	* \file drm.h	2	* \file drm.h
3	* Header for the Direct Rendering Manager	3	* Header for the Direct Rendering Manager
4	*	4	*
5	* \author Rickard E. (Rik) Faith	5	* \author Rickard E. (Rik) Faith
6	*	6	*
7	* \par Acknowledgments:	7	* \par Acknowledgments:
8	* Dec 1999, Richard Henderson , move to generic \c cmpxchg.	8	* Dec 1999, Richard Henderson , move to generic \c cmpxchg.
9	*/	9	*/
10		10
11	/*	11	/*
12	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.	12	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.	13	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14	* All rights reserved.	14	* All rights reserved.
15	*	15	*
16	* Permission is hereby granted, free of charge, to any person obtaining a	16	* Permission is hereby granted, free of charge, to any person obtaining a
17	* copy of this software and associated documentation files (the "Software"),	17	* copy of this software and associated documentation files (the "Software"),
18	* to deal in the Software without restriction, including without limitation	18	* to deal in the Software without restriction, including without limitation
19	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	19	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
20	* and/or sell copies of the Software, and to permit persons to whom the	20	* and/or sell copies of the Software, and to permit persons to whom the
21	* Software is furnished to do so, subject to the following conditions:	21	* Software is furnished to do so, subject to the following conditions:
22	*	22	*
23	* The above copyright notice and this permission notice (including the next	23	* The above copyright notice and this permission notice (including the next
24	* paragraph) shall be included in all copies or substantial portions of the	24	* paragraph) shall be included in all copies or substantial portions of the
25	* Software.	25	* Software.
26	*	26	*
27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	28	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	29	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR	30	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	31	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	32	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33	* OTHER DEALINGS IN THE SOFTWARE.	33	* OTHER DEALINGS IN THE SOFTWARE.
34	*/	34	*/
35		35
36	#ifndef _DRM_H_	36	#ifndef _DRM_H_
37	#define _DRM_H_	37	#define _DRM_H_
38		38
39	#if defined(__KERNEL__) \|\| defined(__linux__)	39	#if defined(__KERNEL__) \|\| defined(__linux__)
40		40
41	#include	41	#include
42	#include	42	#include
43	typedef unsigned int drm_handle_t;	43	typedef unsigned int drm_handle_t;
44		44
45	#else /* One of the BSDs */	45	#else /* One of the BSDs */
46		46
47	#include	47	#include
48	#include	48	#include
49	typedef int8_t __s8;	49	typedef int8_t __s8;
50	typedef uint8_t __u8;	50	typedef uint8_t __u8;
51	typedef int16_t __s16;	51	typedef int16_t __s16;
52	typedef uint16_t __u16;	52	typedef uint16_t __u16;
53	typedef int32_t __s32;	53	typedef int32_t __s32;
54	typedef uint32_t __u32;	54	typedef uint32_t __u32;
55	typedef int64_t __s64;	55	typedef int64_t __s64;
56	typedef uint64_t __u64;	56	typedef uint64_t __u64;
57	typedef unsigned long drm_handle_t;	57	typedef unsigned long drm_handle_t;
58		58
59	#endif	59	#endif
60		60
61	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /	61	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /
62	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /	62	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /
63	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /	63	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /
64	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /	64	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /
65		65
66	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /	66	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /
67	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /	67	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /
68	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)	68	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
69	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)	69	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
70	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))	70	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))
71		71
72	typedef unsigned int drm_context_t;	72	typedef unsigned int drm_context_t;
73	typedef unsigned int drm_drawable_t;	73	typedef unsigned int drm_drawable_t;
74	typedef unsigned int drm_magic_t;	74	typedef unsigned int drm_magic_t;
75		75
76	/**	76	/**
77	* Cliprect.	77	* Cliprect.
78	*	78	*
79	* \warning: If you change this structure, make sure you change	79	* \warning: If you change this structure, make sure you change
80	* XF86DRIClipRectRec in the server as well	80	* XF86DRIClipRectRec in the server as well
81	*	81	*
82	* \note KW: Actually it's illegal to change either for	82	* \note KW: Actually it's illegal to change either for
83	* backwards-compatibility reasons.	83	* backwards-compatibility reasons.
84	*/	84	*/
85	struct drm_clip_rect {	85	struct drm_clip_rect {
86	unsigned short x1;	86	unsigned short x1;
87	unsigned short y1;	87	unsigned short y1;
88	unsigned short x2;	88	unsigned short x2;
89	unsigned short y2;	89	unsigned short y2;
90	};	90	};
91		91
92	/**	92	/**
93	* Drawable information.	93	* Drawable information.
94	*/	94	*/
95	struct drm_drawable_info {	95	struct drm_drawable_info {
96	unsigned int num_rects;	96	unsigned int num_rects;
97	struct drm_clip_rect *rects;	97	struct drm_clip_rect *rects;
98	};	98	};
99		99
100	/**	100	/**
101	* Texture region,	101	* Texture region,
102	*/	102	*/
103	struct drm_tex_region {	103	struct drm_tex_region {
104	unsigned char next;	104	unsigned char next;
105	unsigned char prev;	105	unsigned char prev;
106	unsigned char in_use;	106	unsigned char in_use;
107	unsigned char padding;	107	unsigned char padding;
108	unsigned int age;	108	unsigned int age;
109	};	109	};
110		110
111	/**	111	/**
112	* Hardware lock.	112	* Hardware lock.
113	*	113	*
114	* The lock structure is a simple cache-line aligned integer. To avoid	114	* The lock structure is a simple cache-line aligned integer. To avoid
115	* processor bus contention on a multiprocessor system, there should not be any	115	* processor bus contention on a multiprocessor system, there should not be any
116	* other data stored in the same cache line.	116	* other data stored in the same cache line.
117	*/	117	*/
118	struct drm_hw_lock {	118	struct drm_hw_lock {
119	__volatile__ unsigned int lock; /*< lock variable /	119	__volatile__ unsigned int lock; /*< lock variable /
120	char padding[60]; /*< Pad to cache line /	120	char padding[60]; /*< Pad to cache line /
121	};	121	};
122		122
123	/**	123	/**
124	* DRM_IOCTL_VERSION ioctl argument type.	124	* DRM_IOCTL_VERSION ioctl argument type.
125	*	125	*
126	* \sa drmGetVersion().	126	* \sa drmGetVersion().
127	*/	127	*/
128	struct drm_version {	128	struct drm_version {
129	int version_major; /*< Major version /	129	int version_major; /*< Major version /
130	int version_minor; /*< Minor version /	130	int version_minor; /*< Minor version /
131	int version_patchlevel; /*< Patch level /	131	int version_patchlevel; /*< Patch level /
132	size_t name_len; /*< Length of name buffer /	132	size_t name_len; /*< Length of name buffer /
133	char __user name; /< Name of driver /	133	char __user name; /< Name of driver /
134	size_t date_len; /*< Length of date buffer /	134	size_t date_len; /*< Length of date buffer /
135	char __user date; /< User-space buffer to hold date /	135	char __user date; /< User-space buffer to hold date /
136	size_t desc_len; /*< Length of desc buffer /	136	size_t desc_len; /*< Length of desc buffer /
137	char __user desc; /< User-space buffer to hold desc /	137	char __user desc; /< User-space buffer to hold desc /
138	};	138	};
139		139
140	/**	140	/**
141	* DRM_IOCTL_GET_UNIQUE ioctl argument type.	141	* DRM_IOCTL_GET_UNIQUE ioctl argument type.
142	*	142	*
143	* \sa drmGetBusid() and drmSetBusId().	143	* \sa drmGetBusid() and drmSetBusId().
144	*/	144	*/
145	struct drm_unique {	145	struct drm_unique {
146	size_t unique_len; /*< Length of unique /	146	size_t unique_len; /*< Length of unique /
147	char __user unique; /< Unique name for driver instantiation /	147	char __user unique; /< Unique name for driver instantiation /
148	};	148	};
149		149
150	struct drm_list {	150	struct drm_list {
151	int count; /*< Length of user-space structures /	151	int count; /*< Length of user-space structures /
152	struct drm_version __user *version;	152	struct drm_version __user *version;
153	};	153	};
154		154
155	struct drm_block {	155	struct drm_block {
156	int unused;	156	int unused;
157	};	157	};
158		158
159	/**	159	/**
160	* DRM_IOCTL_CONTROL ioctl argument type.	160	* DRM_IOCTL_CONTROL ioctl argument type.
161	*	161	*
162	* \sa drmCtlInstHandler() and drmCtlUninstHandler().	162	* \sa drmCtlInstHandler() and drmCtlUninstHandler().
163	*/	163	*/
164	struct drm_control {	164	struct drm_control {
165	enum {	165	enum {
166	DRM_ADD_COMMAND,	166	DRM_ADD_COMMAND,
167	DRM_RM_COMMAND,	167	DRM_RM_COMMAND,
168	DRM_INST_HANDLER,	168	DRM_INST_HANDLER,
169	DRM_UNINST_HANDLER	169	DRM_UNINST_HANDLER
170	} func;	170	} func;
171	int irq;	171	int irq;
172	};	172	};
173		173
174	/**	174	/**
175	* Type of memory to map.	175	* Type of memory to map.
176	*/	176	*/
177	enum drm_map_type {	177	enum drm_map_type {
178	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /	178	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /
179	_DRM_REGISTERS = 1, /*< no caching, no core dump /	179	_DRM_REGISTERS = 1, /*< no caching, no core dump /
180	_DRM_SHM = 2, /*< shared, cached /	180	_DRM_SHM = 2, /*< shared, cached /
181	_DRM_AGP = 3, /*< AGP/GART /	181	_DRM_AGP = 3, /*< AGP/GART /
182	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /	182	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /
183	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /	183	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /
184	_DRM_GEM = 6, /*< GEM object (obsolete) /	-
185	};	184	};
186		185
187	/**	186	/**
188	* Memory mapping flags.	187	* Memory mapping flags.
189	*/	188	*/
190	enum drm_map_flags {	189	enum drm_map_flags {
191	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /	190	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /
192	_DRM_READ_ONLY = 0x02,	191	_DRM_READ_ONLY = 0x02,
193	_DRM_LOCKED = 0x04, /*< shared, cached, locked /	192	_DRM_LOCKED = 0x04, /*< shared, cached, locked /
194	_DRM_KERNEL = 0x08, /*< kernel requires access /	193	_DRM_KERNEL = 0x08, /*< kernel requires access /
195	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /	194	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /
196	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /	195	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /
197	_DRM_REMOVABLE = 0x40, /*< Removable mapping /	196	_DRM_REMOVABLE = 0x40, /*< Removable mapping /
198	_DRM_DRIVER = 0x80 /*< Managed by driver /	197	_DRM_DRIVER = 0x80 /*< Managed by driver /
199	};	198	};
200		199
201	struct drm_ctx_priv_map {	200	struct drm_ctx_priv_map {
202	unsigned int ctx_id; /*< Context requesting private mapping /	201	unsigned int ctx_id; /*< Context requesting private mapping /
203	void handle; /< Handle of map /	202	void handle; /< Handle of map /
204	};	203	};
205		204
206	/**	205	/**
207	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls	206	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
208	* argument type.	207	* argument type.
209	*	208	*
210	* \sa drmAddMap().	209	* \sa drmAddMap().
211	*/	210	*/
212	struct drm_map {	211	struct drm_map {
213	unsigned long offset; /*< Requested physical address (0 for SAREA)/	212	unsigned long offset; /*< Requested physical address (0 for SAREA)/
214	unsigned long size; /*< Requested physical size (bytes) /	213	unsigned long size; /*< Requested physical size (bytes) /
215	enum drm_map_type type; /*< Type of memory to map /	214	enum drm_map_type type; /*< Type of memory to map /
216	enum drm_map_flags flags; /*< Flags /	215	enum drm_map_flags flags; /*< Flags /
217	void handle; /< User-space: "Handle" to pass to mmap() /	216	void handle; /< User-space: "Handle" to pass to mmap() /
218	/*< Kernel-space: kernel-virtual address /	217	/*< Kernel-space: kernel-virtual address /
219	int mtrr; /*< MTRR slot used /	218	int mtrr; /*< MTRR slot used /
220	/* Private data */	219	/* Private data */
221	};	220	};
222		221
223	/**	222	/**
224	* DRM_IOCTL_GET_CLIENT ioctl argument type.	223	* DRM_IOCTL_GET_CLIENT ioctl argument type.
225	*/	224	*/
226	struct drm_client {	225	struct drm_client {
227	int idx; /*< Which client desired? /	226	int idx; /*< Which client desired? /
228	int auth; /*< Is client authenticated? /	227	int auth; /*< Is client authenticated? /
229	unsigned long pid; /*< Process ID /	228	unsigned long pid; /*< Process ID /
230	unsigned long uid; /*< User ID /	229	unsigned long uid; /*< User ID /
231	unsigned long magic; /*< Magic /	230	unsigned long magic; /*< Magic /
232	unsigned long iocs; /*< Ioctl count /	231	unsigned long iocs; /*< Ioctl count /
233	};	232	};
234		233
235	enum drm_stat_type {	234	enum drm_stat_type {
236	_DRM_STAT_LOCK,	235	_DRM_STAT_LOCK,
237	_DRM_STAT_OPENS,	236	_DRM_STAT_OPENS,
238	_DRM_STAT_CLOSES,	237	_DRM_STAT_CLOSES,
239	_DRM_STAT_IOCTLS,	238	_DRM_STAT_IOCTLS,
240	_DRM_STAT_LOCKS,	239	_DRM_STAT_LOCKS,
241	_DRM_STAT_UNLOCKS,	240	_DRM_STAT_UNLOCKS,
242	_DRM_STAT_VALUE, /*< Generic value /	241	_DRM_STAT_VALUE, /*< Generic value /
243	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /	242	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /
244	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /	243	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /
245		244
246	_DRM_STAT_IRQ, /*< IRQ /	245	_DRM_STAT_IRQ, /*< IRQ /
247	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /	246	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /
248	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /	247	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /
249	_DRM_STAT_DMA, /*< DMA /	248	_DRM_STAT_DMA, /*< DMA /
250	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /	249	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /
251	_DRM_STAT_MISSED /*< Missed DMA opportunity /	250	_DRM_STAT_MISSED /*< Missed DMA opportunity /
252	/* Add to the END of the list */	251	/* Add to the END of the list */
253	};	252	};
254		253
255	/**	254	/**
256	* DRM_IOCTL_GET_STATS ioctl argument type.	255	* DRM_IOCTL_GET_STATS ioctl argument type.
257	*/	256	*/
258	struct drm_stats {	257	struct drm_stats {
259	unsigned long count;	258	unsigned long count;
260	struct {	259	struct {
261	unsigned long value;	260	unsigned long value;
262	enum drm_stat_type type;	261	enum drm_stat_type type;
263	} data[15];	262	} data[15];
264	};	263	};
265		264
266	/**	265	/**
267	* Hardware locking flags.	266	* Hardware locking flags.
268	*/	267	*/
269	enum drm_lock_flags {	268	enum drm_lock_flags {
270	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /	269	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /
271	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /	270	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /
272	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /	271	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /
273	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /	272	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /
274	/* These HALT flags aren't supported yet	273	/* These HALT flags aren't supported yet
275	-- they will be used to support the	274	-- they will be used to support the
276	full-screen DGA-like mode. */	275	full-screen DGA-like mode. */
277	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /	276	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /
278	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /	277	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /
279	};	278	};
280		279
281	/**	280	/**
282	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.	281	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
283	*	282	*
284	* \sa drmGetLock() and drmUnlock().	283	* \sa drmGetLock() and drmUnlock().
285	*/	284	*/
286	struct drm_lock {	285	struct drm_lock {
287	int context;	286	int context;
288	enum drm_lock_flags flags;	287	enum drm_lock_flags flags;
289	};	288	};
290		289
291	/**	290	/**
292	* DMA flags	291	* DMA flags
293	*	292	*
294	* \warning	293	* \warning
295	* These values \e must match xf86drm.h.	294	* These values \e must match xf86drm.h.
296	*	295	*
297	* \sa drm_dma.	296	* \sa drm_dma.
298	*/	297	*/
299	enum drm_dma_flags {	298	enum drm_dma_flags {
300	/* Flags for DMA buffer dispatch */	299	/* Flags for DMA buffer dispatch */
301	_DRM_DMA_BLOCK = 0x01, /**<	300	_DRM_DMA_BLOCK = 0x01, /**<
302	* Block until buffer dispatched.	301	* Block until buffer dispatched.
303	*	302	*
304	* \note The buffer may not yet have	303	* \note The buffer may not yet have
305	* been processed by the hardware --	304	* been processed by the hardware --
306	* getting a hardware lock with the	305	* getting a hardware lock with the
307	* hardware quiescent will ensure	306	* hardware quiescent will ensure
308	* that the buffer has been	307	* that the buffer has been
309	* processed.	308	* processed.
310	*/	309	*/
311	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /	310	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /
312	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /	311	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /
313		312
314	/* Flags for DMA buffer request */	313	/* Flags for DMA buffer request */
315	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /	314	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /
316	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /	315	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /
317	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /	316	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /
318	};	317	};
319		318
320	/**	319	/**
321	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.	320	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
322	*	321	*
323	* \sa drmAddBufs().	322	* \sa drmAddBufs().
324	*/	323	*/
325	struct drm_buf_desc {	324	struct drm_buf_desc {
326	int count; /*< Number of buffers of this size /	325	int count; /*< Number of buffers of this size /
327	int size; /*< Size in bytes /	326	int size; /*< Size in bytes /
328	int low_mark; /*< Low water mark /	327	int low_mark; /*< Low water mark /
329	int high_mark; /*< High water mark /	328	int high_mark; /*< High water mark /
330	enum {	329	enum {
331	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /	330	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /
332	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /	331	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /
333	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /	332	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /
334	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /	333	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /
335	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /	334	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /
336	} flags;	335	} flags;
337	unsigned long agp_start; /**<	336	unsigned long agp_start; /**<
338	* Start address of where the AGP buffers are	337	* Start address of where the AGP buffers are
339	* in the AGP aperture	338	* in the AGP aperture
340	*/	339	*/
341	};	340	};
342		341
343	/**	342	/**
344	* DRM_IOCTL_INFO_BUFS ioctl argument type.	343	* DRM_IOCTL_INFO_BUFS ioctl argument type.
345	*/	344	*/
346	struct drm_buf_info {	345	struct drm_buf_info {
347	int count; /*< Entries in list /	346	int count; /*< Entries in list /
348	struct drm_buf_desc __user *list;	347	struct drm_buf_desc __user *list;
349	};	348	};
350		349
351	/**	350	/**
352	* DRM_IOCTL_FREE_BUFS ioctl argument type.	351	* DRM_IOCTL_FREE_BUFS ioctl argument type.
353	*/	352	*/
354	struct drm_buf_free {	353	struct drm_buf_free {
355	int count;	354	int count;
356	int __user *list;	355	int __user *list;
357	};	356	};
358		357
359	/**	358	/**
360	* Buffer information	359	* Buffer information
361	*	360	*
362	* \sa drm_buf_map.	361	* \sa drm_buf_map.
363	*/	362	*/
364	struct drm_buf_pub {	363	struct drm_buf_pub {
365	int idx; /*< Index into the master buffer list /	364	int idx; /*< Index into the master buffer list /
366	int total; /*< Buffer size /	365	int total; /*< Buffer size /
367	int used; /*< Amount of buffer in use (for DMA) /	366	int used; /*< Amount of buffer in use (for DMA) /
368	void __user address; /< Address of buffer /	367	void __user address; /< Address of buffer /
369	};	368	};
370		369
371	/**	370	/**
372	* DRM_IOCTL_MAP_BUFS ioctl argument type.	371	* DRM_IOCTL_MAP_BUFS ioctl argument type.
373	*/	372	*/
374	struct drm_buf_map {	373	struct drm_buf_map {
375	int count; /*< Length of the buffer list /	374	int count; /*< Length of the buffer list /
376	void __user virtual; /< Mmap'd area in user-virtual /	375	void __user virtual; /< Mmap'd area in user-virtual /
377	struct drm_buf_pub __user list; /< Buffer information /	376	struct drm_buf_pub __user list; /< Buffer information /
378	};	377	};
379		378
380	/**	379	/**
381	* DRM_IOCTL_DMA ioctl argument type.	380	* DRM_IOCTL_DMA ioctl argument type.
382	*	381	*
383	* Indices here refer to the offset into the buffer list in drm_buf_get.	382	* Indices here refer to the offset into the buffer list in drm_buf_get.
384	*	383	*
385	* \sa drmDMA().	384	* \sa drmDMA().
386	*/	385	*/
387	struct drm_dma {	386	struct drm_dma {
388	int context; /*< Context handle /	387	int context; /*< Context handle /
389	int send_count; /*< Number of buffers to send /	388	int send_count; /*< Number of buffers to send /
390	int __user send_indices; /< List of handles to buffers /	389	int __user send_indices; /< List of handles to buffers /
391	int __user send_sizes; /< Lengths of data to send /	390	int __user send_sizes; /< Lengths of data to send /
392	enum drm_dma_flags flags; /*< Flags /	391	enum drm_dma_flags flags; /*< Flags /
393	int request_count; /*< Number of buffers requested /	392	int request_count; /*< Number of buffers requested /
394	int request_size; /*< Desired size for buffers /	393	int request_size; /*< Desired size for buffers /
395	int __user request_indices; /< Buffer information /	394	int __user request_indices; /< Buffer information /
396	int __user *request_sizes;	395	int __user *request_sizes;
397	int granted_count; /*< Number of buffers granted /	396	int granted_count; /*< Number of buffers granted /
398	};	397	};
399		398
400	enum drm_ctx_flags {	399	enum drm_ctx_flags {
401	_DRM_CONTEXT_PRESERVED = 0x01,	400	_DRM_CONTEXT_PRESERVED = 0x01,
402	_DRM_CONTEXT_2DONLY = 0x02	401	_DRM_CONTEXT_2DONLY = 0x02
403	};	402	};
404		403
405	/**	404	/**
406	* DRM_IOCTL_ADD_CTX ioctl argument type.	405	* DRM_IOCTL_ADD_CTX ioctl argument type.
407	*	406	*
408	* \sa drmCreateContext() and drmDestroyContext().	407	* \sa drmCreateContext() and drmDestroyContext().
409	*/	408	*/
410	struct drm_ctx {	409	struct drm_ctx {
411	drm_context_t handle;	410	drm_context_t handle;
412	enum drm_ctx_flags flags;	411	enum drm_ctx_flags flags;
413	};	412	};
414		413
415	/**	414	/**
416	* DRM_IOCTL_RES_CTX ioctl argument type.	415	* DRM_IOCTL_RES_CTX ioctl argument type.
417	*/	416	*/
418	struct drm_ctx_res {	417	struct drm_ctx_res {
419	int count;	418	int count;
420	struct drm_ctx __user *contexts;	419	struct drm_ctx __user *contexts;
421	};	420	};
422		421
423	/**	422	/**
424	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.	423	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
425	*/	424	*/
426	struct drm_draw {	425	struct drm_draw {
427	drm_drawable_t handle;	426	drm_drawable_t handle;
428	};	427	};
429		428
430	/**	429	/**
431	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.	430	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
432	*/	431	*/
433	typedef enum {	432	typedef enum {
434	DRM_DRAWABLE_CLIPRECTS,	433	DRM_DRAWABLE_CLIPRECTS,
435	} drm_drawable_info_type_t;	434	} drm_drawable_info_type_t;
436		435
437	struct drm_update_draw {	436	struct drm_update_draw {
438	drm_drawable_t handle;	437	drm_drawable_t handle;
439	unsigned int type;	438	unsigned int type;
440	unsigned int num;	439	unsigned int num;
441	unsigned long long data;	440	unsigned long long data;
442	};	441	};
443		442
444	/**	443	/**
445	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.	444	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
446	*/	445	*/
447	struct drm_auth {	446	struct drm_auth {
448	drm_magic_t magic;	447	drm_magic_t magic;
449	};	448	};
450		449
451	/**	450	/**
452	* DRM_IOCTL_IRQ_BUSID ioctl argument type.	451	* DRM_IOCTL_IRQ_BUSID ioctl argument type.
453	*	452	*
454	* \sa drmGetInterruptFromBusID().	453	* \sa drmGetInterruptFromBusID().
455	*/	454	*/
456	struct drm_irq_busid {	455	struct drm_irq_busid {
457	int irq; /*< IRQ number /	456	int irq; /*< IRQ number /
458	int busnum; /*< bus number /	457	int busnum; /*< bus number /
459	int devnum; /*< device number /	458	int devnum; /*< device number /
460	int funcnum; /*< function number /	459	int funcnum; /*< function number /
461	};	460	};
462		461
463	enum drm_vblank_seq_type {	462	enum drm_vblank_seq_type {
464	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /	463	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /
465	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /	464	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /
466	/* bits 1-6 are reserved for high crtcs */	465	/* bits 1-6 are reserved for high crtcs */
467	_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,	466	_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
468	_DRM_VBLANK_EVENT = 0x4000000, /*< Send event instead of blocking /	467	_DRM_VBLANK_EVENT = 0x4000000, /*< Send event instead of blocking /
469	_DRM_VBLANK_FLIP = 0x8000000, /*< Scheduled buffer swap should flip /	468	_DRM_VBLANK_FLIP = 0x8000000, /*< Scheduled buffer swap should flip /
470	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /	469	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /
471	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /	470	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /
472	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking, unsupported /	471	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking, unsupported /
473	};	472	};
474	#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1	473	#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
475		474
476	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)	475	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)
477	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT \| _DRM_VBLANK_SIGNAL \| \	476	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT \| _DRM_VBLANK_SIGNAL \| \
478	_DRM_VBLANK_SECONDARY \| _DRM_VBLANK_NEXTONMISS)	477	_DRM_VBLANK_SECONDARY \| _DRM_VBLANK_NEXTONMISS)
479		478
480	struct drm_wait_vblank_request {	479	struct drm_wait_vblank_request {
481	enum drm_vblank_seq_type type;	480	enum drm_vblank_seq_type type;
482	unsigned int sequence;	481	unsigned int sequence;
483	unsigned long signal;	482	unsigned long signal;
484	};	483	};
485		484
486	struct drm_wait_vblank_reply {	485	struct drm_wait_vblank_reply {
487	enum drm_vblank_seq_type type;	486	enum drm_vblank_seq_type type;
488	unsigned int sequence;	487	unsigned int sequence;
489	long tval_sec;	488	long tval_sec;
490	long tval_usec;	489	long tval_usec;
491	};	490	};
492		491
493	/**	492	/**
494	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.	493	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
495	*	494	*
496	* \sa drmWaitVBlank().	495	* \sa drmWaitVBlank().
497	*/	496	*/
498	union drm_wait_vblank {	497	union drm_wait_vblank {
499	struct drm_wait_vblank_request request;	498	struct drm_wait_vblank_request request;
500	struct drm_wait_vblank_reply reply;	499	struct drm_wait_vblank_reply reply;

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(root)/drivers/include/linux/uapi/drm/drm.h – Rev 4244 → 4559