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Rev 2967 | Rev 3031 | ||
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Line 24... | Line 24... | ||
24 | 24 | ||
25 | /* |
25 | /* |
26 | * Under PCI, each device has 256 bytes of configuration address space, |
26 | * Under PCI, each device has 256 bytes of configuration address space, |
27 | * of which the first 64 bytes are standardized as follows: |
27 | * of which the first 64 bytes are standardized as follows: |
- | 28 | */ |
|
28 | */ |
29 | #define PCI_STD_HEADER_SIZEOF 64 |
29 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
30 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
30 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
31 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
31 | #define PCI_COMMAND 0x04 /* 16 bits */ |
32 | #define PCI_COMMAND 0x04 /* 16 bits */ |
32 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
33 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
Line 123... | Line 124... | ||
123 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
124 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
124 | #define PCI_IO_LIMIT 0x1d |
125 | #define PCI_IO_LIMIT 0x1d |
125 | #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ |
126 | #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ |
126 | #define PCI_IO_RANGE_TYPE_16 0x00 |
127 | #define PCI_IO_RANGE_TYPE_16 0x00 |
127 | #define PCI_IO_RANGE_TYPE_32 0x01 |
128 | #define PCI_IO_RANGE_TYPE_32 0x01 |
128 | #define PCI_IO_RANGE_MASK (~0x0fUL) |
129 | #define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ |
- | 130 | #define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ |
|
129 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
131 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
130 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
132 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
131 | #define PCI_MEMORY_LIMIT 0x22 |
133 | #define PCI_MEMORY_LIMIT 0x22 |
132 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL |
134 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL |
133 | #define PCI_MEMORY_RANGE_MASK (~0x0fUL) |
135 | #define PCI_MEMORY_RANGE_MASK (~0x0fUL) |
Line 207... | Line 209... | ||
207 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
209 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
208 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
210 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
209 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
211 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
210 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
212 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
211 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ |
213 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ |
- | 214 | #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ |
|
212 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
215 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
213 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
216 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
- | 217 | #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ |
|
214 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
218 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
- | 219 | #define PCI_CAP_ID_MAX PCI_CAP_ID_AF |
|
215 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
220 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
216 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
221 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
217 | #define PCI_CAP_SIZEOF 4 |
222 | #define PCI_CAP_SIZEOF 4 |
Line 218... | Line 223... | ||
218 | 223 | ||
Line 274... | Line 279... | ||
274 | 279 | ||
275 | #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ |
280 | #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ |
276 | #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ |
281 | #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ |
277 | #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ |
282 | #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ |
- | 283 | #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ |
|
Line 278... | Line 284... | ||
278 | #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ |
284 | #define PCI_CAP_VPD_SIZEOF 8 |
Line 279... | Line 285... | ||
279 | 285 | ||
280 | /* Slot Identification */ |
286 | /* Slot Identification */ |
Line 295... | Line 301... | ||
295 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
301 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
296 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ |
302 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ |
297 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
303 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
298 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
304 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
299 | #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
305 | #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
- | 306 | #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ |
|
300 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
307 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
301 | #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
308 | #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
- | 309 | #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ |
|
Line 302... | Line 310... | ||
302 | 310 | ||
303 | /* MSI-X registers */ |
311 | /* MSI-X registers */ |
304 | #define PCI_MSIX_FLAGS 2 |
312 | #define PCI_MSIX_FLAGS 2 |
305 | #define PCI_MSIX_FLAGS_QSIZE 0x7FF |
313 | #define PCI_MSIX_FLAGS_QSIZE 0x7FF |
306 | #define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
314 | #define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
307 | #define PCI_MSIX_FLAGS_MASKALL (1 << 14) |
315 | #define PCI_MSIX_FLAGS_MASKALL (1 << 14) |
308 | #define PCI_MSIX_TABLE 4 |
316 | #define PCI_MSIX_TABLE 4 |
309 | #define PCI_MSIX_PBA 8 |
317 | #define PCI_MSIX_PBA 8 |
- | 318 | #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
|
Line 310... | Line 319... | ||
310 | #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
319 | #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ |
311 | 320 | ||
312 | /* MSI-X entry's format */ |
321 | /* MSI-X entry's format */ |
313 | #define PCI_MSIX_ENTRY_SIZE 16 |
322 | #define PCI_MSIX_ENTRY_SIZE 16 |
Line 336... | Line 345... | ||
336 | #define PCI_AF_CAP_FLR 0x02 |
345 | #define PCI_AF_CAP_FLR 0x02 |
337 | #define PCI_AF_CTRL 4 |
346 | #define PCI_AF_CTRL 4 |
338 | #define PCI_AF_CTRL_FLR 0x01 |
347 | #define PCI_AF_CTRL_FLR 0x01 |
339 | #define PCI_AF_STATUS 5 |
348 | #define PCI_AF_STATUS 5 |
340 | #define PCI_AF_STATUS_TP 0x01 |
349 | #define PCI_AF_STATUS_TP 0x01 |
- | 350 | #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ |
|
Line 341... | Line 351... | ||
341 | 351 | ||
Line 342... | Line 352... | ||
342 | /* PCI-X registers */ |
352 | /* PCI-X registers */ |
343 | 353 | ||
Line 372... | Line 382... | ||
372 | #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ |
382 | #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ |
373 | #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ |
383 | #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ |
374 | #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
384 | #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
375 | #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
385 | #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
376 | #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
386 | #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
- | 387 | #define PCI_X_ECC_CSR 8 /* ECC control and status */ |
|
- | 388 | #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ |
|
- | 389 | #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ |
|
- | 390 | #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ |
|
Line 377... | Line 391... | ||
377 | 391 | ||
Line 378... | Line 392... | ||
378 | /* PCI Bridge Subsystem ID registers */ |
392 | /* PCI Bridge Subsystem ID registers */ |
379 | 393 | ||
Line 389... | Line 403... | ||
389 | #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ |
403 | #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ |
390 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ |
404 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ |
391 | #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ |
405 | #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ |
392 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ |
406 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ |
393 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ |
407 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ |
- | 408 | #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */ |
|
394 | #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ |
409 | #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ |
395 | #define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */ |
410 | #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ |
396 | #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
411 | #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
397 | #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ |
412 | #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ |
398 | #define PCI_EXP_DEVCAP 4 /* Device capabilities */ |
413 | #define PCI_EXP_DEVCAP 4 /* Device capabilities */ |
399 | #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ |
414 | #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ |
400 | #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ |
415 | #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ |
Line 459... | Line 474... | ||
459 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
474 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
460 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
475 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
461 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
476 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
462 | #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ |
477 | #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ |
463 | #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ |
478 | #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ |
- | 479 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */ |
|
464 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
480 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
465 | #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
481 | #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
466 | #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ |
482 | #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ |
467 | #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ |
483 | #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ |
468 | #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ |
484 | #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ |
Line 504... | Line 520... | ||
504 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
520 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
505 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
521 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
506 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
522 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
507 | #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ |
523 | #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ |
508 | #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ |
524 | #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ |
- | 525 | /* |
|
- | 526 | * Note that the following PCI Express 'Capability Structure' registers |
|
- | 527 | * were introduced with 'Capability Version' 0x2 (v2). These registers |
|
- | 528 | * do not exist on devices with Capability Version 1. Use pci_pcie_cap2() |
|
- | 529 | * to use these fields safely. |
|
- | 530 | */ |
|
509 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
531 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
510 | #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
532 | #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
511 | #define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ |
533 | #define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ |
512 | #define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */ |
534 | #define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */ |
513 | #define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */ |
535 | #define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */ |
Line 518... | Line 540... | ||
518 | #define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */ |
540 | #define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */ |
519 | #define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */ |
541 | #define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */ |
520 | #define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ |
542 | #define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ |
521 | #define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ |
543 | #define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ |
522 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
544 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
- | 545 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ |
|
- | 546 | #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ |
|
- | 547 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ |
|
- | 548 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ |
|
- | 549 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ |
|
- | 550 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ |
|
523 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
551 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
- | 552 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |
|
524 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
553 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
Line 525... | Line 554... | ||
525 | 554 | ||
526 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
555 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
527 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |
556 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |
528 | #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) |
557 | #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) |
Line -... | Line 558... | ||
- | 558 | #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) |
|
- | 559 | ||
- | 560 | #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ |
|
529 | #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) |
561 | #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ |
- | 562 | #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ |
|
- | 563 | #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ |
|
- | 564 | #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ |
|
- | 565 | #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ |
|
530 | 566 | #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ |
|
- | 567 | #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ |
|
531 | #define PCI_EXT_CAP_ID_ERR 1 |
568 | #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ |
- | 569 | #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ |
|
- | 570 | #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */ |
|
- | 571 | #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ |
|
- | 572 | #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ |
|
- | 573 | #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ |
|
- | 574 | #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ |
|
532 | #define PCI_EXT_CAP_ID_VC 2 |
575 | #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ |
- | 576 | #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ |
|
- | 577 | #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ |
|
533 | #define PCI_EXT_CAP_ID_DSN 3 |
578 | #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ |
- | 579 | #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */ |
|
534 | #define PCI_EXT_CAP_ID_PWR 4 |
580 | #define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */ |
- | 581 | #define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */ |
|
535 | #define PCI_EXT_CAP_ID_VNDR 11 |
582 | #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */ |
- | 583 | #define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */ |
|
- | 584 | #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */ |
|
536 | #define PCI_EXT_CAP_ID_ACS 13 |
585 | #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ |
- | 586 | #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ |
|
537 | #define PCI_EXT_CAP_ID_ARI 14 |
587 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID |
538 | #define PCI_EXT_CAP_ID_ATS 15 |
588 | |
Line 539... | Line 589... | ||
539 | #define PCI_EXT_CAP_ID_SRIOV 16 |
589 | #define PCI_EXT_CAP_DSN_SIZEOF 12 |
540 | #define PCI_EXT_CAP_ID_LTR 24 |
590 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 |
541 | 591 | ||
542 | /* Advanced Error Reporting */ |
592 | /* Advanced Error Reporting */ |
- | 593 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
|
543 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
594 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
544 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
595 | #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
545 | #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
596 | #define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ |
546 | #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
597 | #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
547 | #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ |
598 | #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ |
548 | #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ |
599 | #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ |
549 | #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ |
600 | #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ |
550 | #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ |
601 | #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ |
551 | #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ |
602 | #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ |
- | 603 | #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ |
|
- | 604 | #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ |
|
- | 605 | #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ |
|
- | 606 | #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ |
|
- | 607 | #define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ |
|
552 | #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ |
608 | #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ |
553 | #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ |
609 | #define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ |
554 | #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ |
610 | #define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ |
555 | #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
611 | #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
556 | /* Same bits as above */ |
612 | /* Same bits as above */ |
557 | #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ |
613 | #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ |
558 | /* Same bits as above */ |
614 | /* Same bits as above */ |
559 | #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ |
615 | #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ |
560 | #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ |
616 | #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ |
561 | #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ |
617 | #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ |
- | 618 | #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
|
- | 619 | #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ |
|
- | 620 | #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ |
|
562 | #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
621 | #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ |
563 | #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ |
622 | #define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ |
564 | #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ |
623 | #define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ |
565 | #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
624 | #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
566 | /* Same bits as above */ |
625 | /* Same bits as above */ |
Line 591... | Line 650... | ||
591 | #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ |
650 | #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ |
592 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
651 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
Line 593... | Line 652... | ||
593 | 652 | ||
594 | /* Virtual Channel */ |
653 | /* Virtual Channel */ |
- | 654 | #define PCI_VC_PORT_REG1 4 |
|
595 | #define PCI_VC_PORT_REG1 4 |
655 | #define PCI_VC_REG1_EVCC 0x7 /* extended vc count */ |
- | 656 | #define PCI_VC_PORT_REG2 8 |
|
- | 657 | #define PCI_VC_REG2_32_PHASE 0x2 |
|
- | 658 | #define PCI_VC_REG2_64_PHASE 0x4 |
|
596 | #define PCI_VC_PORT_REG2 8 |
659 | #define PCI_VC_REG2_128_PHASE 0x8 |
597 | #define PCI_VC_PORT_CTRL 12 |
660 | #define PCI_VC_PORT_CTRL 12 |
598 | #define PCI_VC_PORT_STATUS 14 |
661 | #define PCI_VC_PORT_STATUS 14 |
599 | #define PCI_VC_RES_CAP 16 |
662 | #define PCI_VC_RES_CAP 16 |
600 | #define PCI_VC_RES_CTRL 20 |
663 | #define PCI_VC_RES_CTRL 20 |
- | 664 | #define PCI_VC_RES_STATUS 26 |
|
- | 665 | #define PCI_CAP_VC_BASE_SIZEOF 0x10 |
|
Line 601... | Line 666... | ||
601 | #define PCI_VC_RES_STATUS 26 |
666 | #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C |
602 | 667 | ||
603 | /* Power Budgeting */ |
668 | /* Power Budgeting */ |
604 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
669 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
Line 609... | Line 674... | ||
609 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
674 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
610 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
675 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
611 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
676 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
612 | #define PCI_PWR_CAP 12 /* Capability */ |
677 | #define PCI_PWR_CAP 12 /* Capability */ |
613 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
678 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
- | 679 | #define PCI_EXT_CAP_PWR_SIZEOF 16 |
|
- | 680 | ||
- | 681 | /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ |
|
- | 682 | #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ |
|
- | 683 | #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) |
|
- | 684 | #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) |
|
- | 685 | #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) |
|
Line 614... | Line 686... | ||
614 | 686 | ||
615 | /* |
687 | /* |
616 | * Hypertransport sub capability types |
688 | * Hypertransport sub capability types |
617 | * |
689 | * |
Line 641... | Line 713... | ||
641 | #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ |
713 | #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ |
642 | #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ |
714 | #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ |
643 | #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ |
715 | #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ |
644 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ |
716 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ |
645 | #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ |
717 | #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ |
- | 718 | #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ |
|
- | 719 | #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ |
|
Line 646... | Line 720... | ||
646 | 720 | ||
647 | /* Alternative Routing-ID Interpretation */ |
721 | /* Alternative Routing-ID Interpretation */ |
648 | #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ |
722 | #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ |
649 | #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ |
723 | #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ |
650 | #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ |
724 | #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ |
651 | #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ |
725 | #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ |
652 | #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ |
726 | #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ |
653 | #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ |
727 | #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ |
654 | #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ |
728 | #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ |
- | 729 | #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ |
|
Line 655... | Line 730... | ||
655 | #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ |
730 | #define PCI_EXT_CAP_ARI_SIZEOF 8 |
656 | 731 | ||
657 | /* Address Translation Service */ |
732 | /* Address Translation Service */ |
658 | #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ |
733 | #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ |
659 | #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ |
734 | #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ |
660 | #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ |
735 | #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ |
661 | #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ |
736 | #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ |
662 | #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ |
737 | #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ |
- | 738 | #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ |
|
Line 663... | Line 739... | ||
663 | #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ |
739 | #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ |
664 | #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ |
- | |
665 | 740 | #define PCI_EXT_CAP_ATS_SIZEOF 8 |
|
666 | /* Page Request Interface */ |
741 | |
667 | #define PCI_PRI_CAP 0x13 /* PRI capability ID */ |
742 | /* Page Request Interface */ |
668 | #define PCI_PRI_CONTROL_OFF 0x04 /* Offset of control register */ |
743 | #define PCI_PRI_CTRL 0x04 /* PRI control register */ |
669 | #define PCI_PRI_STATUS_OFF 0x06 /* Offset of status register */ |
744 | #define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ |
670 | #define PCI_PRI_ENABLE 0x0001 /* Enable mask */ |
745 | #define PCI_PRI_CTRL_RESET 0x02 /* Reset */ |
671 | #define PCI_PRI_RESET 0x0002 /* Reset bit mask */ |
746 | #define PCI_PRI_STATUS 0x06 /* PRI status register */ |
672 | #define PCI_PRI_STATUS_RF 0x0001 /* Request Failure */ |
747 | #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ |
673 | #define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ |
748 | #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ |
- | 749 | #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ |
|
Line 674... | Line 750... | ||
674 | #define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ |
750 | #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ |
675 | #define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */ |
751 | #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ |
- | 752 | #define PCI_EXT_CAP_PRI_SIZEOF 16 |
|
676 | #define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */ |
753 | |
677 | 754 | /* PASID capability */ |
|
678 | /* PASID capability */ |
755 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ |
679 | #define PCI_PASID_CAP 0x1b /* PASID capability ID */ |
756 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ |
680 | #define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */ |
757 | #define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */ |
- | 758 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ |
|
Line 681... | Line 759... | ||
681 | #define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */ |
759 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ |
682 | #define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */ |
760 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ |
683 | #define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */ |
761 | #define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */ |
684 | #define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */ |
762 | #define PCI_EXT_CAP_PASID_SIZEOF 8 |
Line 711... | Line 789... | ||
711 | #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ |
789 | #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ |
712 | #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ |
790 | #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ |
713 | #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ |
791 | #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ |
714 | #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
792 | #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
715 | #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
793 | #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
- | 794 | #define PCI_EXT_CAP_SRIOV_SIZEOF 64 |
|
Line 716... | Line 795... | ||
716 | 795 | ||
717 | #define PCI_LTR_MAX_SNOOP_LAT 0x4 |
796 | #define PCI_LTR_MAX_SNOOP_LAT 0x4 |
718 | #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 |
797 | #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 |
719 | #define PCI_LTR_VALUE_MASK 0x000003ff |
798 | #define PCI_LTR_VALUE_MASK 0x000003ff |
720 | #define PCI_LTR_SCALE_MASK 0x00001c00 |
799 | #define PCI_LTR_SCALE_MASK 0x00001c00 |
- | 800 | #define PCI_LTR_SCALE_SHIFT 10 |
|
Line 721... | Line 801... | ||
721 | #define PCI_LTR_SCALE_SHIFT 10 |
801 | #define PCI_EXT_CAP_LTR_SIZEOF 8 |
722 | 802 | ||
723 | /* Access Control Service */ |
803 | /* Access Control Service */ |
724 | #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
804 | #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
725 | #define PCI_ACS_SV 0x01 /* Source Validation */ |
805 | #define PCI_ACS_SV 0x01 /* Source Validation */ |
726 | #define PCI_ACS_TB 0x02 /* Translation Blocking */ |
806 | #define PCI_ACS_TB 0x02 /* Translation Blocking */ |
727 | #define PCI_ACS_RR 0x04 /* P2P Request Redirect */ |
807 | #define PCI_ACS_RR 0x04 /* P2P Request Redirect */ |
728 | #define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ |
808 | #define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ |
729 | #define PCI_ACS_UF 0x10 /* Upstream Forwarding */ |
809 | #define PCI_ACS_UF 0x10 /* Upstream Forwarding */ |
- | 810 | #define PCI_ACS_EC 0x20 /* P2P Egress Control */ |
|
730 | #define PCI_ACS_EC 0x20 /* P2P Egress Control */ |
811 | #define PCI_ACS_DT 0x40 /* Direct Translated P2P */ |
731 | #define PCI_ACS_DT 0x40 /* Direct Translated P2P */ |
812 | #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ |
Line -... | Line 813... | ||
- | 813 | #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
|
- | 814 | #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ |
|
- | 815 | ||
- | 816 | #define PCI_VSEC_HDR 4 /* extended cap - vendor specific */ |
|
- | 817 | #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ |
|
- | 818 | ||
- | 819 | /* sata capability */ |
|
- | 820 | #define PCI_SATA_REGS 4 /* SATA REGs specifier */ |
|
- | 821 | #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ |
|
- | 822 | #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ |
|
- | 823 | #define PCI_SATA_SIZEOF_SHORT 8 |
|
- | 824 | #define PCI_SATA_SIZEOF_LONG 16 |
|
- | 825 | ||
- | 826 | /* resizable BARs */ |
|
- | 827 | #define PCI_REBAR_CTRL 8 /* control register */ |
|
- | 828 | #define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ |
|
- | 829 | #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ |
|
- | 830 | ||
- | 831 | /* dynamic power allocation */ |
|
- | 832 | #define PCI_DPA_CAP 4 /* capability register */ |
|
- | 833 | #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ |
|
- | 834 | #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ |
|
- | 835 | ||
- | 836 | /* TPH Requester */ |
|
- | 837 | #define PCI_TPH_CAP 4 /* capability register */ |
|
- | 838 | #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ |
|
- | 839 | #define PCI_TPH_LOC_NONE 0x000 /* no location */ |
|
- | 840 | #define PCI_TPH_LOC_CAP 0x200 /* in capability */ |
|
- | 841 | #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ |
|
- | 842 | #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ |
|
732 | #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
843 | #define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ |