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1 | #ifndef __PCI_H__ |
1 | #ifndef __PCI_H__ |
2 | #define __PCI_H__ |
2 | #define __PCI_H__ |
3 | 3 | ||
4 | #include |
4 | #include |
5 | #include |
5 | #include |
6 | #include |
6 | #include |
7 | #include |
7 | #include |
8 | #include |
8 | #include |
9 | 9 | ||
10 | /* pci_slot represents a physical slot */ |
10 | /* pci_slot represents a physical slot */ |
11 | struct pci_slot { |
11 | struct pci_slot { |
12 | struct pci_bus *bus; /* The bus this slot is on */ |
12 | struct pci_bus *bus; /* The bus this slot is on */ |
13 | struct list_head list; /* node in list of slots on this bus */ |
13 | struct list_head list; /* node in list of slots on this bus */ |
14 | // struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
14 | // struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
15 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
15 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
16 | // struct kobject kobj; |
16 | // struct kobject kobj; |
17 | }; |
17 | }; |
18 | 18 | ||
19 | 19 | ||
20 | #define PCI_ANY_ID (~0) |
20 | #define PCI_ANY_ID (~0) |
21 | 21 | ||
22 | 22 | ||
23 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
23 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
24 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
24 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
25 | 25 | ||
26 | #define PCI_BASE_CLASS_STORAGE 0x01 |
26 | #define PCI_BASE_CLASS_STORAGE 0x01 |
27 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
27 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
28 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
28 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
29 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
29 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
30 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
30 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
31 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
31 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
32 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
32 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
33 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
33 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
34 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
34 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
35 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
35 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
36 | 36 | ||
37 | #define PCI_BASE_CLASS_NETWORK 0x02 |
37 | #define PCI_BASE_CLASS_NETWORK 0x02 |
38 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
38 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
39 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
39 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
40 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
40 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
41 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
41 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
42 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
42 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
43 | 43 | ||
44 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
44 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
45 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
45 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
46 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
46 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
47 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
47 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
48 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
48 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
49 | 49 | ||
50 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
50 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
51 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
51 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
52 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
52 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
53 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
53 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
54 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
54 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
55 | 55 | ||
56 | #define PCI_BASE_CLASS_MEMORY 0x05 |
56 | #define PCI_BASE_CLASS_MEMORY 0x05 |
57 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
57 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
58 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
58 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
59 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
59 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
60 | 60 | ||
61 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
61 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
62 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
62 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
63 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
63 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
64 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
64 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
65 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
65 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
66 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
66 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
67 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
67 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
68 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
68 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
69 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
69 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
70 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
70 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
71 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
71 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
72 | 72 | ||
73 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
73 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
74 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
74 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
75 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
75 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
76 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
76 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
77 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
77 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
78 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
78 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
79 | 79 | ||
80 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
80 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
81 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
81 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
82 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
82 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
83 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
83 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
84 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
84 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
85 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
85 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
86 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
86 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
87 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
87 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
88 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
88 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
89 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
89 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
90 | 90 | ||
91 | #define PCI_BASE_CLASS_INPUT 0x09 |
91 | #define PCI_BASE_CLASS_INPUT 0x09 |
92 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
92 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
93 | #define PCI_CLASS_INPUT_PEN 0x0901 |
93 | #define PCI_CLASS_INPUT_PEN 0x0901 |
94 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
94 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
95 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
95 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
96 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
96 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
97 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
97 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
98 | 98 | ||
99 | #define PCI_BASE_CLASS_DOCKING 0x0a |
99 | #define PCI_BASE_CLASS_DOCKING 0x0a |
100 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
100 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
101 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
101 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
102 | 102 | ||
103 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
103 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
104 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
104 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
105 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
105 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
106 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
106 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
107 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
107 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
108 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
108 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
109 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
109 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
110 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
110 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
111 | 111 | ||
112 | #define PCI_BASE_CLASS_SERIAL 0x0c |
112 | #define PCI_BASE_CLASS_SERIAL 0x0c |
113 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
113 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
114 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
114 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
115 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
115 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
116 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
116 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
117 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
117 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
118 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
118 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
119 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
119 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
120 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
120 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
121 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
121 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
122 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
122 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
123 | 123 | ||
124 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
124 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
125 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
125 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
126 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
126 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
127 | 127 | ||
128 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
128 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
129 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
129 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
130 | 130 | ||
131 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
131 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
132 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
132 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
133 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
133 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
134 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
134 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
135 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
135 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
136 | 136 | ||
137 | #define PCI_BASE_CLASS_CRYPT 0x10 |
137 | #define PCI_BASE_CLASS_CRYPT 0x10 |
138 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
138 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
139 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
139 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
140 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
140 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
141 | 141 | ||
142 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
142 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
143 | #define PCI_CLASS_SP_DPIO 0x1100 |
143 | #define PCI_CLASS_SP_DPIO 0x1100 |
144 | #define PCI_CLASS_SP_OTHER 0x1180 |
144 | #define PCI_CLASS_SP_OTHER 0x1180 |
145 | 145 | ||
146 | #define PCI_CLASS_OTHERS 0xff |
146 | #define PCI_CLASS_OTHERS 0xff |
147 | 147 | ||
148 | 148 | ||
149 | 149 | ||
150 | #define PCI_MAP_REG_START 0x10 |
150 | #define PCI_MAP_REG_START 0x10 |
151 | #define PCI_MAP_REG_END 0x28 |
151 | #define PCI_MAP_REG_END 0x28 |
152 | #define PCI_MAP_ROM_REG 0x30 |
152 | #define PCI_MAP_ROM_REG 0x30 |
153 | 153 | ||
154 | #define PCI_MAP_MEMORY 0x00000000 |
154 | #define PCI_MAP_MEMORY 0x00000000 |
155 | #define PCI_MAP_IO 0x00000001 |
155 | #define PCI_MAP_IO 0x00000001 |
156 | 156 | ||
157 | #define PCI_MAP_MEMORY_TYPE 0x00000007 |
157 | #define PCI_MAP_MEMORY_TYPE 0x00000007 |
158 | #define PCI_MAP_IO_TYPE 0x00000003 |
158 | #define PCI_MAP_IO_TYPE 0x00000003 |
159 | 159 | ||
160 | #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
160 | #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
161 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
161 | #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
162 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
162 | #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
163 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
163 | #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
164 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
164 | #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
165 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
165 | #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
166 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
166 | #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
167 | 167 | ||
168 | #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
168 | #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
169 | 169 | ||
170 | 170 | ||
171 | 171 | ||
172 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
172 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
173 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
173 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
174 | 174 | ||
175 | #define PCI_MAP_IS64BITMEM(b) \ |
175 | #define PCI_MAP_IS64BITMEM(b) \ |
176 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
176 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
177 | 177 | ||
178 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
178 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
179 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
179 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
180 | #define PCIGETMEMORY64(b) \ |
180 | #define PCIGETMEMORY64(b) \ |
181 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
181 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
182 | 182 | ||
183 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
183 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
184 | 184 | ||
185 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
185 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
186 | 186 | ||
187 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
187 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
188 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
188 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
189 | 189 | ||
190 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
190 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
191 | 191 | ||
192 | 192 | ||
193 | #ifndef PCI_DOM_MASK |
193 | #ifndef PCI_DOM_MASK |
194 | # define PCI_DOM_MASK 0x0ffu |
194 | # define PCI_DOM_MASK 0x0ffu |
195 | #endif |
195 | #endif |
196 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
196 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
197 | 197 | ||
198 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
198 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
199 | (((d) & 0x00001fu) << 11) | \ |
199 | (((d) & 0x00001fu) << 11) | \ |
200 | (((f) & 0x000007u) << 8)) |
200 | (((f) & 0x000007u) << 8)) |
201 | 201 | ||
202 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
202 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
203 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
203 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
204 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
204 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
205 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
205 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
206 | 206 | ||
207 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
207 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
208 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
208 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
209 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
209 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
210 | 210 | ||
211 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ |
211 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ |
212 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) |
212 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) |
213 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ |
213 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ |
214 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ |
214 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ |
215 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ |
215 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ |
216 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ |
216 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ |
217 | 217 | ||
218 | 218 | ||
219 | typedef unsigned int __bitwise pci_channel_state_t; |
219 | typedef unsigned int __bitwise pci_channel_state_t; |
220 | 220 | ||
221 | enum pci_channel_state { |
221 | enum pci_channel_state { |
222 | /* I/O channel is in normal state */ |
222 | /* I/O channel is in normal state */ |
223 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
223 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
224 | 224 | ||
225 | /* I/O to channel is blocked */ |
225 | /* I/O to channel is blocked */ |
226 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
226 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
227 | 227 | ||
228 | /* PCI card is dead */ |
228 | /* PCI card is dead */ |
229 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
229 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
230 | }; |
230 | }; |
231 | 231 | ||
232 | 232 | ||
233 | typedef unsigned int PCITAG; |
233 | typedef unsigned int PCITAG; |
234 | 234 | ||
235 | extern inline PCITAG |
235 | extern inline PCITAG |
236 | pciTag(int busnum, int devnum, int funcnum) |
236 | pciTag(int busnum, int devnum, int funcnum) |
237 | { |
237 | { |
238 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
238 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
239 | } |
239 | } |
240 | 240 | ||
241 | /* This defines the direction arg to the DMA mapping routines. */ |
241 | /* This defines the direction arg to the DMA mapping routines. */ |
242 | #define PCI_DMA_BIDIRECTIONAL 0 |
242 | #define PCI_DMA_BIDIRECTIONAL 0 |
243 | #define PCI_DMA_TODEVICE 1 |
243 | #define PCI_DMA_TODEVICE 1 |
244 | #define PCI_DMA_FROMDEVICE 2 |
244 | #define PCI_DMA_FROMDEVICE 2 |
245 | #define PCI_DMA_NONE 3 |
245 | #define PCI_DMA_NONE 3 |
246 | 246 | ||
247 | /* |
247 | /* |
248 | * For PCI devices, the region numbers are assigned this way: |
248 | * For PCI devices, the region numbers are assigned this way: |
249 | */ |
249 | */ |
250 | enum { |
250 | enum { |
251 | /* #0-5: standard PCI resources */ |
251 | /* #0-5: standard PCI resources */ |
252 | PCI_STD_RESOURCES, |
252 | PCI_STD_RESOURCES, |
253 | PCI_STD_RESOURCE_END = 5, |
253 | PCI_STD_RESOURCE_END = 5, |
254 | 254 | ||
255 | /* #6: expansion ROM resource */ |
255 | /* #6: expansion ROM resource */ |
256 | PCI_ROM_RESOURCE, |
256 | PCI_ROM_RESOURCE, |
257 | 257 | ||
258 | /* device specific resources */ |
258 | /* device specific resources */ |
259 | #ifdef CONFIG_PCI_IOV |
259 | #ifdef CONFIG_PCI_IOV |
260 | PCI_IOV_RESOURCES, |
260 | PCI_IOV_RESOURCES, |
261 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
261 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
262 | #endif |
262 | #endif |
263 | 263 | ||
264 | /* resources assigned to buses behind the bridge */ |
264 | /* resources assigned to buses behind the bridge */ |
265 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
265 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
266 | 266 | ||
267 | PCI_BRIDGE_RESOURCES, |
267 | PCI_BRIDGE_RESOURCES, |
268 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
268 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
269 | PCI_BRIDGE_RESOURCE_NUM - 1, |
269 | PCI_BRIDGE_RESOURCE_NUM - 1, |
270 | 270 | ||
271 | /* total resources associated with a PCI device */ |
271 | /* total resources associated with a PCI device */ |
272 | PCI_NUM_RESOURCES, |
272 | PCI_NUM_RESOURCES, |
273 | 273 | ||
274 | /* preserve this for compatibility */ |
274 | /* preserve this for compatibility */ |
275 | DEVICE_COUNT_RESOURCE |
275 | DEVICE_COUNT_RESOURCE |
276 | }; |
276 | }; |
277 | 277 | ||
278 | 278 | ||
279 | /* |
279 | /* |
280 | * For PCI devices, the region numbers are assigned this way: |
280 | * For PCI devices, the region numbers are assigned this way: |
281 | * |
281 | * |
282 | * 0-5 standard PCI regions |
282 | * 0-5 standard PCI regions |
283 | * 6 expansion ROM |
283 | * 6 expansion ROM |
284 | * 7-10 bridges: address space assigned to buses behind the bridge |
284 | * 7-10 bridges: address space assigned to buses behind the bridge |
285 | */ |
285 | */ |
286 | 286 | ||
287 | #define PCI_ROM_RESOURCE 6 |
287 | #define PCI_ROM_RESOURCE 6 |
288 | #define PCI_BRIDGE_RESOURCES 7 |
288 | #define PCI_BRIDGE_RESOURCES 7 |
289 | #define PCI_NUM_RESOURCES 11 |
289 | #define PCI_NUM_RESOURCES 11 |
290 | 290 | ||
291 | #ifndef PCI_BUS_NUM_RESOURCES |
291 | #ifndef PCI_BUS_NUM_RESOURCES |
292 | #define PCI_BUS_NUM_RESOURCES 8 |
292 | #define PCI_BUS_NUM_RESOURCES 8 |
293 | #endif |
293 | #endif |
294 | 294 | ||
295 | #define DEVICE_COUNT_RESOURCE 12 |
295 | #define DEVICE_COUNT_RESOURCE 12 |
296 | 296 | ||
297 | 297 | ||
298 | #define PCI_CFG_SPACE_SIZE 256 |
298 | #define PCI_CFG_SPACE_SIZE 256 |
299 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
299 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
300 | 300 | ||
301 | 301 | ||
302 | typedef int __bitwise pci_power_t; |
302 | typedef int __bitwise pci_power_t; |
303 | 303 | ||
304 | #define PCI_D0 ((pci_power_t __force) 0) |
304 | #define PCI_D0 ((pci_power_t __force) 0) |
305 | #define PCI_D1 ((pci_power_t __force) 1) |
305 | #define PCI_D1 ((pci_power_t __force) 1) |
306 | #define PCI_D2 ((pci_power_t __force) 2) |
306 | #define PCI_D2 ((pci_power_t __force) 2) |
307 | #define PCI_D3hot ((pci_power_t __force) 3) |
307 | #define PCI_D3hot ((pci_power_t __force) 3) |
308 | #define PCI_D3cold ((pci_power_t __force) 4) |
308 | #define PCI_D3cold ((pci_power_t __force) 4) |
309 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
309 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
310 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
310 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
311 | 311 | ||
312 | 312 | ||
313 | enum pci_bar_type { |
313 | enum pci_bar_type { |
314 | pci_bar_unknown, /* Standard PCI BAR probe */ |
314 | pci_bar_unknown, /* Standard PCI BAR probe */ |
315 | pci_bar_io, /* An io port BAR */ |
315 | pci_bar_io, /* An io port BAR */ |
316 | pci_bar_mem32, /* A 32-bit memory BAR */ |
316 | pci_bar_mem32, /* A 32-bit memory BAR */ |
317 | pci_bar_mem64, /* A 64-bit memory BAR */ |
317 | pci_bar_mem64, /* A 64-bit memory BAR */ |
318 | }; |
318 | }; |
319 | 319 | ||
320 | /* |
320 | /* |
321 | * The pci_dev structure is used to describe PCI devices. |
321 | * The pci_dev structure is used to describe PCI devices. |
322 | */ |
322 | */ |
323 | struct pci_dev { |
323 | struct pci_dev { |
324 | struct list_head bus_list; /* node in per-bus list */ |
324 | struct list_head bus_list; /* node in per-bus list */ |
325 | struct pci_bus *bus; /* bus this device is on */ |
325 | struct pci_bus *bus; /* bus this device is on */ |
326 | struct pci_bus *subordinate; /* bus this device bridges to */ |
326 | struct pci_bus *subordinate; /* bus this device bridges to */ |
327 | 327 | ||
328 | void *sysdata; /* hook for sys-specific extension */ |
328 | void *sysdata; /* hook for sys-specific extension */ |
329 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
329 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
330 | struct pci_slot *slot; /* Physical slot this device is in */ |
330 | struct pci_slot *slot; /* Physical slot this device is in */ |
331 | u32_t busnr; |
331 | u32_t busnr; |
332 | unsigned int devfn; /* encoded device & function index */ |
332 | unsigned int devfn; /* encoded device & function index */ |
333 | unsigned short vendor; |
333 | unsigned short vendor; |
334 | unsigned short device; |
334 | unsigned short device; |
335 | unsigned short subsystem_vendor; |
335 | unsigned short subsystem_vendor; |
336 | unsigned short subsystem_device; |
336 | unsigned short subsystem_device; |
337 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
337 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
338 | u8 revision; /* PCI revision, low byte of class word */ |
338 | u8 revision; /* PCI revision, low byte of class word */ |
339 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
339 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
340 | u8 pcie_cap; /* PCI-E capability offset */ |
340 | u8 pcie_cap; /* PCI-E capability offset */ |
341 | u8 pcie_type; /* PCI-E device/port type */ |
341 | u8 pcie_type; /* PCI-E device/port type */ |
342 | u8 rom_base_reg; /* which config register controls the ROM */ |
342 | u8 rom_base_reg; /* which config register controls the ROM */ |
343 | u8 pin; /* which interrupt pin this device uses */ |
343 | u8 pin; /* which interrupt pin this device uses */ |
344 | 344 | ||
345 | // struct pci_driver *driver; /* which driver has allocated this device */ |
345 | // struct pci_driver *driver; /* which driver has allocated this device */ |
346 | u64 dma_mask; /* Mask of the bits of bus address this |
346 | u64 dma_mask; /* Mask of the bits of bus address this |
347 | device implements. Normally this is |
347 | device implements. Normally this is |
348 | 0xffffffff. You only need to change |
348 | 0xffffffff. You only need to change |
349 | this if your device has broken DMA |
349 | this if your device has broken DMA |
350 | or supports 64-bit transfers. */ |
350 | or supports 64-bit transfers. */ |
351 | 351 | ||
352 | // struct device_dma_parameters dma_parms; |
352 | // struct device_dma_parameters dma_parms; |
353 | 353 | ||
354 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
354 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
355 | this is D0-D3, D0 being fully functional, |
355 | this is D0-D3, D0 being fully functional, |
356 | and D3 being off. */ |
356 | and D3 being off. */ |
357 | int pm_cap; /* PM capability offset in the |
357 | int pm_cap; /* PM capability offset in the |
358 | configuration space */ |
358 | configuration space */ |
359 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
359 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
360 | can be generated */ |
360 | can be generated */ |
361 | unsigned int pme_interrupt:1; |
361 | unsigned int pme_interrupt:1; |
362 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
362 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
363 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
363 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
364 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
364 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
365 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
365 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
366 | decoding during bar sizing */ |
366 | decoding during bar sizing */ |
367 | unsigned int wakeup_prepared:1; |
367 | unsigned int wakeup_prepared:1; |
368 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
368 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
369 | 369 | ||
370 | pci_channel_state_t error_state; /* current connectivity state */ |
370 | pci_channel_state_t error_state; /* current connectivity state */ |
371 | struct device dev; /* Generic device interface */ |
371 | struct device dev; /* Generic device interface */ |
372 | 372 | ||
373 | int cfg_size; /* Size of configuration space */ |
373 | int cfg_size; /* Size of configuration space */ |
374 | 374 | ||
375 | /* |
375 | /* |
376 | * Instead of touching interrupt line and base address registers |
376 | * Instead of touching interrupt line and base address registers |
377 | * directly, use the values stored here. They might be different! |
377 | * directly, use the values stored here. They might be different! |
378 | */ |
378 | */ |
379 | unsigned int irq; |
379 | unsigned int irq; |
380 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
380 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
381 | 381 | ||
382 | /* These fields are used by common fixups */ |
382 | /* These fields are used by common fixups */ |
383 | unsigned int transparent:1; /* Transparent PCI bridge */ |
383 | unsigned int transparent:1; /* Transparent PCI bridge */ |
384 | unsigned int multifunction:1;/* Part of multi-function device */ |
384 | unsigned int multifunction:1;/* Part of multi-function device */ |
385 | /* keep track of device state */ |
385 | /* keep track of device state */ |
386 | unsigned int is_added:1; |
386 | unsigned int is_added:1; |
387 | unsigned int is_busmaster:1; /* device is busmaster */ |
387 | unsigned int is_busmaster:1; /* device is busmaster */ |
388 | unsigned int no_msi:1; /* device may not use msi */ |
388 | unsigned int no_msi:1; /* device may not use msi */ |
389 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
389 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
390 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
390 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
391 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
391 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
392 | unsigned int msi_enabled:1; |
392 | unsigned int msi_enabled:1; |
393 | unsigned int msix_enabled:1; |
393 | unsigned int msix_enabled:1; |
394 | unsigned int ari_enabled:1; /* ARI forwarding */ |
394 | unsigned int ari_enabled:1; /* ARI forwarding */ |
395 | unsigned int is_managed:1; |
395 | unsigned int is_managed:1; |
396 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
396 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
397 | Use pci_is_pcie() instead */ |
397 | Use pci_is_pcie() instead */ |
398 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
398 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
399 | unsigned int state_saved:1; |
399 | unsigned int state_saved:1; |
400 | unsigned int is_physfn:1; |
400 | unsigned int is_physfn:1; |
401 | unsigned int is_virtfn:1; |
401 | unsigned int is_virtfn:1; |
402 | unsigned int reset_fn:1; |
402 | unsigned int reset_fn:1; |
403 | unsigned int is_hotplug_bridge:1; |
403 | unsigned int is_hotplug_bridge:1; |
404 | unsigned int __aer_firmware_first_valid:1; |
404 | unsigned int __aer_firmware_first_valid:1; |
405 | unsigned int __aer_firmware_first:1; |
405 | unsigned int __aer_firmware_first:1; |
406 | 406 | ||
407 | 407 | ||
408 | // u32 saved_config_space[16]; /* config space saved at suspend time */ |
408 | // u32 saved_config_space[16]; /* config space saved at suspend time */ |
409 | // struct hlist_head saved_cap_space; |
409 | // struct hlist_head saved_cap_space; |
410 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
410 | // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
411 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
411 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
412 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
412 | // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
413 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
413 | // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
414 | }; |
414 | }; |
415 | 415 | ||
416 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
416 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
417 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
417 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
418 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
418 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
419 | #define pci_resource_len(dev,bar) \ |
419 | #define pci_resource_len(dev,bar) \ |
420 | ((pci_resource_start((dev), (bar)) == 0 && \ |
420 | ((pci_resource_start((dev), (bar)) == 0 && \ |
421 | pci_resource_end((dev), (bar)) == \ |
421 | pci_resource_end((dev), (bar)) == \ |
422 | pci_resource_start((dev), (bar))) ? 0 : \ |
422 | pci_resource_start((dev), (bar))) ? 0 : \ |
423 | \ |
423 | \ |
424 | (pci_resource_end((dev), (bar)) - \ |
424 | (pci_resource_end((dev), (bar)) - \ |
425 | pci_resource_start((dev), (bar)) + 1)) |
425 | pci_resource_start((dev), (bar)) + 1)) |
426 | 426 | ||
427 | struct pci_device_id |
427 | struct pci_device_id |
428 | { |
428 | { |
429 | u16_t vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ |
429 | u16_t vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ |
430 | u16_t subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
430 | u16_t subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
431 | u32_t class, class_mask; /* (class,subclass,prog-if) triplet */ |
431 | u32_t class, class_mask; /* (class,subclass,prog-if) triplet */ |
432 | u32_t driver_data; /* Data private to the driver */ |
432 | u32_t driver_data; /* Data private to the driver */ |
433 | }; |
433 | }; |
434 | 434 | ||
435 | typedef struct |
435 | typedef struct |
436 | { |
436 | { |
437 | struct list_head link; |
437 | struct list_head link; |
438 | struct pci_dev pci_dev; |
438 | struct pci_dev pci_dev; |
439 | }pci_dev_t; |
439 | }pci_dev_t; |
440 | 440 | ||
441 | 441 | ||
442 | typedef unsigned short __bitwise pci_bus_flags_t; |
442 | typedef unsigned short __bitwise pci_bus_flags_t; |
443 | enum pci_bus_flags { |
443 | enum pci_bus_flags { |
444 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
444 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
445 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
445 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
446 | }; |
446 | }; |
447 | 447 | ||
448 | struct pci_sysdata |
448 | struct pci_sysdata |
449 | { |
449 | { |
450 | int domain; /* PCI domain */ |
450 | int domain; /* PCI domain */ |
451 | int node; /* NUMA node */ |
451 | int node; /* NUMA node */ |
452 | #ifdef CONFIG_X86_64 |
452 | #ifdef CONFIG_X86_64 |
453 | void *iommu; /* IOMMU private data */ |
453 | void *iommu; /* IOMMU private data */ |
454 | #endif |
454 | #endif |
455 | }; |
455 | }; |
456 | 456 | ||
457 | struct pci_bus; |
457 | struct pci_bus; |
458 | 458 | ||
459 | struct pci_ops |
459 | struct pci_ops |
460 | { |
460 | { |
461 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
461 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
462 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
462 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
463 | }; |
463 | }; |
464 | 464 | ||
465 | /* |
465 | /* |
466 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
466 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
467 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
467 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
468 | * buses below host bridges or subtractive decode bridges) go in the list. |
468 | * buses below host bridges or subtractive decode bridges) go in the list. |
469 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
469 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
470 | */ |
470 | */ |
471 | 471 | ||
472 | /* |
472 | /* |
473 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
473 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
474 | * and there's no way to program the bridge with the details of the window. |
474 | * and there's no way to program the bridge with the details of the window. |
475 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
475 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
476 | * decode bit set, because they are explicit and can be programmed with _SRS. |
476 | * decode bit set, because they are explicit and can be programmed with _SRS. |
477 | */ |
477 | */ |
478 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
478 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
479 | 479 | ||
480 | struct pci_bus_resource { |
480 | struct pci_bus_resource { |
481 | struct list_head list; |
481 | struct list_head list; |
482 | struct resource *res; |
482 | struct resource *res; |
483 | unsigned int flags; |
483 | unsigned int flags; |
484 | }; |
484 | }; |
485 | 485 | ||
486 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
486 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
487 | 487 | ||
488 | struct pci_bus { |
488 | struct pci_bus { |
489 | struct list_head node; /* node in list of buses */ |
489 | struct list_head node; /* node in list of buses */ |
490 | struct pci_bus *parent; /* parent bus this bridge is on */ |
490 | struct pci_bus *parent; /* parent bus this bridge is on */ |
491 | struct list_head children; /* list of child buses */ |
491 | struct list_head children; /* list of child buses */ |
492 | struct list_head devices; /* list of devices on this bus */ |
492 | struct list_head devices; /* list of devices on this bus */ |
493 | struct pci_dev *self; /* bridge device as seen by parent */ |
493 | struct pci_dev *self; /* bridge device as seen by parent */ |
494 | struct list_head slots; /* list of slots on this bus */ |
494 | struct list_head slots; /* list of slots on this bus */ |
495 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
495 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
496 | struct list_head resources; /* address space routed to this bus */ |
496 | struct list_head resources; /* address space routed to this bus */ |
497 | 497 | ||
498 | struct pci_ops *ops; /* configuration access functions */ |
498 | struct pci_ops *ops; /* configuration access functions */ |
499 | void *sysdata; /* hook for sys-specific extension */ |
499 | void *sysdata; /* hook for sys-specific extension */ |
500 | 500 | ||
501 | unsigned char number; /* bus number */ |
501 | unsigned char number; /* bus number */ |
502 | unsigned char primary; /* number of primary bridge */ |
502 | unsigned char primary; /* number of primary bridge */ |
503 | unsigned char secondary; /* number of secondary bridge */ |
503 | unsigned char secondary; /* number of secondary bridge */ |
504 | unsigned char subordinate; /* max number of subordinate buses */ |
504 | unsigned char subordinate; /* max number of subordinate buses */ |
505 | 505 | ||
506 | char name[48]; |
506 | char name[48]; |
507 | 507 | ||
508 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
508 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
509 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
509 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
510 | // struct device *bridge; |
510 | // struct device *bridge; |
511 | // struct device dev; |
511 | // struct device dev; |
512 | // struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
512 | // struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
513 | // struct bin_attribute *legacy_mem; /* legacy mem */ |
513 | // struct bin_attribute *legacy_mem; /* legacy mem */ |
514 | unsigned int is_added:1; |
514 | unsigned int is_added:1; |
515 | }; |
515 | }; |
516 | 516 | ||
517 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
517 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
518 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
518 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
519 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
519 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
520 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
520 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
521 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
521 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
522 | 522 | ||
523 | 523 | ||
524 | static inline int pci_domain_nr(struct pci_bus *bus) |
524 | static inline int pci_domain_nr(struct pci_bus *bus) |
525 | { |
525 | { |
526 | struct pci_sysdata *sd = bus->sysdata; |
526 | struct pci_sysdata *sd = bus->sysdata; |
527 | return sd->domain; |
527 | return sd->domain; |
528 | } |
528 | } |
529 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
529 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
530 | 530 | ||
531 | /* |
531 | /* |
532 | * Error values that may be returned by PCI functions. |
532 | * Error values that may be returned by PCI functions. |
533 | */ |
533 | */ |
534 | #define PCIBIOS_SUCCESSFUL 0x00 |
534 | #define PCIBIOS_SUCCESSFUL 0x00 |
535 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
535 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
536 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
536 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
537 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
537 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
538 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
538 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
539 | #define PCIBIOS_SET_FAILED 0x88 |
539 | #define PCIBIOS_SET_FAILED 0x88 |
540 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
540 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
541 | 541 | ||
542 | /* Low-level architecture-dependent routines */ |
542 | /* Low-level architecture-dependent routines */ |
543 | 543 | ||
544 | struct pci_bus_region { |
544 | struct pci_bus_region { |
545 | resource_size_t start; |
545 | resource_size_t start; |
546 | resource_size_t end; |
546 | resource_size_t end; |
547 | }; |
547 | }; |
548 | 548 | ||
549 | 549 | ||
550 | 550 | ||
551 | 551 | ||
552 | 552 | ||
553 | 553 | ||
554 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
554 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
555 | 555 | ||
556 | 556 | ||
557 | int enum_pci_devices(void); |
557 | int enum_pci_devices(void); |
558 | 558 | ||
559 | struct pci_device_id* |
559 | struct pci_device_id* |
560 | find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist); |
560 | find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist); |
561 | 561 | ||
562 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
562 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
563 | 563 | ||
564 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
564 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
565 | 565 | ||
566 | struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata); |
566 | struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata); |
567 | struct pci_bus * pci_find_bus(int domain, int busnr); |
567 | struct pci_bus * pci_find_bus(int domain, int busnr); |
568 | int pci_find_capability(struct pci_dev *dev, int cap); |
568 | int pci_find_capability(struct pci_dev *dev, int cap); |
569 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
569 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
570 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
570 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
571 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
571 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
572 | int cap); |
572 | int cap); |
573 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
573 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
574 | struct pci_bus * pci_find_next_bus(const struct pci_bus *from); |
574 | struct pci_bus * pci_find_next_bus(const struct pci_bus *from); |
575 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
575 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
576 | void pcibios_fixup_bus(struct pci_bus *b); |
576 | void pcibios_fixup_bus(struct pci_bus *b); |
577 | 577 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
|
- | 578 | ||
578 | 579 | ||
579 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
580 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
580 | { |
581 | { |
581 | return !(pbus->parent); |
582 | return !(pbus->parent); |
582 | } |
583 | } |
583 | 584 | ||
584 | /** |
585 | /** |
585 | * pci_pcie_cap - get the saved PCIe capability offset |
586 | * pci_pcie_cap - get the saved PCIe capability offset |
586 | * @dev: PCI device |
587 | * @dev: PCI device |
587 | * |
588 | * |
588 | * PCIe capability offset is calculated at PCI device initialization |
589 | * PCIe capability offset is calculated at PCI device initialization |
589 | * time and saved in the data structure. This function returns saved |
590 | * time and saved in the data structure. This function returns saved |
590 | * PCIe capability offset. Using this instead of pci_find_capability() |
591 | * PCIe capability offset. Using this instead of pci_find_capability() |
591 | * reduces unnecessary search in the PCI configuration space. If you |
592 | * reduces unnecessary search in the PCI configuration space. If you |
592 | * need to calculate PCIe capability offset from raw device for some |
593 | * need to calculate PCIe capability offset from raw device for some |
593 | * reasons, please use pci_find_capability() instead. |
594 | * reasons, please use pci_find_capability() instead. |
594 | */ |
595 | */ |
595 | static inline int pci_pcie_cap(struct pci_dev *dev) |
596 | static inline int pci_pcie_cap(struct pci_dev *dev) |
596 | { |
597 | { |
597 | return dev->pcie_cap; |
598 | return dev->pcie_cap; |
598 | } |
599 | } |
599 | 600 | ||
600 | /** |
601 | /** |
601 | * pci_is_pcie - check if the PCI device is PCI Express capable |
602 | * pci_is_pcie - check if the PCI device is PCI Express capable |
602 | * @dev: PCI device |
603 | * @dev: PCI device |
603 | * |
604 | * |
604 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
605 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
605 | */ |
606 | */ |
606 | static inline bool pci_is_pcie(struct pci_dev *dev) |
607 | static inline bool pci_is_pcie(struct pci_dev *dev) |
607 | { |
608 | { |
608 | return !!pci_pcie_cap(dev); |
609 | return !!pci_pcie_cap(dev); |
609 | } |
610 | } |
610 | 611 | ||
611 | 612 | ||
612 | int pci_read_config_dyte(struct pci_dev *dev, int where, u16 *val); |
613 | int pci_read_config_dyte(struct pci_dev *dev, int where, u16 *val); |
613 | int pci_read_config_word(struct pci_dev *dev, int where, u16 *val); |
614 | int pci_read_config_word(struct pci_dev *dev, int where, u16 *val); |
614 | int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
615 | int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
615 | 616 | ||
616 | 617 | ||
617 | static inline int pci_iov_init(struct pci_dev *dev) |
618 | static inline int pci_iov_init(struct pci_dev *dev) |
618 | { |
619 | { |
619 | return -ENODEV; |
620 | return -ENODEV; |
620 | } |
621 | } |
621 | static inline void pci_iov_release(struct pci_dev *dev) |
622 | static inline void pci_iov_release(struct pci_dev *dev) |
622 | 623 | ||
623 | { |
624 | { |
624 | } |
625 | } |
625 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
626 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
626 | enum pci_bar_type *type) |
627 | enum pci_bar_type *type) |
627 | { |
628 | { |
628 | return 0; |
629 | return 0; |
629 | } |
630 | } |
630 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
631 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
631 | { |
632 | { |
632 | } |
633 | } |
633 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
634 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
634 | { |
635 | { |
635 | return 0; |
636 | return 0; |
636 | } |
637 | } |
637 | 638 | ||
638 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
639 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
639 | { |
640 | { |
640 | return -ENODEV; |
641 | return -ENODEV; |
641 | } |
642 | } |
642 | static inline void pci_disable_ats(struct pci_dev *dev) |
643 | static inline void pci_disable_ats(struct pci_dev *dev) |
643 | { |
644 | { |
644 | } |
645 | } |
645 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
646 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
646 | { |
647 | { |
647 | return -ENODEV; |
648 | return -ENODEV; |
648 | } |
649 | } |
649 | static inline int pci_ats_enabled(struct pci_dev *dev) |
650 | static inline int pci_ats_enabled(struct pci_dev *dev) |
650 | { |
651 | { |
651 | return 0; |
652 | return 0; |
652 | } |
653 | } |
653 | 654 | ||
- | 655 | int acpi_get_irq(struct pci_dev *dev); |
|
- | 656 | ||
654 | #define pci_name(x) "radeon" |
657 | #define pci_name(x) "" |
655 | 658 | ||
656 | #endif //__PCI__H__(n))-1)) |
659 | #endif //__PCI__H__(n))-1)) |
657 | 660 | ||
658 | int><(n))-1)) |
661 | int><(n))-1)) |
659 | 662 | ||
660 | int>><>><>><>><>><>><>><>><>><> |
663 | int>><>><>><>><>><>><>><>><>><> |