WebSVN – Kolibri OS – Diff – /drivers/include/linux/pci.h

 #include
 #include
+#include
 #ifndef __PCI_H__
+#define __PCI_H__
+/* pci_slot represents a physical slot */
+struct pci_slot {
+    struct pci_bus *bus;        /* The bus this slot is on */
+    struct list_head list;      /* node in list of slots on this bus */
+//    struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
+    unsigned char number;       /* PCI_SLOT(pci_dev->devfn) */
+//    struct kobject kobj;
+};
 #define __PCI_H__
 #define PCI_ANY_ID (~0)
 #define PCI_CLASS_OTHERS                0xff
-/*
- * Under PCI, each device has 256 bytes of configuration address space,
- * of which the first 64 bytes are standardized as follows:
- */
-#define PCI_VENDOR_ID                   0x000    /* 16 bits */
-#define PCI_DEVICE_ID                   0x002    /* 16 bits */
-#define PCI_COMMAND                     0x004    /* 16 bits */
-#define  PCI_COMMAND_IO                 0x001    /* Enable response in I/O space */
-#define  PCI_COMMAND_MEMORY             0x002    /* Enable response in Memory space */
-#define  PCI_COMMAND_MASTER             0x004    /* Enable bus mastering */
-#define  PCI_COMMAND_SPECIAL            0x008    /* Enable response to special cycles */
-#define  PCI_COMMAND_INVALIDATE         0x010    /* Use memory write and invalidate */
-#define  PCI_COMMAND_VGA_PALETTE        0x020    /* Enable palette snooping */
-#define  PCI_COMMAND_PARITY             0x040    /* Enable parity checking */
-#define  PCI_COMMAND_WAIT               0x080    /* Enable address/data stepping */
-#define  PCI_COMMAND_SERR               0x100    /* Enable SERR */
-#define  PCI_COMMAND_FAST_BACK          0x200    /* Enable back-to-back writes */
-#define  PCI_COMMAND_INTX_DISABLE       0x400    /* INTx Emulation Disable */
-#define PCI_STATUS                      0x006    /* 16 bits */
-#define  PCI_STATUS_CAP_LIST            0x010    /* Support Capability List */
-#define  PCI_STATUS_66MHZ               0x020    /* Support 66 Mhz PCI 2.1 bus */
-#define  PCI_STATUS_UDF                 0x040    /* Support User Definable Features [obsolete] */
-#define  PCI_STATUS_FAST_BACK           0x080    /* Accept fast-back to back */
-#define  PCI_STATUS_PARITY              0x100    /* Detected parity error */
-#define  PCI_STATUS_DEVSEL_MASK         0x600    /* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST         0x000
-#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
-#define  PCI_STATUS_DEVSEL_SLOW         0x400
-#define  PCI_STATUS_SIG_TARGET_ABORT    0x800    /* Set on target abort */
-#define  PCI_STATUS_REC_TARGET_ABORT    0x1000   /* Master ack of " */
-#define  PCI_STATUS_REC_MASTER_ABORT    0x2000   /* Set on master abort */
-#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000   /* Set when we drive SERR */
-#define  PCI_STATUS_DETECTED_PARITY     0x8000   /* Set on parity error */
-#define PCI_CLASS_REVISION               0x08    /* High 24 bits are class, low 8 revision */
-#define PCI_REVISION_ID                  0x08    /* Revision ID */
-#define PCI_CLASS_PROG                   0x09    /* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE                 0x0a    /* Device class */
-#define PCI_CACHE_LINE_SIZE              0x0c    /* 8 bits */
-#define PCI_LATENCY_TIMER                0x0d    /* 8 bits */
-#define PCI_HEADER_TYPE                  0x0e    /* 8 bits */
-#define  PCI_HEADER_TYPE_NORMAL             0
-#define  PCI_HEADER_TYPE_BRIDGE             1
-#define  PCI_HEADER_TYPE_CARDBUS            2
-#define PCI_BIST                         0x0f    /* 8 bits */
-#define  PCI_BIST_CODE_MASK              0x0f    /* Return result */
-#define  PCI_BIST_START                  0x40    /* 1 to start BIST, 2 secs or less */
-#define  PCI_BIST_CAPABLE                0x80    /* 1 if BIST capable */
-/*
- * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of
- * 0xffffffff to the register, and reading it back.  Only
- * 1 bits are decoded.
- */
-#define  PCI_BASE_ADDRESS_0             0x10    /* 32 bits */
-#define  PCI_BASE_ADDRESS_1             0x14    /* 32 bits [htype 0,1 only] */
-#define  PCI_BASE_ADDRESS_2             0x18    /* 32 bits [htype 0 only] */
-#define  PCI_BASE_ADDRESS_3             0x1c    /* 32 bits */
-#define  PCI_BASE_ADDRESS_4             0x20    /* 32 bits */
-#define  PCI_BASE_ADDRESS_5             0x24    /* 32 bits */
-#define  PCI_BASE_ADDRESS_SPACE         0x01    /* 0 = memory, 1 = I/O */
-#define  PCI_BASE_ADDRESS_SPACE_IO      0x01
-#define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
-#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
-#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
-#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
-#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
-/* bit 1 is reserved if address_space = 1 */
-#define PCI_ROM_ADDRESS1                0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
-/* Header type 0 (normal devices) */
-#define PCI_CARDBUS_CIS                  0x28
-#define PCI_SUBSYSTEM_VENDOR_ID          0x2c
-#define PCI_SUBSYSTEM_ID                 0x2e
-#define PCI_ROM_ADDRESS                  0x30    /* Bits 31..11 are address, 10..1 reserved */
-#define  PCI_ROM_ADDRESS_ENABLE          0x01
-#define PCI_ROM_ADDRESS_MASK             (~0x7ffUL)
-#define PCI_INTERRUPT_LINE               0x3c    /* 8 bits */
-#define PCI_INTERRUPT_PIN                0x3d    /* 8 bits */
-#define PCI_CB_SUBSYSTEM_VENDOR_ID       0x40
-#define PCI_CB_SUBSYSTEM_ID              0x42
-#define PCI_CAPABILITY_LIST              0x34    /* Offset of first capability list entry */
-#define PCI_CB_CAPABILITY_LIST           0x14
-/* Capability lists */
-#define PCI_CAP_LIST_ID                  0       /* Capability ID */
-#define  PCI_CAP_ID_PM                   0x01    /* Power Management */
-#define  PCI_CAP_ID_AGP                  0x02    /* Accelerated Graphics Port */
-#define  PCI_CAP_ID_VPD                  0x03    /* Vital Product Data */
-#define  PCI_CAP_ID_SLOTID               0x04    /* Slot Identification */
-#define  PCI_CAP_ID_MSI                  0x05    /* Message Signalled Interrupts */
-#define  PCI_CAP_ID_CHSWP                0x06    /* CompactPCI HotSwap */
-#define  PCI_CAP_ID_PCIX                 0x07    /* PCI-X */
-#define  PCI_CAP_ID_HT                   0x08    /* HyperTransport */
-#define  PCI_CAP_ID_VNDR                 0x09    /* Vendor specific capability */
-#define  PCI_CAP_ID_SHPC                 0x0C    /* PCI Standard Hot-Plug Controller */
-#define  PCI_CAP_ID_EXP                  0x10    /* PCI Express */
-#define  PCI_CAP_ID_MSIX                 0x11    /* MSI-X */
-#define PCI_CAP_LIST_NEXT                1       /* Next capability in the list */
-#define PCI_CAP_FLAGS                    2       /* Capability defined flags (16 bits) */
-#define PCI_CAP_SIZEOF                   4
-/* AGP registers */
-#define PCI_AGP_VERSION                     2   /* BCD version number */
-#define PCI_AGP_RFU                         3   /* Rest of capability flags */
-#define PCI_AGP_STATUS                      4   /* Status register */
-#define  PCI_AGP_STATUS_RQ_MASK        0xff000000  /* Maximum number of requests - 1 */
-#define  PCI_AGP_STATUS_SBA            0x0200   /* Sideband addressing supported */
-#define  PCI_AGP_STATUS_64BIT          0x0020   /* 64-bit addressing supported */
-#define  PCI_AGP_STATUS_FW             0x0010   /* FW transfers supported */
-#define  PCI_AGP_STATUS_RATE4          0x0004   /* 4x transfer rate supported */
-#define  PCI_AGP_STATUS_RATE2          0x0002   /* 2x transfer rate supported */
-#define  PCI_AGP_STATUS_RATE1          0x0001   /* 1x transfer rate supported */
-#define PCI_AGP_COMMAND                     8   /* Control register */
-#define  PCI_AGP_COMMAND_RQ_MASK    0xff000000  /* Master: Maximum number of requests */
-#define  PCI_AGP_COMMAND_SBA           0x0200   /* Sideband addressing enabled */
-#define  PCI_AGP_COMMAND_AGP           0x0100   /* Allow processing of AGP transactions */
-#define  PCI_AGP_COMMAND_64BIT         0x0020   /* Allow processing of 64-bit addresses */
-#define  PCI_AGP_COMMAND_FW            0x0010   /* Force FW transfers */
-#define  PCI_AGP_COMMAND_RATE4         0x0004   /* Use 4x rate */
-#define  PCI_AGP_COMMAND_RATE2         0x0002   /* Use 2x rate */
-#define  PCI_AGP_COMMAND_RATE1         0x0001   /* Use 1x rate */
 #define PCI_AGP_SIZEOF                     12
 #define PCI_DEVFN(slot, func)  ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 #define PCI_SLOT(devfn)        (((devfn) >> 3) & 0x1f)
 #define PCI_FUNC(devfn)        ((devfn) & 0x07)
+/* Ioctls for /proc/bus/pci/X/Y nodes. */
+#define PCIIOC_BASE		('P' << 24 | 'C' << 16 | 'I' << 8)
+#define PCIIOC_CONTROLLER	(PCIIOC_BASE | 0x00)	/* Get controller for PCI device. */
+#define PCIIOC_MMAP_IS_IO	(PCIIOC_BASE | 0x01)	/* Set mmap state to I/O space. */
+#define PCIIOC_MMAP_IS_MEM	(PCIIOC_BASE | 0x02)	/* Set mmap state to MEM space. */
+#define PCIIOC_WRITE_COMBINE	(PCIIOC_BASE | 0x03)	/* Enable/disable write-combining. */
+typedef unsigned int __bitwise pci_channel_state_t;
+enum pci_channel_state {
+    /* I/O channel is in normal state */
+    pci_channel_io_normal = (__force pci_channel_state_t) 1,
+    /* I/O to channel is blocked */
+    pci_channel_io_frozen = (__force pci_channel_state_t) 2,
+    /* PCI card is dead */
+    pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
 };
          unsigned long flags;
          struct resource *parent, *sibling, *child;
 };
+/* This defines the direction arg to the DMA mapping routines. */
+#define PCI_DMA_BIDIRECTIONAL	0
+#define PCI_DMA_TODEVICE	1
+#define PCI_DMA_FROMDEVICE	2
+#define PCI_DMA_NONE		3
 /*
  *  For PCI devices, the region numbers are assigned this way:
  */
 /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
 #define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
 /*
  *  For PCI devices, the region numbers are assigned this way:
+ *
 #endif
 #define DEVICE_COUNT_RESOURCE   12
+#define PCI_CFG_SPACE_SIZE      256
+#define PCI_CFG_SPACE_EXP_SIZE  4096
+typedef int __bitwise pci_power_t;
+#define PCI_D0      ((pci_power_t __force) 0)
+#define PCI_D1      ((pci_power_t __force) 1)
+#define PCI_D2      ((pci_power_t __force) 2)
+#define PCI_D3hot   ((pci_power_t __force) 3)
+#define PCI_D3cold  ((pci_power_t __force) 4)
+#define PCI_UNKNOWN ((pci_power_t __force) 5)
+#define PCI_POWER_ERROR ((pci_power_t __force) -1)
 /*
  * The pci_dev structure is used to describe PCI devices.
  */
 struct pci_dev {
-//    struct list_head bus_list;  /* node in per-bus list */
+    struct list_head bus_list;  /* node in per-bus list */
-//    struct pci_bus  *bus;       /* bus this device is on */
+    struct pci_bus  *bus;       /* bus this device is on */
-//    struct pci_bus  *subordinate;   /* bus this device bridges to */
+    struct pci_bus  *subordinate;   /* bus this device bridges to */
-//    void        *sysdata;       /* hook for sys-specific extension */
+    void        *sysdata;       /* hook for sys-specific extension */
 //    struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
-//    struct pci_slot *slot;      /* Physical slot this device is in */
+    struct pci_slot *slot;      /* Physical slot this device is in */
-    u32_t        bus;
+    u32_t        busnr;
-    u32_t        devfn;          /* encoded device & function index */
+	unsigned int	devfn;		/* encoded device & function index */
-    u16_t        vendor;
+	unsigned short	vendor;
-    u16_t        device;
+	unsigned short	device;
-    u16_t        subsystem_vendor;
+	unsigned short	subsystem_vendor;
-    u16_t        subsystem_device;
+	unsigned short	subsystem_device;
-    u32_t        class;         /* 3 bytes: (base,sub,prog-if) */
+	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
+	u8		revision;	/* PCI revision, low byte of class word */
-    uint8_t      revision;      /* PCI revision, low byte of class word */
+	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
-    uint8_t      hdr_type;      /* PCI header type (`multi' flag masked out) */
+	u8		pcie_cap;	/* PCI-E capability offset */
-    uint8_t      pcie_type;     /* PCI-E device/port type */
+    u8           pcie_type;     /* PCI-E device/port type */
-    uint8_t      rom_base_reg;   /* which config register controls the ROM */
+	u8		rom_base_reg;	/* which config register controls the ROM */
-    uint8_t      pin;           /* which interrupt pin this device uses */
+	u8		pin;  		/* which interrupt pin this device uses */
  //   struct pci_driver *driver;  /* which driver has allocated this device */
-    uint64_t     dma_mask;   /* Mask of the bits of bus address this
+	u64		dma_mask;	/* Mask of the bits of bus address this
                        device implements.  Normally this is
 xffffffff.  You only need to change
                        this if your device has broken DMA
                        or supports 64-bit transfers.  */
  //   struct device_dma_parameters dma_parms;
-//    pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
+    pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
- //                      this is D0-D3, D0 being fully functional,
+                                       this is D0-D3, D0 being fully functional,
+                                       and D3 being off. */
-//                       and D3 being off. */
+    int     pm_cap;     /* PM capability offset in the
-//    int     pm_cap;     /* PM capability offset in the
+                           configuration space */
-//                       configuration space */
+    unsigned int    pme_support:5;  /* Bitmask of states from which PME#
+                       can be generated */
+	unsigned int	pme_interrupt:1;
+    unsigned int    d1_support:1;   /* Low power state D1 is supported */
+    unsigned int    d2_support:1;   /* Low power state D2 is supported */
-    unsigned int    pme_support:5;  /* Bitmask of states from which PME#
+    unsigned int    no_d1d2:1;  /* Only allow D0 and D3 */
-                       can be generated */
+	unsigned int	mmio_always_on:1;	/* disallow turning off io/mem
-    unsigned int    d1_support:1;   /* Low power state D1 is supported */
+						   decoding during bar sizing */
-    unsigned int    d2_support:1;   /* Low power state D2 is supported */
+	unsigned int	wakeup_prepared:1;
-    unsigned int    no_d1d2:1;  /* Only allow D0 and D3 */
+	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
-//    pci_channel_state_t error_state;    /* current connectivity state */
+    pci_channel_state_t error_state;    /* current connectivity state */
     unsigned int    msi_enabled:1;
     unsigned int    msix_enabled:1;
     unsigned int    ari_enabled:1;  /* ARI forwarding */
     unsigned int    is_managed:1;
-    unsigned int    is_pcie:1;
+	unsigned int	is_pcie:1;	/* Obsolete. Will be removed.
+					   Use pci_is_pcie() instead */
-    unsigned int    state_saved:1;
+	unsigned int    needs_freset:1; /* Dev requires fundamental reset */
+    unsigned int    state_saved:1;
     unsigned int    is_physfn:1;
     unsigned int    is_virtfn:1;
-//    pci_dev_flags_t dev_flags;
+	unsigned int	reset_fn:1;
+	unsigned int    is_hotplug_bridge:1;
-//    atomic_t    enable_cnt;   /* pci_enable_device has been called */
+	unsigned int    __aer_firmware_first_valid:1;
+	unsigned int	__aer_firmware_first:1;
 //    u32     saved_config_space[16]; /* config space saved at suspend time */
 //    struct hlist_head saved_cap_space;
 //    struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
 //    int rom_attr_enabled;       /* has display of the rom attribute been enabled? */
     int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
     int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
 };
+/*
+ * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
+ * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
+ * buses below host bridges or subtractive decode bridges) go in the list.
+ * Use pci_bus_for_each_resource() to iterate through all the resources.
+ */
+/*
+ * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
+ * and there's no way to program the bridge with the details of the window.
+ * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
+ * decode bit set, because they are explicit and can be programmed with _SRS.
+ */
+#define PCI_SUBTRACTIVE_DECODE	0x1
+struct pci_bus_resource {
+	struct list_head list;
+	struct resource *res;
+	unsigned int flags;
+};
+#define PCI_REGION_FLAG_MASK	0x0fU	/* These bits of resource flags tell us the PCI region flags */
 struct pci_bus {
     struct list_head node;      /* node in list of buses */
     struct pci_bus  *parent;    /* parent bus this bridge is on */
 };
 #define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
+#define pci_dev_b(n)    list_entry(n, struct pci_dev, bus_list)
+#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
+#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
 static inline int pci_domain_nr(struct pci_bus *bus)
+{
     struct pci_sysdata *sd = bus->sysdata;
+    return sd->domain;
+}
+static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
+/*
+ * Error values that may be returned by PCI functions.
+ */
+#define PCIBIOS_SUCCESSFUL		0x00
+#define PCIBIOS_FUNC_NOT_SUPPORTED	0x81
+#define PCIBIOS_BAD_VENDOR_ID		0x83
+#define PCIBIOS_DEVICE_NOT_FOUND	0x86
+#define PCIBIOS_BAD_REGISTER_NUMBER	0x87
+#define PCIBIOS_SET_FAILED		0x88
+#define PCIBIOS_BUFFER_TOO_SMALL	0x89
+/* Low-level architecture-dependent routines */
+struct pci_bus_region {
+	resource_size_t start;
+	resource_size_t end;
+};
     return sd->domain;
 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
 struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata);
+struct pci_bus * pci_find_bus(int domain, int busnr);
+int pci_find_capability(struct pci_dev *dev, int cap);
+int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
+int pci_find_ext_capability(struct pci_dev *dev, int cap);
+int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
+				int cap);
-struct pci_bus * pci_find_bus(int domain, int busnr);
+int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
+struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
+static inline bool pci_is_root_bus(struct pci_bus *pbus)
+{
+    return !(pbus->parent);
+}
+/**
+ * pci_pcie_cap - get the saved PCIe capability offset
+ * @dev: PCI device
+ *
+ * PCIe capability offset is calculated at PCI device initialization
+ * time and saved in the data structure. This function returns saved
+ * PCIe capability offset. Using this instead of pci_find_capability()
+ * reduces unnecessary search in the PCI configuration space. If you
+ * need to calculate PCIe capability offset from raw device for some
+ * reasons, please use pci_find_capability() instead.
+ */
+static inline int pci_pcie_cap(struct pci_dev *dev)
+{
+    return dev->pcie_cap;
+}
+/**
+ * pci_is_pcie - check if the PCI device is PCI Express capable
+ * @dev: PCI device
+ *
+ * Retrun true if the PCI device is PCI Express capable, false otherwise.
+ */
+static inline bool pci_is_pcie(struct pci_dev *dev)
 struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
     return !!pci_pcie_cap(dev);

Subversion Repositories Kolibri OS

(root)/drivers/include/linux/pci.h – Rev 1627 → 1628