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| 1 | /************************************************************************** |
1 | /************************************************************************** |
| 2 | * |
2 | * |
| 3 | * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA |
3 | * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA |
| 4 | * All Rights Reserved. |
4 | * All Rights Reserved. |
| 5 | * |
5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
12 | * the following conditions: |
| 13 | * |
13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
16 | * of the Software. |
| 17 | * |
17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
25 | * |
| 26 | **************************************************************************/ |
26 | **************************************************************************/ |
| 27 | /* |
27 | /* |
| 28 | * Authors: Thomas Hellstrom |
28 | * Authors: Thomas Hellstrom |
| 29 | */ |
29 | */ |
| 30 | 30 | ||
| 31 | #ifndef _TTM_PLACEMENT_H_ |
31 | #ifndef _TTM_PLACEMENT_H_ |
| 32 | #define _TTM_PLACEMENT_H_ |
32 | #define _TTM_PLACEMENT_H_ |
| 33 | /* |
33 | /* |
| 34 | * Memory regions for data placement. |
34 | * Memory regions for data placement. |
| 35 | */ |
35 | */ |
| 36 | 36 | ||
| 37 | #define TTM_PL_SYSTEM 0 |
37 | #define TTM_PL_SYSTEM 0 |
| 38 | #define TTM_PL_TT 1 |
38 | #define TTM_PL_TT 1 |
| 39 | #define TTM_PL_VRAM 2 |
39 | #define TTM_PL_VRAM 2 |
| 40 | #define TTM_PL_PRIV0 3 |
40 | #define TTM_PL_PRIV0 3 |
| 41 | #define TTM_PL_PRIV1 4 |
41 | #define TTM_PL_PRIV1 4 |
| 42 | #define TTM_PL_PRIV2 5 |
42 | #define TTM_PL_PRIV2 5 |
| 43 | #define TTM_PL_PRIV3 6 |
43 | #define TTM_PL_PRIV3 6 |
| 44 | #define TTM_PL_PRIV4 7 |
44 | #define TTM_PL_PRIV4 7 |
| 45 | #define TTM_PL_PRIV5 8 |
45 | #define TTM_PL_PRIV5 8 |
| 46 | #define TTM_PL_SWAPPED 15 |
46 | #define TTM_PL_SWAPPED 15 |
| 47 | 47 | ||
| 48 | #define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM) |
48 | #define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM) |
| 49 | #define TTM_PL_FLAG_TT (1 << TTM_PL_TT) |
49 | #define TTM_PL_FLAG_TT (1 << TTM_PL_TT) |
| 50 | #define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM) |
50 | #define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM) |
| 51 | #define TTM_PL_FLAG_PRIV0 (1 << TTM_PL_PRIV0) |
51 | #define TTM_PL_FLAG_PRIV0 (1 << TTM_PL_PRIV0) |
| 52 | #define TTM_PL_FLAG_PRIV1 (1 << TTM_PL_PRIV1) |
52 | #define TTM_PL_FLAG_PRIV1 (1 << TTM_PL_PRIV1) |
| 53 | #define TTM_PL_FLAG_PRIV2 (1 << TTM_PL_PRIV2) |
53 | #define TTM_PL_FLAG_PRIV2 (1 << TTM_PL_PRIV2) |
| 54 | #define TTM_PL_FLAG_PRIV3 (1 << TTM_PL_PRIV3) |
54 | #define TTM_PL_FLAG_PRIV3 (1 << TTM_PL_PRIV3) |
| 55 | #define TTM_PL_FLAG_PRIV4 (1 << TTM_PL_PRIV4) |
55 | #define TTM_PL_FLAG_PRIV4 (1 << TTM_PL_PRIV4) |
| 56 | #define TTM_PL_FLAG_PRIV5 (1 << TTM_PL_PRIV5) |
56 | #define TTM_PL_FLAG_PRIV5 (1 << TTM_PL_PRIV5) |
| 57 | #define TTM_PL_FLAG_SWAPPED (1 << TTM_PL_SWAPPED) |
57 | #define TTM_PL_FLAG_SWAPPED (1 << TTM_PL_SWAPPED) |
| 58 | #define TTM_PL_MASK_MEM 0x0000FFFF |
58 | #define TTM_PL_MASK_MEM 0x0000FFFF |
| 59 | 59 | ||
| 60 | /* |
60 | /* |
| 61 | * Other flags that affects data placement. |
61 | * Other flags that affects data placement. |
| 62 | * TTM_PL_FLAG_CACHED indicates cache-coherent mappings |
62 | * TTM_PL_FLAG_CACHED indicates cache-coherent mappings |
| 63 | * if available. |
63 | * if available. |
| 64 | * TTM_PL_FLAG_SHARED means that another application may |
64 | * TTM_PL_FLAG_SHARED means that another application may |
| 65 | * reference the buffer. |
65 | * reference the buffer. |
| 66 | * TTM_PL_FLAG_NO_EVICT means that the buffer may never |
66 | * TTM_PL_FLAG_NO_EVICT means that the buffer may never |
| 67 | * be evicted to make room for other buffers. |
67 | * be evicted to make room for other buffers. |
| - | 68 | * TTM_PL_FLAG_TOPDOWN requests to be placed from the |
|
| - | 69 | * top of the memory area, instead of the bottom. |
|
| 68 | */ |
70 | */ |
| 69 | 71 | ||
| 70 | #define TTM_PL_FLAG_CACHED (1 << 16) |
72 | #define TTM_PL_FLAG_CACHED (1 << 16) |
| 71 | #define TTM_PL_FLAG_UNCACHED (1 << 17) |
73 | #define TTM_PL_FLAG_UNCACHED (1 << 17) |
| 72 | #define TTM_PL_FLAG_WC (1 << 18) |
74 | #define TTM_PL_FLAG_WC (1 << 18) |
| 73 | #define TTM_PL_FLAG_SHARED (1 << 20) |
75 | #define TTM_PL_FLAG_SHARED (1 << 20) |
| 74 | #define TTM_PL_FLAG_NO_EVICT (1 << 21) |
76 | #define TTM_PL_FLAG_NO_EVICT (1 << 21) |
| - | 77 | #define TTM_PL_FLAG_TOPDOWN (1 << 22) |
|
| 75 | 78 | ||
| 76 | #define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \ |
79 | #define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \ |
| 77 | TTM_PL_FLAG_UNCACHED | \ |
80 | TTM_PL_FLAG_UNCACHED | \ |
| 78 | TTM_PL_FLAG_WC) |
81 | TTM_PL_FLAG_WC) |
| 79 | 82 | ||
| 80 | #define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING) |
83 | #define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING) |
| 81 | 84 | ||
| 82 | /* |
85 | /* |
| 83 | * Access flags to be used for CPU- and GPU- mappings. |
86 | * Access flags to be used for CPU- and GPU- mappings. |
| 84 | * The idea is that the TTM synchronization mechanism will |
87 | * The idea is that the TTM synchronization mechanism will |
| 85 | * allow concurrent READ access and exclusive write access. |
88 | * allow concurrent READ access and exclusive write access. |
| 86 | * Currently GPU- and CPU accesses are exclusive. |
89 | * Currently GPU- and CPU accesses are exclusive. |
| 87 | */ |
90 | */ |
| 88 | 91 | ||
| 89 | #define TTM_ACCESS_READ (1 << 0) |
92 | #define TTM_ACCESS_READ (1 << 0) |
| 90 | #define TTM_ACCESS_WRITE (1 << 1) |
93 | #define TTM_ACCESS_WRITE (1 << 1) |
| 91 | 94 | ||
| 92 | #endif |
95 | #endif |