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Rev 2161 Rev 2967
Line 548... Line 548...
548 
#define DRM_IOCTL_RADEON_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 548 
#define DRM_IOCTL_RADEON_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
549 
#define DRM_IOCTL_RADEON_INFO		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
 549 
#define DRM_IOCTL_RADEON_INFO		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
550 
#define DRM_IOCTL_RADEON_GEM_SET_TILING	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
 550 
#define DRM_IOCTL_RADEON_GEM_SET_TILING	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
551 
#define DRM_IOCTL_RADEON_GEM_GET_TILING	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
 551 
#define DRM_IOCTL_RADEON_GEM_GET_TILING	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
552 
#define DRM_IOCTL_RADEON_GEM_BUSY	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
 552 
#define DRM_IOCTL_RADEON_GEM_BUSY	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
- 
 
 553 
#define DRM_IOCTL_RADEON_GEM_VA		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
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553 
 
 554 
 
554 
typedef struct drm_radeon_init {
 555 
typedef struct drm_radeon_init {
555 
	enum {
 556 
	enum {
556 
		RADEON_INIT_CP = 0x01,
 557 
		RADEON_INIT_CP = 0x01,
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	/** Pointer to read the data from. */
 871 
	/** Pointer to read the data from. */
871 
	/* void *, but pointers are not 32/64 compatible */
 872 
	/* void *, but pointers are not 32/64 compatible */
872 
	uint64_t data_ptr;
 873 
	uint64_t data_ptr;
873 
};
 874 
};
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- 
 
 875 
 
- 
 
 876 
#define RADEON_VA_MAP			1
- 
 
 877 
#define RADEON_VA_UNMAP			2
- 
 
 878 
 
- 
 
 879 
#define RADEON_VA_RESULT_OK		0
- 
 
 880 
#define RADEON_VA_RESULT_ERROR		1
- 
 
 881 
#define RADEON_VA_RESULT_VA_EXIST	2
- 
 
 882 
 
- 
 
 883 
#define RADEON_VM_PAGE_VALID		(1 << 0)
- 
 
 884 
#define RADEON_VM_PAGE_READABLE		(1 << 1)
- 
 
 885 
#define RADEON_VM_PAGE_WRITEABLE	(1 << 2)
- 
 
 886 
#define RADEON_VM_PAGE_SYSTEM		(1 << 3)
- 
 
 887 
#define RADEON_VM_PAGE_SNOOPED		(1 << 4)
- 
 
 888 
 
- 
 
 889 
struct drm_radeon_gem_va {
- 
 
 890 
	uint32_t		handle;
- 
 
 891 
	uint32_t		operation;
- 
 
 892 
	uint32_t		vm_id;
- 
 
 893 
	uint32_t		flags;
- 
 
 894 
	uint64_t		offset;
- 
 
 895 
};
874 
 
 896 
 
875 
#define RADEON_CHUNK_ID_RELOCS	0x01
 897 
#define RADEON_CHUNK_ID_RELOCS	0x01
- 
 
 898 
#define RADEON_CHUNK_ID_IB	0x02
- 
 
 899 
#define RADEON_CHUNK_ID_FLAGS	0x03
- 
 
 900 
 
- 
 
 901 
/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
- 
 
 902 
#define RADEON_CS_KEEP_TILING_FLAGS 0x01
- 
 
 903 
#define RADEON_CS_USE_VM            0x02
- 
 
 904 
/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
- 
 
 905 
#define RADEON_CS_RING_GFX          0
- 
 
 906 
#define RADEON_CS_RING_COMPUTE      1
- 
 
 907 
/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
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#define RADEON_CHUNK_ID_IB	0x02
 908 
/* 0 = normal, + = higher priority, - = lower priority */
877 
 
 909 
 
878 
struct drm_radeon_cs_chunk {
 910 
struct drm_radeon_cs_chunk {
879 
	uint32_t		chunk_id;
 911 
	uint32_t		chunk_id;
880 
	uint32_t		length_dw;
 912 
	uint32_t		length_dw;
Line -... Line 913...
- 
 
 913 
	uint64_t		chunk_data;
- 
 
 914 
};
- 
 
 915 
 
881 
	uint64_t		chunk_data;
 916 
/* drm_radeon_cs_reloc.flags */
882 
};
 917 
#define RADEON_RELOC_DONT_SYNC		0x01
883 
 
 918 
 
884 
struct drm_radeon_cs_reloc {
 919 
struct drm_radeon_cs_reloc {
885 
	uint32_t		handle;
 920 
	uint32_t		handle;
Line 910... Line 945...
910 
#define RADEON_INFO_CLOCK_CRYSTAL_FREQ	0x09 /* clock crystal frequency */
 945 
#define RADEON_INFO_CLOCK_CRYSTAL_FREQ	0x09 /* clock crystal frequency */
911 
#define RADEON_INFO_NUM_BACKENDS	0x0a /* DB/backends for r600+ - need for OQ */
 946 
#define RADEON_INFO_NUM_BACKENDS	0x0a /* DB/backends for r600+ - need for OQ */
912 
#define RADEON_INFO_NUM_TILE_PIPES	0x0b /* tile pipes for r600+ */
 947 
#define RADEON_INFO_NUM_TILE_PIPES	0x0b /* tile pipes for r600+ */
913 
#define RADEON_INFO_FUSION_GART_WORKING	0x0c /* fusion writes to GTT were broken before this */
 948 
#define RADEON_INFO_FUSION_GART_WORKING	0x0c /* fusion writes to GTT were broken before this */
914 
#define RADEON_INFO_BACKEND_MAP		0x0d /* pipe to backend map, needed by mesa */
 949 
#define RADEON_INFO_BACKEND_MAP		0x0d /* pipe to backend map, needed by mesa */
- 
 
 950 
/* virtual address start, va < start are reserved by the kernel */
- 
 
 951 
#define RADEON_INFO_VA_START		0x0e
- 
 
 952 
/* maximum size of ib using the virtual memory cs */
- 
 
 953 
#define RADEON_INFO_IB_VM_MAX_SIZE	0x0f
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915 
 
 954 
 
916 
struct drm_radeon_info {
 955 
struct drm_radeon_info {
917 
	uint32_t		request;
 956 
	uint32_t		request;
918 
	uint32_t		pad;
 957 
	uint32_t		pad;